AVIIVA? [ETC]

AViiVA? M4 CL Preliminary [Updated 06/03. 19 Pages] AVIIVA M4 CL 2014: 2048 active pixels. 14 ?m pixel. from 30 MHz to 120 MHz data rate. CameraLink interface ; AVIIVA ? M4 CL初步[更新06/03 。 19页] AVIIVA M4 CL 2014 :2048的有效像素。 14 ?万像素。从30兆赫至120兆赫的数据速率。的CameraLink接口\n
AVIIVA?
型号: AVIIVA?
厂家: ETC    ETC
描述:

AViiVA? M4 CL Preliminary [Updated 06/03. 19 Pages] AVIIVA M4 CL 2014: 2048 active pixels. 14 ?m pixel. from 30 MHz to 120 MHz data rate. CameraLink interface
AVIIVA ? M4 CL初步[更新06/03 。 19页] AVIIVA M4 CL 2014 :2048的有效像素。 14 ?万像素。从30兆赫至120兆赫的数据速率。的CameraLink接口\n

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Features  
High Sensitivity and High SNR Performance Linear CCD  
Resolution:  
– 2048 Pixels with 14 µm Square Pixels  
– 6144 or 8192 Pixels with 7 µm Square Pixels  
100% Aperture, Built-in Antiblooming, No Lag  
CameraLink Data Format (Medium Configuration)  
High Data Rate:  
– 2048 Pixels: 120 Mpixels/s  
– 6144 and 8192 Pixels: 160 Mpixels/s  
Flexible and Easy to Operate Via Serial Control Lines (CameraLink)  
– Integration Time  
CameraLink™  
Linescan  
Camera  
– Gain: 0dB to 30 dB by Steps of 0.04dB  
– Output Format: 8 or 10 Bits Data  
– Offset (for Contrast Expansion)  
– Trigger Mode: Free Run or External Trigger Modes  
Multi-camera Synchronization  
Single Power Supply: 12 to 24V DC Provided on Hirose-6 Connector  
Compact Mechanical Design:  
120 MHz  
– 2048: 56 x 60 x 54 mm (W, H, L)  
– 6144 and 8192: 82 x 60 x 54 mm (W, H, L)  
High Reliability – CE and FCC Compliant  
Available Lens Adapter (Lens Not Supplied):  
– F Mount or T2 Mount for 2048 and 6144 Pixels  
– M72 x 0.75 for 8192 Pixels  
AViiVAM4 CL  
Preliminary  
Description  
This camera has been designed with three concepts in mind: compactness, accuracy  
and versatility.  
Atmel manages the entire process, from the sensor to the camera. The result is a  
camera able to work in 8 or 10 bits, with dedicated electronics offering an  
excellent signal to noise ratio.  
The programmable settings let the user work in different illumination conditions:  
integration time, gain and offset.  
Applications  
The high speed, high resolution, performance and reliability of this camera make it  
well suited for the most demanding industrial applications.  
OCR and barcode reading: postal and parcel sorting, document scanning  
Inspection and metrology: PCB, CD, DVD, display, semiconductor and electronics  
Web inspection: ceramic, printing, currency, textile, wood, paper  
Rev. 5330A–IMAGE–05/03  
Typical Performances  
Table 1. 2k Pixel Cameras Typical Performances  
Parameter  
Value  
Unit  
Sensor Characteristics at Maximum Pixel Rate  
Resolution  
2048  
14  
pixels  
µm  
Pixel size (square)  
Max Line rate  
52  
kHz  
MHz  
Peak data rate  
4 x 30  
x 100  
Antiblooming  
Radiometric Performances at Maximum Pixel Rate  
Output format  
8 or 10  
bit  
nm  
%
Spectral range  
Linearity  
250 – 1100  
2
PRNU  
±6  
10  
10  
%
Sensitivity output matching  
Offset output matching(1)  
%
LSB  
Gain range  
Gmin  
0
Gnom  
18  
Gmax  
30  
(steps of 0.035 dB)  
dB  
Peak response(1)(2)  
SEE  
7
53  
210  
LSB/(nJ/cm2)  
nJ/cm2  
38.5  
4.84  
1.22  
SNR at 25°C  
58  
50 TBC(3)  
260  
42  
30  
dB  
NEE  
pJ/cm2  
LSB/s  
LSB/s  
Dark signal at 25°C(1)  
DSNU at 25°C(1)  
Mechanical and Electrical Interface  
Size (w x h x l)  
2100  
1600  
8500  
6500  
200  
56 x 60 x 54  
mm  
Lens mount  
No optical mount or F mount or T2 mount  
x,y = ±50  
z = 0 – 60  
∆θx,y = ±0.2  
tiltz = 0 – 35  
µm  
µm  
°
Sensor alignment  
µm  
Power supply  
DC, single 12 to 24  
< 10  
V
Power dissipation  
Operating temperature  
Storage temperature  
W
°C  
°C  
0 to 55 (non-condensing)  
-40 to 85 (non-condensing)  
Notes: 1. LSB are given for 8 bit of resolution  
2. nJ/cm² 4 front face temperature  
3. In this specification TBD stands for To Be Defined, TBC for To Be Confirmed  
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Table 2. 6k and 8k Pixel Cameras Typical Performances  
Parameter  
Value  
Unit  
Sensor Characteristics at Maximum Pixel Rate  
6K  
6144  
7
8K  
8192  
7
Resolution  
pixels  
µm  
Pixel size (square)  
Max Line rate  
18.5  
14  
kHz  
MHz  
Peak data rate  
4 x 40  
x 100  
Antiblooming  
Radiometric Performances at Maximum Pixel Rate  
Output format  
8 or 10  
bit  
nm  
%
Spectral range  
Linearity  
250 – 1100  
2
PRNU  
±6  
10  
10  
%
Sensitivity output matching  
Offset output matching(1)  
%
LSB  
Gain range  
Gmin  
0
Gnom  
18  
Gmax  
30  
(steps of 0.035 dB)  
dB  
Peak response(1)(2)  
SEE  
4
34  
135  
1.9  
LSB/(nJ/cm2)  
nJ/cm2  
60  
7.6  
SNR at 25°C  
58  
42  
30  
dB  
NEE  
75 TBC(4)  
pJ/cm2  
LSB/s  
LSB/s  
Dark signal at 25°C(1)  
DSNU RMS at 25°C(1)  
Mechanical and Electrical Interface  
Size (w x h x l)  
450  
3500  
2700  
14000  
11000  
350  
82 x 60 x 54  
M72 x 0.75  
mm  
Lens mount  
x,y = ±50  
z = 0 – 60  
∆θx,y = ±0.2  
tiltz = 0 – 35  
µm  
µm  
°
Sensor alignment  
µm  
Power supply  
DC, single 12 to 24V  
< 10  
V
Power dissipation  
Operating temperature(3)  
Storage temperature  
W
°C  
°C  
0 to 55 (non-condensing)  
-40 to 85 (non-condensing)  
Notes: 1. LSB are given for 8 bit of resolution  
2. nJ/cm² measured on the sensor  
3. Front face temperature  
4. In this specification TBD stands for To Be Defined, TBC for To Be Confirmed  
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Figure 1. Spectral Response  
100%  
80%  
60%  
40%  
20%  
0%  
200  
400  
600  
800  
1000  
Wavelength (nm)  
Description  
CCD  
The CCD uses 4 taps.  
Figure 2. CCD Architecture  
CCD Register 2  
CCD Register 4  
VOS2  
VOS4  
Antiblooming location  
Photodiode area  
1
2
3
N-1  
N
Antiblooming location  
VOS1  
VOS3  
CCD Register 1  
CCD Register 3  
4 prescan elements  
4 prescan elements  
N useful pixels  
Note:  
The prescan pixels are not output from the camera.  
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Camera  
Figure 3. Camera Synoptic  
Power supplies  
DC power  
DATA  
CameraLinkTM  
4 Taps  
transceiver  
Linear CCD  
4 taps  
STROBE,  
LVAL  
pixels analog chain  
PGA, CDS, ADC  
10 bits  
Sequencer  
controller  
TX  
RX  
at 30 or 40 Mpixels/s  
TRIG1,  
TRIG2  
CameraLinkTM  
I/F  
Medium  
Ext CLK  
CCD Drivers  
Serial line  
Microcontroller  
The AViiVA M4 cameras are based on four taps linear CCDs. Therefore, four analog chains  
process pixels of the linear sensor. The analog chains perform the CCD output processing. It  
encompasses the correlated double sampling (CDS), the dark level correction (dark pixel  
clamping), the gain (PGA) and offset correction and finally the analog to digital conversion on  
10 bits (8- or 10-bit output).  
Note: PGA stands for programmable gain array  
A single DC power voltage from 12 to 24 V supplies the camera.  
The functional interface (data and control) is provided by the CameraLinkinterface.  
The camera uses the medium configuration of CameraLinkstandard.  
Note: FVAL=0  
The camera can be used with an external trigger. The camera uses TRIG1 and TRIG2  
signals in the different external trigger modes, (refer to “Camera configuration is set by the  
serial interface. Please refer to “Serial Communication” on page 13 for the detailed  
protocol of the serial line.” on page 7). The camera can be clocked externally, allowing  
system synchronization and/or multi-camera synchronization.  
The camera configuration and settings are performed via a serial line. This interface is used  
for:  
Gain, offset setting  
Dynamic range, data rate setting  
Trigger mode setting: free running or external trigger modes  
Integration time setting: in free running and external trigger mode  
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Standard  
Conformity  
The cameras have been tested in the following conditions:  
Shielded power supply cable.  
Two CameraLink data transfer cables ref. 14B26-SZLB-500-OLC (3M).  
We recommend the use of the same configuration to ensure compliance with the following  
standards.  
CE Conformity  
FCC Conformity  
AViiVA M4 Cameras comply with the requirements of the EMC (European) directive  
89/336/CEE (EN 50081-2, EN 61000-6-2).  
AViiVA M4 Cameras comply with Part 15 of FCC rules.  
Operation is subject to the following two conditions:  
This device may not cause harmful interference, and  
This device must accept any interference received, including interference that may cause  
undesired operation.  
This equipment has been tested and found to comply with the limits for a Class A digital  
device, pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable  
protection against harmful interference when the equipment is operated in a commercial envi-  
ronment. This equipment generates, uses, and can radiate radio frequency energy and, if not  
installed and used in accordance with the instruction manual, may cause harmful interference  
to radio communications. Operation of this equipment in a residential area is likely to cause  
harmful interference in which case the user will be required to correct the interference at his  
own expense.  
Warning: Changes or modifications to this unit not expressly approved by the party responsi-  
ble for compliance could void the user's authority to operate this equipment.  
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Camera  
Commands and  
Controls  
Camera configuration is set by the serial interface. Please refer to “Serial Communication” on  
page 13 for the detailed protocol of the serial line.  
Table 3. Camera Settings  
Functionalities  
Range/Values/Remarks  
Common gain  
Camera gain adjustment  
2 to 35 dB  
Channel 1 gain  
Fine gain adjustment for balance  
Fine gain adjustment for balance  
Fine gain adjustment for balance  
Fine gain adjustment for balance  
Channel offset adjustment  
Channel offset adjustment  
Channel offset adjustment  
Channel offset adjustment  
Channel 2 gain  
Channel 3 gain  
Channel 4 gain  
Channel 1 offset  
Channel 2 offset  
Channel 3 offset  
Channel 4 offset  
Contrast expansion Channel 1  
Contrast expansion Channel 2  
Contrast expansion Channel 3  
Contrast expansion Channel 4  
256 steps  
256 steps  
256 steps  
256 steps  
Table 4. Camera Configuration  
Functionalities  
Range/Values/Remarks  
Output mode (TBC)  
Automatic offset compensation  
Master clock  
2, or 4 outputs  
Allows automatic digital offset compensation  
30 MHz  
Clock source selection  
Internal or external  
Rising or falling edge selection  
Integration time  
Trigger mode  
1 to 32000 steps  
Each step = 1.00 µs  
Free run  
Integration time set by serial line  
External trigger mode  
One signal integration time control  
Two signals integration time control  
Integration time and readout time controlled by  
one or two external signals  
Output data rate  
Master clock period  
Master clock period/2  
Master clock period/4  
Data valid is used  
Data size output  
Output signal  
8 or 10 bits  
Pattern  
Raw video  
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Table 5. Configuration Settings  
Storage/Restoration  
Functionalities  
Range/Values/Remarks  
One factory settings and four customer  
settings  
The maximum number of write cycles allowed by  
the EEPROM is 100,000  
Table 6. Camera Readout  
Camera status  
Functionalities  
Range/Values/Remarks  
Camera gives information on an external  
clock or trigger presence  
Factory ID readout  
Allows ID and serial number readout  
Allows customer ID readout  
Customer ID readout/storage  
Timing  
Synchronization  
Mode  
Four different modes may be used under user control.  
The TRIG1 and TRIG2 signals may be used to trigger an external event and control the  
integration time.  
The Master clock is either external or internal.  
Times are given in seconds or in number of master clock periods (MCP).  
M.C.P is 33 nsecs when master clock frequency is 30 MHz  
Free Run Mode  
Integration time is set by the serial line.  
The integration and readout periods start automatically and immediately after the previous  
period. The readout time depends on the pixel number and pixel rate.  
Table 7. Timing Specification  
Label  
Description  
Min  
Typ  
Max  
(1)  
ti  
tt  
tt  
tt  
Integration time duration  
32 ms  
Integration period to readout delay at master clock H  
Integration period to readout delay at master clock H/2  
Integration period to readout delay at master clock H/4  
21 MCP  
44 MCP  
90 MCP  
Note:  
1. The Integration time is set by the serial line and should be higher than the readout time + tt  
(otherwise it is adjusted to the readout time + tt).  
Figure 4. Timing Diagram  
tt  
Readout N-1  
Readout N  
Integration N  
Integration N+1  
ti  
Trigger Mode  
The integration period starts immediately after the rising edge of TRIG1 input signal. The inte-  
gration time is set by the serial line. This integration period is immediately followed by a  
readout period. The readout time depends on the pixel number and the pixel rate.  
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A 270 ns jitter may occur between the rising edge of TRIG1 and the beginning of real integra-  
tion time.  
Table 8. Timing Specification: Selected output data rate = master clock  
Label  
Description  
Min  
1,9 µs  
Typ  
Max  
ti  
Integration time duration  
32 ms  
td  
tt  
TRIG1 rising to integration period delay  
Integration period stop to readout delay  
Integration period to TRIG1 rising set-up time  
TRIG1 hold time (pulse high duration)  
21 MCP  
See Table 7  
ts  
th  
80 MCP  
8 MCP  
Figure 5. Timing Diagram  
ti  
ts  
th  
td  
tt  
TRIG1  
Integration N  
Integration N+1  
Readout N  
ITC Mode (One Signal)  
In the Integration Time Control (ITC) mode, the integration period starts immediately after the  
falling edge of TRIG1 input signal and stops immediately after the rising edge of TRIG1 input  
signal. It is immediately followed by a readout period. The readout time depends on the pixel  
number and pixel rate.  
Table 9. Timing Specification: Selected output data rate period = Master Clock  
Label  
ti  
Description  
Min  
Typ  
Max  
Integration time duration  
1,9 µs  
td1  
td2  
tt  
21 MCP  
39 MCP  
See Table 7  
TRIG1 falling to starting integration period delay  
TRIG1 rising to ending integration period delay  
Integration period to readout delay  
TRIG1 hold time (pulse high duration)  
th  
8 MCP  
Figure 6. Timing Diagram  
th  
ti  
TRIG1  
td1  
td2  
Readout N-1  
Readout N  
Integration N  
Integration N+1  
tt  
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ITC Mode  
(Two Signals)  
The TRIG2 rising edge starts the integration period.  
The TRIG1 rising edge stops the integration period.  
This period is immediately followed by a readout period.  
Table 10. Timing Specification : Selected Output Data Rate = Master Clock  
Label  
ti  
Description  
Min  
Typ  
Max  
Integration time duration  
1,9 µs  
td1  
td2  
tt  
TRIG2 rising to starting integration period delay  
TRIG1 rising to ending integration period delay  
Integration period to readout delay  
TRIG1 and TRIG2 hold time (pulse high duration)  
21 MCP  
39 MCP  
See Table 7  
th  
8 MCP  
Figure 7. Timing Diagram  
th  
ti  
TRIG2  
td1  
td2  
TRIG1  
Integration N  
Integration N+1  
Readout N-1  
Readout N  
tt  
10  
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Output Data  
Timing  
Table 11. Timing Specification  
Label  
tp  
Description  
Min  
Typ  
5 µs  
Max  
Input to output clock propagation delay  
STROBE to synchronize signal delay  
td  
1.8 µs  
Figure 8. Timing Diagram  
tp  
Internal Clock  
or  
CLOCK_IN  
td  
td  
LVAL  
td  
STROBE  
DATA  
First valid pixel  
Last valid pixel  
Note:  
DVAL, as defined in the CameraLink standard is active at high level  
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Electrical  
Interface  
Power Supply  
It is recommended to insert a 1A fuse between the power supply and the camera. The voltage  
ripple of the power supply should be below ±50 mVp-p at BW = 50MHz for full camera  
performance.  
Table 12. Power Supply  
Signal Name  
PWR  
I/O  
P
Type  
Description  
DC power input: +12 to +24V  
Electrical and mechanical ground  
GND  
P
Note:  
I = input, O = output, IO = bi-directional signal, P = power/ground, NC = not connected  
Command and  
Control  
The CameraLink interface provides four LVDS signals dedicated to camera control (CC1 to  
CC4). On the AViiVA, three of them are used to synchronize the camera on external events.  
1. FVAL, as defined in the CameraLink standard, is not used. FVAL is permanently tied to  
0 (low) level.  
2. CC3 is not used  
Table 13. Signal Definitions  
Signal Name  
TRIG1  
I/O(2)  
Type  
Description  
I
I
I
RS644  
RS644  
RS644  
CC1 – Synchronization input(1)  
TRIG2  
CC2 – Start Integration period in dual synchro mode(1)  
CC4 – External clock for (multi-) camera synchronization(1)  
CLOCK_IN  
Notes: 1. Refer to “Synchronization Mode” on page 8.  
2. I = input, O = output, IO = bi-directional signal, P = power/ground, NC = not  
connected  
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Video Data  
Data and enable signals are provided on the CameraLink interfaces.  
1. FVAL, as defined in the CameraLink standard, is not used. FVAL is permanently tied to  
0 (low) level.  
2. DVAL, as defined in the CameraLink standard, when used is active at high level.  
Table 14. Video Data  
Signal Name  
OUT1-D[9-0]  
OUT2-D[9-0]  
OUT3-D[9-0]  
OUT4-D[9-0]  
STROBE  
I/O(2)  
Type  
Description  
Out 1 pixel data, OUT1-0 = LSB, OUT1-9 = MSB(1)  
O
RS644  
RS644  
RS644  
RS644  
RS644  
RS644  
RS644  
Out 2 pixel data, OUT2-0 = LSB, OUT2-9 = MSB(1)  
Out 3 pixel data, OUT3-0 = LSB, OUT3-9 = MSB(1)  
Out 4 pixel data, OUT4-0 = LSB, OUT4-9 = MSB(1)  
Output data clock, data valid on the rising edge(1)  
Line valid or line enable, active high signal(1)  
Data valid, active high signal  
O
O
O
O
LVAL  
O
DVAL  
O
Notes: 1. Refer to “Output Data Timing” on page 11  
2. I = input, O = output, IO = bi-directional signal, P = power/ground, NC = not connected  
Serial  
Communication  
The CameraLink interface provides two LVDS signal pairs for the communication between the  
camera and the frame grabber. This is an asynchronous serial communication based on the  
RS-232 protocol.  
The configuration of the serial line is:  
Full duplex/without handshaking  
9600 bauds, 8-bit data, no parity, 1 stop bit.  
Table 15. Signal Definition  
Signal Name  
SerTFG  
I/O  
O
I
Type  
Description  
RS644  
RS644  
Differential pair for serial communication to the frame grabber  
Differential pair for serial communication from the frame grabber  
SerTC  
The camera will be delivered with:  
Software dedicated to camera control.  
.dll and .h files to allow camera control in a customer development software.  
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Connector  
Description  
All connectors are on the rear panel. Better results are obtained by using shielded cables (foil  
and braid).  
CameraLink  
Connector  
Standard CameraLink cables should be used to ensure the full electrical compatibility.  
Camera connector type: 2 x MDR-26 (female) ref. 10226-2210VE  
Cable connector type: Standard CameraLink cable should be used (ex. 3M™ – 14B26-SZLB-  
x00-OLC)  
Table 16. CameraLink Connector  
Signal  
GND  
X0-  
Pin  
1
Signal  
GND  
Pin  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
2
X0+  
X1-  
3
X1+  
X2-  
4
X2+  
Xclk-  
X3-  
5
Xclk+  
X3+  
6
SerTC+  
SerTFG-  
CC1-  
CC2+  
CC3-  
CC4+  
GND  
7
SerTC-  
SerTFG+  
CC1+  
CC2-  
CC3+  
CC4-  
GND  
8
9
10  
11  
12  
13  
Bit Assignment  
This bit assignment is compliant with CameraLink specifications in the Medium Configura-  
tion with two cables (see AIA CameraLink documentation).  
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Power Supply  
Camera connector type: Hirose HR10A-7R-6PB (male)  
Cable connector type: Hirose HR10A-7P-6S (female), one connector is delivered with each  
camera.  
Table 17. Power Connector J01  
Signal  
PWR  
PWR  
PWR  
Pin  
1
Signal  
GND  
GND  
GND  
Pin  
4
2
5
3
6
Figure 9. Receptacle Viewed from the Rear of the Camera  
1
6
2
5
3
4
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Ordering Codes  
Table 18. Cameras  
Item  
Part Number  
AVIIVA M4 CameraLink 2048 pixels 14 µm  
AVIIVA M4 CameraLink 6144 pixels 7 µm  
AVIIVA M4 CameraLink 8192 pixels 7 µm  
AT71XM4CL2014-BA0  
AT71XM4CL6007-BA0  
AT71XM4CL8007-BA0  
Note:  
The cameras are delivered with a power supply connector.  
Table 19. Optical Mount  
Item  
Part Number  
F Mount for Aviiva M4 2k or 6k  
T2 Mount for Aviiva M4 2k or 6k  
M72 x 0.75 Mount for Aviiva M4 8k  
AT71-AVIIVAX4-F  
AT71-AVIIVAX4-T2  
AT71-AVIIVAX4-M72  
Note:  
The cameras are delivered without an optical mount.  
Table 20. BG38 Filters  
Item  
Part Number  
Kit BG38 for 2k and 6k  
Kit BG38 for 8k  
AT71ABG38AVIVX4-6K  
AT71ABG38AVIVX4-8K  
Note:  
Filters are held by an optical mount  
Table 21. Accessories  
Item  
Part Number  
2 CameraLink cables (5 meters long)  
Optional heatsink  
AT71KAVIIVA-X4-CL  
Please contact factory  
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Mechanical  
Characteristics  
Weight  
The camera typical weight (without lens) is 500g (TBC).  
Dimensions  
Figure 10. 2k  
60 ±0.2  
48  
5.6  
4 holes M3 dpt:6  
= 32 ±0.2 =  
C
B
6 ±0.2  
1 hole 1/4 UNC dpt:5  
F
4x2 holes M4 dpt:6  
2.8 ±0.2  
4 holes M3 dpt:6  
1st pixel  
= 30 ±0.2 =  
= 52 ±0.2 =  
A
Z
X
Figure 11. 6k and 8k  
60 ±0.2  
5.6  
48  
6 ±0.2  
= 32 ±0.2 =  
B
4 holes M3 dpt:6  
C
1 hole 1/4 UNC dpt:5  
F
4x2 holes M4 dpt:6  
4 holes M3 dpt:6  
1st pixel  
2.8 ±0.2  
= 30 ±0.2 =  
A
Z
= 52 ±0.2 =  
X
17  
5330A–IMAGE–05/03  
Figure 12. Rear Face  
F
19  
31  
DC 12-24V  
CL2  
+
+
+
CL1  
14.5  
Note:  
The 2k rear face doesn’t have the two heat sinks.  
18  
AViiVA M4 CL  
5330A–IMAGE–05/03  
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5330A–IMAGE–05/03  
0M  

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