BQ3285LC [ETC]
Real-Time Clock (RTC) ; 实时时钟（ RTC ）\n
| 型号： | BQ3285LC |
| 厂家： | 
ETC |
| 描述： | Real-Time Clock (RTC)
|
| 文件： | 总26页 (文件大小：832K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
bq3285EC/LC
(
)
Real-Time Clock RTC
in battery-backup mode. In battery
backup mode, current drain is less
than 500nA.
Features
General Description
➤ Direct clock/calendar replace-
ment for IBM® AT-compatible
computers and other applications
The CMOS bq3285EC/LC is a low-
power microprocessor peripheral pro-
viding a time-of-day clock and 100-
year calendar with alarm features
and battery operation. The architec-
ture is based on the bq3285/7 RTC
with added features: low-voltage op-
eration, 32.768kHz output, and an
extra 128 bytes of CMOS.
The bq3285EC/LC write-protects the
clock, calendar, and storage registers
du r in g power fa ilu r e. A ba cku p
battery then maintains data and oper-
ates the clock and calendar.
➤ 2.7–5.5V operation (bq3285LC);
4.5–5.5V operation (bq3285EC)
➤ 242 bytes of general nonvolatile
The bq3285EC/LC is a fully com-
patible real-time clock for IBM AT-
compatible computers and other ap-
plications. The only external compo-
nents are a 32.768kHz crystal and a
backup battery.
storage
➤ Dedicated 32.768kHz output pin
A 32.768kHz output is available for
sustaining power-management ac-
tivities. The bq3285EC 32kHz out-
put is always on whenever VCC is
valid. For the bq3285LC, the output
is on when the oscillator is turned
on . I n VC C s t a n d by m od e, t h e
32kHz is active, and the bq3285LC
t ypica lly dr a ws 100µA wh ile t h e
bq3285EC typically draws 300µA.
Wake-up capability is provided by
an alarm interrupt, which is active
➤ System wake-up capability—
alarm interrupt output active in
battery-backup mode
The bq3285EC is intended for use in
5V systems. The bq3285LC is in-
tended for use in 3V systems; the
bq3285LC, however, may also oper-
ate at 5V and then go into a 3V
power-down state, write-protecting
as if in a 3V system.
➤ Less than 0.5µA load under bat-
tery operation
➤ Selectable Intel or Motorola bus
timing
➤ 24-pin plastic SOIC or SSOP
Pin Connections
Pin Names
AD0–AD7 Multiplexed address/
data input/output
32K
32.768kHz output
EXTRAM Extended RAM enable
MOT
24
1
V
CC
MOT
CS
Bus type select input
Chip select input
Address strobe input
Data strobe input
Read/write input
Interrupt request output
Reset input
X1
X2
23
22
2
3
32k
EXTRAM
RCL
BC
RAM clear input
3V backup cell input
Crystal inputs
Power supply
Ground
4
RCL
BC
AD
AD
AD
AD
AD
AD
AD
21
20
19
18
17
16
15
14
13
0
1
2
3
4
5
6
5
AS
6
INT
RST
DS
V
SS
R/W
X1–X2
VCC
7
DS
8
9
R/W
INT
RST
10
11
12
VSS
AS
CS
AD
7
V
SS
24-Pin SSOP
PN3285EC.eps
July 1996
1
bq3285EC/LC
Block Diagram
X
X
1
Time-
Base
Oscillator
÷ 8
÷ 64
÷ 64
2
3
4
16 1 MUX
:
32K
INT
RST
32K
Driver
Control/Status
Registers
MOT
CS
Interupt
Generator
R/W
AS
Clock/Calendar, Alarm
and Control Bytes
µ
Bus
I/F
P
AD –AD
0
7
User Buffer
(14 Bytes)
DS
Control/Calendar
Update
Storage Registers
(114 Bytes)
RCL
Storage Registers
(128 Bytes)
EXTRAM
CS
V
V
Power-
Fail
Control
CC
OUT
BC
Write
Protect
BD328501.eps
AD0–AD7 Mu ltiplexed addr ess/data
in pu t/ou tpu t
Pin Descriptions
MOT
Bu s typ e select in p u t
The bq3285EC/LC bus cycle consists of two
phases: the address phase and the data-
transfer phase. The address phase pre-
cedes the data-transfer phase. During the
a d d r es s p h a s e, a n a d d r es s p la ced on
AD0–AD7 and EXTRAM is latched into the
bq3285EC/LC on the falling edge of the AS
signal. During the data-transfer phase of
the bus cycle, the AD0–AD7 pins serve as a
bidirectional data bus.
MOT selects bus timing for either Motorola
or Intel architecture. This pin should be
tied to VCC for Motorola timing or to VSS for
Intel timing (see Table 1). The setting
should not be changed during system opera-
tion. MOT is internally pulled low by a 30K
Ω resistor.
Table 1. Bus Setup
AS
Ad d r ess str obe in p u t
Bus
Type
MOT
DS
R/W
AS
AS serves to demultiplex the address/data
bus. The falling edge of AS latches the ad-
dress on AD0–AD7 and EXTRAM. This de-
multiplexing process is independent of the
CS signal. For DIP and SOIC packages
with MOT = VSS, the AS input is provided a
signal similar to ALE in an Intel-based sys-
tem.
Level Equivalent Equivalent Equivalent
DS, E, or
Motorola
VCC
R/W
AS
Φ2
RD,
WR,
Intel
VSS MEMR, or MEMW, or ALE
I/OR I/OW
July 1996
2
bq3285EC/LC
DS
Da ta str obe in p u t
RCL
RAM clea r in p u t
When MOT = VCC, DS controls data trans-
fer during a bq3285EC/LC bus cycle. Dur-
ing a read cycle, the bq3285EC/LC drives
the bus after the rising edge on DS. During
a write cycle, the falling edge on DS is used
to latch write data into the chip.
A low level on the RCL pin causes the con-
tents of each of the 242 storage bytes to be
set to FF(hex). The contents of the clock
and control registers are unaffected. This
pin should be used as a user-interface input
(pushbutton to ground) and not connected
to the output of any active component. RCL
input is only recognized when held low for
at least 125ms in the presence of VCC. Us-
ing RAM clear does not affect the battery
load. This pin is connected internally to a
30kΩ pull-up resistor.
When MOT = VSS, the DS input is provided
a signal similar to RD, MEMR, or I/OR in
an Intel-based system. The falling edge on
DS is used to enable the outputs during a
read cycle.
Read/wr ite in pu t
R/W
BC
3V ba ck u p cell in p u t
When MOT = VCC, the level on R/W identi-
fies the direction of data transfer. A high
level on R/W indicates a read bus cycle,
whereas a low on this pin indicates a write
bus cycle.
BC should be connected to a 3V backup cell
for RTC operation and storage register non-
volatility in the absence of system power.
When VCC slews down past VBC (3V typi-
cal), the integral control circuitry switches
the power source to BC. When VCC returns
above VBC, the power source is switched to
When MOT = VSS, R/W is provided a signal
similar to WR, MEMW, or I/OW in an Intel-
ba sed syst em . The rising edge on R/W
latches data into the bq3285EC/LC.
VCC
.
Upon power-up, a voltage within the VBC
range must be present on the BC pin for
the oscillator to start up.
CS
Ch ip select in p u t
CS should be driven low and held stable
during the data-transfer phase of a bus cy-
cle accessing the bq3285EC/LC.
RST
Reset in p u t
The bq3285EC/LC is reset when RST is
pulled low. When reset, INT becomes high
impedance, and the bq3285EC/LC is not ac-
cessible. Table 4 in the Control/Status Reg-
isters section lists the register bits that are
cleared by a reset.
INT
In ter r u p t r equ est ou tp u t
INT is an open-drain output. This allows
alarm INT to be valid in battery-backup
m ode. To u se t h is fea t u r e, con n ect INT
through a resistor to a power supply other
than VCC. INT is asserted low when any
event fla g is set a n d t he correspon ding
event enable bit is also set. INT becomes
high-impedance whenever register C is read
(see the Control/Status Registers section).
Reset may be disabled by connecting RST
to VCC
. This allows the control bits to re-
t a in t h e ir s t a t e s t h r ou gh p ow e r -
down/power-up cycles.
X1–X2
Cr ysta l in p u ts
32K
32.768 k Hz ou tp u t
The X1–X2 inputs are provided for an ex-
ternal 32.768kHz quartz crystal, Daiwa
DT-26 or equivalent, with 6pF load capaci-
tance. A trimming capacitor may be neces-
sary for extremely precise time-base gen-
eration.
32K provides a buffered 32.768 kHz output.
Th e fr equ en cy r em a in s on a n d fixed a t
32.768kHz as long as VCC is valid.
EXTRAM Exten d ed RAM en a ble
Enables 128 bytes of additional nonvolatile
In the absence of a crystal, a 32.768kHz
waveform can be fed into the X1 input.
SRAM. It is connected internally to a 30kΩ
pull-down resistor. To access the RTC regis-
ters, EXTRAM must be low.
July 1996
3
bq3285EC/LC
each update period (see Figure 2). The alarm flag bit
may also be set during the update cycle.
Functional Description
The bq3285EC/LC copies the local register updates into
the user buffer accessed by the host processor. When a 1
is written to the update transfer inhibit bit (UTI) in reg-
ister B, the user copy of the clock and calendar bytes re-
mains unchanged, while the local copy of the same bytes
continues to be updated every second.
Address Map
The bq3285EC/LC provides 14 bytes of clock and con-
trol/status registers and 242 bytes of general nonvolatile
storage. Figure 1 illustrates the address map for the
bq3285EC/LC.
The update-in-progress bit (UIP) in register A is set
tBUC time before the beginning of an update cycle (see
Figure 2). This bit is cleared and the update-complete
flag (UF) is set at the end of the update cycle.
Update Period
The update period for the bq3285EC/LC is one second.
The bq3285EC/LC updates the contents of the clock and
calendar locations during the update cycle at the end of
Figure 1. Address Map
Figure 2. Update Period Timing and UIP
July 1996
4
bq3285EC/LC
2. Write new values to all the time, alarm, and
Programming the RTC
calendar locations.
The time-of-day, alarm, and calendar bytes can be writ-
ten in either the BCD or binary format (see Table 2).
3. Clear the UTI bit to allow update transfers.
On the next update cycle, the RTC updates all 10 bytes
in the selected format.
These steps may be followed to program the time, alarm,
and calendar:
1. Modify the contents of register B:
a. Write a 1 to the UTI bit to prevent trans-
fers between RTC bytes and user buffer.
b. Write the appropriate value to the data
format (DF) bit to select BCD or binary
format for all time, alarm, and calendar
bytes.
c.
Write the appropriate value to the hour
format (HF) bit.
Table 2. Time, Alarm, and Calendar Formats
Range
Binary-Coded
Decimal
Decimal
0–59
Binary
Address
RTC Bytes
0
1
2
3
Seconds
00H–3BH
00H–3BH
00H–3BH
00H–3BH
00H–59H
00H–59H
00H–59H
00H–59H
Seconds alarm
Minutes
0–59
0–59
Minutes alarm
0–59
01H–OCH AM;
81H–8CH PM
01H–12H AM;
81H–92H PM
Hours, 12-hour format
1–12
4
5
Hours, 24-hour format
0–23
1–12
00H–17H
00H–23H
01H–OCH AM;
81H–8CH PM
01H–12H AM;
81H–92H PM
Hours alarm, 12-hour format
Hours alarm, 24-hour format
Day of week (1=Sunday)
Day of month
0–23
1–7
00H–17H
01H–07H
01H–1FH
01H–0CH
00H–63H
00H–23H
01H–07H
01H–31H
01H–12H
00H–99H
6
7
8
9
1–31
1–12
0–99
Month
Year
July 1996
5
bq3285EC/LC
Each of the three interrupt events is enabled by an indi-
vidual interrupt-enable bit in register B. When an event
occurs, its event flag bit in register C is set. If the corre-
sponding event enable bit is also set, then an interrupt
request is generated. The interrupt request flag bit
(INTF) of register C is set with every interrupt request.
Reading register C clears all flag bits, including INTF,
and makes INT high-impedance.
32kHz Output
The bq3285EC/LC provides for a 32.768kHz output. For
the bq3285EC, the output is always active whenever VCC
is valid (VPFD + tCSR). The bq3285EC output is not af-
fected by the bit settings in Register A. Time-keeping
aspects, however, still require setting OS0-OS2. The
bq3285LC output is active when the oscillator is turned
on by setting the OSC0-OSC2 bits in Register A.
Two methods can be used to process bq3285EC/LC in-
terrupt events:
Interrupts
Enable interrupt events and use the interrupt
request output to invoke an interrupt service routine.
The bq3285EC/LC allows three individually selected in-
terrupt events to generate an interrupt request. These
three interrupt events are:
Do not enable the interrupts and use
routine to periodically check the status of the flag
bits.
a polling
The periodic interrupt, programmable to occur once
every 122µs to 500ms.
The individual interrupt sources are described in detail
in the following sections.
The alarm interrupt, programmable to occur once per
second to once per day, is active in battery-backup
mode, providing a “wake-up” feature.
The update-ended interrupt, which occurs at the end
of each update cycle.
Table 3. Periodic Interrupt Rate
Register A Bits
Periodic Interrupt
OSC2
OSC1
OSC0
RS3
0
RS2
0
RS1
0
RS0
0
Period
None
3.90625
Units
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
ms
ms
µs
0
0
1
0
7.8125
122.070
244.141
488.281
976.5625
1.95315
3.90625
7.8125
15.625
31.25
0
0
1
1
0
1
0
0
µs
0
1
0
1
µs
0
1
1
0
µs
0
1
1
1
ms
ms
ms
ms
ms
ms
ms
ms
ms
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
62.5
1
1
0
1
125
1
1
1
0
250
1
1
1
1
500
same as above defined
by RS3–RS0
0
1
1
X
X
X
X
July 1996
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bq3285EC/LC
Periodic Interrupt
Update Cycle Interrupt
If the periodic interrupt event is enabled by writing a 1
to the periodic interrupt enable bit (PIE) in register C,
an interrupt request is generated once every 122µs to
500ms. The period between interrupts is selected with
bits RS3-RS0 in register A (see Table 3).
The update cycle ended flag bit (UF) in register C is set to
a 1 at the end of an update cycle. If the update interrupt
enable bit (UIE) of register B is 1, and the update transfer
inhibit bit (UTI) in register B is 0, then an interrupt re-
quest is generated at the end of each update cycle.
Alarm Interrupt
Accessing RTC bytes
The alarm interrupt is active in battery-backup mode,
providing a “wake-up” capability. During each update
cycle, the RTC compares the hours, minutes, and sec-
onds bytes with the three corresponding alarm bytes. If
a match of all bytes is found, the alarm interrupt event
flag bit, AF in register C, is set to 1. If the alarm event
is enabled, an interrupt request is generated.
The EXTRAM pin must be low to access the RTC regis-
ters. Time and calendar bytes read during an update
cycle may be in error. Three methods to access the time
and calendar bytes without ambiguity are:
Enable the update interrupt event to generate
interrupt requests at the end of the update cycle.
The interrupt handler has a maximum of 999ms to
access the clock bytes before the next update cycle
begins (see Figure 3).
An alarm byte may be removed from the comparison by
setting it to a “don't care” state. An alarm byte is set to
a “don't care” state by writing a 1 to each of its two
most-significant bits. A “don't care” state may be used to
select the frequency of alarm interrupt events as follows:
Poll the update-in-progress bit (UIP) in register A. If
UIP = 0, the polling routine has a minimum of tBUC
time to access the clock bytes (see Figure 3).
If none of the three alarm bytes is “don't care,” the
frequency is once per day, when hours, minutes, and
seconds match.
Use the periodic interrupt event to generate
interrupt requests every tPI time, such that UIP = 1
always occurs between the periodic interrupts. The
interrupt handler has a minimum of tPI/2 + tBUC
time to access the clock bytes (see Figure 3).
If only the hour alarm byte is “don't care,” the
frequency is once per hour, when minutes and
seconds match.
If only the hour and minute alarm bytes are “don't
care,” the frequency is once per minute, when seconds
match.
Oscillator Control
When power is first applied to the bq3285LC and VCC is
above VPFD, the internal oscillator and frequency divider
are turned on by writing a 010 pattern to bits 4 through
6 of register A. A pattern of 11X turns the oscillator on
but keeps the frequency divider disabled. Any other pat-
tern to these bits keeps the oscillator off. A pattern of
010 must be set for the bq3285EC/LC to keep time in
battery backup mode.
If the hour, minute, and second alarm bytes are
“don't care,” the frequency is once per second.
Figure 3. Update-Ended/Periodic Interrupt Relationship
July 1996
7
bq3285EC/LC
Time-keeping
Power-Down/Power-Up Cycle
Register A provides:
Status of the update cycle.
The bq3285EC and bq3285LC power-up/power-down cy-
cles are different. The bq3285LC continuously monitors
VCC for out-of-tolerance. During a power failure, when
VCC falls below VPFD (2.53V typical), the bq3285LC write-
protects the clock and storage registers. The power source
is switched to BC when VCC is less than VPFD and BC is
greater than VPFD, or when VCC is less than VBC and VBC
RS0–RS3 - Frequency Select
7
-
6
-
5
-
4
-
3
2
1
0
RS3 RS2 RS1 RS0
is less than VPFD. RTC operation and storage data are
sustained by a valid backup energy source. When VCC is
above VPFD, the power source is VCC. Write-protection con-
These bits select the periodic interrupt rate, as shown in
Table 3.
tinues for tCSR time after VCC rises above VPFD
.
OS0–OS2 - Oscillator Control
The bq3285EC continuously monitors VCC for out-of-
tolerance. During a power failure, when VCC falls below
VPFD (4.17V typical), the bq3285EC write-protects the
clock and storage registers. When VCC is below VBC (3V
typical), the power source is switched to BC. RTC opera-
tion and storage data are sustained by a valid backup
energy source. When VCC is above VBC, the power
source is VCC. Write-protection continues for tCSR time
7
-
6
5
4
3
-
2
-
1
-
0
-
OS2 OS1 OS0
These three bits control the state of the oscillator and
divider stages. A pattern of 010 or 011 enables RTC op-
eration by turning on the oscillator and enabling the fre-
quency divider. This pattern must be set to turn the os-
cillator on for the bq3285LC and to ensure that the
bq3285EC/LC will keep time in battery-backup mode. A
pattern of 11X turns the oscillator on, but keeps the fre-
quency divider disabled. When 010 is written, the RTC
begins its first update after 500ms.
after VCC rises above VPFD
.
Control/Status Registers
The four control/status registers of the bq3285EC/LC
are accessible regardless of the status of the update cy-
cle (see Table 4).
UIP - Update Cycle Status
Register A
7
6
-
5
-
4
-
3
-
2
-
1
-
0
-
UIP
Register A Bits
7
6
5
4
3
2
1
0
This read-only bit is set prior to the update cycle. When
UIP equals 1, an RTC update cycle may be in progress.
UIP is cleared at the end of each update cycle. This bit
is also cleared when the update transfer inhibit (UTI)
bit in register B is 1.
UIP OS2 OS1 OS0 RS3 RS2 RS1 RS0
Register A programs:
The frequency of the periodic event rate.
Oscillator operation.
Table 4. Control/Status Registers
Bit Name and State on Reset
Loc.
Reg. (Hex) Read Write
7 (MSB)
6
5
4
3
2
1
0 (LSB)
A
B
C
D
0A
0B
0C
0D
Yes Yes1 UIP na OS2 na OS1 na OS0 na RS3 na RS2 na RS1 na RS0 na
Yes
Yes
Yes
Yes UTI na PIE
0
0
0
AIE
AF
-
0
0
0
UIE
UF
-
0
0
0
-
-
-
0
0
0
DF na HF na DSE na
No INTF
0
PF
-
-
-
na
0
-
-
0
0
-
-
0
0
No VRT na
Notes:
na = not affected.
1. Except bit 7.
July 1996
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bq3285EC/LC
UIE - Update Cycle Interrupt Enable
Register B
7
-
6
-
5
-
4
3
-
2
-
1
-
0
-
Register B Bits
UIE
7
6
5
4
3
-
2
1
0
UTI PIE
AIE UIE
DF
HF
DSE
This bit enables an interrupt request due to an update
ended interrupt event:
Register B enables:
1 = Enabled
0 = Disabled
Update cycle transfer operation
Interrupt events
The UIE bit is automatically cleared when the UTI bit
equals 1.
Daylight saving adjustment
Register B selects:
AIE - Alarm Interrupt Enable
Clock and calendar data formats
All bits of register B are read/write.
Bit 3 - Un u sed Bit.
7
-
6
-
5
4
-
3
-
2
-
1
-
0
-
AIE
This bit enables an interrupt request due to an alarm
interrupt event:
DSE - Daylight Saving Enable
7
-
6
-
5
-
4
-
3
-
2
-
1
-
0
1 = Enabled
0 = Disabled
DSE
This bit enables daylight-saving time adjustments when
written to 1:
PIE - Periodic Interrupt Enable
7
-
6
5
-
4
-
3
-
2
-
1
-
0
-
On the last Sunday in October, the first time the
bq3285EC/LC increments past 1:59:59 AM, the time
falls back to 1:00:00 AM.
PIE
This bit enables an interrupt request due to a periodic
interrupt event:
On the first Sunday in April, the time springs
forward from 2:00:00 AM to 3:00:00 AM.
1 = Enabled
0 = Disabled
HF - Hour Format
7
-
6
-
5
-
4
-
3
-
2
-
1
0
-
UTI - Update Transfer Inhibit
HF
7
6
-
5
-
4
-
3
-
2
-
1
-
0
-
This bit selects the time-of-day and alarm hour format:
1 = 24-hour format
UTI
This bit inhibits the transfer of RTC bytes to the user
buffer:
0 = 12-hour format
DF - Data Format
1 = Inhibits transfer and clears UIE
0 = Allows transfer
7
-
6
-
5
-
4
-
3
-
2
1
-
0
-
DF
This bit selects the numeric format in which the time,
alarm, and calendar bytes are represented:
1 = Binary
0 = BCD
July 1996
9
bq3285EC/LC
Register C
Register D
Register C Bits
Register D Bits
7
6
5
4
3
0
2
-
1
0
0
0
7
6
0
5
0
4
0
3
0
2
0
1
0
0
0
INTF PF
AF
UF
VRT
Register C is the read-only event status register.
Register D is the read-only data integrity status regis-
ter.
Bits 0, 1, 2, 3 - Unused Bits
7
-
6
0
5
0
4
0
3
0
2
0
1
0
0
0
7
-
6
-
5
-
4
-
3
0
2
-
1
0
0
0
These bits are always set to 0.
Bits 0–6 - Unused Bits
These bits are always set to 0.
UF - Update Event Flag
7
-
6
-
5
-
4
3
-
2
-
1
-
0
-
7
6
-
5
-
4
-
3
-
2
-
1
-
0
-
UF
VRT
This bit is set to a 1 at the end of the update cycle.
Reading register C clears this bit.
VRT - Valid RAM and Time
1 = Valid backup energy source
0 = Backup energy source is depleted
AF - Alarm Event Flag
When the backup energy source is depleted (VRT = 0),
data integrity of the RTC and storage registers is not
guaranteed.
7
-
6
-
5
4
-
3
-
2
-
1
-
0
-
AF
This bit is set to a 1 when an alarm event occurs. Read-
ing register C clears this bit.
PF - Periodic Event Flag
7
-
6
5
-
4
-
3
-
2
-
1
-
0
-
PF
This bit is set to a 1 every tPI time, where tPI is the time
period selected by the settings of RS0–RS3 in register A.
Reading register C clears this bit.
INTF - Interrupt Request Flag
7
6
-
5
-
4
-
3
-
2
-
1
-
0
-
INTF
This flag is set to a 1 when any of the following is true:
AIE = 1 and AF = 1
PIE = 1 and PF = 1
UIE = 1 and UF = 1
Reading register C clears this bit.
July 1996
10
bq3285EC/LC
Absolute Maximum Ratings—bq3285EC
Symbol
Parameter
Value
Unit
Conditions
VCC
DC voltage applied on VCC relative to VSS
-0.3 to 7.0
V
DC voltage applied on any pin excluding VCC
relative to VSS
VT
-0.3 to 7.0
V
VT ≤ VCC + 0.3
TOPR
TSTG
TBIAS
Operating temperature
Storage temperature
Temperature under bias
0 to +70
-55 to +125
-40 to +85
260
°C
°C
°C
°C
Commercial
TSOLDER Soldering temperature
For 10 seconds
Note:
Permanent device damage may occur if Absolu te Ma xim u m Ra tin gs are exceeded. Functional opera-
tion should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Expo-
sure to conditions beyond the operational limits for extended periods of time may affect device reliability.
Absolute Maximum Ratings—bq3285LC
Symbol
Parameter
Value
Unit
Conditions
VCC
DC voltage applied on VCC relative to VSS
-0.3 to 7.0
V
DC voltage applied on any pin excluding VCC
relative to VSS
VT
-0.3 to 7.0
V
V
T ≤ VCC + 0.3
TOPR
TSTG
TBIAS
Operating temperature
Storage temperature
Temperature under bias
0 to +70
-55 to +125
-40 to +85
260
°C
°C
°C
°C
Commercial
TSOLDER Soldering temperature
For 10 seconds
Note:
Permanent device damage may occur if Absolu te Ma xim u m Ra tin gs are exceeded. Functional opera-
tion should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Expo-
sure to conditions beyond the operational limits for extended periods of time may affect device reliability.
July 1996
11
bq3285EC/LC
Recommended DC Operating Conditions—bq3285EC (TA = TOPR
)
Symbol
VCC
Parameter
Supply voltage
Minimum
Typical
Maximum
Unit
V
4.5
0
5.0
5.5
VSS
VIL
VIH
VBC
Supply voltage
0
-
0
0.8
V
Input low voltage
Input high voltage
Backup cell voltage
-0.3
2.2
2.4
V
-
VCC + 0.3
4.0
V
-
V
Note:
Typical values indicate operation at TA = 25°C.
Recommended DC Operating Conditions—bq3285LC (TA = TOPR
)
Symbol
VCC
Parameter
Supply voltage
Minimum
Typical
Maximum
Unit
V
2.7
0
3.0
5.5
VSS
VIL
VIH
VBC
Supply voltage
0
-
0
0.6
V
Input low voltage
Input high voltage
Backup cell voltage
-0.3
2.2
2.4
V
-
VCC + 0.3
4.0
V
-
V
Note:
Typical values indicate operation at TA = 25°C.
Crystal Specifications—bq3285EC/LC (DT-26 or Equivalent)
Symbol
Parameter
Oscillation frequency
Minimum
Typical
Maximum
Unit
fO
-
32.768
-
kHz
pF
CL
TP
Load capacitance
-
6
-
30
Temperature turnover point
Parabolic curvature constant
Quality factor
20
25
°C
k
-
-
-0.042
-
ppm/°C
Q
40,000
70,000
R1
Series resistance
-
-
-
-
-
-
1.1
430
-
45
KΩ
C0
Shunt capacitance
Capacitance ratio
1.8
600
1
pF
C0/C1
DL
∆f/fO
Drive level
µW
Aging (first year at 25°C)
1
-
ppm
July 1996
12
bq3285EC/LC
DC Electrical Characteristics—bq3285EC (TA = TOPR, VCC = 5V )
Symbol
ILI
Parameter
Minimum Typical Maximum Unit
Conditions/Notes
Input leakage current
-
-
-
-
± 1
± 1
µA VIN = VSS to VCC
AD0–AD7 and INT in
µA high impedance,
VOUT = VSS to VCC
ILO
Output leakage current
VOH
VOL
Output high voltage
Output low voltage
2.4
-
-
-
-
V
V
IOH = -2.0 mA
IOL = 4.0 mA
0.4
Min. cycle, duty = 100%,
IOH = 0mA, IOL = 0mA
ICC
Operating supply current
Standby supply current
-
-
7
15
-
mA
VIN = VSS or VCC
,
ICCSB
300
µA
CS ≥ VCC - 0.2
VSO
Supply switch-over voltage
Battery operation current
Power-fail-detect voltage
Input current when RCL = VSS
-
VBC
-
V
ICCB
VPFD
IRCL
-
4.0
-
0.3
0.5
4.35
185
-185
0
µA VBC = 3V, TA = 25°C
V
4.17
.
-
-
-
µA Internal 30K pull-up
µA Internal 30K pull-down
µA Internal 30K pull-down
Input current when MOT = VCC
Input current when MOT = VSS
-
IMOTH
-
Input current when EXTRAM =
VCC
-
-
-
-
-185
0
µA Internal 30K pull-down
µA Internal 30K pull-down
IXTRAM
Input current when EXTRAM =
VSS
Note:
Typical values indicate operation at TA = 25°C, VCC = 5V or VBC = 3V.
July 1996
13
bq3285EC/LC
DC Electrical Characteristics—bq3285LC (TA = TOPR, VCC = 3V ± 10%)
Symbol
ILI
Parameter
Minimum Typical1 Maximum Unit
Conditions/Notes
Input leakage current
-
-
-
-
± 1
± 1
µA VIN = VSS to VCC
AD0–AD7 and INT in high
µA impedance,
ILO
Output leakage current
VOUT = VSS to VCC
VOH
VOL
Output high voltage
Output low voltage
2.2
-
-
-
-
V
V
IOH = -1.0 mA
0.4
IOL = 2.0 mA
Min. cycle, duty = 100%,
ICC
Operating supply current
Standby supply current
-
-
52
9
-
mA
IOH
= 0mA, IOL = 0mA
VIN = VSS or VCC
,
ICCSB
1003
µA
CS ≥ VCC - 0.2
-
-
VPFD
VBC
-
-
V
V
VBC > VPFD
VBC < VPFD
VSO
Supply switch-over voltage
Battery operation current
VBC = 3V, TA = 25°C,
VCC < VBC
ICCB
-
0.3
0.5
µA
VPFD
IRCL
Power-fail-detect voltage
2.4
2.53
2.65
120
-120
0
V
Input current when RCL = VSS
.
-
-
-
-
-
-
-
-
µA Internal 30K pull-up
µA Internal 30K pull-down
µA Internal 30K pull-down
µA Internal 30K pull-down
Input current when MOT = VCC
Input current when MOT = VSS
IMOTH
Input current when EXTRAM =
VCC
-120
IXTRAM
Input current when EXTRAM =
VSS
-
-
0
µA Internal 30K pull-down
Notes:
1. Typical values indicate operation at TA = 25°C, VCC = 3V.
2. 7mA at VCC = 5V
3. 300µA at VCC = 5V
July 1996
14
bq3285EC/LC
Capacitance—bq3285EC/LC (TA = 25°C, F = 1MHz, VCC = 5.0V)
Symbol
CI/O
Parameter
Input/output capacitance
Input capacitance
Minimum
Typical
Maximum
Unit
pF
Conditions
VOUT = 0V
-
-
-
-
7
5
CIN
pF
VIN = 0V
Note:
This parameter is sampled and not 100% tested. It does not include the X1 or X2 pin.
AC Test Conditions—bq3285EC
Parameter
Input pulse levels
Test Conditions
0 to 3.0 V
Input rise and fall times
5 ns
Input and output timing reference levels
Output load (including scope and jig)
1.5 V (unless otherwise specified)
See Figures 4 and 5
+5V
960
+5V
1.15k
For all outputs
except INT
INT
510
50pF
130pF
Figure 5. Output Load—bq3285EC
Figure 4. Output Load—bq3285EC
July 1996
15
bq3285EC/LC
AC Test Conditions—bq3285LC
Parameter
Input pulse levels
Test Conditions
0 to 2.3 V, VCC = 3V1
5 ns
Input rise and fall times
Input and output timing reference levels
Output load (including scope and jig)
1.2 V (unless otherwise specified)
See Figures 6 and 7
Note:
1. For 5V timing, please refer to bq3285EC.
+3.3V
+3.3V
1238
1.45k
For all outputs
except INT
INT
130pF
1164
50pF
Figure 6. Output Load—bq3285LC
Figure 7. Output Load B—bq3285LC
July 1996
16
bq3285EC/LC
Read/Write Timing—bq3285EC (TA = TOPR, VCC = 5V ± 10%)
Symbol
tCYC
tDSL
tDSH
tRWH
tRWS
tCS
Parameter
Minimum
Typical
Maximum
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Cycle time
160
80
55
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
DS low or RD/WR high time
DS high or RD/WR low time
R/W hold time
-
-
R/W setup time
10
5
-
Chip select setup time
Chip select hold time
Read data hold time
Write data hold time
Address setup time
Address hold time
-
tCH
0
-
tDHR
tDHW
tAS
0
25
-
0
20
5
-
tAH
-
tDAS
tASW
Delay time, DS to AS rise
Pulse width, AS high
10
30
-
-
Delay time, AS to DS rise (RD/WR
fall)
tASD
tOD
35
-
-
-
-
ns
ns
Output data delay time from DS rise
(RD fall)
50
tDW
tBUC
tPI
Write data setup time
30
-
-
244
-
-
-
-
-
ns
µs
-
Delay time before update cycle
Periodic interrupt time interval
Time of update cycle
-
See Table 3
tUC
-
1
µs
July 1996
17
bq3285EC/LC
Read/Write Timing—bq3285LC (TA = TOPR, VCC = 3V ± 10%)
Symbol
tCYC
tDSL
tDSH
tRWH
tRWS
tCS
Parameter
Minimum
Typical
Maximum
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Cycle time
270
135
90
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
DS low or RD/WR high time
DS high or RD/WR low time
R/W hold time
-
-
R/W setup time
15
8
-
Chip select setup time
Chip select hold time
Read data hold time
-
tCH
0
-
tDHR
tDHW
tAS
0
40
-
Write data hold time
Address setup time
0
30
15
15
50
55
-
tAH
Address hold time
-
tDAS
tASW
tASD
Delay time, DS to AS rise
Pulse width, AS high
Delay time, AS to DS rise (RD/WR fall)
-
-
-
Output data delay time from DS rise
(RD fall)
tOD
-
-
100
ns
tDW
tBUC
tPI
Write data setup time
50
-
-
244
-
-
-
-
-
ns
µs
-
Delay time before update cycle
Periodic interrupt time interval
Time of update cycle
-
See Table 3
tUC
-
1
µs
July 1996
18
bq3285EC/LC
Motorola Bus Read/Write Timing—bq3285EC/LC
July 1996
19
bq3285EC/LC
Intel Bus Read Timing—bq3285EC/LC
Intel Bus Write—bq3285EC/LC
July 1996
20
bq3285EC/LC
Power-Down/Power-Up Timing—bq3285EC (TA = TOPR
)
Symbol
Parameter
Minimum
300
Typical
Maximum
Unit
Conditions
tF
VCC slew from 4.5V to 0V
VCC slew from 0V to 4.5V
-
-
-
-
µs
µs
tR
100
Internal write-protection
tCSR
CS at VIH after power-up
20
-
200
ms
period after VCC passes VPFD
on power-up.
Ca u tion : Nega tive u n d er sh oots below th e a bsolu te m a xim u m r a tin g of -0.3V in ba tter y-ba ck u p m od e
m a y a ffect d a ta in tegr ity.
Power-Down/Power-Up Timing—bq3285EC
July 1996
21
bq3285EC/LC
Power-Down/Power-Up Timing—bq3285LC (TA = TOPR
)
Symbol
Parameter
Minimum
300
Typical
Maximum
Unit
µs
Conditions
tF
VCC slew from 2.7V to 0V
VCC slew from 0V to 2.7V
-
-
-
-
tR
100
µs
Internal write-protection
period after VCC passes VPFD
on power-up.
tCSR
CS at VIH after power-up
20
-
200
ms
Ca u tion : Nega tive u n d er sh oots below th e a bsolu te m a xim u m r a tin g of -0.3V in ba tter y-ba ck u p m od e
m a y a ffect d a ta in tegr ity.
Power-Down/Power-Up Timing—bq3285LC
July 1996
22
bq3285EC/LC
Interrupt Delay Timing—bq3285EC/LC (TA = TOPR
)
Symbol
tRSW
Parameter
Reset pulse width
Minimum
Typical
Maximum
Unit
µs
5
-
-
-
-
-
2
2
tIRR
INT release from RST
INT release from DS
µs
tIRD
-
µs
Interrupt Delay Timing—bq3285EC/LC
July 1996
23
bq3285EC/LC
24-Pin SOIC (S)
(
)
24-Pin S 0.300" SOIC
Inches
Millimeters
Min.
Max.
Min.
Max.
Dimension
B
e
A
A1
B
0.095
0.004
0.013
0.008
0.600
0.290
0.045
0.395
0.020
0.105
0.012
0.020
0.013
0.615
0.305
0.055
0.415
0.040
2.41
0.10
0.33
0.20
15.24
7.37
1.14
10.03
0.51
2.67
0.30
0.51
0.33
15.62
7.75
1.40
10.54
1.02
D
C
D
E
E
H
e
H
L
A
C
.004
A1
L
24-Pin SSOP (SS)
(
)
24-Pin SS 0.150" SSOP
Inches
Millimeters
Min.
0.061
0.004
0.008
0.007
0.337
0.150
Max.
0.068
0.010
0.012
0.010
0.344
0.157
Min.
1.55
0.10
0.20
0.18
8.56
3.81
Max.
1.73
0.25
0.30
0.25
8.74
3.99
Dimension
A
A1
B
C
D
E
e
.025 BSC
0.64 BSC
H
L
0.230
0.016
0.244
0.035
5.84
0.41
6.20
0.89
July 1996
24
bq3285EC/LC
Ordering Information
bq3285EC/LC
-
Tem p er a tu r e:
blank = Commercial (0 to +70°C)
Pa ck a ge Op tion :
SS= 24-pin SSOP (0.150)
Device:
bq3285EC Real-Time Clock with 242
bytes of general storage
or
bq3285LC Real-Time Clock with 242
bytes of general storage
(3V operation)
July 1996
25
IMPORTANT NOTICE
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TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
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Copyright 1999, Texas Instruments Incorporated
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