BR93LC56-W [ETC]
Microwire Serial EEPROM ; Microwire串行EEPROM\n
| 型号： | BR93LC56-W |
| 厂家： | 
ETC |
| 描述： | Microwire Serial EEPROM
|
| 文件： | 总11页 (文件大小：134K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
BR93LC56-W / BR93LC56F-W / BR93LC56RF-W
BR93LC56FJ-W / BR93LC56RFJ-W / BR93LC56FV-W
Memory ICs
128×16bits serial EEPROM
BR93LC56-W / BR93LC56F-W / BR93LC56RF-W /
BR93LC56FJ-W / BR93LC56RFJ-W / BR93LC56FV-W
The BR93LC56-W series are CMOS serial input / output-type memory circuits (EEPROMs) that can be programmed
electrically. Each is configured of 128 words x 16 bits (2,048 bits), and each word can be accessed individually and data
read from it and written to it. Operation control is performed using five types of commands.
The commands, addresses, and data are input through the DI pin under the control of the CS and SK pins. In a write
operation, the internal status signal (READY or BUSY) can be output from the DO pin.
!Applications
VCRs, TVs, printers, car stereos, cordless telephones, short wave radios, programmable DIP switches, and
other battery-powered equipment requiring low voltage and low current
!Features
6) A write instruction inhibit function allows :
- write protection when power supply voltage is low.
- write disable state at power up.
1) 128 words × 16 bits EEPROM
2) Operating voltage range
When reading : 2.0 to 5.5V
When writing : 2.7 to 5.5V
- writing using command codes.
3) Low current consumption
7) Compact packages
Operating (at 5V) : 3mA (Max.)
Standby (at 5V) : 5µA (Max.)
8) Display of READY / BUSY status
9) TTL-compatible input / output
4) Address can be incremented automatically during
read operations.
10) Rewriting possible up to 100,000 times
11) Data can be stored for ten years without corruption.
5) Auto erase and auto complete functions can be used
during write operations.
!Block diagram
Power supply
CS
voltage detector
Command decode
Control
Clock generation
SK
High voltage
generator
Write
disable
Address
Address
decoder
7bits
Command
buffer
7bits
DI
register
2,048-bits
EEPROM array
Data
R / W
16bits
16bits
register
amplifier
DO
Dummy bits
BR93LC56-W / BR93LC56F-W / BR93LC56RF-W
BR93LC56FJ-W / BR93LC56RFJ-W / BR93LC56FV-W
Memory ICs
!Pin descriptions
CS
SK
DI
V
CC
N.C.
N.C.
GND
DO
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
N.C.
N.C.
GND
VCC
BR93LC56-W
BR93LC56RF-W
BR93LC56RFJ-W
BR93LC56F-W
BR93LC56FJ-W
BR93LC56FV-W
CS
SK
DO
DI
Fig.1
Fig.2
Pin No.
Pin
name
BR93LC56-W
BR93LC56RF-W
BR93LC56RFJ-W
BR93LC56F-W
BR93LC56FJ-W
BR93LC56FV-W
Function
1
2
3
4
5
6
7
8
3
4
5
6
7
8
1
2
CS
SK
Chip select input
Serial clock input
Start bit, operating code, address, and serial data input
DI
DO
GND
N.C.
Serial data output, READY / BUSY internal status display output
Ground
Not connected
N.C. Not connected
Power supply
V
CC
!Absolute maximum ratings (Ta = 25°C)
Parameter
Symbol
Limits
Unit
V
Applied voltage
VCC
−0.3~+6.5
1
∗
BR93LC56-W
Power
dissipation
500
2
∗
BR93LC56F-W / RF-W / FJ-W / RFJ-W
BR93LC56FV-W
Pd
mW
350
3
∗
300
Storage temperature
Operating temperature
Terminal voltage
Tstg
Topr
−
−65~+125
−40~+85
°C
°C
V
−0.3~VCC+0.3
∗1 Reduced by 5.0mW for each increase in Ta of 1°C over 25°C.
∗2 Reduced by 3.5mW for each increase in Ta of 1°C over 25°C.
∗3 Reduced by 3.0mW for each increase in Ta of 1°C over 25°C.
!Electrical characteristics (Ta = 25°C)
Parameter
Symbol
Min.
2.7
2.0
0
Typ.
Max.
5.5
Unit
V
Writing
−
−
−
Power supply
V
CC
voltage
5.5
V
Reading
Input voltage
V
IN
V
CC
V
BR93LC56-W / BR93LC56F-W / BR93LC56RF-W
BR93LC56FJ-W / BR93LC56RFJ-W / BR93LC56FV-W
Memory ICs
!Electrical characteristic curves
For 5V operation (unless otherwise noted, Ta = −40 to + 85°C, VCC = 5.0V 10%)
Parameter
Input low level voltage
Input high level voltage
Output low level voltage 1
Output high level voltage 1
Output low level voltage 2
Output high level voltage 2
Input leakage current
Output leakage current
Operating current
Symbol
Min.
−0.3
2.0
Typ.
Max.
Unit
Conditions
Measurement circuit
V
IL
IH
OL1
OH1
OL2
OH2
−
0.8
V
−
−
−
V
−
V
CC+0.3
V
−
V
−
−
0.4
−
V
I
I
I
I
OL=2.1mA
Fig.3
Fig.4
Fig.3
Fig.4
Fig.5
Fig.6
V
2.4
−
V
OH=−0.4mA
OL=10µA
V
−
−
0.2
−
V
V
V
CC−0.4
−1.0
−1.0
−
V
OH=−10µA
I
LI
−
1.0
1.0
µA
µA
V
V
V
IN=0V
OUT=0V
IN=VIH / VIL, DO=OPEN,
~VCC
I
LO
−
~VCC, CS=GND
I
CC1
−
1.5
3.0
mA
Fig.7
dissipation 1
f=1MHz, WRITE
IN=VIH / VIL, DO=OPEN,
Operating current
V
I
CC2
−
−
0.7
1.0
1.5
5.0
mA
Fig.7
Fig.8
dissipation 2
f=1MHz, READ
Standby current
I
SB
µA
CS=SK=DI=GND, DO=OPEN
For 3V operation (unless otherwise noted, Ta = −40 to + 85°C, VCC = 3.0V 10%)
Parameter
Input low level voltage
Input high level voltage
Output low level voltage
Output high level voltage
Input leakage current
Output leakage current
Operating current
Symbol
Min.
Typ.
Max.
Unit
Conditions
Measurement circuit
V
IL
IH
OL
−0.3
−
−
−
−
−
−
0.15×VCC
V
−
−
−
V
0.7×V
CC
V
CC+0.3
V
−
V
−
0.2
−
V
I
I
OL=10µA
OH=−10µA
Fig.3
Fig.4
Fig.5
Fig.6
V
OH
LI
V
CC−0.4
−1.0
V
I
1.0
1.0
µA
µA
V
V
V
IN=0V~VCC
ILO
−1.0
OUT=0V~VCC, CS=GND
IN=VIH / VIL, DO=OPEN,
I
CC1
−
0.5
2.0
mA
Fig.7
f=250kHz, WRITE
dissipation 1
Operating current
V
IN=VIH / VIL, DO=OPEN,
I
CC2
−
−
0.2
0.4
1.0
3.0
mA
Fig.7
Fig.8
f=250kHz, READ
dissipation 2
Standby current
I
SB
µA
CS=SK=DI=GND, DO=OPEN
For 2V operation (unless otherwise noted, Ta = −40 to + 85°C, VCC = 2.0V)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Conditions
Measurement circuit
Input low level voltage
Input high level voltage
Output low level voltage
Output high level voltage
Input leakage current
Output leakage current
Operating current
V
IL
IH
OL
−0.3
−
−
−
−
−
−
0.15
×
V
CC
V
−
−
−
V
0.7×
V
CC
V
CC+
0.3
V
−
V
−
0.2
−
V
I
I
OL=10µA
OH=−10µA
Fig.3
Fig.4
Fig.5
Fig.6
VOH
V
CC−0.4
−1.0
V
I
LI
1.0
1.0
µA
µA
V
IN=0V
OUT=0V
IN=VIH / VIL, DO=OPEN,
~VCC
V
~VCC, CS=GND
I
LO
−1.0
V
I
CC2
−
−
0.2
0.4
1.0
3.0
mA
Fig.7
Fig.8
dissipation 2
f=200kHz, READ
Standby current
I
SB
µA
CS=SK=DI=GND, DO=OPEN
BR93LC56-W / BR93LC56F-W / BR93LC56RF-W
BR93LC56FJ-W / BR93LC56RFJ-W / BR93LC56FV-W
Memory ICs
!Measurement circuits
V
CC
V
CC
V
V
CC
CC
V
CC
V
CC
I
OL
IOH
I
LI
DO
DO
CS,SK,DI
A
GND
GND
V
V
OL
V
VOH
V
IN = O~VCC
GND
Control output to "HIGH"
Control output to "LOW"
Fig.3 "LOW" output voltage circuit
Fig.4 "HIGH" output voltage circuit
Fig.5 Input leak current circuit
V
V
CC
CC
V
CC
VCC
A
I
CC
A
I
SB
I
OL
A
V
CC
CS
DO
VCC
CS
SK
DI
CS
SK
f
SK=1MHz / 250kHz / 200kHz
IN=VIH / VIL
WRITE / READ INPUT
V
DO
OPEN
VO=O~VCC
GND
DO
OPEN
DI
GND
GND
Fig.6 Output leak current circuit
Fig.7 Supply current circuit
Fig.8 Standby current circuit
!Circuit operation
(1) Command mode
With these ICs, commands are not recognized or acted upon until the start bit is received. The start bit is taken as
the first “1” that is received after the CS pin rises.
Start Operating
Command
Address
Data
bit
code
1
∗
Read (READ)
1
10
0A6~A0
11XXXXXX
0A6~A0
−
−
Write enabled (WEN)
1
00
2
∗
Write (WRITE)
1
01
D15~D0
2
∗
Write all addresses (WRAL)
Write disabled (WDS)
1
00
01XXXXXX D15~D0
1
00
00XXXXXX
0A6~A0
−
−
−
3
∗
Erase (ERASE)
1
11
3
∗
1
00
10XXXXXX
Chip erase (ERAL)
X: Either VIH or VIL
∗1 After setting of the read command and input of the SK clock, data corresponding to the specified address is
output, with data corresponding to upper addresses then output in sequence. (Auto increment function)
∗2 When the write or write all addresses command is executed, all data in the selected memory cell is
erased automatically, and the input data is written to the cell.
∗3 These modes are optional modes. Please contact Rohm for information on operation timing.
BR93LC56-W / BR93LC56F-W / BR93LC56RF-W
BR93LC56FJ-W / BR93LC56RFJ-W / BR93LC56FV-W
Memory ICs
(2) Operation timing characteristics
For 5V operation (unless otherwise noted, Ta = −40 to + 85°C, VCC = 5.0V 10%)
Parameter
Symbol Min.
Typ.
Max.
Unit
MHz
ns
f
SK
SKH
SKL
CS
CSS
DIS
CSH
−
450
450
450
50
100
0
−
1
SK clock frequency
t
−
−
SK "HIGH" time
t
−
−
ns
SK "LOW" time
t
−
−
ns
CS "LOW" time
t
−
−
ns
CS setup time
t
−
−
ns
DI setup time
t
−
−
ns
CS hold time
t
DIH
PD1
PD0
100
−
−
−
ns
DI hold time
Data "1" output delay time
Data "0" output delay time
Time from CS to output confirmation
Time from CS to output High impedance
Write cycle time
t
t
−
500
500
500
100
10
ns
−
−
ns
t
SV
DF
−
−
ns
t
−
−
ns
t
E / W
−
−
ms
For low voltage operation (unless otherwise noted, Ta = −40 to + 85°C, VCC = 3.0V 10%)
Parameter
Symbol Min.
Typ.
Max.
250
−
Unit
kHz
µs
SK clock frequency
f
SK
SKH
SKL
CS
CSS
DIS
CSH
−
1
−
SK "HIGH" time
t
−
SK "LOW" time
t
1
−
−
µs
CS "LOW" time
t
1
−
−
µs
CS setup time
t
200
400
0
−
−
ns
DI setup time
t
−
−
ns
CS hold time
t
−
−
ns
DI hold time
t
DIH
PD1
PD0
400
−
−
−
ns
Data "1" output delay time
Data "0" output delay time
Time from CS to output confirmation
Time from CS to output High impedance
Write cycle time
t
t
−
2
µs
µs
µs
ns
−
−
2
t
SV
DF
−
−
2
t
−
−
400
25
t
E / W
−
−
ms
When reading at low voltage (unless otherwise noted, Ta = −40 to + 85°C, VCC = 2.0V)
Parameter
Symbol Min.
Typ.
Max.
Unit
kHz
µs
µs
µs
ns
f
SK
SKH
SKL
CS
CSS
DIS
CSH
−
2
−
200
−
SK clock frequency
t
−
SK "HIGH" time
t
2
−
−
SK "LOW" time
CS "LOW" time
t
2
−
−
CS setup time
t
400
800
0
−
−
DI setup time
t
−
−
ns
CS hold time
t
−
−
ns
DI hold time
t
DIH
PD1
PD0
800
−
−
−
ns
Data "1" output delay time
Data "0" output delay time
Time from CS to output High impedance
Not designed for radioactive rays.
t
t
−
4
µs
µs
ns
−
−
4
t
DF
−
−
800
BR93LC56-W / BR93LC56F-W / BR93LC56RF-W
BR93LC56FJ-W / BR93LC56RFJ-W / BR93LC56FV-W
Memory ICs
!Timing chart
CS
t
t
CSS
t
SKH
tSKL
t
CSH
SK
DI
DIS
tDIH
t
PD0
t
PD1
t
t
DF
DF
DO (READ)
STATUS VALID
DO (WRITE)
·
·
·
Data is acquired from DI in synchronization with the SK rise.
During a reading operation, data is output from DO in synchronization with the SK rise.
During a writing operation, a Status Valid (READY or BUSY) is valid from the time CS is HIGH until time tCS after CS falls following the input of a write
command and before the output of the next command start bit. Also, DO must be in a HIGH-Z state when CS is LOW.
·
After the completion of each mode, make sure that CS is set to LOW, to reset the internal circuit, before changing modes.
Fig.9 Synchronized data timing
(4) Reading (Fig.10)
When the read command is acknowledged, the data (16 bits) for the input address is output serially. The data is
synchronized with the SK rise during A0 acquisition and a “0” (dummy bit) is output. All further data is output in
synchronization with the SK pulse rises.
CS
1
∗
1
2
4
0
11
A0
12
27 28
SK
DI
1
1
0
A6
A5
A1
2
∗
D15 D14
D1 D0 D15 D14
DO
0
High-Z
∗1 If the first data input following the rise of the start bit CS is "1", the start bit is acknowledged. Also, if a "1" is input following several zeroes in succession, the "1" is
recognized as the start bit, and subsequent operation commences. This applies also to all commands described subsequently.
∗2 Address auto increment function: These ICs are equipped with an address auto increment function which is effective only during reading operations. With this
function, if the SK clock is input following execution of one of the above reading commands, data is read from upper addresses in succession. CS is held in HIGH
state during automatic incrementing.
Fig.10 Read cycle timing (READ)
BR93LC56-W / BR93LC56F-W / BR93LC56RF-W
BR93LC56FJ-W / BR93LC56RFJ-W / BR93LC56FV-W
Memory ICs
(5) Write enable (Fig.11)
These ICs are set to the write disabled state by the internal reset circuit when the power is turned on. Therefore,
before performing a write command, the write enable command must be executed. When this command is
executed, it remains valid until a write disable command is issued or the power supply is cut off. However, read
commands can be used in either the write enable or write disable state.
CS
SK
DI
1
0
0
1
1
DO
High-Z
Fig.11 Write enable cycle timing
(6) Write (Fig.12)
This command writes the input 16 bits data (D15 to D0) to the specified address (A6 to A0). Actual writing of the data
begins after CS falls (following the 27th clock pulse after the start bit input), and D0 is in the Acquire state.
STATUS is not detected if CS = LOW after the time tE / W. When STATUS is detected (CS = HIGH), no commands are
accepted while DO is LOW (BUSY). Therefore, no commands should be input during this period.
CS
t
CS
STATUS
1
2
0
4
0
11
12
27
SK
DI
A6 A5
A1 A0 D15 D14
D1
D0
1
1
t
SV
DO
BUSY READY
High-Z
t
E / W
Fig.12 Write cycle timing (WRITE)
(STATUS)
After time tCS following the fall of CS, after input of the write command), if CS is set to HIGH, the write execute = BUSY
(LOW) and the command wait status READY (HIGH) are output.
If in the command wait status (STATUS = READY), the next command can be performed within the time tE / W. Thus, if
data is input via SK and DI with CS = HIGH in the tE / W period, erroneous operations may be performed. To avoid this,
make sure that DI = LOW when CS = HIGH. (Caution is especially important when common input ports are used.) This
applies to all of the write commands.
BR93LC56-W / BR93LC56F-W / BR93LC56RF-W
BR93LC56FJ-W / BR93LC56RFJ-W / BR93LC56FV-W
Memory ICs
(7) All address write (Fig.13)
With this command, the input 16 bits data is written simultaneously to all of the addresses (128 words). Rather than
writing one word at a time, in succession, data is written all at one time, enabling a write time of tE / W.
CS
STATUS
t
CS
1
2
5
12
27
SK
DI
D0
D15 D14
D1
1
0
0
0
1
t
SV
DO
BUSY READY
High-Z
t
E / W
Fig.13 Write all address cycle timing (WRAL)
(8) Write disable (Fig.14)
When the power supply is turned on, the IC enters the write disable status. Similarly, when the write disable command
is issued, the IC enters the same status. When in this status, all write commands are ignored, but read commands
may be executed.
In the write enable status, writing begins even if a write command is entered accidentally. To prevent errors of this type,
we recommend executing a write disable command after writing has been completed.
CS
SK
DI
1
0
0
0
0
DO
High-Z
Fig.14 Write disable cycle timing (WDS)
!Operation notes
(1) Cancelling modes
〈READ〉
Operating code
2 bits
Start bit
1 bit
Address
8 bits
Data
16 bits
Cancel can be performed for the entire read mode space
Cancellation method: CS LOW
〈WRITE, WRAL〉
Operating code
2 bits
Address
8 bits
tE / W
Start bit
1 bit
Data
16 bits
a
b
a: Canceled by setting CS LOW or VCC OFF (∗)
b: Cannot be canceled by any method. If VCC is set to OFF during this time, the data
in the designated address is not secured.
∗: VCC OFF (VCC is turned off after CS is set to LOW)
Fig.15
BR93LC56-W / BR93LC56F-W / BR93LC56RF-W
BR93LC56FJ-W / BR93LC56RFJ-W / BR93LC56FV-W
Memory ICs
(2) Timing in the standby mode
As shown in Fig.16, during standby, if CS rises when SK is HIGH, the DI state may be read on the rising edge. If this
happens, and DI is HIGH, this is taken to be the start bit, causing a bit error (see point “a” in Fig.16).
Make sure all inputs are LOW during standby or when turning the power supply on or off (see Fig.17).
Point a: Start bit position during erroneous operation
Point b: Timing during normal operation
SK
CS
DI
SK
CS
DI
0
1
0
1
b
a
b
Fig.16 Erroneous operation timing
Fig.17 Normal operation timing
(3) Precautions when turning power on and off
When turning the power supply on and off, make sure CS is set to LOW (see Fig.18).
When CS is HIGH, the EEPROM enters the active state. To avoid this, make sure CS is set to LOW (disable mode)
when turning on the power supply. (When CS is LOW, all input is cancelled.)
When the power supply is turned off, the low power state can continue for a long time because of the capacity of the
power supply line. Erroneous operations and erroneous writing can occur at such times for the same reasons as
described above. To avoid this, make sure CS is set to LOW before turning off the power supply.
To prevent erroneous writing, these ICs are equipped with a POR (Power On Reset) circuit, but in order to achieve
operation at a low power supply, VCC is set to operate at approximately 1.3V. After the POR has been activated,
writing is disabled, but if CS is set to HIGH, writing may be enabled because of noise or other factors. However, the
POR circuit is effective only when the power supply is on, and will not operate when the power is off.
Also, to prevent erroneous writing at low voltages, these ICs are equipped with a built-in circuit (VCC-lockout circuit)
which resets the write command if VCC drops to approximately 2V or lower (typ.) (∗).
+ 5V
VCC
GND
+ 5V
CS
GND
Bad example
Good example
(Bad example) Here, the CS pin is pulled up to VCC. In this case, CS is HIGH
(active state). Please be aware that the EEPROM may perform
erroneous operations or write erroneous data because of noise
or other factors. This can occur even if the CS input is high-Z.
(Good example) In this case, CS is LOW when the power supply is turned on or off.
Fig.18
(4) Clock (SK) rise conditions
If the clock pin (SK) signal of the BR93LC56-W has a long rise time (tr) and if noise on the signal line exceeds a
certain level, erroneous operation can occur due to erroneous counts in the clock. To prevent this, a Schmitt trigger is
built into the SK input of the BR93LC56-W. The hysteresis amplitude of this circuit is set to approximately 0.2V, so if
the noise exceeds the SK input, the noise amplitude should be set to 0.2VP-P or lower. Furthermore, rises and falls in
the clock input should be accelerated as much as possible.
BR93LC56-W / BR93LC56F-W / BR93LC56RF-W
BR93LC56FJ-W / BR93LC56RFJ-W / BR93LC56FV-W
Memory ICs
(5) Power supply noise
The BR93LC56-W discharge high volumes of high voltage when a write is completed. The power supply may
fluctuate at such times. Therefore, make sure a capacitor of 1000pF or greater is connected between VCC (Pin 8) and
GND (Pin 5).
(6) Connecting DI and DO directly
The BR93LC56-W have an independent input pin (DI) and output pin (DO). These are treated as individual signals
on the timing chart but can be controlled through one control line. Control can be initiated on a single control line by
inserting a resistor R.
µ-COM
BR93LC56
I / O PORT
DI
R
DO
Fig.19 Common connections for
the DI and DO control line
1) Data collision between the µ-COM output and the DO output
Within the input and output timing of the BR93LC56-W the drive from the µ-COM output to the DI input and a signal
output from the DO output can be emitted at the same time. This happens only for the 1 clock cycle (a dummy bit
“0” is output to the DO pin) which acquires the A0 address data during a read cycle.
When the address data A0 = 1, the µ-COM output becomes a direct current source for the DO pin. The resistor R
is the only resistance which limits this current. Therefore, a resistor with a value which satisfies the µ-COM and the
BR93LC56-W current capacity is required. When using a single control line, when a dummy bit “0” is output to the
DO, the µ-COM I / O address data A0 is also output. Therefore, the dummy bit cannot be detected.
2) Feedback to the DI input from the DO output
Data is output from the DO pin and then feeds back into the DI input through the resistor R. This happens when:
•
DO data is output during a read operation
A READY / BUSY signal is output during WRITE or WRAL operation
•
Such feedback does not cause problems in the basic operation of the BR93LC56-W.
The µ-COM input level must be adequately maintained for the voltage drop at R which is caused by the total input
leakage current for the µ-COM and the BR93LC56-W. In the state in which SK is input, when the READY / BUSY
function is used, make sure that CS is dropped to LOW within four clock pulses of the output of the READY signal
HIGH and the standby mode is restored. For input after the fifth clock pulse, the READY HIGH will be taken as the
start bit and WDS or some other mode will be activated, depending on the DI state.
BR93LC56-W / BR93LC56F-W / BR93LC56RF-W
BR93LC56FJ-W / BR93LC56RFJ-W / BR93LC56FV-W
Memory ICs
!External dimensions (Units : mm)
BR93LC56-W
BR93LC56F-W / RF-W
9.3 0.3
8
5
5.0 0.2
8
5
1
4
7.62
1
4
1.27 0.4 0.1
0.3Min.
0.15
2.54
0.5 0.1
0° ~ 15°
DIP8
SOP8
BR93LC56FJ-W / RFJ-W
BR93LC56FV-W
4.9 0.2
3.0 0.2
8
7
6
5
8
5
1
2
3
4
1
4
0.22 0.1
0.65
0.45Min.
0.3Min.
(0.52)
1.27
0.42 0.1
0.1
0.1
SOP-J8
SSOP-B8
相关型号：
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