BS616LV1623 [ETC]
Very Low Power/Voltage CMOS SRAM 1M x 16 or 2M x 8 bit switchable; 非常低的功率/电压CMOS SRAM 1M ×16或2M ×8位切换
| 型号： | BS616LV1623 |
| 厂家： | 
ETC |
| 描述： | Very Low Power/Voltage CMOS SRAM 1M x 16 or 2M x 8 bit switchable |
| 文件： | 总10页 (文件大小：258K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Very Low Power/Voltage CMOS SRAM
1M x 16 or 2M x 8 bit switchable
BSI
BS616LV1623
FEATURES
DESCRIPTION
• Vcc operation voltage : 2.7 ~ 3.6V
• Very low power consumption :
The BS616LV1623 is a high performance, very low power CMOS Static
Random Access Memory organized as 1,048,676 words by 16 bits or
2,097,152 bytes by 8 bits selectable by CIO pin and operates in a Vcc
range of 2.7V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current
of 3.0uA at 3.0V/25oC and maximum access time of 55ns at 3.0V/85oC .
This device provide three control inputs and three states output drivers
for easy memory expansion.
Vcc = 3.0V C-grade: 45mA (@55ns) operating current
I -grade: 46mA (@55ns) operating current
C-grade: 36mA (@70ns) operating current
I -grade: 37mA (@70ns) operating current
3.0uA (Typ.) CMOS standby current
• High speed access time :
-55
-70
55ns
70ns
The BS616LV1623 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS616LV1623 is available in 48-pin 12mmx20mm TSOP1 package.
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE1, CE2 and OE options
• I/O Configuration x8/x16 selectable by CIO, LB and UB pin
PRODUCT FAMILY
POWER DISSIPATION
SPEED
(ns)
STANDBY
Operating
OPERATING
TEMPERATURE
Vcc
RANGE
(ICCSB1, Max)
(ICC, Max)
PRODUCT FAMILY
PKG TYPE
55ns : 3.0~3.6V
70ns : 2.7~3.6V
Vcc=3V
Vcc=3V
70ns
Vcc=3V
10
55ns
BS616LV1623TC
BS616LV1623TI
+0 O C to +70O
-40O C to +85O
C
C
2.7V ~ 3.6V
2.7V ~ 3.6V
55 / 70
55 / 70
45mA
36mA TSOP1-48(12mmx20mm)
uA
20 uA
37mA
46mA
TSOP1-48(12mmx20mm)
BLOCK DIAGRAM
PIN CONFIGURATIONS
A19
A15
A14
A13
A4
A3
A2
A1
A0
1
48
47
46
A5
A6
A7
A12
A11
A10
A9
Address
Input
/OE
/UB
/LB
CE2
SAE
D15
D14
D13
D12
Vss
Vcc
D11
D10
D9
24
4096
Row
Decoder
Memory Array
4096 x 4096
/CE1
D0
Buffer
A8
A17
A7
D1
D2
D3
Vcc
CIO
Vss
9
10
A6
4096
37
BS616LV1623TC
BS616LV1623T I
Data
Input
13
16(8)
16(8)
Column I/O
D4
D5
D0
Buffer
.
.
.
.
.
.
.
.
Write Driver
Sense Amp
16
17
D6
D7
A19
16(8)
16(8)
D8
A8
256(512)
Data
Output
Buffer
/WE
A18
A17
A16
A9
Column Decoder
D15
A10
A11
A12
A13
27
25
CE1
CE2
A15
A14
16(18)
24
WE
OE
UB
Control
Address Input Buffer
LB
A16 A0 A1 A2 A3
A5
A18(SAE)
A4
CIO
48-pin 12mmx20mm TSOP1 top view
Vdd
Vss
Brilliance Semiconductor, Inc. reserves the right to modify document contents without notice.
Revision 1.1
Jan. 2004
R0201-BS616LV1623
1
BSI
BS616LV1623
PIN DESCRIPTIONS
Name
Function
A0-A19 Address Input
These 20 address inputs select one of the 1,048,576 x 16-bit words in the RAM.
SAE Address Input
This address input incorporates with the above 20 address inputs select one of the
2,097,152 x 8-bit bytes in the RAM if the CIO is LOW. Don't use when CIO is HIGH.
CIO x8/x16 select input
This input selects the organization of the SRAM. 1,048,576
x 16-bit words
configuration is selected if CIO is HIGH. 2,097,152 x 8-bit bytes configuration is
selected if CIO is LOW.
CE1 Chip Enable 1 Input
CE2 Chip Enable 2 Input
CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when
data read from or write to the device. If either chip enable is not active, the device is
deselected and is in a standby power mode. The DQ pins will be in the high
impedance state when the device is deselected.
WE Write Enable Input
OE Output Enable Input
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
Lower byte and upper byte data input/output control pins. The chip is deselected when
both LB and UB pins are HIGH.
LB and UB Data Byte Control Input
D0 - D15 Data Input/Output Ports
These 16 bi-directional ports are used to read data from or write data into the RAM.
Vcc
Power Supply
Ground
Gnd
Revision 1.1
Jan. 2004
R0201-BS616LV1623
2
BSI
BS616LV1623
TRUTH TABLE
MODE
CE1 CE2
OE
WE
CIO
LB
UB
SAE
D0~7
D8~15
High-Z
VCC Current
H
X
L
X
L
X
X
X
L
H
L
L
H
L
X
X
X
H
L
L
H
L
L
Fully Standby
Output Disable
X
H
X
H
X
X
X
X
High-Z
ICCSB, ICCSB1
H
High-Z
Dout
High-Z
Dout
Din
High-Z
High-Z
Dout
Dout
X
ICC
Read from SRAM
( WORD mode )
L
L
H
H
L
X
H
L
H
H
X
X
ICC
Write to SRAM
( WORD mode )
ICC
X
Din
Din
Din
Read from SRAM
( BYTE Mode )
L
L
H
H
L
X
H
L
L
L
X
X
X
X
A-1
A-1
Dout
Din
High-Z
X
ICC
Write to SRAM
( BYTE Mode )
ICC
ABSOLUTE MAXIMUM RATINGS(1)
OPERATING RANGE
SYMBOL
PARAMETER
Terminal Voltage with
Respect to GND
RATING
-0.5 to
UNITS
AMBIENT
TEMPERATURE
0 O C to +70 O
RANGE
Vcc
V
TERM
V
BIAS
T
STG
T
T
P
Vcc+0.5
O C
O C
W
Commercial
Industrial
C
2.7V ~ 3.6V
2.7V ~ 3.6V
Temperature Under Bias
Storage Temperature
Power Dissipation
-40 to +85
-60 to +150
1.0
-40 O C to +85O
C
DC Output Current
20
mA
CAPACITANCE (1) (TA = 25oC, f = 1.0 MHz)
OUT
I
PARAMETER CONDITIONS MAX.
UNIT
SYMBOL
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
Input
10
12
CIN
VIN=0V
pF
Capacitance
Input/Output
Capacitance
DQ
I/O
=0V
C
V
pF
1. This parameter is guaranteed and not 100% tested.
Revision 1.1
Jan. 2004
R0201-BS616LV1623
3
BSI
BS616LV1623
DC ELECTRICAL CHARACTERISTICS ( TA = -40oC to + 85oC )
PARAMETER
(1)
UNITS
PARAMETER
TEST CONDITIONS
MIN. TYP.
MAX.
0.8
NAME
Guaranteed Input Low
--
--
--
--
-0.5
2.0
--
Vcc=3V
Vcc=3V
VIL
V
(3)
Voltage
Guaranteed Input High
VIH
IIL
Vcc+0.3
V
(3)
Voltage
IN
Input Leakage Current
Output Leakage Current
Vcc = Max, V = 0V to Vcc
1
1
uA
uA
ViL, or
Vcc = Max, CE1 = VIH, or CE2 =
ILO
--
IH
I/O
OE = V , V = 0V to Vcc
Vcc=3V
Vcc=3V
--
VOL
VOH
--
--
OL
Output Low Voltage
Output High Voltage
Vcc = Max, I = 2mA
0.4
--
V
V
OH
Vcc = Min, I = -1mA
2.4
(4)
55ns
70ns
--
--
--
--
46
37
IL
Operating Power Supply CE1 = V and CE2 =
Current
V
IH
ICC
Vcc=3V
Vcc=3V
mA
mA
(2)
DQ
, I = 0mA, F =Fmax
CE1 = VIH or CE2 =V
, I = 0mA
IL
--
--
ICCSB
Standby Current-TTL
1.3
DQ
≧
CE1 Vcc-0.2V, or
(5)
Vcc=3V
≧
--
ICCSB1
≦
Vcc - 0.2V
Standby Current-CMOS
CE2 0.2V, VIN
3
20
uA
≦
or VIN 0.2V
1. Typical characteristics are at TA = 25oC.
2. Fmax = 1/tRC .
3. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
4. Icc_Max. is 45mA(@55ns) / 36mA(@70ns) during 0~70oC operation.
5. IccsB1 is 10uA at Vcc=3.0V and TA=70oC.
Revision 1.1
R0201-BS616LV1623
4
Jan.
2004
BSI
BS616LV1623
DATA RETENTION CHARACTERISTICS ( TA = -40oC to +85oC )
SYMBOL
PARAMETER
TEST CONDITIONS
MIN.
TYP.(1)
MAX.
UNITS
CE1 ≧ Vcc - 0.2V or CE2 ≦ 0.2V or
LB ≧ Vcc - 0.2V and UB ≧ Vcc - 0.2V
VIN ≧ Vcc - 0.2V or VIN ≦ 0.2V
V
VDR
Vcc for Data Retention
1.5
--
--
CE1 ≧ Vcc - 0.2V or CE2 ≦ 0.2V or
LB ≧ Vcc - 0.2V and UB ≧ Vcc - 0.2V
VIN ≧ Vcc - 0.2V or VIN ≦ 0.2V
(3)
ICCDR
Data Retention Current
--
0
1.5
5
uA
Chip Deselect to Data
Retention Time
tCDR
--
--
--
--
ns
ns
See Retention Waveform
(2)
tR
Operation Recovery Time
TRC
1. Vcc = 1.5V, TA = + 25OC
2. tRC = Read Cycle Time
3. IccDR(Max.) is 2.5uA at TA=70OC.
LOW VCC DATA RETENTION WAVEFORM (1) ( CE1 Controlled )
Data Retention Mode
DR ≧ 1.5V
V
Vcc
Vcc
Vcc
CE1
t
R
t
CDR
CE1 ≧ Vcc - 0.2V
VIH
VIH
LOW VCC DATA RETENTION WAVEFORM (2) ( CE2 Controlled )
Data Retention Mode
DR ≧ 1.5V
V
Vcc
Vcc
Vcc
CE2
t
R
t
CDR
CE2 ≦ 0.2V
VIL
VIL
Revision 1.1
R0201-BS616LV1623
5
Jan.
2004
BSI
BS616LV1623
AC TEST CONDITIONS
KEY TO SWITCHING WAVEFORMS
(Test Load and Input/Output Reference)
WAVEFORM
INPUTS
OUTPUTS
Input Pulse Levels
Vcc / 0V
MUST BE
STEADY
MUST BE
STEADY
Input Rise and Fall Times
1V/ns
MAY CHANGE
FROM H TO L
WILL BE
CHANGE
FROM H TO L
Input and Output
Timing Reference Level
0.5Vcc
MAY CHANGE
FROM L TO H
WILL BE
CHANGE
FROM L TO H
Output Load
CL = 30pF+1TTL
CL = 100pF+1TTL
,
DON T CARE:
CHANGE :
STATE
UNKNOWN
ANY CHANGE
PERMITTED
DOES NOT
APPLY
CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
AC ELECTRICAL CHARACTERISTICS ( TA = -40oC to +85oC )
READ CYCLE
JEDEC
PARAMETER
NAME
CYCLE TIME : 70ns CYCLE TIME : 55ns
PARAMETER
DESCRIPTION
Read Cycle Time
Vcc = 2.7~3.6V
Vcc = 3.0~3.6V
UNIT
NAME
MIN. TYP. MAX.
MIN. TYP. MAX.
tAVAX
tRC
70
--
--
--
--
--
10
5
--
--
--
--
--
--
--
--
--
--
--
--
--
55
--
--
--
--
--
10
5
--
--
--
--
--
--
--
--
--
--
--
--
--
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAVQV
tELQV
tELQV
tBA
tAA
Address Access Time
70
70
70
35
35
--
55
55
55
30
30
--
tACS1
tACS2
(CE1)
(CE2)
Chip Select Access Time
Chip Select Access Time
(1)
tBA
(LB,UB)
Data Byte Control Access Time
Output Enable to Output Valid
Chip Select to Output Low Z
Data Byte Control to Output Low Z
Output Enable to Output in Low Z
Chip Deselect to Output in High Z
tGLQV
tELQX
tBE
tOE
tCLZ
tBE
(CE2,CE1)
(LB,UB)
--
--
tGLQX
tEHQZ
tBDO
tGHQZ
tOLZ
tCHZ
tBDO
tOHZ
5
--
5
--
(CE2,CE1)
--
--
--
35
35
30
--
--
--
30
30
25
Data Byte Control to Output High Z (LB,UB)
Output Disable to Output in High Z
t
t
AXOX
OH
Data Hold from Address Change
10
--
--
10
--
--
ns
NOTE :
1. tBA is 35ns/30ns (@speed=70ns/55ns) with address toggle .
tBA is 70ns/55ns (@speed=70ns/55ns) without address toggle .
R0201-BS616LV1623
Revision 1.1
Jan. 2004
6
BSI
BS616LV1623
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1 (1,2,4)
t
RC
ADDRESS
t
AA
t
OH
t
OH
D OUT
READ CYCLE2 (1,3,4)
CE2
t
t
ACS2
ACS1
CE1
(5)
CHZ
(5)
CLZ
t
t
D OUT
READ CYCLE3 (1,4)
ADDRESS
t
RC
t
AA
OE
t
OH
t
OE
CE2
CE1
t
ACS2
t
OLZ
(5)
t
ACS1
t
OHZ
(1,5)
CHZ
(5)
t
CLZ
t
LB,UB
t
BE
t
BDO
t
BA
D OUT
NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE1 = VIL and CE2 = VIH.
3. Address valid prior to or coincident with CE1 transition low and CE2 transition high.
4. OE = VIL .
5. The parameter is guaranteed but not 100% tested.
Revision 1.1
Jan. 2004
R0201-BS616LV1623
7
BSI
BS616LV1623
AC ELECTRICAL CHARACTERISTICS ( TA = -40oC to +85oC )
WRITE CYCLE
JEDEC
CYCLE TIME : 70ns CYCLE TIME : 55ns
PARAMETER
PARAMETER
NAME
DESCRIPTION
Write Cycle Time
Vcc = 3.0~3.6V
MIN. TYP. MAX.
UNIT
Vcc = 2.7~3.6V
MIN. TYP. MAX.
NAME
tAVAX
tE1LWH
tAVWL
tAVWH
tWLWH
tWHAX
tBW
tWC
tCW
tAS
70
--
--
--
--
--
--
--
--
--
--
--
--
--
55
55
0
--
--
--
--
--
--
--
--
--
--
--
--
--
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Select to End of Write
Address Setup Time
70
0
--
--
Address Valid to End of Write
Write Pulse Width
tAW
tWP
tWR
70
--
55
30
0
--
35
--
--
Write recovery Time
(CE2,CE1,WE)
0
--
--
(1)
Date Byte Control to End of Write
Write to Output in High Z
tBW
(LB,UB) 30
--
25
--
--
tWLQZ
tDVWH
tWHDX
tGHQZ
tWHZ
tDW
tDH
--
30
0
30
--
25
--
Data to Write Time Overlap
Data Hold from Write Time
Output Disable to Output in High Z
25
0
--
--
tOHZ
--
30
--
25
tWHOX
tOW
End of Write to Output Active
5
--
--
5
--
--
ns
NOTE :
1. tBW is 30ns/25ns (@speed=70ns/55ns) with address toggle. ; tBW is 70ns/55ns (@speed=70ns/55ns) without address toggle.
SWITCHING WAVEFORMS (WRITE CYCLE)
WRITE CYCLE1 (1)
t
WC
ADDRESS
OE
(3)
WR
t
(5)
(5)
CE2
CE1
(11)
CW
t
t
BW
(5)
LB,UB
t
AW
(3)
t
WP
(2)
t
AS
WE
(4,10)
t
OHZ
D OUT
t
DH
t
DW
D IN
Revision 1.1
Jan. 2004
R0201-BS616LV1623
8
BSI
BS616LV1623
WRITE CYCLE2 (1,6)
t
WC
ADDRESS
CE2
(11)
CW
t
(5)
(5)
CE1
t
BW
LB,UB
t
WR
t
AW
(3)
t
WP
(2)
WE
t
AS
(4,10)
WHZ
(7)
(8)
t
t
OW
D OUT
t
DW
(8,9)
t
DH
D IN
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE2, CE1 and WE low.
All signals must be active to initiate a write and any one signal can terminate
a write by going inactive. The data input setup and hold timing should be referenced to the
second transition edge of the signal that terminates the write.
3. TWR is measured from the earlier of CE2 going low, or CE1 or WE going high at the end of write cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite
phase to the outputs must not be applied.
5. If the CE2 high transition or CE1 low transition or LB,UB low transition occurs simultaneously with the WE low transitions
or after the WE transition, output remain in a high impedance state.
6. OE is continuously low (OE = VIL ).
7. DOUT is the same phase of write data of this write cycle.
8. DOUT is the read data of next address.
9. If CE2 is high or CE1 is low during this period, DQ pins are in the output state. Then the
data input signals of opposite phase to the outputs must not be applied to them.
10. The parameter is guaranteed but not 100% tested.
11. TCW is measured from the later of CE2 going high or CE1 going low to the end of write.
Revision 1.1
R0201-BS616LV1623
9
Jan.
2004
BSI
BS616LV1623
ORDERING INFORMATION
BS616LV1623 X X Z Y Y
SPEED
55: 55ns
70: 70ns
PKG MATERIAL
-: Normal
G: Green
P: Pb free
GRADE
C: +0oC ~ +70oC
I: -40oC ~ +85oC
PACKAGE
T : TSOP1-48(12mmx20mm)
Note:
BSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described herein. BSI does not authorize its products
for use as critical components in any application in which the failure of the BSI product may be expected to result in significant injury or death, including life-support
systems and critical medical instruments.
PACKAGE DIMENSIONS
TSOP1-48 (12mm x 20mm)
Revision 1.1
Jan. 2004
R0201-BS616LV1623
10
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