BT457KG80_技术文档

Bt457/Bt458

125 MHz/135 MHz/165 MHz Monolithic CMOS 256 Color Palette

RAMDAC

The Bt457 and Bt458 are pin- and software-compatible RAMDACs designed specifically Distinguishing Features

for high-performance, high-resolution color graphics. The architecture enables a display

of 1280 x 1024 bit-mapped color graphics (up to 8 bits per pixel plus up to 2 bits of

overlay information). This minimizes the use of costly ECL interfacing, because most of

the high-speed (pixel clock) logic is contained on-chip. The multiple pixel ports and

internal multiplexing enable TTL-compatible interface (up to 32 MHz) to the frame

buffer, while maintaining the 165 MHz video data rates required for sophisticated color

graphics.

The Bt457 is a single-channel version of the Bt458 and has a 256 x 8 color lookup

table with a single 8-bit video D/A converter. It includes a PLL output to enable subpixel

synchronization of multiple Bt457s.

•

165, 135, 125, 110, 80 MHz

operation

•

4:1 or 5:1 input mux

256-word dual-port color palette

Four dual-port overlay registers

RS-343A-compatible outputs

Bit plane read and blink masks

Standard MPU interface

84-pin PLCC or PGA package

+5 V CMOS monolithic

construction

On-chip features include programmable blink rates, bit plane masking and blinking,

color overlay capability, and a dual-port color palette RAM.

Applications

•

High-resolution color graphics

CAE/CAD/CAM

Image processing

Video reconstruction

Functional Block Diagram

CLOCK* CLOCK

VAA

GND

FSADJUST VREF

COMP

Load

Control

MUX

Control

Blink

Control

LD*

4(8)

256 X 12

(24)

IOR (N/C)

40

8

P[7:0]

(A-E)

Color

Palette

4(8)

Read Blink

Mask Mask

IOG (IOUT)

IOB (PLL)

MUX

Latch

4 x 12

(24)

Overlay

OL[1,0]

(A-E)

10

2

4(8)

SYNC*

BLANK*

Bus Control

ADDR Reg

8

R

G

B

4(8)

CLOCK

CE* R/W CO C1

D[7:0]

Data Sheet

L45801 Rev. N

September 2, 1999

Ordering Information

Ambient

Temperature

Range

Model Number

RAM

DACs

Speed

Package

Bt458LG165

Bt458KG135

Bt458KG125

Bt458KG110

Bt458KG80

256 x 24

256 x 8

Triple 8-bit

Single 8-bit

165 MHz

135 MHz

125 MHz

110 MHz

80 MHz

84-Pin Ceramic PGA

84-Pin Plastic J-Lead

84-Pin Ceramic PGA

84-Pin Plastic J-Lead

0 to + 70 °C

Bt458LPJ165

Bt458LPJ135

Bt458LPJ125

Bt458LPJ110

Bt458LPJ80

Bt457KG135

Bt457KG125

Bt457KG110

Bt457KG80

165 MHz

135 MHz

125 MHz

110 MHz

80 MHz

135 MHz

125 MHz

110 MHz

80 MHz

Bt457KPJ135

Bt457KPJ125

Bt457KPJ110

Bt457KPJ80

135 MHz

125 MHz

110 MHz

80 MHz

Information provided by Conexant Systems, Inc. (Conexant) is believed to be accurate and reliable. However, no responsibility is

assumed by Conexant for its use, nor any infringement of patents or other rights of third parties which may result from its use. No

license is granted by implication or otherwise under any patent rights of Conexant other than for circuitry embodied in Conexant

products. Conexant reserves the right to change circuitry at any time without notice. This document is subject to change without

notice.

Conexant products are not designed or intended for use in life support appliances, devices, or systems where malfunction of a

Conexant product can reasonably be expected to result in personal injury or death. Conexant customers using or selling Conexant

products for use in such applications do so at their own risk and agree to fully indemnify Conexant for any damages resulting from

such improper use or sale.

The trademarks “Conexant” and the Conexant symbol are trademarks of Conexant Systems, Inc.

Product names or services listed in this publication are for identification purposes only, and may be trademarks or registered

trademarks of their respective companies. All other marks mentioned herein are the property of their respective holders.

Printed in U.S.A.

Reader Response: Conexant strives to produce quality documentation, and welcomes your feedback. Please send

comments and suggestions to conexant.tech.pubs@conexant.com. For technical questions, contact your local

Conexant sales office or field applications engineer.

L45801 Rev. N

Conexant

Table of Contents

List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v

List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii

1.0

Circuit Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

1.1 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

1.2 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3

1.3 MPU Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6

2.0

Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

2.1 Internal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

2.1.1

Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

2.2 Read Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3

2.3 Blink Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3

2.4 Bt458 Test Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3

2.5 Bt457 Control/Test Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5

3.0

PC Board Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

3.1 PC Board Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

3.2 Power and Ground Planes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2

3.3 Device Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

3.4 Power Supply Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

3.5 COMP Decoupling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6

3.6 Digital Signal Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6

3.7 Analog Signal Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7

3.8 Analog Output Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7

4.0

Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

4.1 Clock Interfacing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

4.2 Using Multiple Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5

4.3 Bt457 Nonvideo Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5

L45801 Rev. N

Conexant

iii

Table of Contents

Bt457/Bt458

125 MHz/135 MHz/165 MHz Monolithic CMOS 256 Color Palette RAMDAC

4.4 Initializing the Bt458. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6

4.5 Initializing the Bt457 (Monochrome) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8

4.6 Initializing the Bt457 (Color) 24-bit MPU Data Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9

4.7 Initializing the Bt457 (Color) 8-bit MPU Data Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9

5.0

Parametric Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

5.1 DC Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

5.2 AC Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5

5.3 Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11

5.4 Package Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13

5.5 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15

iv

Conexant

L45801 Rev. N

Bt457/Bt458

List of Figures

125 MHz/135 MHz/165 MHz Monolithic CMOS 256 Color Palette RAMDAC

List of Figures

Figure 1-1.

Figure 1-2.

Figure 1-3.

Figure 1-4.

Figure 3-1.

Figure 3-2.

Figure 4-1.

Figure 4-2.

Figure 4-3.

Figure 5-1.

Figure 5-2.

Figure 5-3.

Figure 5-4.

Bt457/Bt458 84-Pin J-Lead Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

Bt457/Bt458 84-Pin PGA Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2

Video Input/Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8

Composite Video Output Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10

Sample Layout Showing Power and Ground Plane Isolation Gaps . . . . . . . . . . . . . . . . . . . 3-2

Typical Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4

Generating the Bt458 Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

Generating the Bt457 Signals (Monochrome Application). . . . . . . . . . . . . . . . . . . . . . . . . . 4-2

Generating the Bt457 Clock Signals (Color Application) . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4

Video Input/Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11

MPU Read/Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12

84-Pin Plastic J-Lead (PLCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13

84-Pin Ceramic PGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14

L45801 Rev. N

Conexant

v

List of Figures

Bt457/Bt458

125 MHz/135 MHz/165 MHz Monolithic CMOS 256 Color Palette RAMDAC

vi

Conexant

L45801 Rev. N

Bt457/Bt458

List of Tables

125 MHz/135 MHz/165 MHz Monolithic CMOS 256 Color Palette RAMDAC

List of Tables

Table 1-1.

Table 1-2.

Table 1-3.

Table 1-4.

Table 1-5.

Table 2-1.

Table 2-2.

Table 2-3.

Table 3-1.

Table 5-1.

Table 5-2.

Table 5-3.

Table 5-4.

Table 5-5.

Table 5-6.

Table 5-7.

Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3

Pin Labels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

Address Register (ADDR) Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6

Palette and Overlay Select Truth Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9

Video Output Truth Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10

Command Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

Bt458 Test Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3

Bt457 Control Test Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5

Typical Parts List. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5

Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2

DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3

AC Characteristics for 165 MHz and 135 MHz Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5

AC Characteristics for 125 MHz and 110 MHz Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7

AC Characteristics for 80 MHz Device. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15

L45801 Rev. N

Conexant

vii

List of Tables

Bt457/Bt458

125 MHz/135 MHz/165 MHz Monolithic CMOS 256 Color Palette RAMDAC

viii

Conexant

L45801 Rev. N

1

1.0 Circuit Description

1.1 Pin Descriptions

The Bt457/Bt458 is available in both 84-pin Plastic Leaded Chip Carrier (PLCC)

and Ceramic PGA packages, as illustrated in Figures 1-1 and 1-2. Table 1-1

provides pin descriptions. Table 1-2 gives pin labels for the PGA package.

Figure 1-1. Bt457/Bt458 84-Pin J-Lead Package

P4E

P5A

53

52

P2A

P1E

P1D

P1C

P1B

P1A

P0E

P0D

P0C

75

76

77

78

79

80

81

82

83

84

51

50

49

P5B

P5C

P5D

P5E

48

47

46

P6A

P6B

45

44

43

P6C

P6D

P6E

P0B

P0A

OL1E

OL1D

OL1C

OL1B

OL1A

OL0E

OL0D

1

2

42

41

40

39

P7A

3

4

P7B

P7C

P7D

P7E

5

6

7

8

9

10

11

38

37

36

35

34

33

VAA

GND

VAA

GND

VREF

OL0C

OL0B

OL0A

Pin Bt458 Bt457

28 IOR

29 IOG IOUT

30 IOB PLL

N/C

457-8_002

L45801 Rev. N

Conexant

1-1

1.0 Circuit Description

Bt457/Bt458

1.1 Pin Descriptions

125 MHz/135 MHz/165 MHz Monolithic CMOS 256 Color Palette RAMDAC

Figure 1-2. Bt457/Bt458 84-Pin PGA Package

COMP GND VAA P7D P7B

P6E P6C P6B

P7A P6D P6A

P5E

P5D

P5C P5B

P4B

12

11

10

IOB GND VAA

IOG FSADJ VREF

VAA IOR

P7E P7C

P5A P4C P4A

P4D P4B SYNC*

BLK* LD*

9

8

7

6

5

4

3

2

C1

R/W

CO

CLK* CLK

VAA

VAA VAA

P3E GND

Bt457/458

(TOP VIEW)

GND GND

CE* D[7]

P3C P3D

D[6] D[5]

P3A

P3B

D[4] D[2] D[0]

P2A P2C P2E

P1D P1E P2D

D[3] D[1] OL0B OL0E OL1B OL1E P0B P0D

OL0A OL0C OL0D OL1A OL1C OL1D P0A P0C

P1A

P0E

J

P1B P1C P2B

1

B

A

C

D

E

F

G

H

K

L

M

Alignment Marker (on top)

12

11

10

P4E

P4A

P5B P5C P5E P6B

P4C P5A P5D P6A

P6C P6E

P7B

P7D VAA GND COMP

P7E VAA GND IOB

VREF FSADJ IOG

P6D P7A P7C

SYNC* P4B P4D

9

8

7

6

5

4

3

2

LD*

BLK*

CLK*

IOR

R/W

VAA

C1

CLK

VAA

P3E

CO

VAA

(BOTTOM VIEW)

GND

P3D

P3B

P2E

P2D

P3C

D7

CE*

D[6]

D[4]

D[3]

P3A

D[5]

D[0] D[2]

P2C P2A

P1E P1D P1A P0D

P0B OL1E OL1B OL0E OL0B D[1]

1

P2B P1C P1B P0E P0C

P0A OL1D OL1C OL1A OL0D OL0C OL0A

M

L

K

J

H

G

F

E

D

C

B

A

Pin Bt458 Bt457

IOG IOUT

A10

A11

IOB

PLL

N/C

B9 IOR

457-8_003

1-2

Conexant

L45801 Rev. N

Bt457/Bt458

1.0 Circuit Description

125 MHz/135 MHz/165 MHz Monolithic CMOS 256 Color Palette RAMDAC

1.2 Pin Descriptions

Table 1-1. Pin Descriptions (1 of 2)

Pin Name

Description

BLANK*

Composite blank control input (TTL compatible). A logical 0 drives the analog outputs to the blanking level, as

specified in Table 1-5. BLANK* is latched on the rising edge of LD*. When BLANK* is a logical 0, the pixel and

overlay inputs are ignored.

SYNC*

LD*

Composite sync control input (TTL compatible). A logical 0 on this input switches off a 40 IRE current source on

the IOG output (see Figure 1-4). SYNC* does not override any other control or data input, as illustrated in

Table 1-5; therefore, it should be asserted only during the blanking interval. It is latched on the rising edge of

LD*.

If sync information is not generated on the IOG output, this pin should be connected to GND.

Load control input (TTL compatible). The P[7:0] {A–E}, OL[1,0] {A–E}, BLANK*, and SYNC* inputs are latched on

the rising edge of LD*. While LD* is either one fourth or one fifth the CLOCK rate, it can be phase independent of

the CLOCK and CLOCK* inputs. LD* can have any duty cycle within the limits specified in the AC Characteristics

section.

P[7:0]

{A–E}

Pixel select inputs (TTL compatible). These inputs are used to specify, on a pixel basis, which of the 256 entries

in the color palette RAM is used to provide color information. Either 4 or 5 consecutive pixels (up to 8 bits per

pixel) are input through this port. They are latched on the rising edge of LD*. Unused inputs should be connected

to GND.

The {A} pixel is output first, followed by the {B} pixel, then the {C} pixel, etc., until all 4 or 5 pixels have been

output, at which point the cycle repeats.

OL[1,0]

{A–E}

Overlay select inputs (TTL compatible). These control inputs are latched on the rising edge of LD*. In conjunction

with bit 6 of the command register, they specify which palette is to be used for color information, as follows:

OL1

OL0

CR6 = 1

CR6 = 0

0

1

0

1

0

1

Color Palette RAM

Overlay Color 1

Overlay Color 2

Overlay Color 3

Overlay Color 0

Overlay Color 1

Overlay Color 2

Overlay Color 3

When accessing the overlay palette, the P[7:0] {A–E} inputs are ignored. Overlay information bits (up to 2 bits per

pixel) for either 4 or 5 consecutive pixels are input through this port. Unused inputs should be connected to GND.

IOR, IOG,

IOB, IOUT

Red, green, and blue video current outputs. These high-impedance current sources can directly drive a doubly

terminated 75 Ω coaxial cable (see Figure 3-2). The Bt457 outputs IOUT rather than IOR, IOG, and IOB.

L45801 Rev. N

Conexant

1-3

1.0 Circuit Description

Bt457/Bt458

1.2 Pin Descriptions

125 MHz/135 MHz/165 MHz Monolithic CMOS 256 Color Palette RAMDAC

Table 1-1. Pin Descriptions (2 of 2)

Pin Name

Description

PLL

Phase lock loop current output—Bt457 only. This high-impedance current source is used to enable multiple

Bt457s to be synchronized with subpixel resolution when used with an external PLL. A logical 1 on the BLANK*

input results in no current being output onto this pin, while a logical 0 results in the following current being

output:

PLL (mA) = 3,227 * VREF (V) / RSET (Ω)

If subpixel synchronization of multiple devices is not required, this output should be connected to GND (either

directly or through a resistor up to 150 Ω).

COMP

Compensation pin. This pin provides compensation for the internal reference amplifier. A 0.1 µF ceramic

capacitor must be connected between this pin and VAA (Figure 3-2). Connecting the capacitor to VAA rather than

to GND provides the highest possible power supply noise rejection. The COMP capacitor must be as close to the

device as possible to keep lead lengths to an absolute minimum and to maximize the capacitor's self-resonant

frequency to be greater than the LD* frequency. The PC Board Layout Considerations section contains critical

layout criteria.

FSADJUST

Full-scale adjust control. A resistor (RSET) connected between this pin and GND controls the magnitude of the

full-scale video signal (Figure 3-1). The IRE relationships in Figure 1-4 are maintained, regardless of the full-scale

output current.

The relationship between RSET and the full-scale output current on IOG (or IOUT for the Bt457) is as follows:

RSET (Ω) = 11,294 * VREF (V) / IOG (mA)

The full-scale output current on IOR and IOB (for the Bt458) for a given RSET is as follows:

IOR, IOB (mA) = 8,067 * VREF (V) / RSET (Ω)

VREF

Voltage reference input. An external voltage reference circuit, such as that illustrated in Figure 3-2, must supply

this input with a 1.235 V (typical) reference. The use of a resistor network to generate the reference is not

recommended, because any low-frequency power supply noise on VREF is directly coupled onto the analog

outputs. A 0.1 µF ceramic capacitor is used to decouple this input to VAA, as shown in Figure 3-2. If VAA is

excessively noisy, better performance can be obtained by decoupling VREF to GND. The decoupling capacitor

must be as close to the device as possible to keep lead lengths to an absolute minimum. Refer to the PC Board

Layout Considerations section for critical layout criteria.

CLOCK,

CLOCK*

Clock inputs. These differential clock inputs are driven by ECL logic configured for single-supply (+5 V)

operation. The clock rate is typically the pixel clock rate of the system. Refer to the PC Board Layout

Considerations section for critical layout criteria.

CE*

Chip enable control input (TTL compatible). This input must be a logical 0 to enable data to be written to or read

from the device. During write operations, data is internally latched on the rising edge of CE*. Glitches should be

avoided on this edge-triggered input.

R/W

Read/write control input (TTL compatible). To write data to the device, both CE* and R/W must be a logical 0. To

read data from the device, CE* must be a logical 0 and R/W must be a logical 1. R/W is latched on the falling edge

of CE*.

C[1,0]

D[7:0]

VAA

Command control inputs (TTL compatible). C0 and C1 specify the type of read or write operation being

performed, as presented in Table 1-3. They are latched on the falling edge of CE*.

Data bus (TTL compatible). Data transfers into and out of the device over this 8-bit bidirectional data bus. D0 is

the least significant bit.

Analog power. All VAA pins must be connected together on the same PCB plane to prevent latchup. Refer to the

PC Board Layout Considerations section for critical layout criteria.

GND

Analog ground. All GND pins must be connected together on the same PCB plane to prevent latchup. Refer to the

PC Board Layout Considerations section for critical layout criteria.

1-4

Conexant

L45801 Rev. N

Bt457/Bt458

1.0 Circuit Description

125 MHz/135 MHz/165 MHz Monolithic CMOS 256 Color Palette RAMDAC

1.2 Pin Descriptions

Table 1-2. Pin Labels

Pin Number

Pin Label

Pin Number

Pin Label

Pin Number

Pin Label

L9

M10

M9

L8

BLANK*

SYNC*

LD*

K11

L12

K12

J11

J12

P5A

P5B

P5C

P5D

P5E

C12

C11

A9

VAA

CLOCK*

CLOCK

L7

M8

M7

A7

G1

G2

H1

H2

J1

P0A

P0B

P0C

P0D

P0E

H11

H12

G12

G11

F12

P6A

P6B

P6C

P6D

P6E

B12

B11

M6

B6

GND

A6

J2

K1

L1

K2

L2

P1A

P1B

P1C

P1D

P1E

F11

E12

E11

D12

D11

P7A

P7B

P7C

P7D

P7E

A12

B10

C10

COMP

FS ADJUST

VREF

A5

B8

A8

B7

CE*

R/W

C1

K3

M1

L3

P2A

P2B

P2C

P2D

P2E

A1

C2

B1

C1

D2

OL0A

OL0B

OL0C

OL0D

OL0E

C0

M2

M3

C3

B2

B3

A2

A3

B4

A4

B5

D[0]

D[1]

D[2]

D[3]

D[4]

D[5]

D[6]

D[7]

L4

M4

L5

P3A

P3B

P3C

P3D

P3E

D1

E2

E1

F1

F2

OL1A

OL1B

OL1C

OL1D

OL1E

M5

L6

M11

L10

L11

K10

M12

P4A

P4B

P4C

P4D

P4E

A10

A11

B9

IOG(IOUT)

IOB (PLL)

IOR (N/C)

NOTE(S): Bt457 Pin names are in parentheses.

L45801 Rev. N

Conexant

1-5

1.0 Circuit Description

Bt457/Bt458

1.3 MPU Interface

125 MHz/135 MHz/165 MHz Monolithic CMOS 256 Color Palette RAMDAC

1.3 MPU Interface

As illustrated in the functional block diagram on the cover page, the Bt457/458

supports a standard MPU bus interface, allowing the MPU direct access to the

internal control registers and color/overlay palettes. The dual-port color palette

RAM and dual-port overlay registers allow color updating, without contention,

with the display refresh process.

As presented in Table 1-3, the C0 and C1 control inputs, in conjunction with

the internal address register, specify which control register, color palette RAM

entry, or overlay register is accessed by the MPU.

The 8-bit address register (ADDR[7:0]) is used to address the internal RAM

and registers, eliminating the requirement for external address multiplexers.

ADDR0 corresponds to D[0] and is the least significant bit.

Table 1-3. Address Register (ADDR) Operation

ADDR[7:0]

C1

C0

Addressed by MPU

$xx

$00–$FF

$00

0

1

0

1

0

Address Register

Color Palette RAM

Overlay Color 0

$01

Overlay Color 1

$02

Overlay Color 2

$03

Overlay Color 3

$04

Read Mask Register

Blink Mask Register

Command Register

Control/Test Register

$05

$06

$07

Bt458 Reading/Writing

Color Data

To write color data, the MPU loads the address register with the address of the

color palette RAM location or overlay register to be modified. The MPU

performs three successive write cycles (red, green, and blue), using C0 and C1 to

select either the color palette RAM or overlay registers. During the blue write

cycle, the three bytes of color information are concatenated into a 24-bit word and

written to the location specified by the address register. The address register then

increments to the next location, which the MPU can modify by writing another

sequence of red, green, and blue data.

To read color data, the MPU loads the address register with the address of the

color palette RAM location or overlay register to be read. The MPU performs

three successive read cycles (red, green, and blue), using C0 and C1 to select

either the color palette RAM or overlay registers. Following the blue read cycle,

the address register increments to the next location, which the MPU can read by

reading another sequence of red, green, and blue data.

1-6

Conexant

L45801 Rev. N

Bt457/Bt458

1.0 Circuit Description

125 MHz/135 MHz/165 MHz Monolithic CMOS 256 Color Palette RAMDAC

1.3 MPU Interface

When accessing the color palette RAM, the address register resets to $00 after

a blue read or write cycle to location $FF. When accessing the overlay registers,

the address register increments to $04 following a blue read or write cycle to

overlay register three. To keep track of the red, green, and blue read/write cycles,

the address register has two additional bits that count modulo three. They are reset

to 0 when the MPU reads or writes to the address register. The MPU does not

have access to these bits. The other 8 bits of the address register (ADDR[7:0]) are

accessible to the MPU.

Bt457 Reading/Writing

Color Data

To write color data, the MPU loads the address register with the address of the

color palette RAM location or overlay register to be modified. The MPU

performs a color write cycle, using C0 and C1 to select either the color palette

RAM or the overlay registers. The address register then increments to the next

location, which the MPU can modify by writing another color.

Reading color data is similar to writing it, except the MPU executes read

cycles.

(Normal Mode)

This mode is useful if a 24-bit data bus is available, because 24 bits of color

information (8 bits each of red, green, and blue) can be read or written to three

Bt457s in a single MPU cycle. In this application, the CE* inputs of all three

Bt457s are connected together. If only an 8-bit data bus is available, the CE*

inputs must be individually selected during the appropriate color write cycle (red

CE* during red write cycle, blue CE* during blue write cycle, and green CE*

during green write cycle).

When accessing the color palette RAM, the address register resets to $00 after

a read or write cycle to location $FF. When accessing the overlay registers, the

address register increments to $04 following a read or write cycle to overlay

register three.

Bt457 Reading/Writing

Color Data (RGB Mode)

To write color data, the MPU loads the address register with the address of the

color palette RAM location or overlay register to be modified. The MPU

performs three successive write cycles (8 bits each of red, green, and blue), using

C0 and C1 to select either the color palette RAM or the overlay registers. After

the blue write cycle, the address register then increments to the next location,

which the MPU can modify by writing another sequence of red, green, and blue

data. Reading color data is similar to writing it, except the MPU executes read

cycles.

This mode is useful if only an 8-bit data bus is available. Each Bt457 is

programmed to be a red, green, or blue RAMDAC and responds only to the

assigned color read or write cycle. In this application, the Bt457s share a common

8-bit data bus. The CE* inputs of all three Bt457s must be asserted

simultaneously only during color read/write cycles and address register write

cycles.

When accessing the color palette RAM, the address register resets to $00 after

a blue read or write cycle to location $FF. When accessing the overlay registers,

the address register increments to $04 following a blue read or write cycle to

overlay register three. To keep track of the red, green, and blue read/write cycles,

the address register has two additional bits that count modulo three. They are reset

to 0 when the MPU reads or writes to the address register. The MPU does not

have access to these bits. The other 8 bits of the address register (ADDR[7:0]) are

accessible to the MPU.

L45801 Rev. N

Conexant

1-7

1.0 Circuit Description

Bt457/Bt458

1.3 MPU Interface

125 MHz/135 MHz/165 MHz Monolithic CMOS 256 Color Palette RAMDAC

Additional Information

Although the color palette RAM and overlay registers are dual-ported, if the pixel

and overlay data are addressing the same palette entry being written to by the

MPU during the write cycle, one or more of the pixels on the display screen can

be disturbed. A maximum of one pixel is disturbed if the write data from the

MPU is valid during the entire chip enable time.

The control registers are also accessed through the address register in

conjunction with the C0 and C1 inputs, as specified in Table 1-3. All control

registers can be written to or read by the MPU at any time. The address register

does not increment following read or write cycles to the control registers,

facilitating read-modify-write operations.

If an invalid address loads into the address register, data written to the device

is ignored, and invalid data is read by the MPU.

Frame Buffer Interface

To enable pixel data to be transferred from the frame buffer at TTL data rates, the

Bt457/458 incorporates internal latches and multiplexers. As illustrated in

Figure 1-3, on the rising edge of LD*, sync and blank information, color (up to 8

bits per pixel), and overlay (up to 2 bits per pixel) information, for either 4 or 5

consecutive pixels, are latched into the device. With this configuration, the sync

and blank timing is recognized only with 4- or 5-pixel resolution. Typically, the

LD* signal is used to clock external circuitry to generate basic video timing.

Each clock cycle, the Bt457/458 outputs color information based on the {A}

inputs, followed by the {B} inputs, then the {C} inputs, etc., until all 4 or 5 pixels

have been output, at which point the cycle repeats.

Figure 1-3. Video Input/Output Timing

LD*

P[7:0] (A–E),

OL[1,0] (A–E),

DATA

SYNC*, BLANK*

IOR, IOG, IOB

(IOUT–Bt457)

CLOCK

457-8_014

The overlay inputs can have pixel timing, facilitating the use of additional bit

planes in the frame buffer to control overlay selection on a pixel basis. On the

other hand, they can be controlled by external character or cursor generation

logic.

To simplify the frame buffer interface timing, LD* can be phase shifted in any

amount relative to CLOCK. This enables the LD* signal to be derived by

externally dividing CLOCK by 4 or 5 independent of the propagation delays of

the LD* generation logic. As a result, the pixel and overlay data are latched on the

rising edge of LD*, independent of the clock phase.

1-8

Conexant

L45801 Rev. N

Bt457/Bt458

1.0 Circuit Description

125 MHz/135 MHz/165 MHz Monolithic CMOS 256 Color Palette RAMDAC

1.3 MPU Interface

Internal logic maintains an internal LOAD signal synchronous to CLOCK and

is guaranteed to follow the LD* signal by at least one, but not more than four,

clock cycles. This LOAD signal transfers the latched pixel and overlay data into a

second set of latches, which are then internally multiplexed at the pixel clock rate.

If 4:1 multiplexing is specified, only one rising edge of LD* should occur

every four clock cycles. If 5:1 multiplexing is specified, only one rising edge of

LD* should occur every five clock cycles. Otherwise, the internal LOAD

generation circuitry assumes it is not locked onto the LD* signal and

continuously attempts to resynchronize itself to LD*.

Color Selection

Each clock cycle, 8 bits of color information (P7:0) and 2 bits of overlay

information (OL1,0) for each pixel are processed by the read mask, blink mask,

and command registers. Through the control registers, individual bit planes can

be enabled or disabled for display, and/or blinked at one of four blink rates and

duty cycles.

To ensure blinking does not cause a color change to occur during the active

display time (i.e., in the middle of the screen), the Bt457/458 monitors the

BLANK* input to determine vertical retrace intervals. A vertical retrace interval

is recognized by determining that BLANK* has been a logical 0 for at least 256

LD* cycles.

The processed pixel data is then used to select which color palette entry or

overlay register is to provide color information. P[0] is the LSB when addressing

the color palette RAM. Table 1-4 is the truth table used for color selection.

Table 1-4. Palette and Overlay Select Truth Table

CR[6]

OL[1]

OL[0]

P[7:0]

Addressed by Frame

1

:

0

:

0

:

$00

$01

:

Color Palette Entry $00

Color Palette Entry $01

:

1

0

x

0

1

0

1

0

1

$FF

$xx

Color Palette Entry $FF

Overlay Color 0

Overlay Color 1

Overlay Color 2

Overlay Color 3

Video Generation

Every clock cycle, the selected color information, from the color palette RAMs or

overlay registers, is presented to the D/A converters.

The SYNC* and BLANK* inputs are pipelined to maintain synchronization

with the pixel data. They add appropriately weighted currents to the analog

outputs, producing the specific output levels required for video applications, as

described in Figure 1-4.

Varying output current from each D/A converter produces a corresponding

voltage level, used to drive the color CRT monitor. Only the green output (IOG)

on the Bt458 contains sync information. Table 1-5 details how the SYNC* and

BLANK* inputs modify the output levels.

The D/A converters on the Bt457 and Bt458 use a segmented architecture in

which bit currents are routed to either the current output or GND by a

sophisticated decoding scheme. This architecture eliminates the need for

L45801 Rev. N

Conexant

1-9

1.0 Circuit Description

Bt457/Bt458

1.3 MPU Interface

125 MHz/135 MHz/165 MHz Monolithic CMOS 256 Color Palette RAMDAC

precision component ratios and greatly reduces the switching transients

associated with turning current sources on or off. Monotonicity and low glitch are

guaranteed by using identical current sources and current steering their outputs.

An on-chip operational amplifier stabilizes the D/A converter’s full-scale output

current against temperature and power supply variations.

Figure 1-4. Composite Video Output Waveforms

NO SYNC

MA

19.05 0.714 26.67 1.000

SYNC

V

MA

V

WHITE LEVEL

92.5 IRE

BLACK LEVEL

BLANK LEVEL

1.44 0.054

0.00 0.000

9.05 0.340

7.62 0.286

7.5 IRE

40 IRE

0.000

0.00

SYNC LEVEL

457-8_004

Table 1-5. Video Output Truth Table

IOG (Iout)

IOR, IOB

(mA)

Description

Sync*

BLANK*

DAC Input Data

(mA)

White

DATA

26.67

data + 9.05

data + 1.44

9.05

19.5

1

0

1

0

1

0

1

0

$FF

data

$00

$xx

data + 1.44

DATA - SYNC

BLACK

data + 1.44

1.44

0

BLACK-SYNC

BLACK

1.44

7.62

SYNC

0

NOTE(S): Typical with full-scale IOG = 26.67 mA. RSET = 523 Ω and VREF = 1.235 V.

1-10

Conexant

L45801 Rev. N

2

2.0 Registers

2.1 Internal

2.1.1 Command Register

The command register can be written or read by the MPU at any time and is not

initialized. For proper operation, it must be initialized by the user after power-up.

CR0 corresponds to data bus bit D[0].

Table 2-1. Command Registers (1 of 2)

Function

Description

CR7

Multiplex select

4:1 Multiplexing

This bit specifies whether 4:1 or 5:1 multiplexing is to be used for the

pixel and overlay inputs. If 4:1 is specified, the {E} pixel and {E} overlay

inputs are ignored and should be connected to GND, and the LD* input

should be one fourth the CLOCK rate. If 5:1 is specified, all of the pixel

and overlay inputs are used, and the LD* input should be one fifth the

CLOCK rate.

(0)

(1)

5:1 Multiplexing

The pipeline delay of the Bt457/458 can be reset to a fixed eight clock

cycles. In this instance, each time the input multiplexing is changed, the

Bt457/458 must again be reset to a fixed pipeline delay.

CR6

RAM Enable

When the overlay select bits are 00, this bit specifies whether to use the

color palette RAM or overlay color 0 to provide color information.

(0)

(1)

Use Overlay Color 0

Use Color Palette RAM

CR5,4

Blink Rate Selection

These 2 bits control the blink rate cycle time and duty cycle, and are

specified as the number of vertical retrace intervals. The numbers in

parentheses specify the duty cycle (percent on/off).

(00)

(01)

(10)

(11)

16 on, 48 off (25/75)

16 on, 16 off (50/50)

32 on, 32 off (50/50)

64 on, 64 off (50/50)

CR3

OL1 Blink Enable

If a logical 1, this bit forces the OL1 {A–E} inputs to toggle between a

logical 0 and the input value at the selected blink rate prior to palette

section. A value of logical 0 does not affect the value of the OL1 {A–E}

inputs. In order for overlay 1 bit plane to blink, bit CR1 must be set to a

logical 1.

L45801 Rev. N

Conexant

2-1

2.0 Registers

Bt457/Bt458

2.1 Internal

125 MHz/135 MHz/165 MHz Monolithic CMOS 256 Color Palette RAMDAC

Table 2-1. Command Registers (2 of 2)

Function

Description

CR2

OL0 Blink Enable

If a logical 1, this bit forces the OL0 {A–E} inputs to toggle between a

logical 0 and the input value at the selected blink rate prior to palette

selection. A value of the logical 0 does not affect the value of the OL0

{A–E} inputs. In order for overlay 0 bit plane to blink, bit CR0 must be set

to a logical 1.

CR1

CR0

OL1 Display Enable

If a logical 0, this bit forces the OL1 {A–E} inputs to a logical 0 prior to

selecting the palettes. A value of a logical 1 does not affect the value of

the OL1 {A–E} inputs.

(0)

(1)

Disable

Enable

OL0 Display Enable

If a logical 0, this bit forces the OL0 {A–E} inputs to a logical 0 prior to

selecting the palettes. A value of a logical 1 does not affect the value of

the OL0 {A–E} inputs.

(0)

(1)

Disable

Enable

2-2

Conexant

L45801 Rev. N

Bt457/Bt458

2.0 Registers

125 MHz/135 MHz/165 MHz Monolithic CMOS 256 Color Palette RAMDAC

2.2 Read Mask Register

The read mask register enables (logical 1) or disables (logical 0) a bit plane from

addressing the color palette RAM. D[0] corresponds to bit plane 0 (P0 {A–E}),

and D[7] corresponds to bit plane 7 (P7 {A–E}). Each register bit is logically

ANDed with the corresponding bit plane input. This register can be written to or

read by the MPU at any time and is not initialized. For proper operation, it must

be initialized by the user after power-up.

2.3 Blink Mask Register

The blink mask register enables (logical 1) or disables (logical 0) a bit plane from

blinking at the blink rate and duty cycle specified by the command register. D[0]

corresponds to bit plane 0 (P0 {A–E}), and D[7] corresponds to bit plane 7 (P7

{A–E}). In order for a bit plane to blink, the corresponding bit in the read mask

register must be a logical 1. This register can be written to or read by the MPU at

any time and is not initialized. For proper operation, it must be initialized by the

user after power-up.

2.4 Bt458 Test Register

The test register provides diagnostic capability by enabling the MPU to read

the D/A converters inputs. It can be written to or read by the MPU at any time and

is not initialized. For proper operation, it must be initialized by the user after

power-up. When writing to the register, the upper 4 bits (D[7:4]) are ignored.

The contents of the test register are defined as follows:

Table 2-2. Bt458 Test Register

D[7:4]

Color Information

D[3]

D[2]

D[1]

D[0]

Low (Logical 1) or High (Logical 0) Nibble

Blue Enable

Green Enable

Red Enable

To use the test register, the host MPU writes to it, setting only one of the red,

green, or blue enable bits. These bits specify which four bits of color information

the MPU wishes to read (R[3:0], G[3:0], B[3:0], R[7:4], G[7:4], or B[7:4]). When

the MPU reads the test register, the four bits of color information from the DAC

L45801 Rev. N

Conexant

2-3

2.0 Registers

Bt457/Bt458

2.4 Bt458 Test Register

125 MHz/135 MHz/165 MHz Monolithic CMOS 256 Color Palette RAMDAC

inputs are contained in the upper four bits, and the lower four bits contain the red,

green, blue, and low or high nibble enable information previously written. Either

the CLOCK must be slowed down to the MPU cycle time, or the same pixel and

overlay data must be presented to the device during the entire MPU read cycle.

For example, to read the upper four bits of red color information being

presented to the D/A converters, the MPU writes to the test register, setting only

the red enable bit. The MPU then reads the test register, keeping the pixel data

stable, which results in D[7:4] containing R[7:4] color bits and D[3:0] containing

red, green, blue, and low or high nibble enable information, as illustrated below:

D[7]

D[6]

D[5]

D[4]

R7

R6

R5

R4

D[3]

D[2]

D[1]

D[0]

0

1

2-4

Conexant

L45801 Rev. N

Bt457/Bt458

2.0 Registers

125 MHz/135 MHz/165 MHz Monolithic CMOS 256 Color Palette RAMDAC

2.5 Bt457 Control/Test Register

The control/test register provides diagnostic capability by enabling the MPU to

read the D/A converter inputs. It can be written to or read by the MPU at any time

and is not initialized. For proper operation, it must be initialized by the user after

power-up. When writing to the register, the upper four bits (D[7:4]) are ignored.

The contents of the test register are defined as follows:

Table 2-3. Bt457 Control Test Register

D[7:4]

Color Information

D[3]

D[2]

D[1]

D[0]

Low (Logical 1) or High (Logical 0) Nibble

Blue Channel Enable

Green Channel Enable

Red Channel Enable

To use the control/test register, the MPU writes to it, specifying the low or

high nibble of color information. When the MPU reads the register, the four bits

of color information from the DAC inputs are contained in the upper four bits,

and the lower four bits contain whatever was previously written to the register.

Either the CLOCK must be slowed down to the MPU cycle time, or the same

pixel and overlay data must be presented to the device during the entire MPU read

cycle.

The red, green, and blue enable bits specify the mode in which color data is

written to and read from, the Bt457. If all three enable bits are logical 0s, each

write cycle to the color palette RAM or overlay registers loads 8 bits of color data.

During each read cycle of the color palette RAM or overlay registers, 8 bits of

color data are output onto the data bus. If a 24-bit data bus is available, three

Bt457s can be accessed simultaneously.

If any of the red, green, or blue enable bits is a logical 1, the Bt457 assumes

the MPU is reading and writing color information using red-green-blue cycles,

such as are used in the Bt458. Setting the appropriate enable bit configures the

Bt457 to output or input color data only for the color read/write cycle

corresponding to the enabled color. Thus, if the green enable bit is a logical 1, and

a red-green-blue write cycle occurred, the Bt457 would input data only during the

green write cycle. If a red-green-blue read cycle occurred, the Bt457 would output

data only during the green read cycle. CE* must be a logical 0 during each of the

red-green-blue cycles. Only one of the enable bits must be a logical 1. This mode

of operation is useful when only an 8-bit data bus is available and the software

drivers are written for RGB operation.

L45801 Rev. N

Conexant

2-5

2.0 Registers

Bt457/Bt458

2.5 Bt457 Control/Test Register

125 MHz/135 MHz/165 MHz Monolithic CMOS 256 Color Palette RAMDAC

2-6

Conexant

L45801 Rev. N

3

3.0 PC Board Layout Considerations

3.1 PC Board Considerations

The Bt457 and Bt458 layouts should be optimized for lowest noise on their power

and ground lines by shielding the digital inputs and providing good decoupling.

The trace length between groups of VAA and GND pins should be as short as

possible to minimize inductive ringing.

A well-designed power distribution network is critical to eliminate digital

switching noise. The ground plane must provide a low-impedance return path for

the digital circuits. A PC board with a minimum of six layers is recommended.

The ground layer is used as a shield to isolate noise from the analog traces with

layer 1 (top) the analog traces, layer two the ground plane, layer three the analog

power plane, and the remaining layers used for digital traces and digital power

supplies.

The optimum layout enables the Bt457 and Bt458 to be located as close as

possible to the power supply connector and the video output connector.

L45801 Rev. N

Conexant

3-1

3.0 PC Board Layout Considerations

Bt457/Bt458

3.2 Power and Ground Planes

125 MHz/135 MHz/165 MHz Monolithic CMOS 256 Color Palette RAMDAC

3.2 Power and Ground Planes

Power and ground planes need isolation gaps to minimize digital switching noise

effects on the analog signals and components. These gaps need to be at least

1/8-inch wide. They are placed so that digital currents cannot flow through a

peninsula that contains the analog components, signals, and video connector.

Figure 3-1 illustrates a sample layout.

Figure 3-1. Sample Layout Showing Power and Ground Plane Isolation Gaps

Digital Area

Analog

RAMDAC

Area

Digital Area

Edge of PCB

457-8_005

3-2

Conexant

L45801 Rev. N

Bt457/Bt458

3.0 PC Board Layout Considerations

125 MHz/135 MHz/165 MHz Monolithic CMOS 256 Color Palette RAMDAC

3.3 Device Decoupling

For optimum performance, all capacitors should be located as close as possible to

the device, using the shortest possible leads (consistent with reliable operation) to

reduce the lead inductance. Chip capacitors are recommended for minimum lead

inductance. Radial lead ceramic capacitors can be substituted for chip capacitors

and are better than axial lead capacitors for self-resonance. Values chosen have

self-resonance above the pixel clock.

3.4 Power Supply Decoupling

The best power supply decoupling performance is obtained by providing a 0.1 µF

ceramic capacitor in parallel with a 0.01 µF chip capacitor to decouple each group

of VAA pins to GND. The capacitors should be placed as close as possible to the

device VAA and GND pins.

The 10 µF capacitor illustrated in Figure 3-2 is for low-frequency power

supply ripple; the 0.1 µF and 0.01 µF capacitors are for high-frequency power

supply noise rejection. The decoupling capacitors should be connected at the

VAA and GND pins, using short, wide traces.

When using a linear regulator, the power-up sequence must be verified to

prevent latchup. A linear regulator is recommended to filter the analog power

supply if the power supply noise is greater than 200 mV. This is especially

important when using a switching power supply and the switching frequency is

close to the raster scan frequency.

NOTE: About 10 percent of power supply hum and ripple noise less than 1 MHz

will couple onto the analog outputs.

L45801 Rev. N

Conexant

3-3

3.0 PC Board Layout Considerations

Bt457/Bt458

3.4 Power Supply Decoupling

125 MHz/135 MHz/165 MHz Monolithic CMOS 256 Color Palette RAMDAC

Figure 3-2. Typical Connection Diagram

COMP

C8

ANALOG POWER PLANE

VAA

C9

R4

C2–C4

C5–C7

+5 V (VCC)

VREF

+

C1

C10

Z1

Bt457/458

GROUND

(POWER SUPPLY

CONNECTOR)

GND

RSET

R1 R2 R3

FS ADJUST

(N/C) IOR

(1)

P

TO

VIDEO

(OUT) IOG

(PLL) IOB

CONNECTOR

VAA

P

1N4148/9

TO MONITOR

1N4148/9

DAC

OUTPUT

NOTE(S):

(1)

Not used with Bt457.

2. Bt457 pin names are in parentheses. Each pair of device VAA and GND pins must be separately decoupled with 0.1 µF and

0.01 µF capacitors

457-8_006

3-4

Conexant

L45801 Rev. N

Bt457/Bt458

3.0 PC Board Layout Considerations

125 MHz/135 MHz/165 MHz Monolithic CMOS 256 Color Palette RAMDAC

3.4 Power Supply Decoupling

Table 3-1. Typical Parts List

Location

C1–C4, C8, C9

Description‘

Vendor Part Number

0.1 µF Ceramic Capacitor

0.01 µF Ceramic Chip Capacitor

10 µF Tantalum Capacitor

Ferrite Bead

Erie RPE112Z5U104M50V

AVX 12102T103QA1018

Mallory CSR13G106KM

Fair-Rite 2743001111

Dale CMF-55C

C5–C7

C10

L1

R1, R2, R3

R4

75 Ω 1% Metal Film Resistor

1000 Ω 1% Metal Film Resistor

523 Ω 1% Metal Film Resistor

1.2 V Voltage Reference

Dale CMF-55C

RSET

Z1

Dale CMF-55C

National Semiconductor LM385Z-1.2

NOTE(S): The vendor numbers above are listed only as a guide. Substitution of devices with similar characteristics does not affect

the performance of the Bt457/458. R3 is not used with Bt457 (see Section 4.0, Application Information).

L45801 Rev. N

Conexant

3-5

3.0 PC Board Layout Considerations

Bt457/Bt458

3.5 COMP Decoupling

125 MHz/135 MHz/165 MHz Monolithic CMOS 256 Color Palette RAMDAC

3.5 COMP Decoupling

The COMP pin must be decoupled to VAA, typically with a 0.1 µF ceramic

capacitor. Low-frequency supply noise requires a larger value. The COMP

capacitor must be as close as physically possible to the COMP and VAA pins. A

surface-mount ceramic chip capacitor is preferred for minimal lead inductance,

which degrades the noise rejection of the circuit. Short, wide traces also reduce

lead inductance.

If the display has a ghosting problem, additional capacitance connected in

parallel with the COMP capacitor can help.

3.6 Digital Signal Interconnect

Digital inputs to the Bt457 and Bt458 should be isolated as much as possible from

the analog outputs and other analog circuitry. Also, these input signals should not

overlay the analog power and output signals.

Most noise on the analog outputs is caused by excessive edge rates (less than 3

ns), overshoot, undershoot, and ringing on the digital inputs.

The digital edge rates should be no faster than necessary, because feedthrough

noise is proportional to the digital edge rates. Lower speed applications benefit

from using lower speed logic (3–5 ns edge rates) to reduce data-related noise on

the analog outputs.

Transmission lines mismatch if the lines do not match the source and

destination impedance. This degrades signal fidelity if the line length reflection

time is greater than one fourth the signal edge time. Line termination or line

length reduction is the solution. For example, logic edge rates of 2 ns require line

lengths of less than four inches without using termination. Ringing can be

reduced by damping the line with a series resistor (30–300 Ω).

Radiation of digital signals can also be picked up by the analog circuitry. This

is prevented by reducing the digital edge rates (rise/fall time), minimizing ringing

with damping resistors, and minimizing coupling through PC board capacitance

by routing the signals 90 degrees to any analog signals.

The clock driver and all other digital devices on the circuit board must be

adequately decoupled to prevent the noise generated by digital devices from

coupling into the analog circuitry.

3-6

Conexant

L45801 Rev. N

Bt457/Bt458

3.0 PC Board Layout Considerations

125 MHz/135 MHz/165 MHz Monolithic CMOS 256 Color Palette RAMDAC

3.7 Analog Signal Interconnect

The Bt457 and Bt458 should be located as close as possible to the output

connectors. This minimizes noise pickup and reflections caused by impedance

mismatch.

Analog outputs are susceptible to crosstalk from digital lines; digital traces

must not be routed under or adjacent to the analog output traces.

To maximize the high-frequency power supply rejection, the video output

signals should not overlay the analog power plane.

For maximum performance, the analog video output impedance, cable

impedance, and load impedance should be the same.

Analog output video edges exceeding the CRT monitor bandwidth can be

reflected, producing cable-length dependent ghosts. Simple pulse filters can

reduce high-frequency energy, reducing EMI and noise. The filter impedance

must match the line impedance.

3.8 Analog Output Protection

The Bt457 and Bt458 analog outputs should be protected against high-energy

discharges, such as those from monitor arc-over or from “hot-switching”

AC-coupled monitors.

The diode protection circuit illustrated in Figure 3-2 can prevent latchup under

severe discharge conditions without adversely degrading analog transition times.

The 1N4148/9 are low-capacitance, fast-switching diodes, which are available in

multiple-device packages (FSA250X or FSA270X) or surface-mountable pairs

(BAV99 or MMBD7001).

L45801 Rev. N

Conexant

3-7

3.0 PC Board Layout Considerations

Bt457/Bt458

3.8 Analog Output Protection

125 MHz/135 MHz/165 MHz Monolithic CMOS 256 Color Palette RAMDAC

3-8

Conexant

L45801 Rev. N

4

4.0 Application Information

4.1 Clock Interfacing

Because of the high clock rates at which the Bt457 and Bt458 can operate, they

will accept differential clock signals (CLOCK and CLOCK*). These clock inputs

are generated by ECL logic operating at +5 V. The CLOCK and CLOCK* inputs

require termination resistors (220 Ω to GND) that should be located as close as

possible to the clock driver. A 150 Ω chip resistor connected between the

RAMDAC’s CLOCK and CLOCK* pins is also required to ensure proper

termination. It should be located as close as possible to the RAMDAC. Figure 4-1

illustrates the location.

Figure 4-1. Generating the Bt458 Clock Signals

+5V

14

+5V

CLOCK

MONITOR

PRODUCTS

970E

220

330

220

150

Bt458

7

CLOCK*

Bt438

LDA*

LDA

VAA

0.1

VREF

1K

457-8_007

L45801 Rev. N

Conexant

4-1

4.0 Application Information

Bt457/Bt458

4.1 Clock Interfacing

125 MHz/135 MHz/165 MHz Monolithic CMOS 256 Color Palette RAMDAC

Applications of 165 MHz require robust ECL clock signals with strong

pulldown (–20 mA at VOH) and double termination for clock trace lengths

greater than 2 inches.

The CLOCK and CLOCK* inputs must be differential signals and greater

than 0.6 V peak to peak because of the noise margins of the CMOS process. The

Bt457/458 will not function if it uses a single-ended clock with CLOCK*

connected to ground.

Typically, LD* is generated by dividing CLOCK by 4 or 5 (depending on

whether 4:1 or 5:1 multiplexing was specified) and translating the result to TTL

levels. As LD* can be phase shifted relative to CLOCK, propagation delays need

not be considered when the LD* signal is derived. LD* can be used as the shift

clock for the video DRAMs and to generate the fundamental video timing of the

system (e.g., SYNC* and BLANK*).

It is recommended that the Bt438 or Bt439 Clock Generator Chips be used to

generate the clock and load signals. Both support the 4:1 and 5:1 input

multiplexing of the Bt457/458, and set the pipeline delay of the Bt457 and Bt458

to eight clock cycles. Figure 4-1 and Figure 4-2 illustrate use of the Bt438 with

the Bt457/458.

When a single Bt457 is used, the PLL output is ignored and should be

connected to GND (either directly or through a resistor up to 150 Ω).

Figure 4-2. Generating the Bt457 Signals (Monochrome Application)

+5V

14

+5V

CLOCK

MONITOR

PRODUCTS

970E

220

330

220

150

Bt457

7

CLOCK*

Bt438

LDA*

LDA

VAA

0.1

VREF

1K

457-8_008

Setting the Pipeline

Delay (Bt457 and Bt458)

The pipeline delay of the Bt457/458, although fixed after a power-up condition,

can be anywhere from six to ten clock cycles. The Bt457/458 contains additional

circuitry enabling the pipeline delay to be fixed at eight clock cycles. The Bt438

and Bt439 Clock Generator Chips support this mode of operation when they are

used with the Bt457/458.

To reset the Bt457/458, it should be powered up with LD*, CLOCK, and

CLOCK* running. The CLOCK and CLOCK* signals should be stopped with

CLOCK high and CLOCK* low for at least three rising edges of LD*. The device

can be held with CLOCK and CLOCK* stopped for an unlimited time.

4-2

Conexant

L45801 Rev. N

Bt457/Bt458

4.0 Application Information

125 MHz/135 MHz/165 MHz Monolithic CMOS 256 Color Palette RAMDAC

4.1 Clock Interfacing

CLOCK and CLOCK* should be restarted so that the first edge of the signals

is as close as possible to the rising edge of LD*. (The falling edge of CLOCK

leads the rising edge of LD* by no more than 1 clock cycle or follows the rising

edge of LD* by no more than 1.5 clock cycles). When the clocks are restarted, the

minimum clock pulse width must not be violated.

When the Bt457/458 is reset to an eight-clock-cycle pipeline delay, the blink

counter circuitry is not reset. Therefore, if multiple Bt457/458s are used in

parallel, the on-chip blink counters cannot be synchronized. In this instance, the

blink mask register should be $00, and the overlay blink enable bits should be

logical 0s. Software can control blinking through the read mask register and

overlay display enable bits.

In standard operation, the Bt457/458 must be reset only following a power-up

or reset condition. Under these circumstances the on-chip blink circuitry can be

used.

Bt457 Color Display

Applications

For color display applications in which up to four Bt457s are used, it is

recommended that the Bt439 Clock Generator Chip be used to generate the clock

and load signals. It supports the 4:1 and 5:1 input multiplexing of the Bt457,

synchronizes the clock and load signals to subpixel resolution, and sets the

pipeline delay of the Bt457 to eight clock cycles. The Bt439 can also be used to

interface the Bt457 to a TTL clock. Figure 4-3 illustrates use of the Bt439 with

the Bt457.

L45801 Rev. N

Conexant

4-3

4.0 Application Information

Bt457/Bt458

4.1 Clock Interfacing

125 MHz/135 MHz/165 MHz Monolithic CMOS 256 Color Palette RAMDAC

Figure 4-3. Generating the Bt457 Clock Signals (Color Application)

+5V

PLL0

PLL

Q1

R2

14

+5V

CLOCK 0

CLOCK

R1

CLOCK 0*

MONITOR

PRODUCTS

970E

220

330

CLOCK*

Bt457

#1

VAA

7

Bt439

+5V

PLL

PLL1

CLOCK1

CLOCK1*

Q1

R2

+5V

R1

CLOCK

CLOCK*

Q1

2.2K

430

Bt457

#2

2N3904

LD*

VAA

TO

Bt439

FROM

Bt457

VREF

70

Q1

R2

PLL2

PLL

CLOCK 2

CLOCK

R1

CLOCK2*

CLOCK*

LD*

R1

R2

Bt457

#3

LD

220

150

VAA

VREF

457-8_009

Subpixel synchronization is supported by the PLL output. Essentially, PLL

provides a signal to indicate the amount of analog output delay of the Bt457

relative to CLOCK. The Bt439 compares the phase of the PLL signals generated

by up to four Bt457s, and adjusts the phase of each of the CLOCK and CLOCK*

signals to the Bt457s to minimize the PLL phase difference. There should be

minimal layout skew in the CLOCK and PLL trace paths to ensure proper clock

alignment.

If subpixel synchronization of multiple Bt457s is not necessary, the Bt438

Clock Generator Chip can be used rather than the Bt439. In this instance, the

CLOCK, CLOCK*, and LD* inputs of up to four Bt457s are connected together

and driven by a single Bt438 (daisy chain with single balanced termination for

<100 MHz or through a 10H116 buffer for >100 MHz). The VREF inputs of the

Bt457s must still have a 0.1 µF bypass capacitor to VAA. The PLL outputs would

not be used and should be connected to GND (either directly or through a resistor

up to 150 Ω).

4-4

Conexant

L45801 Rev. N

Bt457/Bt458

4.0 Application Information

125 MHz/135 MHz/165 MHz Monolithic CMOS 256 Color Palette RAMDAC

4.2 Using Multiple Devices

When multiple RAMDACs are used, each RAMDAC should have its own power

plane ferrite bead. In addition, a single voltage reference can drive multiple

devices; however, isolation resistors are recommended to reduce color channel

crosstalk.

Higher performance can be obtained if each RAMDAC has its own voltage

reference. This can further reduce the amount of color channel crosstalk and color

palette interaction.

Each RAMDAC must still have its own RSET resistor, analog output

termination resistors, power supply bypass capacitors, COMP capacitor, and

VREF capacitor.

4.3 Bt457 Nonvideo Applications

The Bt457 can be used in nonvideo applications by disabling the video-specific

control signals. SYNC* should be a logical 0, and BLANK* should be a logical 1.

The relationship between RSET and the full-scale output current (Iout) in this

configuration is as follows:

RSET (Ω) = 7,457 * VREF (V) / Iout (mA)

With the DAC data inputs at $00, there is a DC offset current (Imin) defined

as follows:

Imin (mA) = 610 * VREF (V) / RSET (Ω)

Therefore, the total full-scale output current is Iout + Imin.

L45801 Rev. N

Conexant

4-5

4.0 Application Information

Bt457/Bt458

4.4 Initializing the Bt458

125 MHz/135 MHz/165 MHz Monolithic CMOS 256 Color Palette RAMDAC

4.4 Initializing the Bt458

Following a power-on sequence, the Bt458 must be initialized. If the clock/LD*

sequence is controlled to reset the pipeline delay of the Bt458 to a fixed pipeline

delay of eight clock cycles, this initialization sequence must be performed after

the reset sequence. The command register must also be reinitialized when the

multiplex selection changes (e.g., from 4:1 to 5:1 input multiplexing).

This sequence configures the Bt458 as follows:

4:1 Multiplexed Operation

No Overlays

No Blinking

Control Register Initialization

Write $04 to address register

C1,C0

00

Write $FF to read mask register

Write $05 to address register

10

00

Write $00 to blink mask register

Write $06 to address register

10

00

Write $40 to command register

Write $07 to address register

10

00

Write $00 to test register

10

Color Palette RAM Initialization

Write $00 to address register

00

01

:

Write red data to RAM (location $00)]

Write green data to RAM (location $00)

Write blue data to RAM (location $00)

Write red data to RAM (location $01)

Write green data to RAM (location $01)

Write blue data to RAM (location $01)

:

Write red data to RAM (location $FF)

Write green data to RAM (location $FF)

Write blue data to RAM (location $FF)

Overlay Color Palette Initialization

Write $00 to address register

01

00

11

Write red data to overlay (location $00)

Write green data to overlay (location $00)

Write blue data to overlay (location $00)

Write red data to overlay (location $01)

4-6

Conexant

L45801 Rev. N

Bt457/Bt458

4.0 Application Information

125 MHz/135 MHz/165 MHz Monolithic CMOS 256 Color Palette RAMDAC

4.4 Initializing the Bt458

Write green data to overlay (location $01)

Write blue data to overlay (location $01)

:

11

:

Write red data to overlay (location $03)

Write green data to overlay (location $03)

Write blue data to overlay (location $03)

11

L45801 Rev. N

Conexant

4-7

4.0 Application Information

Bt457/Bt458

4.5 Initializing the Bt457 (Monochrome) 125 MHz/135 MHz/165 MHz Monolithic CMOS 256 Color Palette RAMDAC

4.5 Initializing the Bt457 (Monochrome)

Following a power-on sequence, the Bt457 must be initialized. If the clock/LD*

sequence is controlled to reset the pipeline delay of the Bt457 to a fixed pipeline

delay of eight clock cycles, this initialization sequence must be performed after

the reset sequence. The command register must also be reinitialized when the

multiplex selection changes (e.g., from 4:1 to 5:1 input multiplexing).

This sequence configures the Bt457 as follows:

4:1 Multiplexed Operation

No Overlays

No Blinking

Color data written/read every cycle

Control Register Initialization

Write $04 to address register

Write $FF to read mask register

Write $05 to address register

Write $00 to blink mask register

Write $06 to address register

Write $40 to command register

Write $07 to address register

Write $00 to test register

C1,C0

00

10

00

10

00

10

00

10

Color Palette RAM Initialization

Write $00 to address register

Write data to RAM (location $00)

Write data to RAM (location $01)

:

00

01

:

Write data to RAM (location $FF)

Overlay Color Palette Initialization

Write $00 to address register

Write data to overlay (location $00)

Write data to overlay (location $01)

:

01

00

11

:

Write data to overlay (location $03)

11

4-8

Conexant

L45801 Rev. N

Bt457/Bt458

4.0 Application Information

125 MHz/135 MHz/165 MHz Monolithic CMOS 256 Color Palette RAMDAC4.6 Initializing the Bt457 (Color) 24-bit MPU

4.6 Initializing the Bt457 (Color) 24-bit MPU

Data Bus

In this example, three Bt457s are used in parallel to generate true color. A 24-bit

MPU data bus is available to access all three Bt457s in parallel.

The operation and initialization are the same as the monochrome application

of the Bt457.

4.7 Initializing the Bt457 (Color) 8-bit MPU Data

Bus

In this example, three Bt457s are used in parallel to generate true color. An 8-bit

MPU data bus is available to access the Bt457s.

While accessing the command, read mask, blink mask, and control/test and

address registers, each Bt457 must be accessed individually. While accessing the

color palette RAM or overlay registers, all three Bt457s are accessed

simultaneously.

Following a power-on sequence, the Bt457s must be initialized. If the

clock/LD* sequence is controlled to reset the pipeline delay of the Bt457s to a

fixed pipeline delay of eight clock cycles, this initialization sequence must be

performed after the reset sequence. The command register must also be

reinitialized when the multiplex selection changes (e.g., from 4:1 to 5:1 input

multiplexing).

This sequence configures the Bt457s as follows:

4:1 Multiplexed Operation

No Overlays

No Blinking

Each Bt457 initialized as a red, green, or blue device

Control Register Initialization

Red Bt457

C1,C0

Write $04 to address register

Write $FF to read mask register

Write $05 to address register

Write $00 to blink mask register

Write $06 to address register

Write $40 to command register

Write $07 to address register

Write $00 to test register

00

10

00

10

00

10

00

10

L45801 Rev. N

Conexant

4-9

4.0 Application Information

Bt457/Bt458

4.7 Initializing the Bt457 (Color) 8-bit MPU Data Bus 125 MHz/135 MHz/165 MHz Monolithic CMOS 256 Color Palette

Green Bt457

Write $04 to address register

00

10

00

10

00

10

00

10

Write $FF to read mask register

Write $05 to address register

Write $00 to blink mask register

Write $06 to address register

Write $40 to command register

Write $07 to address register

Write $02 to test register

Blue Bt457

Write $04 to address register

00

10

00

10

00

10

00

10

Write $FF to read mask register

Write $05 to address register

Write $00 to blink mask register

Write $06 to address register

Write $40 to command register

Write $07 to address register

Write $04 to test register

Color Palette RAM Initialization

Write $00 to all three address registers

Write red data to RAM (location $00)

Write green data to RAM (location $00)

Write blue data to RAM (location $00)

Write red data to RAM (location $01)

Write green data to RAM (location $01)

Write blue data to RAM (location $01)

:

00

01

:

Write red data to RAM (location $FF)

Write green data to RAM (location $FF)

Write blue data to RAM (location $FF)

Overlay Color Palette Initialization

Write $00 to all three address registers

Write red data to overlay (location $00)

Write green data to overlay (location $00)

Write blue data to overlay (location $00)

Write red data to overlay (location $01)

Write green data to overlay (location $01)

Write blue data to overlay (location $01)

:

01

00

11

:

Write red data to overlay (location $03)

Write green data to overlay (location $03)

Write blue data to overlay (location $03)

11

4-10

Conexant

L45801 Rev. N

5

5.0 Parametric Information

5.1 DC Electrical Parameters

Table 5-1. Recommended Operating Conditions

Parameter

Power Supply

Symbol

Min

Typ

Max

Units

VAA

TA

4.75

0

5.00

—

5.25

+70

—

V

°C

Ω

V

Ambient Operating Temperature

Output Load

RL

—

37.5

1.235

523

Reference Voltage

VREF

RSET

1.20

—

1.26

—

FS ADJUST Resistor

Ω

L45801 Rev. N

Conexant

5-1

5.0 Parametric Information

Bt457/Bt458

5.1 DC Electrical Parameters

125 MHz/135 MHz/165 MHz Monolithic CMOS 256 Color Palette RAMDAC

Table 5-2. Absolute Maximum Ratings

Parameter

Symbol

Min

Typ

Max

Units

VAA (Measured to GND)

—

GND–0.5

—

7.0

VAA +0.5

—

V

Voltage on Any Signal Pin⁽¹⁾

Analog Output Short-Circuit Duration to

Any Power Supply or Common

ISC

Indefinite

—

Ambient Operating Temperature

Storage Temperature

Junction Temperature

Ceramic Package

TA

TS

—

–55

–65

—

°C

+125

+150

+175

+150

260

TJ

—

Plastic Package

—

Soldering Temperature

TSOL

—

(5 Seconds, 1/4” from Pin)

Vapor Phase Soldering (1 Minute)

TVSOL

—

220

°C

NOTE(S):

(1)

This device uses high-impedance CMOS devices on all signal pins. It should be handled as an ESD-sensitive device. Voltage

on any signal pin that exceeds the power supply voltage by more than +0.5 V can induce destructive latchup.

2. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress

rating only, and functional operation of the device at these or any other conditions above those listed in the operational

sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may

affect device reliability.

5-2

Conexant

L45801 Rev. N

Bt457/Bt458

5.0 Parametric Information

125 MHz/135 MHz/165 MHz Monolithic CMOS 256 Color Palette RAMDAC

5.1 DC Electrical Parameters

Table 5-3. DC Characteristics (1 of 2)

Parameter

Symbol

Min

Typ

Max

Units

Analog Outputs

—

8 (4)

—

8 (4)

—

8 (4)

—

Resolution (Each DAC)

Accuracy (Each DAC)

Bits

—

Integral Linearity Error

IL

—

1 (1/8)

1 (1/16)

5

LSB

Differential Linearity Error

Gray-Scale Error

DL

—

LSB

—

%Gray Scale

Monotonicity

—

Guaranteed

—

Binary

—

V

Coding

—

Digital Inputs (Except CLOCK, CLOCK*)

Input High Voltage

—

VIH

VIL

IIH

IIL

2.0

GND – 0.5

—

VAA + 0.5

0.8

1

Input Low Voltage

—

V

Input High Current (Vin = 4.0 V)

Input Low Current (Vin = 0.4 V)

Input Capacitance (f = 1 MHz, Vin = 2.4 V)

Clock Inputs (CLOCK, CLOCK*)

Differential Input Voltage

Input High Current (Vin = 4.0 V)

Input Low Current (Vin = 0.4 V)

Input Capacitance (f = 1 MHz, Vin = 4.0 V)

Digital Outputs D[7:0]

—

µA

pF

—

–1

CIN

—

4

10

—

V

VIN

IKIH

IIKIL

CKIN

—

0.6

—

6

—

1

µA

pF

—

–1

—

4

10

—

V

Output High Voltage (IOH = –800 µA)

Output Low Voltage (IOL = 6.4 mA)

3-State Current

VOH

VOL

IOZ

CDOUT

—

2.4

—

0.4

10

V

—

µA

pF

Output Capacitance

—

10

—

Analog Outputs

—

mA

µA

mA

µA

—

Output Current

—

White Level Relative to Blank

White Level Relative Black

Black Level Relative to Blank

Blank Level on IOR, IOB

Blank Level on IOG or IOUT

Sync Level on IOG or IOUT

LSB Size

—

17.69

16.74

0.95

0

19.05

17.62

1.44

5

20.40

18.50

1.90

50

—

6.29

0

7.62

5

8.96

50

—

L45801 Rev. N

Conexant

5-3

5.0 Parametric Information

Bt457/Bt458

5.1 DC Electrical Parameters

125 MHz/135 MHz/165 MHz Monolithic CMOS 256 Color Palette RAMDAC

Table 5-3. DC Characteristics (2 of 2)

Parameter

Symbol

Min

Typ

Max

Units

Bt457, Bt458

—

69.1

2

—

5

µA

%

DA0-to-DAC Matching⁽¹⁾

Output Compliance

Output Impedance

VOC

–0.5

—

50

13

+1.2

—

V

RAOUT

CAOUT

kΩ

pF

Output Capacitance

—

20

(f = 1 MHz, IOUT = 0 mA)

Voltage Reference Input Current

IREF

—

10

—

µA

Power Supply Rejection Ratio

(COMP = 0.1 µF, f = 1 kHz)

PSRR

0.5

% / %∆ VAA

NOTE(S):

(1)

Does not apply to the Bt457.

2. Test conditions (unless otherwise specified): “Recommended Operating Conditions” with RSET = 523 Ω and VREF = 1.235 V.

As the parameters are guaranteed over the full temperature range, temperature coefficients are not specified or required.

Typical values are based on nominal temperature, i.e., room temperature, and nominal voltage, i.e., 5 V.

5-4

Conexant

L45801 Rev. N

Bt457/Bt458

5.0 Parametric Information

125 MHz/135 MHz/165 MHz Monolithic CMOS 256 Color Palette RAMDAC

5.2 AC Electrical Parameters

Table 5-4. AC Characteristics for 165 MHz and 135 MHz Devices (1 of 2)

165 MHz Devices

135 MHz Devices

Min Typ Max

Parameter

Symbol

Min

Typ

Max

Units

Clock Rate

LD* Rate

Fmax

LDmax

1

—

0

—

12

2

165

41.25

—

75

15

—

8

—

0

—

12

2

135

33.75

—

75

15

—

8

MHz

ns

R/W, C0, C1 Setup Time

R/W, C0, C1 Hold Time

CE* Low Tiime

2

15

50

25

7

15

50

25

7

ns

3

ns

CE* High Time

4

ns

CE* Asserted to Data Bus Driven

CE* Asserted to Data Valid

CE* Negated to Data Bus 3-Stated

Write Data Setup Time

Write Data Hold Time

5

ns

6

—

35

3

—

35

3

ns

7

ns

8

ns

9

ns

Pixel and Control Setup Time

Pixel and Control Hold Time

Clock Cycle Time

10

11

12

13

14

15

16

17

18

19

20

—

3

ns

2

ns

6.06

2.6

24.24

10

—

6

7.4

3

ns

Clock Pulse Width High Time

Clock Pulse Width Low Time

LD* Cycle Time

ns

3

ns

29.63

12

—

ns

LD* Pulse Width High Time

LD* Pulse Width Low Time

Analog Output Delay

ns

Analog Output Rise/Fall Time

Analog Output Settling Time

Clock and Data Feedthrough⁽¹⁾

Glitch Impulse⁽¹⁾

ns

—

35

50

0

—

35

50

0

ns

—

2

—

2

pV–sec

ns

Analog Output Skew⁽²⁾

Pipeline Delay

—

10

—

Clocks

L45801 Rev. N

Conexant

5-5

5.0 Parametric Information

Bt457/Bt458

5.2 AC Electrical Parameters

125 MHz/135 MHz/165 MHz Monolithic CMOS 256 Color Palette RAMDAC

Table 5-4. AC Characteristics for 165 MHz and 135 MHz Devices (2 of 2)

165 MHz Devices

135 MHz Devices

Parameter

Symbol

Min

Typ

Max

Min

Typ

Max

Units

VAA Supply Current⁽³⁾

IAA

—

310

n/a

—

370

n/a

—

mA

Bt458

Bt457

235

207

340

257

—

NOTE(S):

(1)

Clock and data feedthrough is a function of the number of edge rates and the amount of overshoot and undershoot on the

digital inputs. For this test, the TTL digital inputs have a 1 k Ω resistor to GND and are driven by 74HC logic. Settling time

does not include clock and data feedthrough. Glitch impulse includes clock and data feedthrough, and –3 dB test

bandwidth = 2x clock rate.

Does not apply to the Bt457.

At Fmax. IAA (typ) at VAA = 5.0 V and TA = 20° C. IAA (max) at VAA = 5.25 V and TA = 0° C.

(2)

(3)

4. Test conditions (unless otherwise specified): "Recommended Operating Conditions" with RSET = 523 Ω and VREF = 1.235 V.

TTL input values are 0–3 V with input rise/fall times ≤ 4 ns, measured between the 10% and 90% points. ECL input values are

VAA–0.8 to VAA–1.8 V with input rise/fall times ≤ 2 ns, measured between the 20% and 80% points. Timing reference points

at 50% for inputs and outputs. Analog output load ≤ 10 pF and D[7:0] output load ≤ 75 pF. See timing notes in Figure 5-1. As

the above parameters are guaranteed over the full temperature range, temperature coefficients are not specified or required.

Typical values are based on nominal temperature, i.e., room temperature, and nominal voltage, i.e., 5 V.

5-6

Conexant

L45801 Rev. N

Bt457/Bt458

5.0 Parametric Information

125 MHz/135 MHz/165 MHz Monolithic CMOS 256 Color Palette RAMDAC

5.2 AC Electrical Parameters

Table 5-5. AC Characteristics for 125 MHz and 110 MHz Devices (1 of 2)

125 MHz Devices

110 MHz Devices

Min Typ Max

Parameter

Symbol

Min

Typ

Max

Units

Clock Rate

LD* Rate

Fmax

LDmax

1

—

0

—

12

2

125

31.25

—

75

15

—

8

—

0

—

12

2

110

27.5

—

75

15

—

8

MHz

ns

R/W, C0, C1 Setup Time

R/W, C0, C1 Hold Time

CE* Low Time

2

15

50

25

7

15

50

25

7

ns

3

ns

CE* High Time

4

ns

CE* Asserted to Data Bus Driven

CE* Asserted to Data Valid

CE* Negated to Data Bus 3-Stated

Write Data Setup Time

Write Data Hold Time

5

ns

6

—

35

3

—

35

3

ns

7

ns

8

ns

9

ns

Pixel and Control Setup Time

Pixel and Control Hold Time

Clock Cycle Time

10

11

12

13

14

15

16

17

18

19

20

—

3

ns

2

ns

8

9.09

4

ns

Clock Pulse Width High Time

Clock Pulse Width Low Time

LD* Cycle Time

3.2

13

—

6

ns

4

ns

36.36

15

—

6

ns

LD* Pulse Width High Time

LD* Pulse Width Low Time

Analog Output Delay

ns

Analog Output Rise/Fall Time

Analog Output Settling Time

Clock and Data Feedthrough⁽¹⁾

Glitch Impulse⁽¹⁾

ns

—

35

50

0

—

35

50

0

ns

—

2

—

2

pV–sec

ns

Analog Output Skew⁽²⁾

Pipeline Delay

—

10

—

10

Clocks

L45801 Rev. N

Conexant

5-7

5.0 Parametric Information

Bt457/Bt458

5.2 AC Electrical Parameters

125 MHz/135 MHz/165 MHz Monolithic CMOS 256 Color Palette RAMDAC

Table 5-5. AC Characteristics for 125 MHz and 110 MHz Devices (2 of 2)

125 MHz Devices

110 MHz Devices

Parameter

Symbol

Min

Typ

Max

Min

Typ

Max

Units

VAA Supply Current⁽³⁾

IAA

—

mA

Bt458

Bt457

225

200

330

250

210

190

315

240

—

NOTE(S):

(1)

Clock and data feedthrough is a function of the number of edge rates and the amount of overshoot and undershoot on the

digital inputs. For this test, the TTL digital inputs have a 1 k Ω resistor to GND and are driven by 74HC logic. Settling time

does not include clock and data feedthrough. Glitch impulse includes clock and data feedthrough, and –3 dB test

bandwidth = 2x clock rate.

Does not apply to the Bt457.

At Fmax. IAA (typ) at VAA = 5.0 V and TA = 20° C. IAA (max) at VAA = 5.25 V and TA = 0° C.

(2)

(3)

4. Test conditions (unless otherwise specified): "Recommended Operating Conditions" with RSET = 523 Ω and VREF = 1.235 V.

TTL input values are 0–3 V with input rise/fall times ≤ 4 ns, measured between the 10% and 90% points. ECL input values are

VAA–0.8 to VAA–1.8 V with input rise/fall times ≤ 2 ns, measured between the 20% and 80% points. Timing reference points

at 50% for inputs and outputs. Analog output load ≤ 10 pF and D[7:0] output load ≤ 75 pF. See timing notes in Figure 5-1. As

the above parameters are guaranteed over the full temperature range, temperature coefficients are not specified or required.

Typical values are based on nominal temperature, i.e., room temperature, and nominal voltage, i.e., 5 V.

5-8

Conexant

L45801 Rev. N

Bt457/Bt458

5.0 Parametric Information

125 MHz/135 MHz/165 MHz Monolithic CMOS 256 Color Palette RAMDAC

5.2 AC Electrical Parameters

Table 5-6. AC Characteristics for 80 MHz Device (1 of 2)

80 MHz Devices

Parameter

Symbol

Min

Typ

Max

Units

Clock Rate

LD* Rate

Fmax

LDmax

1

—

0

—

12

2

80

20

—

75

15

—

8

MHz

ns

R/W, C0, C1 Setup Time

R/W, C0, C1 Hold Time

CE* Low Time

2

15

50

25

7

ns

3

ns

CE* High Time

4

ns

CE* Asserted to Data Bus Driven

CE* Asserted to Data Valid

CE* Negated to Data Bus 3-Stated

Write Data Setup Time

Write Data Hold Time

5

ns

6

—

35

3

ns

7

ns

8

ns

9

ns

Pixel and Control Setup Time

Pixel and Control Hold Time

Clock Cycle Time

10

11

12

13

14

15

16

17

18

19

20

—

4

ns

2

ns

12.5

5

ns

Clock Pulse Width High Time

Clock Pulse Width Low Time

LD* Cycle Time

ns

5

ns

50

20

—

6

ns

LD* Pulse Width High Time

LD* Pulse Width Low Time

Analog Output Delay

ns

Analog Output Rise/Fall Time

Analog Output Settling Time

Clock and Data Feedthrough⁽¹⁾

Glitch Impulse⁽¹⁾

ns

—

35

50

0

ns

—

2

pV–sec

ns

Analog Output Skew⁽²⁾

Pipeline Delay

—

10

Clocks

L45801 Rev. N

Conexant

5-9

5.0 Parametric Information

Bt457/Bt458

5.2 AC Electrical Parameters

125 MHz/135 MHz/165 MHz Monolithic CMOS 256 Color Palette RAMDAC

Table 5-6. AC Characteristics for 80 MHz Device (2 of 2)

80 MHz Devices

Typ

Parameter

VAA Supply Current⁽³⁾

Symbol

Min

Max

Units

IAA

—

mA

Bt458

Bt457

200

170

285

220

—

NOTE(S):

(1)

Clock and data feedthrough is a function of the number of edge rates and the amount of overshoot and undershoot on the

digital inputs. For this test, the TTL digital inputs have a 1 k Ω resistor to GND and are driven by 74HC logic. Settling time does

not include clock and data feedthrough. Glitch impulse includes clock and data feedthrough, and –3 dB test bandwidth = 2x

clock rate.

Does not apply to the Bt457.

At Fmax. IAA (typ) at VAA = 5.0 V and TA = 20° C. IAA (max) at VAA = 5.25 V and TA = 0° C.

(2)

(3)

4. Test conditions (unless otherwise specified): "Recommended Operating Conditions" with RSET = 523 Ω and VREF = 1.235 V.

TTL input values are 0–3 V with input rise/fall times ≤ 4 ns, measured between the 10% and 90% points. ECL input values are

VAA–0.8 to VAA–1.8 V with input rise/fall times ≤ 2 ns, measured between the 20% and 80% points. Timing reference points

at 50% for inputs and outputs. Analog output load ≤ 10 pF and D[7:0] output load ≤ 75 pF. See timing notes in Figure 5-1. As

the above parameters are guaranteed over the full temperature range, temperature coefficients are not specified or required.

Typical values are based on nominal temperature, i.e., room temperature, and nominal voltage, i.e., 5 V.

5-10

Conexant

L45801 Rev. N

Bt457/Bt458

5.0 Parametric Information

125 MHz/135 MHz/165 MHz Monolithic CMOS 256 Color Palette RAMDAC

5.3 Timing Waveforms

Figure 5-1. Video Input/Output Timing

15

16

17

LD*

P[7:0]{A–E},

OL[1.0]{A–E},

SYNC*, BLANK*

10

20

11

IOR, IOG, IOB

(IOUT–Bt457)

19

12

13

CLOCK

14

NOTE(S):

1. Output delay time is measured from the 50% point of the rising clock edge to the 50% point of full-scale transition.

2. Output settling time is measured from the 50% point of full-scale transition to the output settling within 1 LSB for the

Bt457/458.

3. Output rise/fall time is measured between the 10% and 90% points of full-scale transition.

457-8_010

L45801 Rev. N

Conexant

5-11

5.0 Parametric Information

Bt457/Bt458

5.3 Timing Waveforms

125 MHz/135 MHz/165 MHz Monolithic CMOS 256 Color Palette RAMDAC

Figure 5-2. MPU Read/Write Timing

2

1

VALID

R/W, CO, C1

3

CE*

4

6

5

7

DATA OUT (RW = 1)

DATA IN (RW = 0)

D[7:0](READ)

D[7:0](WRITE)

8

9

457-8_011

5-12

Conexant

L45801 Rev. N

Bt457/Bt458

5.0 Parametric Information

125 MHz/135 MHz/165 MHz Monolithic CMOS 256 Color Palette RAMDAC

5.4 Package Drawing

Figure 5-3. 84-Pin Plastic J-Lead (PLCC)

D

D₁

SEE DETAIL "A"

.042

.048

.042

.056

X 45 º

.056 BSC.

D₂

E₂

D₃

E₃

E E₁

D₂

E₂

A₁

A

.025/.045 R.

S

Y

M

INCHES

MIN. NOM. MAX.

MILLIMETERS

MIN. NOM. MAX.

B

O

L

A

A₁

.165

.090

.200

.130

4.20

2.29

5.08

3.30

.026

.032

D

D₁

D₂.545

D₃

1.185

1.150

1.195 30.10

1.158 29.21

.565 13.84

30.35

29.41

14.35

1.000 REF.

25.40 REF.

.013

.021

E

1.185

1.150

.545

1.195 30.10

1.158 29.21

.565 13.84

30.35

29.41

14.35

E₁

E₂

E₃

1.000 REF.

25.40 REF.

.020 MIN.

DETAIL "A"

NOTE(S):

1. Dimensions are in inches [millimeters].

2. Tolerances are: .xxx 0.005 [0.127].

3. PLCC Packages are intended for surface mounting on solder lands on 0.050 [1.27] centers.

457-8_012

L45801 Rev. N

Conexant

5-13

5.0 Parametric Information

Bt457/Bt458

5.4 Package Drawing

125 MHz/135 MHz/165 MHz Monolithic CMOS 256 Color Palette RAMDAC

Figure 5-4. 84-Pin Ceramic PGA

1.1000 TYP

[27.94]

0.100

0.050 TYP

[1.27]

1.215 SQ

[30.86]

TYP

0.075

[1.91]

[2.54]

PIN NO. 1

IDENTIFIER

NO. 1 INDEX

0.150–0.170

[3.81–4.318]

0.018

[0.457]

DIA

^{SEE DETAIL}A

0.045 [1.143]

0.024 [0.609]

0.050 [1.27]

^DETAILA

4 PL

NOTE(S):

1. Dimensions are in inches [millimeters].

2. Tolerances are: .xxx 0.005 [0.127].

3. Pins are intended for insertion in hole rows on 0.100" [2.54] centers.

457-8_013

5-14

Conexant

L45801 Rev. N

Bt457/Bt458

5.0 Parametric Information

125 MHz/135 MHz/165 MHz Monolithic CMOS 256 Color Palette RAMDAC

5.5 Revision History

Table 5-7. Revision History

Datasheet Revision

Change From Previous Revision

I

Expanded PC Board Layout Considerations section. Changed AC parameter "CE* asserted to

data bus driven" from 10 ns to 7 ns minimum.

J

Changed AC parameter "VAA Supply Current (Max)" for the Bt457: 80 MHz changed from

190 mA to 220 mA, 110 MHz changed from 210 mA to 240 mA, and 125 MHz changed from

220 mA to 250 mA.

K

Changed speed grade from 170 MHz to 165 MHz. Changed PLL feedback circuitry.

Consolidated Bt458 power specifications. Changed AC Characteristics CLOCK, Load Cycle,

and Pulse Width times. Changed typical analog output delay times.

L

M

N

Added 135 MHz speed grade.

Revised PCB Layout section.

Bt451 obsolete.

L45801 Rev. N

Conexant

5-15

5.0 Parametric Information

Bt457/Bt458

5.5 Revision History

125 MHz/135 MHz/165 MHz Monolithic CMOS 256 Color Palette RAMDAC

5-16

Conexant

L45801 Rev. N

0.0 Sales Offices

Further Information

literature@conexant.com

Hong Kong

Phone: (852) 2827 0181

1-800-854-8099 (North America)

33-14-906-3980 (International)

Fax: (852) 2827 6488

India

Web Site

www.conexant.com

Phone: (91 11) 692 4780

Fax: (91 11) 692 4712

Korea

Phone: (82 2) 565 2880

Fax: (82 2) 565 1440

World Headquarters

Conexant Systems, Inc.

4311 Jamboree Road

P. O. Box C

Phone: (82 53) 745 2880

Fax: (82 53) 745 1440

Newport Beach, CA

92658-8902

Phone: (949) 483-4600

Fax: (949) 483-6375

Europe Headquarters

Conexant Systems France

Les Taissounieres B1

1681 Route des Dolines

BP 283

U.S. Florida/South America

Phone: (727) 799-8406

Fax: (727) 799-8306

06905 Sophia Antipolis Cedex

FRANCE

Phone: (33 1) 41 44 36 50

Fax: (33 4) 93 00 33 03

U.S. Los Angeles

Phone: (805) 376-0559

Fax: (805) 376-8180

Europe Central

Phone: (49 89) 829 1320

Fax: (49 89) 834 2734

U.S. Mid-Atlantic

Phone: (215) 244-6784

Fax: (215) 244-9292

Europe Mediterranean

Phone: (39 02) 9317 9911

Fax: (39 02) 9317 9913

U.S. North Central

Phone: (630) 773-3454

Fax: (630) 773-3907

Europe North

Phone: (44 1344) 486 444

Fax: (44 1344) 486 555

U.S. Northeast

Phone: (978) 692-7660

Fax: (978) 692-8185

Europe South

Phone: (33 1) 41 44 36 50

Fax: (33 1) 41 44 36 90

U.S. Northwest/Pacific West

Phone: (408) 249-9696

Fax: (408) 249-7113

Middle East Headquarters

Conexant Systems

Commercial (Israel) Ltd.

P. O. Box 12660

U.S. South Central

Phone: (972) 733-0723

Fax: (972) 407-0639

Herzlia 46733, ISRAEL

Phone: (972 9) 952 4064

Fax: (972 9) 951 3924

U.S. Southeast

Phone: (919) 858-9110

Fax: (919) 858-8669

Japan Headquarters

Conexant Systems Japan Co., Ltd.

Shimomoto Building

1-46-3 Hatsudai,

U.S. Southwest

Phone: (949) 483-9119

Fax: (949) 483-9090

Shibuya-ku, Tokyo

151-0061 JAPAN

Phone: (81 3) 5371-1567

Fax: (81 3) 5371-1501

APAC Headquarters

Conexant Systems Singapore, Pte.

Ltd.

1 Kim Seng Promenade

Great World City

#09-01 East Tower

SINGAPORE 237994

Phone: (65) 737 7355

Fax: (65) 737 9077

Taiwan Headquarters

Conexant Systems, Taiwan Co., Ltd.

Room 2808

International Trade Building

333 Keelung Road, Section 1

Taipei 110, TAIWAN, ROC

Phone: (886 2) 2720 0282

Fax: (886 2) 2757 6760

Australia

Phone: (61 2) 9869 4088

Fax: (61 2) 9869 4077

China

Phone: (86 2) 6361 2515

Fax: (86 2) 6361 2516


型号：	BT457KG80
厂家：	ETC
描述：	Video DAC with Color Palette (RAMDAC) 视频DAC与调色板（ RAMDAC ）\n 转换器
文件：	总60页 (文件大小：611K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

BT457KG80 [ETC]

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