BU-61580_技术文档

BU-65170/61580 and BU-61585

MIL-STD-1553A/B NOTICE 2 RT and BC/RT/MT,

ADVANCED COMMUNICATION ENGINE (ACE)

ACE User’s Guide

FEATURES

Also Available

Fully Integrated MIL-STD-1553

Interface Terminal

•

DESCRIPTION

DDC's BU-65170, BU-61580 and configured as 12K x 16 or 8K x 17.

BU-61585 Bus Controller / Remote The 8K x 17 RAM feature provides

Flexible Processor/Memory

Interface

•

Terminal

/

Monitor

Terminal capability for memory integrity check-

(BC/RT/MT)

A d v a n c e d ing by implementing RAM parity gen-

Communication Engine (ACE) termi- eration and verification on all access-

nals comprise a complete integrated es. To minimize board space and

interface between a host processor “glue” logic, the ACE provides ultimate

and a MIL-STD-1553 A and B or flexibility in interfacing to a host

Standard 4K x 16 RAM and

Optional 12K x 16 or 8K x 17 RAM

Available

STANAG 3838 bus.

processor and internal/external RAM.

Optional RAM Parity

Generation/Checking

•

The ACE series is packaged in a 1.9 - The advanced functional architecture

square-inch, 70-pin, low-profile, of the ACE terminals provides soft-

cofired MultiChip Module (MCM) ware

ceramic package that is well suited for Advanced Integrated Multiplexer (AIM)

applications with stringent height series hybrids, while incorporating a

compatibility

to

DDC's

Automatic BC Retries

•

Programmable BC Gap Times

BC Frame Auto-Repeat

requirements.

multiplicity of architectural enhance-

ments. It allows flexible operation

while off-loading the host processor,

ensuring data sample consistency,

and supports bulk data transfers.

The BU-61585 ACE integrates dual

transceiver, protocol, memory man-

agement, processor interface logic,

and a total of 12K words of RAM in a

Flexible RT Data Buffering

Programmable Illegalization

Selective Message Monitor

Simultaneous RT/Monitor Mode

choice of DIP or flat pack packages. The ACE hybrids may be operated at

The BU-61585 requires +5 V power either 12 or 16 MHz. Wire bond

and either -15 V or -12 V power. options allow for programmable RT

address (hardwired is standard) and

The BU-61585 internal RAM can be external transmitter inhibit inputs.

TX/RX_A

SHARED

*

RAM

TRANSCEIVER

A

CH. A

DATA

BUFFERS

PROCESSOR

D15-D0

DATA BUS

TX/RX_A

TX/RX_B

DUAL

ENCODER/DECODER,

MULTIPROTOCOL

AND

MEMORY

MANAGEMENT

ADDRESS

BUFFERS

PROCESSOR

ADDRESS BUS

A15-A0

ADDRESS BUS

TRANSCEIVER

B

CH. B

TX/RX_B

TRANSPARENT/BUFFERED, STRBD, SELECT,

RD/WR, MEM/REG, TRIGGER_SEL/MEMENA-IN,

MSB/LSB/DTGRT

PROCESSOR

AND

MEMORY

INTERFACE

LOGIC

PROCESSOR

AND

MEMORY

CONTROL

RT ADDRESS

RTAD4-RTAD0, RTADP

INCMD

IOEN, MEMENA-OUT, READYD

ADDR_LAT/MEMOE, ZERO_WAIT/MEMWR,

8/16-BIT/DTREQ, POLARITY_SEL/DTACK

INT

INTERRUPT

REQUEST

CLK_IN, TAG_CLK,

MSTCLR,SSFLAG/EXT_TRG

MISCELLANEOUS

* SEE ORDERING INFORMATION FOR AVAILABLE MEMORY

FIGURE 1. ACE BLOCK DIAGRAM

1992, 1999 Data Device Corporation

©

TABLE 1. “ACE” SERIES SPECIFICATIONS (CONTD)

PARAMETER MIN TYP MAX UNITS

LOGIC (cont’d)

TABLE 1. “ACE” SERIES SPECIFICATIONS

PARAMETER

MIN

TYP

MAX

UNITS

ABSOLUTE MAXIMUM RATING

Supply Voltage

! Logic +5V

! INCMD, INT MEMENA_OUT,

READYD, IOEN, TXA, TXA,

TXB, TXB, TX_INH_OUT_A,

TX_INH_OUT_B,

3.2

mA

-0.3

-18.0

7.0

0.3

V

! Transceiver +5V

! -15V

IOH

! -12V

! DB15-DB0, A15-A0, MEMOE/

ADDR_LAT, MEMWR/

-6.4

-3.2

mA

Logic

! Voltage Input Range

-0.3

Vcc+0.3

V

ZEROWAIT, DTREQ/16/8,

DTACK/POLARITY_SEL

! INCMD, INT, MEMENA_OUT,

READYD, IOEN, TXA, TXA,

TXB, TXB, TX_INH_OUT_A,

TX_INH_OUT_B,

CI (Input Capacitance)

CIO (Bi-directional signal input

capacitance)

RECEIVER

Differential Input Resistance

! (BU-65170/61580/61585X1,

BU-65170/61580/61585X2)

(Notes 1-7)

! (BU-65170/61580/61585X3,

BU-65170/61580/61585X6)

(Notes 1-7)

Differential Input Capacitance

! (BU-65170/61580/61585X1,

BU-65170/61580/61585X2)

(Notes 1-7)

! (BU-65170/61580/61585X3,

BU-65170/61580/61585X6)

(Notes 1-7)

11

kΩ

2.5

50

pF

POWER SUPPLY REQUIREMENTS

Voltages/Tolerances

10

5

pF

! BU-65170/61580/61585X1

• +5V (Logic)

• +5V (Ch. A, Ch. B)

• -15V (Ch. A, Ch. B)

! BU-65170/61580/61585X2

• +5V (Logic)

• +5V (Ch. A, Ch. B)

• -12V (Ch. A, Ch. B)

! BU-65170/61580/61585X3,

BU-65170/61580/61585X6

• +5V (Logic)

4.5

5.0

5.5

V

-15.75 -15.0 -14.25

Threshold Voltage, Transformer

Coupled, Measured on Stub

Common Mode Voltage (Note 7)

0.200

0.860

10

Vp-p

4.5

5.0

5.5

V

Vpeak

-12.6 -12.0 -11.4

TRANSMITTER

Differential Output Voltage

! Direct Coupled Across 35 Ω,

Measured on Bus

6

7

9

Vp-p

4.5

4.75

5.0

5.5

5.25

mA

• +5V (Ch. A, Ch. B)

! Transformer Coupled Across

70 Ω, Measured on Bus

•(BU-65170/61580/61585X1)

•(BU-65170/61580/61585X2,X3, X6)

Output Noise, Differential (Direct

Coupled)

Output Offset Voltage, Transformer

Coupled Across 70 ohms

Rise/Fall Time

Current Drain (Total Hybrid)

! BU-65170/61580X1

• +5V (Logic, Ch. A, Ch. B)

• -15V (Ch. A, Ch. B)

20

18

27

10

Vp-p

mVp-p,

diff

95

190

mA

• Idle

30

68

105

180

60

mA

• 25% Transmitter Duty Cycle

• 50% Transmitter Duty Cycle

• 100% Transmitter Duty Cycle

! BU-65170/61580X2

• +5V (Logic, Ch. A, Ch. B)

• -12V (Ch. A, Ch. B)

108

160

255

-250

100

250

300

mV

150

nsec

95

190

mA

LOGIC

VIH

VIL

2.0

-10

V

µA

• Idle

30

80

130

230

60

mA

0.8

10

• 25% Transmitter Duty Cycle

• 50% Transmitter Duty Cycle

• 100% Transmitter Duty Cycle

! BU-65170/61580X3,

BU-65170/61580X6

• +5V (Logic, Ch. A, Ch. B)

• Idle

• 25% Transmitter Duty Cycle

• 50% Transmitter Duty Cycle

• 100% Transmitter Duty Cycle

! BU-61585X1

• +5V (Logic, Ch. A, Ch. B)

• -15V (Ch. A, Ch. B)

• Idle

• 25% Transmitter Duty Cycle

• 50% Transmitter Duty Cycle

• 100% Transmitter Duty Cycle

120

185

305

IIH (Vcc=5.5V, VIN=Vcc)

IIH (Vcc=5.5V, VIN=2.7V)

! SSFLAG/EXT_TRIG

! All Other Inputs

IIL (Vcc=5.5V, VIN=0.4V)

! SSFLAG/EXT_TRIG

! All Other Inputs

VOH (Vcc=4.5V, VIH=2.7V,

VIL=0.2V, IOH=max)

VOL (Vcc=4.5V, VIH=2.7V,

VIL=0.2V, IOL=max)

IOL

-692

-346

-84

-42

µA

-794

-397

2.4

-100

-50

µA

V

95

200

350

500

800

mA

245

360

590

0.4

V

105

240

mA

! DB15-DB0, A15-A0, MEMOE/

ADDR_LAT, MEMWR/

ZEROWAIT, DTREQ/16/8,

DTACK/POLARITY_SEL

6.4

mA

30

68

105

180

60

mA

108

160

255

Data Device Corporation

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BU-65170/61580/61585

H1 web-09/02-0

2

TABLE 1. “ACE” SERIES SPECIFICATIONS (CONTD)

PARAMETER MIN TYP MAX UNITS

! BU-61585X2

TABLE 1. “ACE” SERIES SPECIFICATIONS (CONTD)

PARAMETER MIN TYP MAX UNITS

! BU-61585X1

• Idle

0.335 0.68

0.600 1.06

0.860 1.45

1.385 2.23

W

• +5V (Logic, Ch. A, Ch. B)

• -12V (Ch. A, Ch. B)

• Idle

• 25% Transmitter Duty Cycle

• 50% Transmitter Duty Cycle

• 100% Transmitter Duty Cycle

! BU-61585X3,

BU-61585X6

• +5V (Logic, Ch. A, Ch. B)

• Idle

105

240

mA

• 25% Transmitter Duty Cycle

• 50% Transmitter Duty Cycle

• 100% Transmitter Duty Cycle

! BU-61585X2

30

80

130

230

60

mA

120

185

305

• Idle

0.290 0.59

0.590 0.92

0.890 1.36

1.490 2.16

W

• 25% Transmitter Duty Cycle

• 50% Transmitter Duty Cycle

• 100% Transmitter Duty Cycle

! BU-61585X3,

BU-61585X6

• Idle

• 25% Transmitter Duty Cycle

• 50% Transmitter Duty Cycle

• 100% Transmitter Duty Cycle

105

255

370

600

250

400

550

850

mA

• 25% Transmitter Duty Cycle

• 50% Transmitter Duty Cycle

• 100% Transmitter Duty Cycle

0.200 0.25

0.630 0.68

0.885 1.11

1.395 1.97

W

POWER DISSIPATION

Total Hybrid

CLOCK INPUT

Frequency

! BU-65170/61580X1

• Idle

0.850 1.85

1.195 2.25

1.450 2.72

1.975 3.52

W

! Nominal Value (programmable)

• Default Mode

• Software Programmable Option

! Long Term Tolerance

• 1553A Mode

• 1553B Mode

! Short Term Tolerance, 1 second

• 1553A Mode

• 25% Transmitter Duty Cycle

• 50% Transmitter Duty Cycle

• 100% Transmitter Duty Cycle

! BU-65170/61580X2

• Idle

• 25% Transmitter Duty Cycle

• 50% Transmitter Duty Cycle

• 100% Transmitter Duty Cycle

! BU-65170/61580X3,

BU-65170/61580X6

16.0

12.0

MHz

0.01

0.1

%

0.835 1.67

1.135 2.10

1.435 2.59

2.035 3.46

W

0.001

0.01

%

• 1553B Mode

! Duty Cycle

• 16 MHz

• 12 MHz

33

40

67

60

%

• Idle

0.475 1.00

0.905 1.43

1.160 1.86

1.670 2.72

W

• 25% Transmitter Duty Cycle

• 50% Transmitter Duty Cycle

• 100% Transmitter Duty Cycle

! BU-61585X1

1553 MESSAGE TIMING

Completion of CPU Write (BC Start)-

to-Start of Next Message

BC Intermessage Gap (Note 8)

BC/RT/MT Response Timeout (Note 9)

! 18.5 nominal

! 22.5 nominal

! 50.5 nominal

! 128.0 nominal

RT Response Timeout (Note 11)

Transmitter Watchdog Timeout

2.5

9.5

µs

• Idle

0.900 2.10

1.245 2.50

1.500 2.97

2.025 3.77

W

• 25% Transmitter Duty Cycle

• 50% Transmitter Duty Cycle

• 100% Transmitter Duty Cycle

! BU-61585X2

17.5 18.5 19.5

21.5 22.5 23.5

49.5 50.5 51.5

127 129.5 131

µs

• Idle

0.885 1.92

1.185 2.35

1.485 2.84

2.085 3.71

W

• 25% Transmitter Duty Cycle

• 50% Transmitter Duty Cycle

• 100% Transmitter Duty Cycle

! BU-61585X3,

BU-61585X6

• Idle

4

7

668

THERMAL

Thermal Resistance, Junction-to-Case,

Hottest Die (θJC)

! BU-65170/61580/61585X1,

BU-65170/61580/61585X2,

! BU-65170/61580/61585X3,

BU-65170/61580/61585X6

Operating Junction Temperature

Storage Temperature

0.525 1.25

0.955 1.68

1.210 2.11

1.720 2.97

W

6.99 °C/W

• 25% Transmitter Duty Cycle

• 50% Transmitter Duty Cycle

• 100% Transmitter Duty Cycle

Hottest Die

! BU-65170/61580X1

• Idle

• 25% Transmitter Duty Cycle

• 50% Transmitter Duty Cycle

• 100% Transmitter Duty Cycle

! BU-65170/61580X2

• Idle

• 25% Transmitter Duty Cycle

• 50% Transmitter Duty Cycle

• 100% Transmitter Duty Cycle

! BU-65170/61580X3,

BU-65170/61580X6

6.8

°C/W

-55

-65

150

+300

°C

0.335 0.68

0.600 1.06

0.860 1.45

1.385 2.23

W

Lead Temperature (soldering, 10 sec.)

PHYSICAL CHARACTERISTICS

Size

! BU-65170/61580/61585 S

1.9 X 1.0 X 0.165

in.

0.290 0.59

0.590 0.92

0.890 1.36

1.490 2.16

W

(48.3 x 25.4 x 4.19) (mm)

1.9 X 1.0 X 0.150 in.

(48.3 x 25.4 x 3.81) (mm)

! BU-65170/61580/61585 V

Weight

! BU-65170/61580/61585 S/V

0.6 (17)

oz (g)

• Idle

0.200 0.25

0.630 0.68

0.885 1.11

1.395 1.97

W

• 25% Transmitter Duty Cycle

• 50% Transmitter Duty Cycle

• 100% Transmitter Duty Cycle

Data Device Corporation

www.ddc-web.com

BU-65170/61580/61585

H1 web-09/02-0

3

Notes for Table 1: Notes 1 through 6 are applicable to the Receiver

Differential Resistance and Differential Capacitance specifications:

(1) Specifications include both transmitter and receiver (tied together

internally).

are programmable by subaddress. These features serve to

ensure data consistency and to off-load the host processor for

bulk data transfer applications.

(2) Measurement of impedance is directly between pins TX/RX A(B)

and TX/RX A(B) of the BU-65170/61580XX hybrid.

(3) Assuming the connection of all power and ground inputs to the

hybrid.

(4) The specifications are applicable for both unpowered and powered

conditions.

(5) The specifications assume a 2 volt rms balanced, differential, sinu-

soidal input. The applicable frequency range is 75 kHz to 1 MHz.

(6) Minimum resistance and maximum capacitance parameters are

guaranteed,but not tested, over the operating range.

(7) Assumes a common mode voltage within the frequency range of dc

to 2MHz, applied to pins of the isolation transformer on the stub

side (either direct or transformer coupled), referenced to hybrid

ground. Use a DDC recommended transformer or other transformer

that provides an equivalent minimum CMRR.

(8) Typical value for minimum intermessage gap time. Under software

control, may be lengthened to (65,535µs minus message time), in

increments of 1µs.

(9) Software programmable (4 options). Includes RT-to-RT Timeout

(Mid-Parity of Transmit Command to Mid-Sync of Transmitting RT

Status).

(10) For both +5V logic and transceiver. +5V for channels A and B.

(11) Measured from mid-parity crossing of Command Word to mid-sync

crossing of RT's Status Word.

(12) Specifications for BU-65171, BU-61581, and BU-61586 are identi-

cal to the specifications for the BU-65170, BU-61580, and BU-

61585 respectively.

The ACE series implements three monitor modes: a word moni-

tor, a selective message monitor, and a combined RT/selective

monitor. Other features include options for automatic retries and

programmable intermessage gap for BC mode, an internal Time

Tag Register, an Interrupt Status Register and internal command

illegalization for RT mode.

FUNCTIONAL OVERVIEW

TRANSCEIVERS

The transceivers in the BU-65170/61580X3(X6) are fully mono-

lithic, requiring only a +5 volt power input. Besides eliminating

the need for an additional power supply, the use of a 5 volt (only)

transceiver requires the use of step-up, rather than step-down,

isolation transformers. This provides the advantage of a higher

terminal input impedance than is possible for a 15 volt or 12 volt

transmitter. As a result, there is greater margin for the input

impedance test, mandated for 1553 validation testing. This

allows for longer cable lengths between an LRU's system con-

nector and the isolation transformers of an embedded 1553 ter-

minal.

For the +5 V and -15 V/-12 V front end, the BU-65170/

61580X1(X2) uses low-power bipolar analog monolithic and

thick-film hybrid technology. The transceiver requires +5 V and -

15 V (-12 V) only (requiring no +15 V/+12 V) and includes volt-

age source transmitters. The voltage source transmitters provide

superior line driving capability for long cables and heavy

amounts of bus loading. In addition, the monolithic transceivers

in the BU-65170/61580X1 provide a minimum stub voltage level

of 20 volts peak-to-peak transformer coupled, making them suit-

able for MIL-STD-1760 applications.

INTRODUCTION

DDC's ACE series of Integrated BC/RT/MT hybrids provide a

complete, flexible interface between a microprocessor and a

MIL-STD-1553A, B Notice 2, McAir, or STANAG 3838 bus,

implementing Bus Controller, Remote Terminal (RT) and Monitor

Terminal (MT) modes. Packaged in a single 1.9-square-inch,

70-pin DIP or surface mountable flatpack or J-lead package, the

ACE series contains dual low-power transceivers and

encoder/decoders, complete BC/RT/MT multi-protocol logic,

memory management and interrupt logic, 4K x 16 of shared sta-

tic RAM and a direct, buffered interface to a host processor bus.

The receiver sections of the BU-65170/61580 are fully compliant

with MIL-STD-1553B in terms of front end overvoltage protec-

tion, threshold, common mode rejection, and word error rate. In

addition, the receiver filters have been designed for optimal oper-

ation with the J´ chip's Manchester II decoders.

The BU-65170/61580 contains internal address latches and bidi-

rectional data buffers to provide a direct interface to a host

processor bus. The BU-65170/61580 may be interfaced directly

to both 16-bit and 8-bit microprocessors in a buffered shared

RAM configuration. In addition, the ACE may connect to a 16-bit

processor bus via a Direct Memory Access (DMA) interface. The

BU-65170/61580 includes 4K words of buffered RAM.

Alternatively, the ACE may be interfaced to as much as 64K

words of external RAM in either the shared RAM or DMA config-

urations.

J´ DIGITAL MONOLITHIC

The J´ digital monolithic represents the cornerstone element of

the ACE family of terminals. The development of the J´ chip rep-

resents the fifth generation of 1553 protocol and interface design

for DDC. Over the years, DDC's 1553 protocol and interface

design has evolved from: (1) discrete component sets, consisting

of multiple hybrids (with large numbers of chips inside the indi-

vidual hybrids) and programmable logic devices, to (2) multiple

custom ASICs to perform the functions of encoder/decoder and

RT protocol within a single hybrid, to (3) the BUS-61553

Advanced Integrated Mux Hybrid (AIM-HY) series, containing, in

addition to a dual monolithic/thick-film transceiver and discrete

RAM chips, a custom protocol chip and a separate custom mem-

ory management/processor interface chip, to (4) the BUS-61559

Advanced Integrated Mux Hybrids with Enhanced RT Features

(AIM-HY'er — the AIM-HY'er series includes memory manage-

ment and processor interface functions beyond those of the AIM-

HY series) , to (5) the full integration of the J´ chip.

The ACE RT mode is multiprotocol, supporting MIL-STD-1553A,

MIL-STD-1553B Notice 2, STANAG 3838 (including EFAbus),

and the McAir A3818, A5232, and A5690 protocols. Full compli-

ance to the McAir specs, however, requires the use of a sinu-

soidal transceiver (transceiver option 5). Refer to the BU-61590

data sheet for additional information on McAir terminals.

The memory management scheme for RT mode provides an

option for separation of broadcast data, in compliance with

1553B Notice 2. Both double buffer and circular buffer options

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The J´ chip consists of a dual encoder/decoder, complete proto-

col for Bus Controller (BC), 1553A/B/McAir Remote Terminal

(RT), and Monitor (MT) modes; memory management and inter-

rupt logic; a flexible, buffered interface to a host processor bus

and optional external RAM; and 4K words of on-chip RAM.

Reference the region within the dotted line of FIGURE 1. Besides

realizing all the protocol, memory management, and interface

functions of the earlier AIM-HY'er series, the J´ chip includes a

large number of enhancements to facilitate hardware and soft-

ware design, and to further off-load the 1553 terminal's host

processor.

put pin (INT) has three software programmable modes of oper-

ation: a pulse, a level output cleared under software control, or a

level output automatically cleared following a read of the

Interrupt Status Register.

Individual interrupts are enabled by the Interrupt Mask Register.

The host processor may easily determine the cause of the inter-

rupt by using the Interrupt Status Register. The Interrupt Status

Register provides the current state of the interrupt conditions.

The Interrupt Status Register may be updated in two ways. In the

standard interrupt handling mode, a particular bit in the Interrupt

Status Register will be updated only if the condition exists and

the corresponding bit in the Interrupt Mask Register is enabled.

In the enhanced interrupt handling mode, a particular bit in the

Interrupt Status Register will be updated if the condition exists

regardless of the contents of the corresponding Interrupt Mask

Register bit. In any case, the respective Interrupt Mask Register

bit enables an interrupt for a particular condition.

DECODERS

The default mode of operation for the BU-65170 RT and BU-

61580 BC/RT/MT requires a 16 MHz clock input. If needed, a

software programmable option allows the device to be operated

from a 12 MHz clock input. Most current 1553 decoders sample

using a 10 MHz or 12 MHz clock. In the 16 MHz mode (default

following a hardware or software reset), the ACE decoders sam-

ple 1553 serial data using the 16 MHz clock. In the 12 MHz

mode, the decoders sample using both clock edges; this pro-

vides a sampling rate of 24 MHz. The faster sampling rate for the

J´ chip’s Manchester II decoders provides superior performance

in terms of bit error rate and zero-crossing distortion tolerance.

ADDRESSING, INTERNAL REGISTERS, AND

MEMORY MANAGEMENT

The software interface of the BU-65170/61580 to the host

processor consists of 17 internal operational registers for normal

operation, an additional 8 test registers, plus 64K x 16 of shared

memory address space.The BU-65170/61580's 4K x 16 of inter-

nal RAM resides in this address space. Reference TABLE 2 and

24.

For interfacing to fiber optic transceivers for MIL-STD-1773 appli-

cations, a transceiverless version of the J´ chip, the BU-65620,

can be used. These versions provide a pin-programmable option

for a direct interface to the single-ended outputs of a fiber optic

receiver. No external logic is needed.

Definition of the address mapping and accessibility for the ACE's

17 non-test registers, and the test registers, is as follows:

Interrupt Mask Register is used to enable and disable interrupt

requests for various conditions.

TIME TAGGING

The ACE includes an internal read/writable Time Tag Register.

This register is a CPU read/writable 16-bit counter with a pro-

grammable resolution of either 2, 4, 8, 16, 32, or 64 µs per LSB.

Also, the Time Tag Register may be clocked from an external

oscillator. Another option allows software-controlled increment-

ing of the Time Tag Register. This supports self-testing for the

Time Tag Register. For each message processed, the value of

the Time Tag register is loaded into the second location of the

respective descriptor stack entry (“TIME TAG WORD”) for both

BC and RT modes.

Configuration Registers #1 and #2 are used to select the BU-

61580's mode of operation, and for software control of RT Status

Word bits, Active Memory Area, BC Stop-on-Error, RT Memory

Management mode selection, and control of the Time Tag oper-

ation.

Start/Reset Register is used for “command” type functions,

such as software reset, BC/MT Start, Interrupt Reset, Time Tag

Reset, and Time Tag Register Test. The Start/Reset Register

includes provisions for stopping the BC in its auto-repeat mode,

either at the end of the current message or at the end of the cur-

rent BC frame.

Additional provided options will: clear the Time Tag Register fol-

lowing a Synchronize (without data) mode command or load the

Time Tag Register following a Synchronize (with data) mode

command; enable an interrupt request and a bit setting in the

Interrupt Status Register when the Time Tag Register rolls over

from 0000 to FFFF. Assuming the Time Tag Register is not

loaded or reset, this will occur at approximately 4-second time

intervals, for 64 µs/LSB resolution, down to 131 ms intervals, for

2 µs/LSB resolution.

BC/RT Command Stack Pointer Register allows the host CPU

to determine the pointer location for the current or most recent

message when the BU-61580 is in BC or RT modes.

BC Control Word/RT Subaddress Control Word Register: In

BC mode, it allows host access to the current, or most recent BC

Control Word. The BC Control Word contains bits that select the

active bus and message format, enable off-line self-test, mask-

ing of Status Word bits, enable retries and interrupts, and spec-

ify MIL-STD-1553A or -1553B error handling. In RT mode, this

register allows host access to the current or most recent

Subaddress Control Word. The Subaddress Control Word is

used to select the memory management scheme and enable

interrupts for the current message. The read/write accessibility

can be used as an aid for testing the ACE.

Another programmable option for RT mode is the automatic

clearing of the Service Request Status Word bit following the

ACE's response to a Transmit Vector Word mode command.

INTERRUPTS

The ACE series components provide many programmable

options for interrupt generation and handling. The interrupt out-

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Word and BC Block Status Word, additional Stop-On-Error and Stop-On-

Status Set functions, frame auto-repeat, programmable intermessage

gap times, automatic retries, expanded Status Word Masking, and the

capability to generate interrupts following the completion of any selected

message. For RT mode, the enhanced mode features include the

expanded RT Block Status Word, the combined RT/Selective Message

Monitor mode, internal wrapping of the RTFAIL output signal (from the J´

chip) to the RTFLAG RT Status Word bit, the double buffering scheme for

individual receive (broadcast) subaddresses, and the alternate (fully soft-

ware programmable) RT Status Word. For MT mode, use of the

enhanced mode enables use of the Selective Message Monitor, the com-

bined RT/Selective Monitor modes, and the monitor triggering capability.

TABLE 2. ADDRESS MAPPING

REGISTER

DESCRIPTION/ACCESSIBILITY

ADDRESS LINES

HEX A4 A3 A2 A1 A0

00

01

02

03

0

1

0

1

0

1

Interrupt Mask Register (RD/WR)

Configuration Register #1 (RD/WR)

Configuration Register #2 (RD/WR)

Start/Reset Register (WR)

BC/RT Command Stack Pointer Register

(RD)

03

04

0

1

0

1

0

BC Control Word*/RT Subaddress Control

Word Register (RD/WR)

Data Stack Address Register is used to point to the current address

location in shared RAM used for storing message words (second

Command Words, Data Words, RT Status Words) in the Selective Word

Monitor mode.

05

06

07

08

09

0A

0B

0

1

0

1

0

1

0

1

0

1

0

1

Time Tag Register (RD/WR)

Interrupt Status Register (RD)

Configuration Register #3 (RD/WR)

Configuration Register #4 (RD/WR)

Configuration Register #5 (RD/WR)

Data Stack Address Register (RD)*

BC Frame Time Remaining Register (RD)*

FrameTime Remaining Register provides a read only indication of the

time remaining in the current BC frame. The resolution of this register is

100 µs/LSB.

Message Time Remaining Register provides a read only indication of

the time remaining before the start of the next message in a BC frame.

The resolution of this register is 1 µs/LSB.

BC Time Remaining to Next Message

Register (RD)*

0C

0D

0

1

0

1

BC Frame/RT Last Command/MT Trigger Word Register: In BC

mode, it programs the BC frame time, for use in the frame auto-repeat

mode. The resolution of this register is 100 µs/LSB, with a range of 6.55

seconds; in RT mode, this register stores the current (or most previous)

1553 Command Word processed by the ACE RT; in the Word Monitor

mode, this register specifies a 16-bit Trigger (Command) Word. The

TriggerWord may be used to start or stop the monitor, or to generate inter-

rupts.

BC Frame Time*/RT Last Command/MT

Trigger Word* Register (RD/WR)

0E

0F

10

•

0

1

0

1

0

1

0

1

0

RT Status Word Register (RD)

RT BIT Word Register (RD)

Test Mode Register 0

•

Status Word Register and BIT Word Registers provide read-only indi-

cations of the BU-65170/61580's RT Status and BIT Words.

17

18

•

1

0

1

0

1

0

1

0

Test Mode Register 7

reserved

Test Mode Registers 0-7: These registers may be used to facilitate pro-

duction or maintenance testing of the BU-65170/61580 and systems

incorporating the BU-65170/61580.

•

1F

1

reserved

* Not applicable to BU-65170/61571

TABLE 3. INTERRUPT MASK REGISTER (READ/WRITE 00h)

Time Tag Register maintains the value of a real-time clock. The resolu-

tion of this register is programmable from among 2, 4, 8, 16, 32, and 64

µs/LSB.The TAG_CLK input signal also may cause an external oscillator

to clock the Time Tag Register. Start-of-Message (SOM) and End-of-

Message (EOM) sequences in BC, RT, and Message Monitor modes

cause a write of the current value of the Time Tag Register to the stack

area of RAM.

BIT

DESCRIPTION

15(MSB) RESERVED

14

13

12

11

10

9

RAM PARITY ERROR

BC/RT TRANSMITTER TIMEOUT

BC/RT COMMAND STACK ROLLOVER

MT COMMAND STACK ROLLOVER

MT DATA STACK ROLLOVER

HS FAIL

Interrupt Status Register mirrors the Interrupt Mask Register and con-

tains a Master Interrupt bit. It allows the host processor to determine the

cause of an interrupt request by means of a single READ operation.

8

BC RETRY

7

RT ADDRESS PARITY ERROR

TIME TAG ROLLOVER

6

Configuration Registers #3, #4, and #5 are used to enable many of the

BU-61580's advanced features. These include all the enhanced mode

features;that is, all the functionality beyond that of the previous generation

product, the BUS-61559 Advanced Integrated Mux Hybrid with Enhanced

RT Features (AIM-HY'er).For all three modes, use of the Enhanced Mode

enables the various read-only bits in Configuration Register #1. For BC

mode, the enhanced mode features include the expanded BC Control

5

RT CIRCULAR BUFFER ROLLOVER

BC CONTROL WORD/RT SUBADDRESS CONTROL WORD EOM

BC END OF FRAME

4

3

2

FORMAT ERROR

BC STATUS SET/RT MODE CODE/MT PATTERN TRIGGER

1

0(LSB) END OF MESSAGE

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TABLE 4. CONFIGURATION REGISTER #1 (READ/WRITE 01H)

BC FUNCTION (Bits

11-0 Enhanced Mode Only)

RT WITHOUT ALTERNATE

STATUS

RT WITH ALTERNATE

STATUS (Enhanced Only) (Enhanced mode only bits 12-0)

MONITOR FUNCTION

BIT

15

RT/BC-MT (logic 0)

(logic 1)

(logic 0)

(MSB)

14

MT/BC-RT (logic 0)

(logic 0)

(logic 1)

13

CURRENT AREA B/A

CURRENT AREA A/B

CURRENT AREA B/A

12

MESSAGE STOP-ON-ERROR

MESSAGE MONITOR ENABLED MESSAGE MONITOR

MESSAGE MONITOR ENABLED

(MMT)

ENABLED (MMT)

11

FRAME STOP-ON-ERROR

DYNAMIC BUS CONTROL

ACCEPTANCE

S10

TRIGGER ENABLED WORD

10

9

STATUS SET STOP-ON-MESSAGE BUSY

S09

S08

S07

START-ON-TRIGGER

STOP-ON-TRIGGER

NOT USED

STATUS SET STOP-ON-FRAME

FRAME AUTO-REPEAT

SERVICE REQUEST

SUBSYSTEM FLAG

8

7

EXTERNAL TRIGGER ENABLED

INTERNAL TRIGGER ENABLED

RTFLAG (Enhanced Mode Only) S06

EXTERNAL TRIGGER ENABLED

NOT USED

6

NOT USED

S05

S04

5

INTERMESSAGE GAP TIMER

ENABLED

NOT USED

4

3

2

1

RETRY ENABLED

NOT USED

S03

S02

S01

S00

NOT USED

DOUBLED/SINGLE RETRY

BC ENABLED (Read Only)

NOT USED

MONITOR ENABLED(Read Only)

BC FRAME IN PROGRESS (Read NOT USED

Only)

MONITOR TRIGGERED

(Read Only)

0

BC MESSAGE IN PROGRESS

RT MESSAGE IN PROGRESS

RT MESSAGE IN PROGRESS MONITOR ACTIVE

(LSB) (Read Only)

(Enhanced mode only,Read Only) (Read Only)

(Read Only)

TABLE 6. START/RESET REGISTER (WRITE 03H)

TABLE 5. CONFIGURATION REGISTER #2 (READ/WRITE 02h)

BIT

DESCRIPTION

BIT

DESCRIPTION

RESERVED

15(MSB)

15(MSB) ENHANCED INTERRUPTS

•

RAM PARITY ENABLE (BU-61585/6 AND BU-65621 ONLY)

14

•

13

BUSY LOOKUP TABLE ENABLE

RX SA DOUBLE BUFFER ENABLE

OVERWRITE INVALID DATA

•

12

11

7

RESERVED

10

256-WORD BOUNDARY DISABLE

TIME TAG RESOLUTION 2(TTR2)

TIME TAG RESOLUTION 1 (TTR1)

TIME TAG RESOLUTION 0 (TTR0)

CLEAR TIME TAG ON SYNCHRONIZE

LOAD TIME TAG ON SYNCHRONIZE

INTERRUPT STATUS AUTO CLEAR

LEVEL/PULSE* INTERRUPT REQUEST

CLEAR SERVICE REQUEST

6

BC/MT STOP-ON-MESSAGE

BC STOP-ON-FRAME

TIME TAG TEST CLOCK

TIME TAG RESET

INTERRUPT RESET

BC/MT START

RESET

9

5

8

4

7

3

6

2

5

1

4

0(LSB)

3

2

1

ENHANCED RT MEMORY MANAGEMENT

SEPARATE BROADCAST DATA

0(LSB)

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TABLE 7. BC/RT COMMAND STACK POINTER REG. (READ 03H)

TABLE 10. TIME TAG REGISTER (READ/WRITE 05H)

DESCRIPTION

BIT

DESCRIPTION

BIT

COMMAND STACK POINTER 15

TIME TAG 15

15(MSB)

•

0(LSB)

TIME TAG 0

0(LSB)

COMMAND STACK POINTER 0

TABLE 11. INTERRUPT STATUS REGISTER (READ 06H)

DESCRIPTION

TABLE 8. BC CONTROL WORD REGISTER

READ/WRITE 04H, (BU-61580 ONLY)

BIT

MASTER INTERRUPT

15(MSB)

BIT

DESCRIPTION

14

13

12

11

10

9

RAM PARITY ERROR

RESERVED

15(MSB)

BC/RT TRANSMITTER TIMEOUT

BC/RT COMMAND STACK ROLLOVER

MT COMMAND STACK ROLLOVER

MT DATA STACK ROLLOVER

HS FAIL

14

M.E. MASK

13

SERVICE REQUEST BIT MASK

SUBSYS BUSY BIT MASK

SUBSYS FLAG BIT MASK

TERMINAL FLAG BIT MASK

RESERVED BITS MASK

RETRY ENABLED

12

11

10

8

BC RETRY

9

7

RT ADDRESS PARITY ERROR

TIME TAG ROLLOVER

8

6

7

BUS CHANNEL A/B

OFF LINE SELF TEST

MASK BROADCAST BIT

EOM INTERRUPT ENABLE

1553A/B SELECT

5

RT CIRCULAR BUFFER ROLLOVER

BC CONTROL WORD/RT SUBADDRESS CONTROL WORD EOM

BC END OF FRAME

6

4

5

3

4

2

FORMAT ERROR

3

2

MODE CODE FORMAT

BROADCAST FORMAT

RT-RT FORMAT

BC STATUS SET/RT MODE CODE/MT PATTERN

TRIGGER

1

0(LSB)

END OF MESSAGE

0(LSB)

TABLE 9. RT SUBADDRESS CONTROL WORD

(READ/WRITE 04H)

TABLE 12. CONFIGURATION REGISTER #3 (READ/WRITE 07H)

BIT

DESCRIPTION

BIT

DESCRIPTION

ENHANCED MODE ENABLE

BC/RT COMMAND STACK SIZE 1

BC/RT COMMAND STACK SIZE 0

MT COMMAND STACK SIZE 1

MT COMMAND STACK SIZE 0

MT DATA STACK SIZE 2

15(MSB)

RX: DOUBLE BUFFER ENABLE

TX: EOM INT

15(MSB)

14

13

TX: CIRC BUF INT

12

TX: MEMORY MANAGEMENT 2 (MM2)

TX: MEMORY MANAGEMENT 1 (MM1)

TX: MEMORY MANAGEMENT 0 (MM0)

RX: EOM INT

11

10

9

MT DATA STACK SIZE 1

9

8

MT DATA STACK SIZE 0

8

RX: CIRC BUF INT

7

ILLEGALIZATION DISABLED

OVERRIDE MODE T/R ERROR

ALTERNATE STATUS WORD ENABLE

ILLEGAL RX TRANSFER DISABLE

BUSY RX TRANSFER DISABLE

RTFAIL-FLAG WRAP ENABLE

1553A MODE CODES ENABLE

ENHANCED MODE CODE HANDLING

7

RX: MEMORY MANAGEMENT 2 (MM2)

RX: MEMORY MANAGEMENT 1 (MM1)

RX: MEMORY MANAGEMENT 0 (MM0)

BCST: EOM INT

6

5

4

3

BCST: CIRC BUF INT

2

BCST:MEMORY MANAGEMENT 2 (MM2)

BCST: MEMORY MANAGEMENT 1 (MM1)

BCST: MEMORY MANAGEMENT 0 (MM0)

1

0(LSB)

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TABLE 13. CONFIGURATION REGISTER #4 (READ/WRITE 08H)

TABLE 16. BC FRAME TIME REMAINING REGISTER

(READ/WRITE 0BH)

BIT

DESCRIPTION

BIT

DESCRIPTION

EXTERNAL BIT WORD ENABLE

15(MSB)

BC FRAME TIME REMAINING 15

15(MSB)

14

INHIBIT BIT WORD IF BUSY

MODE COMMAND OVERRIDE BUSY

EXPANDED BC CONTROL WORD ENABLE

BROADCAST MASK ENABLE/XOR

RETRY IF -A AND M.E.

•

13

•

12

•

11

0(LSB)

BC FRAME TIME REMAINING 0

10

Note: resolution = 1 µs per LSB

9

RETRY IF STATUS SET

8

1ST RETRY ALT/SAME BUS

2ND RETRY ALT/SAME BUS

VALID M.E./NO DATA

7

TABLE 17. BC MESSAGE TIME REMAINING REGISTER

(READ/WRITE 0CH)

6

BIT

DESCRIPTION

5

VALID BUSY/NO DATA

BC MESSAGE TIME REMAINING 15

15(MSB)

4

MT TAG GAP OPTION

•

3

LATCH RT ADDRESS WITH CONFIG #5

TEST MODE 2

2

1

TEST MODE 1

0(LSB)

TEST MODE 0

0(LSB) BC MESSAGE TIME REMAINING 0

Note: resolution = 1 µs per LSB

TABLE 14. CONFIGURATION REGISTER #5 (READ/WRITE 09H)

TABLE 18. BC FRAME TIME/RT LAST COMMAND/T TRIGGER

REGISTER (READ/WRITE 0DH)

BIT

DESCRIPTION

12MHZ CLOCK SELECT

15(MSB)

BIT

DESCRIPTION

14

LOGIC “0”

BIT 15

15(MSB)

13

EXTERNAL TX INHIBIT A, read only BU-65170/61580X6

EXTERNAL TX INHIBIT B, read only BU-65170/61580X6

EXPANDED CROSSING ENABLED

RESPONSE TIMEOUT SELECT 1

RESPONSE TIMEOUT SELECT 0

GAP CHECK ENABLED

•

12

11

10

0(LSB) BIT 0

9

8

TABLE 19. RT STATUS WORD REGISTER (READ/WRITE 0EH)

7

BROADCAST DISABLED

BIT

DESCRIPTION

6

RT ADDRESS LATCH/TRANSPARENT (see NOTE)

RT ADDRESS 4

LOGIC “0”

15(MSB)

5

14

LOGIC “0”

4

RT ADDRESS 3

13

LOGIC “0”

3

RT ADDRESS 2

12

LOGIC “0”

2

RT ADDRESS 1

11

LOGIC “0”

1

RT ADDRESS 0

10

MESSAGE ERROR

INSTRUMENTATION

SERVICE REQUEST

RESERVED

0(LSB)

RT ADDRESS PARITY

9

Notes for TABLE 14: Read only, logic “0” for 65170/61580, logic “1” for

65171/61581/61586.

8

7

6

RESERVED

TABLE 15. MONITOR DATA STACK ADDRESS REGISTER

(READ/WRITE 0AH)

5

RESERVED

BIT

DESCRIPTION

4

BROADCAST COMMAND RECEIVED

BUSY

MONITOR DATA STACK ADDRESS 15

15(MSB)

3

•

2

SUBSYSTEM FLAG

DYNAMIC BUS CONTROL ACCEPT

TERMINAL FLAG

•

1

•

0(LSB)

MONITOR DATA STACK ADDRESS 0

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TABLE 20. RT BIT WORD REGISTER (READ 0FH)

DESCRIPTION

TABLE 22. RT MODE BLOCK STATUS WORD

DESCRIPTION

BIT

TRANSMITTER TIMEOUT

EOM

15(MSB)

14

LOOP TEST FAILURE B

14

SOM

13

LOOP TEST FAILURE A

13

CHANNEL B/A

12

HANDSHAKE FAILURE

12

ERROR FLAG

11

TRANSMITTER SHUTDOWN B

TRANSMITTER SHUTDOWN A

TERMINAL FLAG INHIBITED

CHANNEL B/A

11

RT-RT FORMAT

10

FORMAT ERROR

9

NO RESPONSE TIMEOUT

LOOP TEST FAIL

8

7

HIGH WORD COUNT

7

DATA STACK ROLLOVER

ILLEGAL COMMAND WORD

WORD COUNT ERROR

INCORRECT SYNC

INVALID WORD

6

LOW WORD COUNT

6

5

INCORRECT SYNC RECEIVED

PARITY/MANCHESTER ERROR RECEIVED

RT-RT GAP/SYNCH/ADDRESS ERROR

RT-RT NO RESPONSE ERROR

RT-RT 2ND COMMAND WORD ERROR

COMMAND WORD CONTENTS ERROR

5

4

3

2

RT-RT GAP/SYNC/ADDRESS ERROR

RT-RT 2ND COMMAND ERROR

COMMAND WORD CONTENTS ERROR

1

0(LSB)

NOTE:

TABLE 23. WORD MONITOR IDENTIFICATION WORD

DESCRIPTION

TABLES 21 TO 24 ARE NOT REGISTERS, BUT

THEY ARE WORDS STORED IN RAM.

BIT

15(MSB) GAP TIME

•

TABLE 21. BC MODE BLOCK STATUS WORD

DESCRIPTION

•

BIT

•

EOM

15(MSB)

8

7

6

5

4

3

2

1

GAP TIME

14

SOM

WORD FLAG

THIS RT

13

CHANNEL B/A

12

ERROR FLAG

BROADCAST

ERROR

11

STATUS SET

10

FORMAT ERROR

NO RESPONSE TIMEOUT

LOOP TEST FAIL

COMMAND/DATA

CHANNEL B/A

CONTIGUOUS DATA/GAP

MODE CODE

9

8

7

MASKED STATUS SET

RETRY COUNT 1

RETRY COUNT 0

GOOD DATA BLOCK TRANSFER

WRONG STATUS ADDRESS/NO GAP

WORD COUNT ERROR

INCORRECT SYNC TYPE

INVALID WORD

0(LSB)

6

5

4

TABLE 24. MESSAGE MONITOR MODE BLOCK STATUS WORD

3

BIT

DESCRIPTION

2

EOM

15(MSB)

1

14

SOM

0(LSB)

13

CHANNEL B/A

12

ERROR FLAG

11

RT-RT TRANSFER

10

FORMAT ERROR

9

NO RESPONSE TIMEOUT

GOOD DATA BLOCK TRANSFER

DATA STACK ROLLOVER

RESERVED

8

7

6

5

WORD COUNT ERROR

INCORRECT SYNC

INVALID WORD

4

3

2

RT-RT GAP/SYNC/ADDRESS ERROR

RT-RT 2ND COMMAND ERROR

COMMAND WORD CONTENTS ERROR

1

0(LSB)

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BUS CONTROLLER (BC) ARCHITECTURE

TABLE 25. TYPICAL BC MEMORY ORGANIZATION

(SHOWN FOR 4K RAM)

The BC protocol of the BU-61580 implements all MIL-STD-

1553B message formats. Message format is programmable on a

message-by-message basis by means of bits in the BC Control

Word and the T/R bit of the Command Word for the respective

message. The BC Control Word allows 1553 message format,

1553A/B type RT, bus channel, self-test, and Status Word mask-

ing to be specified on an individual message basis. In addition,

automatic retries and/or interrupt requests may be enabled or

disabled for individual messages. The BC performs all error

checking required by MIL-STD-1553B.This includes validation of

response time, sync type and sync encoding, Manchester II

encoding, parity, bit count, word count, Status Word RT Address

field, and various RT-to-RT transfer errors. The BU-61580's BC

response timeout value is programmable with choices of 18, 22,

50, and 130 µs. The longer response timeout values enable

operation over long buses and/or the use of repeaters.

ADDRESS

DESCRIPTION

(HEX)

0000-00FF

0100

Stack A

Stack Pointer A (fixed location)

Message Count A (fixed location)

0101

Initial Stack Pointer A (see note) (Auto-Frame Repeat

Mode)

0102

0103

Initial Message Count A (see note)

(Auto-Frame Repeat Mode)

0104

0105

Stack Pointer B

Message Count B

Initial Stack Pointer B (see note)

(Auto-Frame Repeat Mode)

0106

0107

Initial Message Count B (see note)

(Auto-Frame Repeat Mode)

FIGURE 2 illustrates BC intermessage gap and frame timing.

The BU-61580 may be programmed to process BC frames of up

to 512 messages with no processor intervention. It is possible to

program for either single frame or frame auto-repeat operation.

In the auto-repeat mode, the frame repetition rate may be con-

trolled either internally, using a programmable BC frame timer, or

from an external trigger input. The internal BC frame time is pro-

grammable up to 6.55 seconds in increments of 100 µs. In addi-

tion to BC frame time, intermessage gap time, measured from

the start of the current message to the start of the subsequent

message, is programmable on an individual message basis. The

time between individual successive messages is programmable

up to 65.5 ms, in increments of 1 µs.

0108-012D

012E-0153

0154-0179

•

Message Block 0

Message Block 1

Message Block 2

•

0ED6-0EFB

0EFC-0EFF

0F00-0FFF

Message Block 93

Not Used

Stack B

Note: Used only in the Enhanced BC mode with Frame Auto-Repeat enabled.

BC MEMORY ORGANIZATION

locate the Stack and BC Message Blocks anywhere else within

the 64K (4K internal) shared RAM address space.

TABLE 25 illustrates a typical memory map for BC mode. It is

important to note that the only fixed locations for the BU-61580

in the Standard BC mode are for the two Stack Pointers (address

locations 0100 (hex) and 0104) and for the two Message Count

locations (0101 and 0105). Enabling the Frame Auto-Repeat

mode will reserve four more memory locations for use in the

Enhanced BC mode; these locations are for the two Initial Stack

Pointers (address locations 102 (hex) and 106) and for the Initial

Message Count locations (103 and 107). The user is free to

For simplicity of illustration, assume the allocation of the maxi-

mum length of a BC message for each message block in the typ-

ical BC memory map of TABLE 25. The maximum size of a BC

message block is 38 words, for an RT-to-RT transfer of 32 Data

Words (Control + 2 Commands + Loopback + 2 Status Words +

32 Data Words). Note, however, that this example assumes the

disabling of the 256-word boundaries.

MESSAGE

GAP TIME

FOR MESSAGE NO. 1

INTERMESSAGE GAP TIME

MESSAGE NO. 2

MESSAGE NO. 1

BC FRAME TIME

FIGURE 2. BC MESSAGE GAP AND FRAME TIMING

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BC MEMORY MANAGEMENT

prior to the processing of the first frame. The single frame mode

does not use these two locations.

FIGURE 3 illustrates the BU-61580's BC memory management

scheme. One of the BC memory management features is the

global double buffering mechanism. This provides for two sets of

the various BC mode data structures: Stack Pointer and

Message Counter locations, Descriptor Stack areas, and BC

message blocks. Bit 13 of Configuration Register #1 selects the

current active area. At any point in time, the BU-61580's internal

1553 memory management logic may access only the various

data structures within the “active” area. FIGURE 3 delineates the

“active” and “inactive” areas by the nonshaded and shaded

areas, respectively; however, at any point in time, both the

“active” and “nonactive” areas are accessible by the host

processor. In most applications, the host processor will access

the “nonactive” area, while the 1553 bus processes the “active”

area messages.

The third and fourth words of the BC block descriptor are the

Intermessage Gap Time and the Message Block Address for the

respective message. These two memory locations must be writ-

ten by the host processor prior to the start of message process-

ing. Use of the Intermessage Gap Time is optional. The Block

Address pointer specifies the starting location for each message

block.The first word of each BC message block is the BC Control

Word.

At the start and end of each message, the Block Status and Time

Tag Words write to the message block descriptor in the stack.

The Block Status Word includes indications of message in

process or message completion, bus channel, status set,

response timeout, retry count, status address mismatch, loop

test (on-line self-test) failure, and other error conditions. TABLE

21 illustrates the bit mapping of the BC Block Status word. The

16-bit Time Tag Word will reflect the current contents of the inter-

nal Time Tag Register. This read/writable register, which oper-

ates for all three modes, has programmable resolution of from 2

to 64 µs/LSB. In addition, the Time Tag register may be clocked

from an external source.

The BC may be programmed to transmit multimessage frames of

up to 512 messages. The number of messages to be processed

is programmable by the Active Area Message Count location in

the shared RAM, initialized by the host processor. In addition, the

host processor must initialize another location, the Active Area

Stack Pointer. The Stack Pointer references the four-word mes-

sage block descriptor in the Stack area of shared RAM for each

message to be processed. The BC Stack size is programmable

with choices of 256, 512, 1024, and 2048 words.

BC MESSAGE BLOCK FORMATS AND BC CONTROL

WORD

In the BC Frame Auto-Repeat mode, the Initial Stack Pointer and

Initial Message Counter locations must be loaded by the host

In BC mode, the BU-61580 supports all MIL-STD-1553 message

formats. For each 1553 message format, the BU-61580 man-

dates a specific sequence of words within the BC Message

INITIAL STACK

POINTERS (NOTE)

MESSAGE

BLOCKS

DESCRIPTOR

STACKS

CONFIGURATION

REGISTER 1

STACK

POINTERS

15

13

0

BLOCK STATUS WORD

CURRENT

AREA B/A

MESSAGE

TIME TAG WORD

BLOCK

INITIAL MESSAGE

COUNTERS (NOTE)

MESSAGE

GAP TIME WORD

MESSAGE

BLOCK ADDR

MESSAGE

BLOCK

MESSAGE

COUNTERS

NOTE:

INITIAL STACK POINTERS AND INITIAL

MESSAGE COUNTERS USED ONLY IN

BC FRAME AUTO-REPEAT MODE.

FIGURE 3. BC MODE MEMORY MANAGEMENT

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Block. This includes locations for the Control, Command and

(transmitted) Data Words that are to be read from RAM by the

BC protocol logic. In addition, subsequent contiguous locations

must be allocated for storage of received Loopback, RT Status

and Data Words. FIGURE 4 illustrates the organization of the BC

message blocks for the various MIL-STD-1553 message for-

mats. Note that for all of the message formats, the BC Control

Word is located in the first location of the message block.

For each of the BC Message Block formats, the first word in the

block is the BC Control Word. The BC Control Word is not trans-

mitted on the 1553 bus. Instead, it contains bits that select the

active bus and message format; enable off-line self-test; mask-

ing of Status Word bits; enable retries and interrupts; and speci-

fies MIL-STD-1553A or -1553B error handling. The bit mapping

and definitions of the BC Control Word are illustrated in

TABLE 8.

The BC Control Word is followed by the Command Word to be

transmitted, and subsequently by a second Command Word (for

an RT-to-RT transfer), followed by Data Words to be transmitted

(for Receive commands). The location after the last word to be

transmitted is reserved for the Loopback Word. The Loopback

Word is an on-line self-test feature. The subsequent locations

after the Loopback Word are reserved for received Status Words

and Data Words (for Transmit commands).

BC-to-RT Transfer

Control Word

RT-to-BC Transfer

Control Word

Receive Command Word

Data Word #1

Transmit Command Word

Transmit Command Looped Back

Status Received

Data Word #2

.

Data Word #1

Data Word #2

.

Last Data Word

Last Data Word Looped Back

Status Received

AUTOMATIC RETRIES

The BU-61580 BC implements automatic message retries.When

enabled, retries will occur, following response timeout or format

error conditions. As additional options, retries may be enabled

when the Message Error Status Word bit is set by a 1553A RT or

following a ”Status Set” condition. For a failed message, either

one or two message retries will occur, the bus channel (same or

alternate) is independently programmable for the first and sec-

ond retry attempts. Retries may be enabled or disabled on an

individual message basis.

Last Data Word

Tx Mode Code;

With Data

Mode Code;

No Data

RT-to-RT Transfer

Control Word

Receive Command

Tx Mode Command

Mode Command

Transmit Command

Mode Command

Looped Back

Mode Command

Looped Back

Transmit Command

Looped Back

Status Received

Data Word

Status Received

Tx RT Status Word

Data #1

BC INTERRUPTS

Data #2

BC interrupts may be enabled by the Interrupt Mask Register for

Stack Rollover, Retry, End-of-Message (global), End-of-

Message (in conjunction with the BC Control Word for individual

messages), response timeout, message error, end of BC frame,

and Status Set conditions. The definition of “Status Set” is pro-

grammable on an individual message basis, by means of the BC

Control Word. This allows for masking (“care/don't care”) of the

individual RT Status Word bits.

.

Last Data

Rx RT Status Word

Rx Mode Code;

With Data

Broadcast

Control Word

Broadcast Command

Data #1

RT-to-RTs (Broadcast)

Transfer

Control Word

Rx Broadcast Command

Tx Command

REMOTE TERMINAL (RT) ARCHITECTURE

Rx Mode Command

The RT protocol design of the BU-65170/61580 represents

DDC's fifth generation implementation of a 1553 RT. One of the

salient features of the ACE's RT architecture is its true multipro-

tocol functionality. This includes programmable options for sup-

port of MIL-STD-1553A, the various McAir protocols, and MIL-

STD-1553B Notice 2. The BU-65170/61580 RT response time is

2 to 5 µs dead time (4 to 7 µs per 1553B), providing compliance

to all the 1553 protocols. Additional multiprotocol features of the

BU-65170/61580 include options for full software control of RT

Status and Built-in-Test (BIT) words. Alternatively, for 1553B

applications, these words may be formulated in real time by the

BU-65170/61580 protocol logic.

Data Word

Data #2

Tx Command

Looped Back

.

Data Word Looped

Back

Status Received

Tx RT Status Word

Data #1

Last Data

Last Data Status

Word

Data #2

.

Last Data

Broadcast Mode Code;

With Data

Broadcast Mode Code;

No Data

The BU-65170/61580 RT protocol design implements all the

MIL-STD-1553B message formats and dual redundant mode

codes. This design is based largely on previous generation prod-

ucts that have passed SEAFAC testing for MIL-STD-1553B com-

pliance. The ACE RT performs comprehensive error checking,

word and format validation, and checks for various RT-to-RT

transfer errors. Other key features of the BU-65170/61580 RT

Control Word

Broadcast Mode Command

Data Word

Control Word

Broadcast Mode Command

Looped Back

Data Word Looped Back

FIGURE 4. BC MESSAGE BLOCK FORMATS

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include a set of interrupt conditions, internal command illegaliza-

tion, and programmable busy by subaddress.

TABLE 26. TYPICAL RT MEMORY MAP (SHOWN FOR 4K RAM)

ADDRESS

DESCRIPTION

(HEX)

RT MEMORY ORGANIZATION

0000-00FF

0100

Stack A

Stack Pointer A (fixed location)

TABLE 26 illustrates a typical memory map for the BU-61580 in

RT mode. As in BC mode, the two Stack Pointers reside in fixed

locations in the shared RAM address space: address 0100 (hex)

for the Area A Stack Pointer and address 0104 for the Area B

Stack Pointer. Besides the Stack Pointer, for RT mode there are

several other areas of the ACE address space designated as

fixed locations. All RT modes of operation require the Area A and

Area B Lookup Tables. Also allocated are several fixed locations

for optional features: Command Illegalization Lookup Table,

Mode Code Selective Interrupt Table, Mode Code Data Table,

and Busy Bit Lookup Table. It should be noted that any unen-

abled optional fixed locations may be used for general purpose

storage (data blocks).

0101-0103

0104

RESERVED

Stack Pointer B (fixed location)

0105-0107

0108-010F

0110-013F

0140-01BF

01C0-023F

0240-0247

0248-025F

0260-027F

0280-02FF

0300-03FF

0400-041F

0420-043F

·•

RESERVED

Mode Code Selective Interrupt Table (fixed area)

Mode Code Data (fixed area)

Lookup Table A (fixed area)

Lookup Table B (fixed area)

Busy Bit Lookup Table (fixed area)

(not used)

Data Block 0

Data Block 1-4

Command Illegalizing Table (fixed area)

The RT Lookup tables, which provide a mechanism for mapping

data blocks for individual Tx/Rx/Bcst-subaddresses to areas in

the RAM, occupy address range locations are 0140 to 01BF for

Area A and 01C0 to 023F for Area B. The RT lookup tables

include Subaddress Control Words and the individual Data Block

Pointers. If used, address range 0300-03FF will be dedicated as

the illegalizing section of RAM. The actual Stack RAM area and

the individual data blocks may be located in any of the nonfixed

areas in the shared RAM address space.

Data Block 5

Data Block 6

•

0FE0-0FFF

Data Block 100

TABLE 27. LOOK-UP TABLES

AREA A

AREA B

DESCRIPTION

COMMENT

RT MEMORY MANAGEMENT

0140

01C0

Rx(/Bcst)_SA0

Receive

One of the salient features of the ACE series products is the flex-

ibility of its RT memory management architecture. The RT archi-

tecture allows the memory management scheme for each trans-

mit, receive, or broadcast subaddress to be programmable on a

subaddress basis. Also, in compliance with MIL-STD-1553B

Notice 2, the BU-65170/61580 provides an option to separate

data received from broadcast messages from nonbroadcast

received data.

.

(/Broadcast)

Lookup Table

015F

01DF

Rx(/Bcst)_SA31

0160

.

01E0

.

Tx_SA0

Transmit

Lookup Table

.

017F

01FF

Tx_SA31

Besides supporting a global double buffering scheme (as in BC

mode), the ACE RT provides a pair of 128-word Lookup Tables

for memory management control. They are programmable on a

subaddress basis (refer to TABLE 27). These 128-word tables

include 32-word tables for transmit message pointers and

receive message pointers. There is also a third, optional Lookup

Table for broadcast message pointers, providing Notice 2 com-

pliance, if necessary.

0180

.

0200

.

Bcst_SA0

Broadcast

Lookup Table

Optional

.

019F

021F

Bcst_SA31

01A0

.

0220

.

SACW_SA0

Subaddress

Control Word

Lookup Table

(Optional)

.

01BF

023F

SACW_SA31

The fourth section of each of the RT Lookup Tables stores the 32

Subaddress Control Words (refer to TABLE 9 and 28). The indi-

vidual Subaddress Control Words may be used to select the RT

memory management option and interrupt scheme for each

transmit, receive, and (optionally) broadcast subaddress.

TABLE 28. SUBADDRESS CONTROL WORD

Memory Management Subaddress Buffer Scheme

MM2

MM1

MM0

DESCRIPTION

COMMENT

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Single Message or Double Buffered

For each transmit subaddress, there are two possible memory

management schemes: (1) single message; and (2) circular

buffer. For each receive (and optionally broadcast) subaddress,

there are three possible memory management schemes: (1) sin-

gle message; (2) double buffered; and (3) circular buffer. For

each transmit, receive and broadcast subaddress, there are two

interrupt conditions that are programmable by the respective

Subaddress Control Word: (1) after every message to the sub-

Circular Buffer of

Specified Size

128-Word

256-Word

512-Word

1024-Word

2048-Word

4096-Word

8192-Word

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address; (2) after a circular buffer rollover. An additional table in

RAM may be used to enable interrupts following selected mode

code messages.

At the end of a valid (or optionally invalid) message, the value of

the Lookup Table entry updates to the next location after the last

address accessed for the current message. As a result, Data

Words for the next message directed to the same Tx/RX(/Bcst)

subaddress will be accessed from the next contiguous block of

address locations within the circular buffer. As a recommended

option, the Lookup Table pointers may be programmed to not

update following an invalid receive (or broadcast) message. This

allows the 1553 bus controller to retry the failed message, result-

ing in the valid (retried) data overwriting the invalid data. This

eliminates overhead for the RT's host processor. When the point-

er reaches the lower boundary of the circular buffer (located at

128, 256, . . . 8192-word boundaries in the BU-65170/61580

address space), the pointer moves to the top boundary of the cir-

cular buffer, as FIGURE 6 shows.

When using the circular buffer scheme for a given subaddress,

the size of the circular buffer is programmable by three bits of the

Subaddress Control Word (see TABLE 28). The options for cir-

cular buffer size are 128, 256, 512, 1024, 2048, 4096, and 8192

Data Words.

SINGLE MESSAGE MODE

FIGURE 5 illustrates the RT Single Message memory manage-

ment scheme. When operating the BU-65170/61580 in its “AIM-

HY” (default) mode, the Single Message scheme is implemented

for all transmit, receive, and broadcast subaddresses. In the

Single Message mode (also in the Double Buffer and Circular

Buffer modes), there is a global double buffering scheme, con-

trolled by bit 13 of Configuration Register #1. This selects from

between the two sets of the various data structures shown in the

figure: the Stack Pointers (fixed addresses), Descriptor Stacks

(user defined addresses), RT Lookup Tables (fixed addresses),

and RT Data Word blocks (user defined addresses). FIGURES 5,

6, and 7 delineate the “active” and “nonactive” areas by the non-

shaded and shaded areas, respectively.

Implementing Bulk Data Transfers

The use of the Circular Buffer scheme is ideal for bulk data trans-

fers; that is, multiple messages to/from the same subaddress.

The recommendation for such applications is to enable the cir-

cular buffer interrupt request. By so doing, the routine transfer of

multiple messages to the selected subaddress, including errors

and retries, is transparent to the RT's host processor. By strate-

gically initializing the subaddresses' Lookup Table pointer prior to

the start of the bulk transfer, the BU-65170/61580 may be con-

figured to issue an interrupt request only after it has received the

anticipated number of valid Data Words to the designated sub-

address.

As shown, the ACE stores the Command Word from each mes-

sage received, in the fourth location within the message descrip-

tor (in the stack) for the respective message. The T/R bit, subad-

dress field, and (optionally) broadcast/own address, index into

the active area Lookup Table, to locate the data block pointer for

the current message. The BU-65170/61580 RT memory man-

agement logic then accesses the data block pointer to locate the

starting address for the Data Word block for the current mes-

sage. The maximum size for an RT Data Word block is 32 words.

SUBADDRESS DOUBLE BUFFERING MODE

For receive (and broadcast) subaddresses, the BU-65170/61580

RT offers a third memory management option, Subaddress

Double Buffering. Subaddress Double Buffering provides a

means of ensuring data consistency. FIGURE 7 illustrates the RT

Subaddress Double Buffering scheme. Like the Single Message

and Circular Buffer modes, the Double Buffering mode may be

selected on a subaddress basis by means of the Subaddress

Control Word. The purpose of the Double Buffering mode is to

provide the host processor a convenient means of accessing the

most recent, valid data received to a given subaddress. This

serves to ensure the highest possible degree of data consisten-

cy by allocating two 32-bit Data Word blocks for each individual

receive (and/or broadcast) subaddress.

For a particular subaddress in the Single Message mode, there

is overwriting of the contents of the data blocks for receive/broad-

cast subaddresses — or overreading, for transmit subaddresses.

In the single message mode, it is possible to access multiple

data blocks for the same subaddress.This, however, requires the

intervention of the host processor to update the respective

Lookup Table pointer.

To implement a data wraparound subaddress, as required by

Notice 2 of MIL-STD-1553B, the Single Message scheme should

be used for the wraparound subaddress. Notice 2 recommends

subaddress 30 as the wraparound subaddress.

At a given point in time, one of the two blocks will be designated

as the “active” 1553 data block while the other will be designat-

ed as the “inactive” block. The Data Words from the next receive

message to that subaddress will be stored in the “active” block.

Upon completion of the message, provided that the message

was valid and Subaddress Double Buffering is enabled, the BU-

65170/61580 will automatically switch the “active” and “inactive”

blocks for the respective subaddress. The ACE accomplishes

this by toggling bit 5 of the subaddress's Lookup Table Pointer

and rewriting the pointer. As a result, the most recent valid block

of received Data Words will always be readily accessible to the

host processor.

CIRCULAR BUFFER MODE

FIGURE 6 illustrates the RT circular buffer memory management

scheme. The circular buffer mode facilitates bulk data transfers.

The size of the RT circular buffer, shown on the right side of the

figure, is programmable from 128 to 8192 words (in even powers

of 2) by the respective Subaddress Control Word. As in the sin-

gle message mode, the host processor initially loads the individ-

ual Lookup Table entries. At the start of each message, the ACE

stores the Lookup Table entry in the third position of the respec-

tive message block descriptor in the stack area of RAM, as in the

Single Message mode. The ACE transfers Receive or Transmit

Data Words to (from) the circular buffer, starting at the location

referenced by the Lookup Table pointer.

As a means of ensuring data consistency, the host processor is

able to reliably access the most recent valid, received Data Word

block by performing the following sequence:

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LOOK-UP TABLE

(DATA BLOCK ADDR)

DESCRIPTOR

STACKS

CONFIGURATION

REGISTER

STACK

POINTERS

DATA

BLOCKS

15 13

0

CURRENT

AREA B/A

BLOCK STATUS WORD

TIME TAG WORD

LOOK-UP

TABLE ADDR

DATA BLOCK

DATA BLOCK POINTER

(See note)

RECEIVED COMMAND

WORD

Note: Lookup table is not used for mode commands when enchanced mode codes are enabled.

FIGURE 5. RT MEMORY MANAGEMENT: SINGLE MESSAGE MODE

CIRCULAR

DATA

CONFIGURATION

REGISTER

STACK

POINTERS

DESCRIPTOR

STACK

LOOK-UP TABLES

BUFFER

15

13

0

CURRENT

AREA B/A

BLOCK STATUS WORD

TIME TAG WORD

POINTER TO

CURRENT

DATA BLOCK

LOOK-UP

TABLE

ADDRESS

DATA BLOCK POINTER

128,

256

LOOK-UP TABLE

ENTRY

RECEIVED COMMAND

WORD

RECEIVED

(TRANSMITTED)

MESSAGE

POINTER TO

NEXT DATA

BLOCK

*

DATA

8192

WORDS

(NEXT LOCATION)

CIRCULAR

BUFFER

ROLLOVER

*

TX/RS/BCST_SA LOOK-UP TABLE ENTRY IS UPDATED

FOLLOWING VALID RECEIVE (BROADCAST) MESSAGE OR

FOLLOWING COMPLETION OF TRANSIT MESSAGE.

FIGURE 6. RT MEMORY MANAGEMENT: CIRCULAR BUFFER MODE

CONFIGURATION

REGISTER

STACK

POINTERS

DESCRIPTOR

STACK

LOOK-UP

TABLES

15

13

0

DATA

BLOCKS

CURRENT

AREA B/A

BLOCK STATUS WORD

TIME TAG WORD

X..X 0 YYYYY

X..X 1 YYYYY

DATA

BLOCK 0

DATA BLOCK POINTER

RECEIVED COMMAND

WORD

DATA

BLOCK 1

RECEIVE DOUBLE

BUFFER ENABLE

MSB

SUBADDRESS

CONTROL WORD

FIGURE 7. RT MEMORY MANAGEMENT: SUBADDRESS DOUBLE BUFFERING MODE

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(1) Disable the double buffering for the respective subad-

dress by the Subaddress Control Word. That is, temporarily

switch the subaddress' memory management scheme to the

Single Message mode.

the need for an external PROM, PLD, or RAM device that does

the illegalizing function. The BU-J1165170/61580's illegalization

scheme provides maximum flexibility, allowing any subset of the

4096 possible combinations of broadcast/own address, T/R bit,

subaddress, and word count/mode code to be illegalized.

Another advantage of the RAM-based illegalization technique is

that it provides for a high degree of self-testability.

(2) Read the current value of the receive (or broadcast) sub-

address's Lookup Table pointer. This points to the current

“active” Data Word block. By inverting bit 5 of this pointer

value, it is possible to locate the start of the “inactive” Data

Word block. This block will contain the Data Words received

during the most recent valid message to the subaddress.

Addressing the Illegalization Table

TABLE 29 illustrates the addressing scheme of the illegalization

RAM. As shown, the base address of the illegalizing RAM is

0300 (hex). The ACE formulates the index into the Illegalizing

Table based on the values of BROADCAST/OWN ADDRESS,

T/R bit, Subaddress, and the MSB of the Word Count/Mode

Code field (WC/MC4) of the current Command Word.

(3) Read out the words from the “inactive” (most recent)

Data Word Block.

(4) Re-enable the Double Buffering mode for the respective

subaddress by the Subaddress Control Word.

RT INTERRUPTS

The internal RAM has 256 words reserved for command illegal-

ization. Broadcast commands may be illegalized separately from

nonbroadcast receive commands and mode commands.

As in BC mode, the BU-65170/61580 RT provides many mask-

able interrupts. RT interrupt conditions include End of (every)

Message, Message Error, Selected Subaddress (Subaddress

Control Word) Interrupt, Circular Buffer Rollover, Selected Mode

Code Interrupt, and Stack Rollover.

Commands may be illegalized down to the word count level. For

example, a one-word receive command to subaddress 1 may be

legal, while a two-word receive command to subaddress 1 may

be illegalized.

DESCRIPTOR STACK

At the beginning and end of each message, the BU-

65170/61580 RT stores a four-word message descriptor in the

active area stack. The RT stack size is programmable, with

choices of 256, 512, 1024, and 2048 words. FIGURES 5, 6 and

7 show the four words: Block Status Word, Time Tag Word, Data

Block Pointer, and the 1553 received Command Word. The RT

Block Status Word includes indications of message in-progress

or message complete, bus channel, RT-to-RT transfer and RT-to-

RT transfer errors, message format error, loop test (self-test) fail-

ure, circular buffer rollover, illegal command, and other error con-

ditions. TABLE 22 shows the bit mapping of the RT Block Status

Word.

The first 64 words of the Illegalization Table refer to broadcast

receive commands (two words per subaddress). The next 64

words refer to broadcast transmit commands. Since nonmode

code broadcast transmit commands are by definition invalid, this

section of the table (except for subaddresses 0 and 31) does not

need to be initialized by the user. The next 64 words correspond

to nonbroadcast receive commands. The final 64 words refer to

nonbroadcast transmit commands. Messages with Word Count/

Mode Code (WC/MC) fields between 0 and 15 may be illegalized

by setting the corresponding data bits for the respective even-

numbered address locations in the illegalization table. Likewise,

messages with WC/MC fields between 16 and 31 may be ille-

galized by setting the corresponding data bits for the respective

odd-numbered address locations in the illegalization table.

As in BC mode, the Time Tag Word stores the current contents

of the BU-65170/61580's read/writable Time Tag Register. The

resolution of the Time Tag Register is programmable from among

2, 4, 8, 16, 32, and 64 µs/LSB. Also, incrementing of the Time

Tag counter may be from an external clock source or via software

command.

The following should be noted with regards to command illegal-

ization:

(1)To illegalize a particular word count for a given broad-

cast/own address-T/R subaddress, the appropriate bit posi-

tion in the respective illegalization word should be set to

logic 1. A bit value of logic 0 designates the respective

Command Word as a legal command. The ACE will respond

to an illegalized nonbroadcast command with the Message

Error bit set in its RT Status Word.

The ACE stores the contents of the accessed Lookup Table loca-

tion for the current message, indicating the starting location of

the Data Word block, as the Data Block Pointer. This serves as a

convenience in locating stored message data blocks. The ACE

stores the full 16-bit 1553 Command Word in the fourth location

of the RT message descriptor.

(2)For subaddresses 00001 through 11110, the “WC/MC”

field specifies the Word Count field of the respective

Command Word. For subaddresses 00000 and 11111, the

“WC/MC” field specifies the Mode Code field of the respec-

tive Command Word.

RT COMMAND ILLEGALIZATION

The BU-65170/61580 provides an internal mechanism for RT

command illegalization. In addition, the Busy Status Word bit

can be set so that it is only a programmed subset of the trans-

mit/receive/broadcast subaddresses.

(3)Since nonmode code broadcast transmit messages are

not defined by MIL-STD-1553B, the sixty (60) words in the

illegalization RAM, addresses 0342 through 037D, corre-

sponding to these commands do not need to be initialized.

The ACE will not respond to a nonmode code broadcast

transmit command, but will automatically set the Message

The illegalization scheme uses a 256-word area in the BU-

65170/61580's address space. A benefit of this feature is the

reduction of printed circuit board requirements, by eliminating

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The strong recommendation for new applications is the use of

the Selective Message Monitor, rather than the Word Monitor.

Besides providing monitor filtering based on RT Address, T/R bit,

and Subaddress, the Message Monitor eliminates the need to

determine the start and end of messages by software.The devel-

opment of such software tends to be a tedious task. Moreover, at

run time, it tends to entail a high degree of CPU overhead.

TABLE 29. ILLEGALIZATION RAM ADDRESS DEFINITION

DESCRIPTION

BIT

0

1

15(MSB)

14

13

12

11

10

WORD MONITOR

9

In the Word Monitor mode, the BU-61580 monitors both 1553

buses. After initializing the Word Monitor and putting it on-line the

BU-61580 stores all Command, Status, and Data Words

received from both buses. For each word received from either

bus, the BU-61580 stores a pair of words in RAM. The first word

is the 16 bits of data from the received word. The second word is

the Monitor Identification (ID), or “Tag” word. The ID Word con-

tains information relating to bus channel, sync type, word validi-

ty, and interword time gaps. The BU-61580 stores data and ID

words in a circular buffer in the shared RAM address space.

TABLE 23 shows the bit mapping for the Monitor ID word.

8

7

BROADCAST/OWN_ADDRESS

6

T/R

5

SA4

SA3

4

3

SA2

2

SA1

1

SA0

0(LSB)

WC4/MC4

Error bit in its internal Status Register, regardless of whether

or not corresponding bit in the illegalization RAM has been

set. If the next message is a Transmit Status or Transmit Last

Command mode code, the ACE will respond with its

Message Error bit set.

MONITOR TRIGGER WORD

There is a Trigger Word Register that provides additional flexibil-

ity for the Word Monitor mode. The BU-61580 stores the value of

the 16-bit Trigger Word in the MT Trigger Word Register.The con-

tents of this register represent the value of the Trigger Command

Word. The BU-61580 has programmable options to start or stop

the Word Monitor, and/or to issue an interrupt request following

receipt of the Trigger Command Word from the 1553 bus.

PROGRAMMABLE BUSY

As a means of providing compliance with Notice 2 of MIL-STD-

1553B, the BU-65170/61580 RT provides a software controllable

means for setting the Busy Status Word bit as a function of sub-

address. By a Busy Lookup Table in the BU-65170/61580

address space, it is possible to set the Busy bit based on com-

mand broadcast/own address, T/R bit, and subaddress. Another

programmable option, allows received Data Words to be either

stored or not stored for messages, when the Busy bit is set.

SELECTIVE MESSAGE MONITOR MODE

The BU-61580 Selective Message Monitor provides features to

greatly reduce the software and processing burden of the host

CPU.The Selective Message Monitor implements selective mon-

itoring of messages from a dual 1553 bus, with the monitor fil-

tering based on the RT Address, T/R bit, and Subaddress fields

of received 1553 Command Words. The Selective Message

Monitor mode greatly simplifies the host processor software by

distinguishing between Command and Status Words. The

Selective Message Monitor maintains two stacks in the BU-

61580 RAM: a Command Stack and a Data Stack.

OTHER RT FUNCTIONS

The BU-65170/61580 allows the hardwired RT Address to be

read by the host processor. Also, there are options for the RT

FLAG Status Word bit to be set under software control and/or

automatically following a failure of the loopback self-test. Other

software controllable RT options include software programmable

RT Status and RT BIT words, automatic clearing of the Service

Request Status Word bit following a Transmit Vector Word mode

command, capabilities to clear and/or load the Time Tag Register

following receipt of Synchronize mode commands, options

regarding Data Word transfers for the Busy and/or Message

Error (Illegal) Status Word bits, and for handling of 1553A and

reserved mode codes.

Simultaneous RT/Message Monitor Mode

The Selective Message Monitor may function as a purely passive

monitor or may be programmed to function as a simultaneous

RT/Monitor. The RT/Monitor mode provides complete Remote

Terminal (RT) operation for the BU-61580's strapped RT address

and bus monitor capability for the other 30 nonbroadcast RT

addresses. This allows the BU-61580 to simultaneously operate

as a full function RT and “snoop” on all or a subset of the bus

activity involving the other RTs on a bus. This type of operation

is sometimes needed to implement a backup bus controller. The

combined RT/Selective Monitor maintains three stack areas in

the BU-61580 address space: an RT Command Stack, a Monitor

Command Stack, and a Monitor Data Stack. The pointers for the

various stacks have fixed locations in the BU-61580 address

space.

MONITOR (MT) ARCHITECTURE

The BU-61580 provides three bus monitor (MT) modes:

(1) The “AIM-HY” (default) or “AIM-HY'er” Word Monitor mode.

(2) A Selective Message Monitor mode.

(3) A Simultaneous Remote Terminal/Selective Message Monitor

mode.

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Selective Message Monitor Memory Organization

TABLE 30. TYPICAL SELECTIVE MESSAGE MONITOR

MEMORY MAP (SHOWN FOR 4K RAM)

TABLE 30 illustrates a typical memory map for the ACE in the

Selective Message Monitor mode. This mode of operation

defines several fixed locations in the RAM. These locations allo-

cate in a manner that is compatible with the combined

RT/Selective Message Monitor mode. Refer to TABLE 30 for an

example of a typical Selective Message Monitor Memory Map.

The fixed memory map consists of two Monitor Command Stack

Pointers (location 102h and 106h), two Monitor Data Stack

Pointers (locations 103h and 107h), and a Selective Message

Monitor Lookup Table (0280-02FFh) based on RT Address, T/R,

and subaddress. Assume a Monitor Command Stack size of 1K

words, and a Monitor Data Stack size of 2K words.

ADDRESS

(HEX)

DESCRIPTION

Not Used

Monitor Command Stack Pointer A (fixed location)

Monitor Data Stack Pointer A (fixed location)

Not Used

0000-0101

0102

0103

0104-0105

0106

Monitor Command Stack Pointer B (fixed location)

Monitor Data Stack Pointer B (fixed location)

Not Used

0107

0108-027F

0280-02FF

0300-03FF

0400-07FF

0800-0FFF

Selective Monitor Lookup Table (fixed area)

Not Used

Refer to FIGURE 8 for an illustration of the Selective Message

Monitor operation. Upon receipt of a valid Command Word, the

BU-61580 will reference the Selective Monitor Lookup Table (a

fixed block of addresses) to check for the condition

(disabled/enabled) of the current command. If disabled, the BU-

61580 will ignore (and not store) the current message; if enabled,

the BU-61580 will create an entry in the Monitor Command

Stack at the address location referenced by the Monitor

Command Stack Pointer.

Monitor Command Stack A

Monitor Data Stack A

subsequent words from the message (possible second

Command Word, Data Word(s), Status Word(s)) into consecutive

locations in the Monitor Data Stack.

The size of the Monitor Command Stack is programmable to

256, 1K, 4K, or 16K words. The Monitor Data Stack size is pro-

grammable to 512, 1K, 2K, 4K, 8K, 16K, 32K, or 64K words.

Similar to RT mode, The ACE stores a Block Status Word, 16-bit

Time Tag Word, and Data Block Pointer in the Message

Descriptor, along with the received 1553 Command Word follow-

ing reception of the Command Word. The ACE writes the Block

Status and Time Tag Words at both the start and end of the mes-

sage. The Monitor Block Status Word contains indications of

message in-progress or message complete, bus channel,

Monitor Data Stack Rollover, RT-to-RT transfer and RT-to-RT

transfer errors, message format error, and other error conditions.

TABLE 24 shows the Message Monitor Block Status Word. The

Data Block Pointer references the first word stored in the Monitor

Data Stack (the first word following the Command Word) for the

current message. The BU-61580 will then proceed to store the

Monitor interrupts may be enabled for Monitor Command Stack

Rollover, Monitor Data Stack Rollover, and/or End-of-Message

conditions. In addition, in the Word Monitor mode there may be

an interrupt enabled for a Monitor Trigger condition.

PROCESSOR AND MEMORY INTERFACE

The ACE terminals provide much flexibility for interfacing to a

host processor and optional external memory. FIGURE 1 shows

that there are 14 control signals, 6 of which are dual purpose, for

the processor/memory interface. FIGURES 9 through 14 illus-

trate six of the configurations that may be used for interfacing a

CONFIGURATION

REGISTER #1

MONITOR COMMAND

STACK POINTERS

MONITOR

COMMAND STACKS

MONITOR DATA

STACKS

15

13

0

CURRENT

AREA B/A

BLOCK STATUS WORD

TIME TAG WORD

MONITOR DATA

BLOCK #N

CURRENT

COMMAND WORD

DATA BLOCK POINTER

MONITOR DATA

BLOCK #N + 1

RECEIVED COMMAND

WORD

MONITOR DATA

STACK POINTERS

NOTE

IF THIS BIT IS "0" (NOT SELECTED)

NO WORDS ARE STORED IN EITHER

THE COMMAND STACK OR DATA STACK.

IN ADDITION, THE COMMAND AND DATA

STACK POINTERS WILL NOT BE UPDATED.

SELECTIVE MONITOR

LOOKUP TABLES

OFFSET BASED ON

RTA4-RTA0, T/R, SA4

SELECTIVE MONITOR

ENABLE

(SEE NOTE)

FIGURE 8. SELECTIVE MESSAGE MONITOR MEMORY MANAGEMENT

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FIGURE 12 illustrates the connections for the 16-bit Direct

Memory Access (DMA) mode. In this configuration the host

processor, rather than the ACE terminal, arbitrates the use of the

address and data buses. The arbitration involves the two DMA

output signals Request (DTREQ) and Acknowledge (DTACK),

and the input signal Grant (DTGRT). The DMA interface allows

the ACE components to interface to large amounts of system

RAM while eliminating the need for external buffers. For system

address spaces larger than 64K words, it is necessary for the

host processor to provide a page register for the upper address

bits (above A15) when the BU-65170/61580 accesses the RAM

(while asserting DTACK low).

BU-65170 or BU-61580 to a host processor bus. The various

possible configurations serve to reduce to an absolute minimum

the amount of glue logic required to interface to 8-, 16-, and 32-

bit processor buses. Also included are features to facilitate inter-

facing to processors that do not have a “wait state” type of hand-

shake acknowledgement. Finally, the ACE supports a reliable

interface to an external dual port RAM. This type of interface

minimizes the portion of the available processor bandwidth

required to access the 1553 RAM.

The 16-bit buffered mode (FIGURE 9) is the most common con-

figuration used. It provides a direct, shared RAM interface to a

16-bit or 32-bit microprocessor. In this mode, the ACE's internal

address and data buffers provide the necessary isolation

between the host processor's address and data buses and the

corresponding internal memory buses. In the buffered mode, the

1553 shared RAM address space limit is the BU-65170/61580's

4K words of internal RAM. The 16-bit buffered mode provides a

pair of pin-programmable options:

The internal RAM is accessible through the standard ACE inter-

face (SELECT, STRBD, READYD, etc). The host CPU may

access external RAM by the ACE's arbitration logic and output

control signals, as illustrated in FIGURE 12. Alternatively, control

of the RAM may be shared by both the host processor and the

ACE, as illustrated in FIGURE 13. The latter requires the use of

external logic, but allows the processor to access the RAM

directly at the full access speed of the RAM, rather than waiting

for the ACE handshake acknowledge output (READYD).

(1) The logic sense of the RD/WR control input is selectable

by the POLARITY_SEL input: For example, write when

RD/WR is low for Motorola 680X0 processors; write when

RD/WR is high for the Intel i960 series microprocessors.

FIGURE 14 illustrates the 8-bit buffered mode. This interface

allows a direct connection to 8-bit microprocessors and 8-bit

microcontrollers. As in the 16-bit buffered configuration, the

buffer RAM limit is the BU-65170/61580's 4K words of internal

RAM. In the 8-bit mode, the host CPU accesses the BU-

65170/61580's internal registers and RAM by a pair of 8-bit reg-

isters embedded in the ACE interface. The 8-bit interface may be

further configured by three strappable inputs: ZERO_WAIT,

POLARITY_SEL, and TRIGGER_SEL. By connecting

ZERO_WAIT to logic "0," the BU-65170/61580 may be interfaced

with minimal "glue" logic to 8-bit microcontrollers, such as the

Intel 8051 series, that do not have an Acknowledge type of hand-

shake input. The programmable inputs POLARITY_SEL and

TRIGGER_SEL allow the BU-65170/61580 to accommodate the

different byte ordering conventions and "A0" logic sense utilized

by different 8-bit processor families.

(2) By strapping the input signal ZERO_WAIT to logic "1,"

the ACE terminals may interface to processors that have an

acknowledge type of handshake input to accommodate

hardware controlled wait states; most current processor

chips have such an input. In this case, the BU-65170/61580

will assert its READYD output low only after it has latched

WRITE data internally or has presented READ data on D15-

D0.

By strapping ZERO_WAIT to logic "0," it is possible to easily

interface the BU-65170/61580 to processors that do not have an

acknowledge type of handshake input. An example of such a

processor is Analog Device's ADSP2101 DSP chip. In this con-

figuration, the processor can clear its strobe output before the

completion of access to the BU-65170/61580 internal RAM or

register. In this case, READYD will go high following the rising

edge of STRBD and will stay high until completion of the trans-

fer. READYD will normally be low when ZERO_WAIT is low.

PROCESSOR INTERFACE TIMING

FIGURES 15 and 16 illustrate the timing for the host processor

to access the ACE's internal RAM or registers in the 16-bit,

buffered, non-zero, wait-mode. FIGURE 15 illustrates the 16-bit

buffered, nonzero wait mode read cycle timing while FIGURE 16

shows the 16-bit, buffered, nonzero wait mode write cycle timing.

Similar to the 16-bit buffered mode, the 16-bit transparent mode

(FIGURE 10) supports a shared RAM interface to a host CPU.

The transparent mode offers the advantage of allowing the

buffer RAM size to be expanded to up to 64K words, using exter-

nal RAM. A disadvantage of the transparent mode is that it

requires external address and data buffers to isolate the proces-

sor buses from the memory/BU-65170/61580 buses.

During a CPU transfer cycle, the signals STRBD and SELECT

must be sampled low on the rising edge of the system clock to

request access to the BU-65170/61580's internal shared RAM.

The transfer will begin on the first rising system clock edge when

(SELECT and STRBD) is low and the 1553 protocol/memory

management unit is not accessing the internal RAM. The falling

edge of the output signal IOEN indicates the start of the transfer.

The ACE latches the signals MEM/REG and RD/WR internally

on the first falling clock edge after the start of the transfer cycle.

The address inputs latch internally on the first rising clock edge

after the signal IOEN goes low. Note that the address lines may

be latched at any time using the ADDR_LAT input signal.

A modified version of the transparent mode involves the use of

dual port RAM, rather than conventional static RAM. Refer to

FIGURE 11. This allows the host to access RAM very quickly,

the only limitation being the access time of the dual port RAM.

This configuration eliminates the BU-65170/61580 arbitration

delays for memory accesses. The worst case delay time occurs

only during a simultaneous access by the host and the BU-

65170/61580 1553 logic to the same memory address. In gen-

eral, this will occur very rarely and the ACE limits the delay to

approximately 250 ns.

The output signal READYD will be asserted low on the third ris-

ing system clock edge after IOEN goes low. The assertion of

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READYD low indicates to the host processor that read data is

available on the parallel data bus, or that write data has been

stored. At this time, the CPU should bring the signal STRBD

high, completing the transfer cycle.

Note that the timeout value of the watchdog timer depends on

the mode of operation selected (1553A or 1553B). A failure of the

loop test results in setting a bit in the message's Block Status

Word and, if enabled, will result in an interrupt request. With

appropriate host processor software, the BC off-line test is able

to exercise the parallel and serial data paths, encoder, decoder,

and a substantial portion of the BC protocol and memory man-

agement logic.

Address Latch Timing

FIGURE 17 illustrates the operation and timing of the address

input latches for the buffered interface mode. In the transparent

mode, the address buffers are always transparent. Since the

transparent mode requires the use of external buffers, external

address latches would be required to demultiplex a multiplexed

address bus. In the buffered mode, however, the ACE's internal

address latches may be used to perform the demultiplexing func-

tion.

There are additional built-in self-test features, that involve the

use of three configuration register bits and the eight test regis-

ters.This allows a test of approximately 99% of the J’ chip's inter-

nal logic. These tests include an encoder test, a decoder test, a

register test, a protocol test, and a test of the fail-safe (transmit-

ter timeout) timer.

The ADDR_LAT input signal controls address latch operation.

When ADDR_LAT is high, the outputs of the latch (which drive

the ACE's internal memory bus) track the state of address inputs

A15 – A00. When it is low, the internal memory bus remains

latched at the state of A15 – A00 just prior to the falling edge of

ADDR_LAT.

There is also a test mode. In the test mode, the host processor

can emulate arbitrary activity on the 1553 buses by writing to a

pair of test registers. The test mode can be operated in conjunc-

tion with the Word Monitor mode to facilitate end-to-end self-

tests.

RAM PARITY GENERATION AND CHECKING

MISCELLANEOUS

SELF-TEST

The architecture of the J’ monolithic is such that the amount of

buffered RAM may be extended beyond the 4K words of on-chip

J’ RAM. For this off-chip buffered RAM, the J’ chip includes pro-

visions to implement parity generation and checking. Parity gen-

eration and checking provides a mechanism for checking the

data integrity of the internal, buffered memory. Furthermore, 17-

bit, rather than 16-bit, wide buffered RAM would be used. For this

RAM, the J’ chip will generate the 17th bit (parity bit) for all (host

and 1553) write accesses and check the parity bit for all read

accesses. If a parity error occurs, an interrupt request may be

issued, and the corresponding bit in the Interrupt Status Register

would be set. The BU-61585 incorporates an additional 8K x 17

RAM chip.

The BU-65170/61580 products incorporate several self-test fea-

tures. These features include an on-line wraparound self-test for

all messages in BC and RT modes, an off-line wraparound self-

test for BC mode, and several other internal self-test features.

The BC/RT on-line loop test involves a wraparound test of the

encoder/decoder and transceiver. The BC off-line self-test

involves the encoder/decoder, but not the transceiver. These

tests entail checking the received version of every transmitted

word for validity (sync, encoding, bit count, parity) and checking

the received version of the last transmitted word for a bit-by-bit

comparison with the encoded word. The loopback test also fails

if there is a timeout of the internal transmitter watchdog timer.

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+15V +5V

16 MHz

CLOCK

CLK IN

OSCILLATOR

D15-D0

A15-A12

A11-A0

55 Ω

TX/RXA

1

8

7

N/C

2

3

CH. A

5

4

TX/RXA

55 Ω

ADDR_LAT

(NOTE 1)

CPU ADDRESS LATCH

TRANSPARENT/BUFFERED

+5V

16/8_BIT

55 Ω

TRIGGER_SEL

+5V

TX/RXB

1

N/C

8

7

MSB/LSB

2

3

CH. B

POLARITY_SEL

(NOTE 2)

5

4

TX/RXB

ZERO_WAIT

(NOTE 3)

HOST

ACE

55 Ω

SELECT

ADDRESS

DECODER

MEM/REG

RD/WR

STRBD

CPU STROBE

RTAD4-RTAD0

RTADP

RT

ADDRESS,

PARITY

CPU ACKNOWLEDGE

READYD

TAG_CLK

(NOTE 4)

+5V

RESET

MSTCLR

SSFLAG/EXT_TRIG

INT

CPU INTERRUPT REQUEST

NOTES:

1. CPU ADDRESS LATCH SIGNAL PROVIDED BY

PROCESSORS WITH MULTIPLEXED ADDRESS/DATA

BUSES.

2. IF POLARITY_SEL = "1", RD/WR IS HIGH TO READ,

LOW TO WRITE.

3. ZERO_WAIT SHOULD BE STRAPPED TO

LOGIC "1" FOR NON-ZERO WAIT INTERFACE

AND TO LOGIC "0" FOR ZERO WAIT INTERFACE.

4. CPU ACKNOWLEDGE PROCESSOR INPUT ONLY

FOR NON-ZERO WAIT TYPE OF INTERFACE.

IF POLARITY_SEL = "0", RD/WR IS LOW TO READ,

HIGH TO WRITE.

* Additional address lines A12 and A13 are required with the BU-61585.

FIGURE 9. 16-BIT BUFFERED MODE

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+15V +5V

16 MHz

CLOCK

CLK IN

OSCILLATOR

CPU D15-D0

D15-D0

'245

55 Ω

DIR EN

TX/RXA

1

8

7

MEMWR

MEMOE

WR

OE

CS

2

3

RAM

64K x 16 MAX

CH. A

5

4

TX/RXA

55 Ω

IOEN

DTREQ

DTGRT

EN

CPU A15-A0

A15-A0

55 Ω

'244

TX/RXB

1

8

7

ADDRESS

DECODER

2

3

MEMENA-IN

CH. B

5

EN

4

TX/RXB

HOST

ACE

55 Ω

MEMENA-OUT

TRANSPARENT/BUFFERED

SELECT

ADDRESS

MEM/REG

DECODER

RD/WR

STRBD

CPU STROBE

RTAD4-RTAD0

RTADP

RT

ADDRESS,

PARITY

CPU ACKNOWLEDGE

READYD

TAG_CLK

+5V

RESET

MSTCLR

SSFLAG/EXT_TRIG

INT

CPU INTERRUPT REQUEST

FIGURE 10. 16-BIT TRANSPARENT MODE

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CS-L

CS-R

MEMENA-OUT

MEMWR

WR-L

WR-R

DUAL

PORT

RAM

OE-L

OE-R

MEMOE

BUSY-L

BUSY-R

N/C

CPU D15-D0

D15-D0

A15-A0

RD/WR

CPU ADDRESS

RD/WR

+5V

DIR

MEMENA-IN

MEM/REG

'245

EN

HOST

ACE

IOEN

DTREQ

DTGRT

1553 RAM SELECT

1553 REG SELECT

ADDRESS

DECODER

EN

CPU A4-A0

A4-A0

'244

DTACK

N/C

SELECT

CPU DATA STROBE

STRBD

+5V

TRANSPARENT/BUFFERED

READYD

CPU READY

+5V

RESET

MSTCLR

INT

CPU INTERRUPT REQUEST

FIGURE 11. 16-BIT TRANSPARENT MODE USING DUAL PORT RAM

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+15V +5V

16 MHz

CLOCK

CLK IN

OSCILLATOR

CPU D15-D0

RD/WR

D15-D0

55 Ω

TX/RXA

1

8

7

RD/WR

2

3

CH. A

5

MEMWR

MEMOE

WR

OE

CS

RAM

64K x 16 MAX

4

TX/RXA

55 Ω

DTREQ

DTGRT

DTACK

55 Ω

CPU A15-A0

A15-A0

TX/RXB

1

8

7

2

3

CH. B

5

ADDRESS

DECODER

4

TX/RXB

MEMENA-IN

HOST

ACE

55 Ω

EN

MEMENA-OUT

SELECT

ADDRESS

DECODER

MEM/REG

+5V

TRANSPARENT/BUFFERED

CPU STROBE

STRBD

READYD

TAG_CLK

RTAD4-RTAD0

RTADP

RT

ADDRESS,

PARITY

CPU ACKNOWLEDGE

+5V

RESET

MSTCLR

SSFLAG/EXT_TRIG

INT

CPU INTERRUPT REQUEST

FIGURE 12. 16-BIT DIRECT MEMORY ACCESS (DMA) MODE

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+15V +5V

16 MHz

CLOCK

CLK IN

OSCILLATOR

CPU D15-D0

RD/WR

D15-D0

RD/WR

55 Ω

TX/RXA

1

8

7

MEMWR

MEMOE

2

3

WR

OE

CS

CH. A

5

RAM

64K x 16 MAX

4

TX/RXA

55 Ω

DTREQ

DTGRT

DTACK

55 Ω

TX/RXB

1

8

7

CPU A15-A0

A15-A0

2

3

CH. B

5

+5V

4

MEMENA-IN

MEMENA-OUT

MEM/REG

TX/RXB

HOST

ACE

55 Ω

1553 RAM SELECT

1553 REG SELECT

ADDRESS

DECODER

SELECT

+5V

TRANSPARENT/BUFFERED

CPU STROBE

STRBD

READYD

TAG_CLK

RTAD4-RTAD0

RTADP

RT

ADDRESS,

PARITY

CPU ACKNOWLEDGE

+5V

RESET

MSTCLR

SSFLAG/EXT_TRIG

INT

CPU INTERRUPT REQUEST

FIGURE 13. 16-BIT DMA MODE WITH EXTERNAL LOGIC TO REDUCE

PROCESSOR ACCESS TIME TO EXTERNAL RAM

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+15V +5V

16 MHz

CLOCK

CLK IN

OSCILLATOR

CPU D7-D0

(NOTE 1)

D15-D8

D7-D0

A15-A12

A11-A0

55 Ω

TX/RXA

1

8

7

N/C

2

3

CH. A

5

CPU A12-A0

A12-A1

4

ADDR_LAT

MSB/LSB

(NOTE 2)

CPU ADDRESS LATCH

CPU A0

TX/RXA

55 Ω

16/8_BIT

TRANSPARENT/BUFFERED

+5V

55 Ω

(NOTE 3)

POLARITY_SEL

ZERO_WAIT

TX/RXB

1

8

7

2

3

CH. B

(NOTE 4)

(NOTE 5)

5

4

TX/RXB

TRIGGER_SEL

HOST

ACE

55 Ω

SELECT

ADDRESS

DECODER

MEM/REG

RD/WR

STRBD

CPU STROBE

CPU ACKNOWLEDGE

RTAD4-RTAD0

RTADP

RT

ADDRESS,

PARITY

READYD

TAG_CLK

(NOTE 6)

+5V

RESET

MSTCLR

SSFLAG/EXT_TRIG

INT

CPU INTERRUPT REQUEST

NOTES:

1. CPU D7-D0 CONNECTS TO BOTH D15-D8 AND

D7-D0.

TRANSFERS ARE TRIGGERED BY THE MOST SIGNIFICANT

BYTE TRANSFER READ ACCESSES AND BY THE

2. CPU ADDRESS LATCH SIGNAL PROVIDED BY PROCESSORS

WITH MULTIPLEXED ADDRESS/DATA BUFFERS.

3. IF POLARITY_SEL = "1", THEN MSB/LSB SELECTS THE MOST

SIGNIFICANT BYTE WHEN LOW, AND THE LEAST

SIGNIFICANT BYTE WHEN HIGH.

IF POLARITY_SEL = "0", THEN MSB/LSB SELECTS THE LEAST

SIGNIFICANT BYTE WHEN LOW, AND THE MOST

SIGNIFICANT BYTE WHEN HIGH.

4. ZERO WAIT SHOULD BE STRAPPED TO LOGIC "1" FOR

NON-ZERO WAIT INTERFACE AND TO LOGIC "0" FOR

ZERO WAIT INTERFACE.

5. OPERATION OF TRIGGER_SELECT INPUT IS AS FOLLOWS:

FOR NON-ZERO WAIT INTERFACE (ZERO WAIT = "1"):

IF TRIGGER_SEL = "1", THEN INTERNAL 16-BIT

LEAST SIGNIFICANT BYTE TRANSFER FOR WRITE ACCESSES.

IF TRIGGER_SEL = "0", THEN INTERNAL 16-BIT

TRANSFERS ARE TRIGGERED BY THE LEAST SIGNIFICANT

BYTE TRANSFER FOR READ ACESSES AND BY THE MOST

SIGNIFICANT BYTE TRANSFER FOR WRITE ACCESSES.

FOR ZERO WAIT INTERFACE (ZERO WAIT = "0"):

IF TRIGGER_SEL = "1", THEN INTERNAL 16-BIT

TRANSFERS ARE TRIGGERED BY THE LEAST SIGNIFICANT

BYTE TRANSFER, FOR BOTH READ AND WRITE ACCESSES.

IF TRIGGER_SEL = "0", THEN INTERNAL 16-BIT

TRANSFERS ARE TRIGGERED BY THE MOST SIGNIFICANT

BYTE TRANSFER, FOR BOTH READ AND WRITE ACCESSES.

6. CPU ACKNOWLEDGE PROCESSOR INPUT ONLY FOR NON-ZERO

WAIT TYPE OF INTERFACE.

* Additional address lines A12 and A13 are required with the BU-61585.

FIGURE 14. 8-BIT BUFFERED MODE

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t5

CLOCK IN

t1

SELECT

(Note 2,7)

t6

t2

t18

t14

STRBD

(Note 2)

VALID

MEM/REG

(Note 3,4,7)

t7

t8

t3

RD/WR

(Note 4,5)

t11

IOEN

(Note 2,6)

t15

t13

READYD

t4

(Note 6)

t12

t9

t19

t10

VALID

A15-A0

(Note 7,8,9)

t16

VALID

D15-D0

(Note 6)

t17

FIGURE 15. CPU READING RAM (SHOWN FOR 16-BIT, BUFFERED, NONZERO WAIT MODE)

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TABLE FOR FIGURE 15. CPU READING RAM OR REGISTERS (SHOWN FOR 16-BIT, BUFFERED, NONZERO WAIT MODE)

REF

t1

DESCRIPTION

MIN

TYP

MAX UNITS

NOTE REFERENCE

notes 2, 10

SELECT and STRBD low setup time prior to clock rising edge

SELECT and STRBD low delay to IOEN low (uncontended access @ 16 MHz)

SELECT and STRBD low delay to IOEN low (contended access @ 16 MHz)

SELECT and STRBD low delay to IOEN low (uncontended access @ 12 MHz)

SELECT and STRBD low delay to IOEN low (contended access @ 12 MHz)

MEM/REG, RD/WR setup time following SELECT and STRBD low(@ 16 MHz)

MEM/REG, RD/WR setup time following SELECT and STRBD low(@ 12 MHz)

Address valid setup time following SELECT and STRBD low (@ 16 MHz)

Address valid setup time following SELECT and STRBD low (@ 12 MHz)

CLOCK IN rising edge delay to IOEN falling edge

10

ns

t2

107.5

2.8

128.3

3.7

10

ns

µs

ns

µs

ns

notes 2, 6

t2

notes 2, 6

t2

notes 2, 6

t2

notes 2, 6

t3

notes 3, 4, 5, 7

t3

20

t4

30

t4

50

t5

35

note 6

note 2

t6

SELECT hold time following IOEN falling

0

t7

MEM/REG, RD/WR setup time prior to CLOCK IN falling edge

MEM/REG, RD/WR hold time prior to CLOCK IN falling edge

Address valid setup time prior to CLOCK IN rising edge

10

notes 3, 4, 5, 7

notes 7, 8, 9

notes 7, 8, 9, 10

notes 6, 10

note 6

t8

30

t9

30

t10

t11

t12

Address hold time following CLOCK IN rising edge

30

IOEN falling delay to READYD falling (reading RAM @ 16 MHz)

IOEN falling delay to READYD falling (reading RAM @ 12 MHz)

IOEN falling delay to READYD falling (reading registers @ 16 MHz)

IOEN falling delay to READYD falling (reading registers @ 12 MHz)

Output Data valid prior to READYD falling (@ 16 MHz)

170

235

170

235

33

187.5

250

205

265

205

265

187.5

250

Output Data valid prior to READYD falling (@ 12 MHz)

54

note 6

t13

t14

t15

CLOCK IN rising edge delay to READYD falling

35

∞

ns

note 6

READYD falling to STRBD rising release time

STRBD rising edge delay to IOEN rising edge and READYD rising edge

30

note 6

t16

t17

t18

t19

Output Data hold time following STRBD rising edge

STRBD rising delay to output Data tri-state

STRBD high hold time from READYD rising

CLOCK IN rising edge delay to Output Data valid

0

ns

40

60

Notes for FIGURE 15 and associated table.

6. The timing for IOEN, READYD and D15-D0 assumes a 50 pf

load. For loading above 50 pf, the validity of IOEN, READYD, and

D15-D0 is delayed by an additional 0.14 ns/pf typ, 0.28 ns/pf max.

7. Timing for A15-A0, MEM/REG and SELECT assumes ADDR-LAT

is connected to logic "1." Refer to Address Latch timing for addition-

al details.

1. For the 16-bit buffered nonzero wait configuration, TRANSPA-

RENT/BUFFERED must be connected to logic "0". ZERO_WAIT

and DTREQ/16/8 must be connected to logic "1". The inputs TRIG-

GER_SEL and MSB/LSB may be connected to either +5 V or

ground.

2. SELECT and STRBD may be tied together. IOEN goes low on

the first rising CLK edge when SELECT• STRBD is sampled low

(satisfying t1) and the BU-65170/61580's protocol/memory manage-

ment logic is not accessing the internal RAM. When this occurs,

IOEN goes low, starting the transfer cycle. After IOEN goes low,

SELECT may be released high.

3. MEM/REG must be presented high for memory access, low for

register access.

4. MEM/REG and RD/WR are buffered transparently until the first

falling edge of CLK after IOEN goes low. After this CLK edge,

MEM/REG and RD/WR become latched internally.

8. Internal RAM is accessed by A11 through A0 (A13 through A0 for

61585 and 61586). Registers are accessed by A4 through A0.

9. The address bus A15-A0 is internally buffered transparently until

the first rising edge of CLK after IOEN goes low. After this CLK

edge, A15-A0 become latched internally.

10. Setup time given for use in worst case timing calculations.

None of the ACE input signals are required to be synchronized to

the system clock. For ACE applications only, where SELECT and

STRBD do not meet the setup time of t1, but occur during the setup

window of an internal flip-flop, an additional clock cycle will be

inserted between the falling clock edge that latches MEM/REG and

RD/WR and the rising clock edge that latches the Address (A15-

A0). When this occurs, the pulse width of IOEN falling to READYD

falling (t11) increases by one clock cycle and the address hold time

(t10) must be increased be one clock cycle.

5. The logic sense for RD/WR in the diagram assumes that POLAR-

ITY_SEL is connected to logic "1." If POLARITY_SEL is connected

to logic "0," RD/WR must be asserted low to read.

Data Device Corporation

www.ddc-web.com

BU-65170/61580/61585

H1 web-09/02-0

29

t6

CLOCK IN

t1

SELECT

(Note 2,7)

t7

t16

t2

t18

STRBD

(Note 2)

VALID

MEM/REG

(Note 3,4,7)

t8

t9

t3

RD/WR

(Note 4,5)

t14

IOEN

(Note 2,6)

t15

t17

READYD

t4

t5

(Note 6)

t10

t12

t13

VALID

A15-A0

(Note 7,8,9,10)

t11

VALID

D15-D0

(Note 9,10)

FIGURE 16. CPU WRITING RAM (SHOWN FOR 16-BIT, BUFFERED, NONZERO WAIT MODE)

Data Device Corporation

www.ddc-web.com

BU-65170/61580/61585

H1 web-09/02-0

30

TABLE FOR FIGURE 16. CPU WRITING RAM OR REGISTERS (SHOWN FOR 16-BIT, BUFFERED, NONZERO WAIT MODE)

REF

t1

DESCRIPTION

MIN

TYP

MAX UNITS NOTE REFERENCE

SELECT and STRBD low setup time prior to CLOCK IN rising edge