BU-61864 [ETC]
MIL-STD-1553 Components |Enhanced Mini-ACE? ; MIL -STD -1553组件|增强型的Mini- ACE ?\n型号: | BU-61864 |
厂家: | ETC |
描述: | MIL-STD-1553 Components |Enhanced Mini-ACE?
|
文件: | 总60页 (文件大小:453K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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BU-6174X/6184X/6186X
®
ENHANCED MINIATURE ADVANCED
COMMUNICATIONS ENGINE
[ENHANCED MINI-ACE/µ-ACE (MICRO-ACE)]
FEATURES
• Fully Integrated 1553A/B Notice 2,
McAir, STANAG 3838 Interface Terminal
• Compatible with Mini-ACE (Plus)
and ACE Generations
• Choice of :
RT or BC/RT/MT In Same Footprint
-
- RT or BC/RT/MT with 4K RAM
- BC/RT/MT with 64K RAM, and RAM
parity
• Choice of 5V or 3.3V Logic
• Package Options:
- 1" Square Ceramic Flat Pack or
Gull Wing
- 0.815" Square BGA (µ-ACE)
DESCRIPTION
• 5V Transceiver with 1760 and McAir
Compatible Options
The Enhanced Miniature Advanced Communications Engine (Enhanced
Mini-ACE) and µ-ACE (Micro-ACE) family of MIL-STD-1553 terminals pro-
vide complete interfaces between a host processor and a 1553 bus, and
integrate dual transceiver, protocol logic, and 4K or 64K words of RAM.
• Comprehensive Built-In Self-Test
• Flexible Processor/Memory Interface,
with Reduced Host Wait Time
At 0.815" square, the µ-ACE (BGA package) option provides the
smallest footprint in the industry.
• Choice of 10, 12, 16, or 20 MHz Clock
• Highly Autonomous BC with
Built-In Message Sequence Control:
- Frame Scheduling
The terminals are powered by a choice of 5V or 3.3V logic.
Multiprotocol support of MIL-STD-1553A/B and STANAG 3838, includ-
ing versions incorporating McAir compatible transmitters, is provided.
There is a choice of 10, 12, 16, or 20 MHz clocks. The BC/RT/MT ver-
sions with 64K words of RAM include built-in RAM parity checking.
- Branching
- Asynchronous Message Insertion
- General Purpose Queue
- User-defined Interrupts
BC features include a built-in message sequence control engine, with
a set of 20 instructions. This feature provides an autonomous means
of implementing multi-frame message scheduling, message retry
schemes, data double buffering, asynchronous message insertion,
and reporting to the host CPU.The Enhanced Mini-ACE/µ-ACE incor-
porates a fully autonomous built-in self-test, providing comprehensive
testing of the internal protocol logic and/or RAM.
• Advanced RT Functions
- Global Circular Buffering
- Interrupt Status Queue
- 50% Circular Buffer Rollover
Interrupts
• Selective Message Monitor
- Selection by Address, T/R Bit,
Subaddress
The RT offers the same choices of subaddress buffering as the ACE
and Mini-ACE (Plus), along with a global circular buffering option,
50% rollover interrupt for circular buffers, an interrupt status queue,
and an "Auto-boot" option to support MIL-STD-1760.
- Command and Data Stacks
- 50% and 100% Stack Rollover
Interrupts
The terminals provide the same flexibility in host interface configura-
tions as the ACE/Mini-ACE, along with a reduction in the host proces-
sor's worst case holdoff time. Most software features are compatible
with the previous generations of the Mini-ACE (Plus) and ACE series.
FOR MORE INFORMATION CONTACT:
Technical Support:
1-800-DDC-5757 ext. 7234
Data Device Corporation
105 Wilbur Place
Bohemia, New York 11716
631-567-5600 Fax: 631-567-7358
www.ddc-web.com
©
2000 Data Device Corporation
TX/RX_A
SHARED
RAM
(1)
TRANSCEIVER
A
CH. A
DATA
PROCESSOR
DATA BUS
DATA BUS
D15-D0
A15-A0
BUFFERS
TX/RX_A
TX/RX_B
DUAL
ENCODER/DECODER,
MULTIPROTOCOL
AND
MEMORY
MANAGEMENT
ADDRESS
BUFFERS
PROCESSOR
ADDRESS BUS
ADDRESS BUS
TRANSCEIVER
B
CH. B
TX/RX_B
TRANSPARENT/BUFFERED, STRBD, SELECT,
RD/WR, MEM/REG, TRIGGER_SEL/MEMENA-IN,
MSB/LSB/DTGRT
PROCESSOR
AND
MEMORY
INTERFACE
LOGIC
PROCESSOR
AND
MEMORY
CONTROL
RT ADDRESS
RTAD4-RTAD0, RTADP
IOEN, READYD
ADDR_LAT/MEMOE, ZERO_WAIT/MEMWR,
8/16-BIT/DTREQ, POLARITY_SEL/DTACK
INCMD/MCRST, INCMD , MCRST
(2)
(2)
INT
INTERRUPT
REQUEST
CLK_IN, TAG_CLK
MSTCLR, SSFLAG/EXT_TRG, TX-INH_A, TX-INH_B,
UPADDREN, RSBITEN
,
(2)
MISCELLANEOUS
(2)
NOTE 1: See Ordering Information for Available Memory Options.
NOTE 2: Indicates signals brought out only on µ-ACE (BGA package) version.
FIGURE 1. ENHANCED MINIATURE ADVANCED COMMUNICATIONS ENGINE BLOCK DIAGRAM
TABLE 1. ENHANCED MINI-ACE/µ-ACE SERIES
SPECIFICATIONS
TABLE 1. ENHANCED MINI-ACE/µ-ACE SERIES
SPECIFICATIONS (CONT.)
PARAMETER
MIN TYP MAX UNITS
PARAMETER
MIN
TYP
MAX
UNITS
LOGIC (CONT)
ABSOLUTE MAXIMUM RATING
Supply Voltage
• Logic +5V or +3.3V
• RAM +5V
• Transceiver +5V (Note 12)
Logic
• Voltage Input Range for +5V
Logic (BU-61XX0/5)
• Voltage Input Range for +3.3V
Logic (BU-61XX0/3/5)
CI (Input Capacitance)
CIO (Bi-directional signal input
capacitance)
50
50
pF
pF
-0.3
-0.3
-0.3
6.0
6.0
7.0
V
V
V
POWER SUPPLY REQUIREMENTS
Voltages/Tolerances
• +5V (RAM for 61860/4/5),
Logic for BU-61XX5) (Note 12)
• +3.3V (Logic for BU-61XX0/3/4)
(Note 12)
-0.3
-0.3
6.0
6.0
V
V
4.5
3.0
5.0
3.3
5.0
5.5
3.6
V
V
V
RECEIVER
• +5V (Ch. A, Ch. B)
4.75
5.25
Differential Input Resistance
(Notes 1-6)
Differential Input Capacitance
(Notes 1-6)
2.5
kΩ
pF
Current Drain (Total Hybrid)
• BU-61865XX-XX0
5
+5V (Logic, RAM, Ch. A, Ch. B)
• Idle
180
285
390
600
mA
mA
mA
mA
Threshold Voltage, Transformer
Coupled, Measured on Stub
Common Mode Voltage (Note 7)
0.200
0.860
10
Vp-p
Vpeak
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
• BU-61865/0X3-XX2
+5V (Logic, RAM, Ch. A, Ch. B)
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
• BU-61864XX-XX0
+5V (RAM, Ch. A, Ch. B)
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
• 3.3V Logic
• BU-61864/0X3-XX2
+5V (RAM, Ch. A, Ch. B)
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
• 3.3V Logic
• BU-61745XX-XX0. BU-61845XX-XX0
+5V (Logic, RAM, Ch. A, Ch. B)
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
• BU-61745/0X3-XX2,
TRANSMITTER
Differential Output Voltage
• Direct Coupled Across 35 Ω,
Measured on Bus
• Transformer Coupled Across
70 Ω, Measured on Bus
(BU-61XXXXX-XX0,
BU-61XXXXX-XX2) (Note 13)
Output Noise, Differential (Direct
Coupled)
Output Offset Voltage, Transformer
Coupled Across 70 ohms
Rise/Fall Time
180
296
412
645
mA
mA
mA
mA
6
7
9
Vp-p
18
20
20
22
27
27
10
Vp-p
Vp-p
mVp-p
120
225
330
540
40
mA
mA
mA
mA
mA
-250
250
mVp
100
200
150
250
300
300
nsec
nsec
(BU-61XXXX3,
BU-61XXXX4)
120
236
352
585
40
mA
mA
mA
mA
mA
LOGIC
VIH
All signals except CLK_IN
CLK_IN
VIL
All signals except CLK_IN
CLK_IN
Schmidt Hysteresis
All signals except CLK_IN
CLK_IN
2.1
0.8•Vcc
V
V
0.7
0.2•Vcc
V
V
160
265
370
580
mA
mA
mA
mA
0.4
1.0
V
V
IIH, IIL
All signals except CLK_IN
IIH (Vcc=5.25V, VIN=Vcc)
IIH (Vcc=5.25V, VIN=2.7V)
IIH (Vcc=3.6V, VIN=Vcc)
IIH (Vcc=3.6V, VIN=2.7V)
IIL (Vcc=5.25V, VIN=0.4V)
IIL (Vcc=3.6V, VIN=0.4V)
CLK_IN
BU-61845/0X3-XX2
+5V (Logic, RAM, Ch. A, Ch. B)
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
• BU-61743XX-XX0, BU-61843XX-XX0
+5V (Ch. A, Ch. B)
-10
-350
-10
-350
-350
-350
10
-50
10
-33
-50
-33
µA
µA
µA
µA
µA
µA
160
276
392
625
mA
mA
mA
mA
IIH
IIL
-10
-10
2.4
10
10
µA
µA
V
• Idle
100
205
310
520
40
mA
mA
mA
mA
mA
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
• 3.3V Logic
• BU-61743/0X3-XX2,
BU-61843/0X3-XX2
+5V (Ch. A, Ch. B)
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
• 3.3V Logic
VOH (Vcc=4.5V, VIH=2.7V,
VIL=0.2V, IOH=max)
VOH (Vcc=3.0V, VIH=2.7V,
VIL=0.2V, IOH=max)
VOL (Vcc=4.5V, VIH=2.7V,
VIL=0.2V, IOL=max)
VOL (Vcc=3.0V, VIH=2.7V,
VIL=0.2V, IOL=max)
IOL
2.4
3.4
V
V
V
0.4
0.4
100
216
332
565
40
mA
mA
mA
mA
mA
mA
mA
IOH
-3.4
Data Device Corporation
www.ddc-web.com
BU-6174X/6184X/6186X
web rev G2-03/03-0
3
TABLE 1. ENHANCED MINI-ACE/µ-ACE SERIES
SPECIFICATIONS (CONT.)
TABLE 1. ENHANCED MINI-ACE/µ-ACE SERIES
SPECIFICATIONS (CONT.)
PARAMETER
MIN TYP MAX UNITS
PARAMETER
MIN TYP MAX UNITS
POWER DISSIPATION (NOTE 14)
Total Hybrid
• BU-61865XX-XX0
CLOCK INPUT (CONT)
• Short Term Tolerance, 1 second
• 1553A Compliance
• 1553B Compliance
• Duty Cycle
-0.001
-0.01
40
0.001
0.01
60
%
%
%
• Idle
0.99
1.22
1.45
1.90
W
W
W
W
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
• BU-61865/0X3-XX2
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
• BU-61864XX-XX0
1553 MESSAGE TIMING
Completion of CPU Write
(BC Start)-to-Start of First Message
(for Non-enhanced BC Mode)
BC Intermessage Gap (Note 8)
Non-enhanced
2.5
9.5
µs
µs
µs
0.99
1.28
1.58
2.16
W
W
W
W
(Mini-ACE compatible) BC mode
Enhanced BC mode (Note 9)
10.0
to
10.5
• Idle
0.80
1.03
1.26
1.71
W
W
W
W
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
• BU-61864/0X3-XX2
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
• BU-61745XX-XX0, BU-61845XX-XX0
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
• BU-61745/0X3-XX2,
BU-61845/0X3-XX2
BC/RT/MT Response Timeout (Note 10)
• 18.5 nominal
• 22.5 nominal
• 50.5 nominal
• 128.0 nominal
RT Response Time
(mid-parity to mid-sync) (Note 11)
Transmitter Watchdog Timeout
17.5 18.0 19.5
21.5 22.5 23.5
49.5 50.5 51.5
127 129.5 131
µs
µs
µs
µs
µs
0.80
1.09
1.39
1.97
W
W
W
W
4
7
660.5
µs
0.88
1.11
1.33
1.79
W
W
W
W
THERMAL
Operating Case/Ball Temperature
-1XX, -4XX
-2XX, -5XX
-3XX, -8XX
-55
-40
0
-55
-65
+125
+85
+70
160
160
°C
°C
°C
°C
°C
°C
°C
• Idle
0.88
1.17
1.46
2.05
W
W
W
W
Operating Junction Temperature
Storage Temperature
Lead Temperature (soldering, 10 sec.)
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
• BU-61743XX-XX0, BU-61843XX-XX0
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
• BU-61743/0X3-XX2,
+300
Thermal Resistance
Enhanced Mini-ACE
Ceramic Flat pack / Gull Wing package
Junction-to-Case, Hottest Die (θJC)
0.69
0.92
1.15
1.60
W
W
W
W
9
11
22
°C/W
µ-ACE
BU-61843/0X3-XX2
BGA package
• Idle
0.69
0.98
1.28
1.86
W
W
W
W
(see Thermal Management Section)
Junction-to-Balls, Hottest Die (θJB)
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
Hottest Die
• BU-61XXXXX-XX0
• Idle
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
• BU-61XXXX3-XX2
18
°C/W
in.
PHYSICAL CHARACTERISTICS
Size
Enhanced Mini-ACE
1.0 X 1.0 X 0.155
Ceramic Flat pack / Gull Wing package
(25.4 x 25.4 x 3.94) (mm)
0.28
0.51
0.75
1.22
W
W
W
W
µ-ACE
BGA package
0.815 X 0.815 X 0.140
in.
(20.7 x 20.7 x 3.58) (mm)
Weight
Enhanced Mini-ACE
Ceramic Flat pack / Gull Wing package
0.6
(17)
oz
(g)
• Idle
0.28
0.58
0.88
1.48
W
W
W
W
• 25% Transmitter Duty Cycle
• 50% Transmitter Duty Cycle
• 100% Transmitter Duty Cycle
µ-ACE
BGA package
.088
(2.5)
oz
(g)
CLOCK INPUT
Frequency
• Nominal Value
• Default Mode
• Option
• Option
• Option
• Long Term Tolerance
• 1553A Compliance
• 1553B Compliance
TABLE 1 NOTES:
16.0
12.0
10.0
20.0
MHz
MHz
MHz
MHz
Notes 1 through 6 are applicable to the Receiver Differential Resistance
and Differential Capacitance specifications:
(1) Specifications include both transmitter and receiver (tied together
internally).
-0.01
-0.10
0.01
0.10
%
%
(2) Impedance parameters are specified directly between pins TX/RX_A(B)
and TX/RX_A(B) of the Enhanced Mini-ACE/µ-ACE hybrid.
Data Device Corporation
www.ddc-web.com
BU-6174X/6184X/6186X
web rev G2-03/03-0
4
TABLE 1 NOTES: (Cont’d)
INTRODUCTION
(3) It is assumed that all power and ground inputs to the hybrid are con-
nected.
The BU-61740/61743/61745 RT, and BU-61840/61843/61845/
61860/61864/61865 BC/RT/MT Enhanced Mini-ACE/µ-ACE
family of MIL-STD-1553 terminals comprise a complete integrat-
ed interface between a host processor and a MIL-STD-1553 bus.
The Enhanced Mini-ACE is available as a 1.0 square inch flat
pack or gull wing package. The µ-ACE is available as a 0.815
square inch BGA package. These terminals are nearly 100%
software compatible with the previous generation Mini-ACE and
Mini-ACE Plus terminals, and are software compatible with the
original ACE series.
(4) The specifications are applicable for both unpowered and powered
conditions.
(5) The specifications assume a 2 volt rms balanced, differential, sinu-
soidal input. The applicable frequency range is 75 kHz to 1 MHz.
(6) Minimum resistance and maximum capacitance parameters are
guaranteed over the operating range, but are not tested.
(7) Assumes a common mode voltage within the frequency range of dc
to 2 MHz, applied to pins of the isolation transformer on the stub
side (either direct or transformer coupled), and referenced to hybrid
ground. Transformer must be a DDC recommended transformer or
other transformer that provides an equivalent minimum CMRR.
(8) Typical value for minimum intermessage gap time. Under software
control, this may be lengthened (to 65,535 ms - message time) in
increments of 1 µs. If ENHANCED CPU ACCESS, bit 14 of
Configuration Register #6, is set to logic "1", then host accesses
during BC Start-of-Message (SOM) and End-of-Message (EOM)
transfer sequences could have the effect of lengthening the inter-
message gap time. For each host access during an SOM or EOM
sequence, the intermessage gap time will be lengthened by 6 clock
cycles. Since there are 7 internal transfers during SOM and 5 dur-
ing EOM, this could theoretically lengthen the intermessage gap by
up to 72 clock cycles; i.e., up to 7.2 ms with a 10 MHz clock, 6.0 µs
with a 12 MHz clock, 4.5 µs with a 16 MHz clock, or 3.6 µs with a
20 MHz clock.
The Enhanced Mini-ACE provides complete multiprotocol support of
MIL-STD-1553A/B/McAir and STANAG 3838. All versions integrate
a dual transceiver, along with protocol, host interface, memory man-
agement logic, and either 4K or 64K words of RAM. In addition, the
BU-61864 and BU-61865 BC/RT/MT terminals include 64K words
of internal RAM, with built-in parity checking.
The Enhanced Mini-ACE includes a 5V voltage source transceiv-
er for improved line driving capability, with options for MIL-STD-
1760 and McAir compatibility, and the µ-ACE is MIL-STD-1760
compatible. As a means of reducing power consumption, there
are versions for which the logic is powered by 3.3V, rather than
5V. To provide further flexibility, the Enhanced Mini-ACE/µ-ACE
may operate with a choice of 10, 12, 16, or 20 MHz clock inputs.
(9) For Enhanced BC mode, the typical value for intermessage gap
time is approximately 10 clock cycles longer than for the non-
enhanced BC mode. That is, an addition of 1.0 µs at 10 MHz, 833
ns at 12 MHz, 625 ns at 16 MHz, or 500 ns at 20 MHz.
(10) Software programmable (4 options). Includes RT-to-RT Timeout
(measured mid-parity of transmit Command Word to mid-sync of
transmitting RT Status Word).
One of the new salient features of the Enhanced Mini-ACE/µ-ACE
is its Enhanced bus controller architecture. The Enhanced BC's
highly autonomous message sequence control engine provides
a means for offloading the host processor for implementing multi-
frame message scheduling, message retry schemes, data dou-
ble buffering, and asynchronous message insertion. For the pur-
pose of performing messaging to the host processor, the
Enhanced BC mode includes a General Purpose Queue, along
with user-defined interrupts.
(11) Measured from mid-parity crossing of Command Word to mid-sync
crossing of RT's Status Word.
(12) External 10 µF tantalum and 0.1 µF capacitors should be located as
close as possible to input signals “+5V Vcc CH A” and “+5V Vcc CH
B”, and a 0.1 µF to input signal “+5V/+3.3V Logic”. For the BU-
61864 and BU-61865, and BU-61860 versions, there should also be
a 0.1 µF capacitor for the input signal “+5V RAM”.
A second major new feature of the Enhanced Mini-ACE/µ-ACE is
the incorporation of a fully autonomous built-in self-test. This test
provides comprehensive testing of the internal protocol logic. A
separate test verifies the operation of the internal RAM. Since
the self-tests are fully autonomous, they eliminate the need for
the host to write and read stimulus and response vectors.
(13) MIL-STD-1760 requires a 20 Vp-p minimum output on the stub con-
nection.
(14) Power dissipation specifications assume a transformer coupled
configuration with external dissipation (while transmitting) of:
0.14 watts for the active isolation transformer,
The Enhanced Mini-ACE/µ-ACE RT offers the same choices of
single, double, and circular buffering for individual subaddresses
as ACE and Mini-ACE (Plus). New enhancements to the RT
architecture include a global circular buffering option for multiple
(or all) receive subaddresses, a 50% rollover interrupt for circu-
lar buffers, an interrupt status queue for logging up to 32 inter-
rupt events, and an option to automatically initialize to RT mode
with the Busy bit set.The interrupt status queue and 50% rollover
interrupt features are also included as improvements to the
Enhanced Mini-ACE/µ-ACE's Monitor architecture.
0.08 watts for the active bus coupling transformer,
0.45 watts for each of the two bus isolation resistors and
0.15 watts for each of the two bus termination resistors.
Data Device Corporation
www.ddc-web.com
BU-6174X/6184X/6186X
web rev G2-03/03-0
5
To minimize board space and "glue" logic, the Enhanced Mini-
ACE/µ-ACE terminals provide the same wide choice of host
interface configurations as the ACE and Mini-ACE (Plus). This
includes support of interfaces to 16-bit or 8-bit processors, mem-
ory or port type interfaces, and multiplexed or non-multiplexed
address/data buses. In addition, with respect to ACE/Mini-ACE
(Plus), the worst case processor wait time has been significant-
ly reduced. For example, assuming a 16 MHz clock, this time has
been reduced from 2.8 µs to 632 ns for read accesses, and to
570 ns for write accesses.
TABLE 2. ADDRESS MAPPING
REGISTER
DESCRIPTION/ACCESSIBILITY
ADDRESS LINES
A4 A3 A2 A1 A0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
Interrupt Mask Register #1 (RD/WR)
Configuration Register #1 (RD/WR)
Configuration Register #2 (RD/WR)
Start/Reset Register (WR)
Non-Enhanced BC/RT Command Stack Pointer /
Enhanced BC Instruction List Pointer Register
(RD)
0
0
0
0
0
1
1
0
1
0
The Enhanced Mini-ACE series terminals operate over the full
military temperature range of -55 to +125°C. Available screened
to MIL-PRF-38534C, the terminals are ideal for military and
industrial processor-to-1553 applications.
BC Control Word /
RT Subaddress Control Word Register (RD/WR)
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
Time Tag Register (RD/WR)
Interrupt Status Register #1 (RD)
TEST COMPONENTS
Configuration Register #3 (RD/WR)
Configuration Register #4 (RD/WR)
Configuration Register #5 (RD/WR)
RT / Monitor Data Stack Address Register (RD)
BC Frame Time Remaining Register (RD)
Daisy chain mechanical samples of the µ-ACE, 128-ball BGA
(BU-61863B3-601) are available. These are used to verify both
the electrical and mechanical integrity of the solder joints
between the BGA package and the board. Ball pairs are inter-
nally wired so that the user can test for electrical continuity
between balls. Refer to TABLE 57 for connection details.
BC Time Remaining to Next Message Register
(RD)
0
0
1
1
1
1
0
0
0
1
Although these units are inert, they are fully populated with sili-
con die so that they closely match the thermal and mechanical
characteristics of standard production units. Internal daisy chain
interconnections are made by gold wire bonds between the sub-
strate pads.
Non-Enhanced BC Frame Time / Enhanced BC
Initial Instruction Pointer / RT Last Command /
MT Trigger Word Register(RD/WR)
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
RT Status Word Register (RD)
RT BIT Word Register (RD)
Test Mode Register 0
TRANSCEIVERS
The transceivers in the Enhanced Mini-ACE/µ-ACE series termi-
nals are fully monolithic, requiring only a +5 volt power input.
The transmitters are voltage sources, which provide improved
line driving capability over current sources. This serves to
improve performance on long buses with many taps. The trans-
mitters also offer an option which satisfies the MIL-STD-1760
requirement for a minimum of 20 volts peak-to-peak, transformer
coupled output.
Test Mode Register 1
Test Mode Register 2
Test Mode Register 3
Test Mode Register 4
Test Mode Register 5
Test Mode Register 6
Test Mode Register 7
Configuration Register #6 (RD/WR)
Configuration Register #7 (RD/WR)
RESERVED
Besides eliminating the demand for an additional power supply, the
use of a +5V only transceiver requires the use of a step-up, rather
than a step-down, isolation transformer. This provides the advan-
tage of a higher terminal input impedance than is possible for a 15
volt or 12 volt transmitter. As a result, there is a greater margin for
the input impedance test, mandated for the 1553 validation test.
This allows for longer cable lengths between a system connector
and the isolation transformers of an embedded 1553 terminal.
BC Condition Code Register (RD)
BC General Purpose Flag Register (WR)
BIT Test Status Register (RD)
Interrupt Mask Register #2 (RD/WR)
Interrupt Status Register #2 (RD)
To provide compatibility to McAir specs, the Enhanced Mini-
ACE’s are available with an option for transmitters with increased
rise and fall times.
BC General Purpose Queue Pointer /
RT-MT Interrupt Status Queue Pointer Register
(RD/WR)
1
1
1
1
1
Additionally, for MIL-STD-1760 applications, the Enhanced Mini-
ACE provides an option for a minimum stub voltage level of 20
volts peak-to-peak, transformer coupled.
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TABLE 3. INTERRUPT MASK REGISTER #1
(READ/WRITE 00H)
The receiver sections of the Enhanced Mini-ACE/µ-ACE are
fully compliant with MIL-STD-1553B Notice 2 in terms of front
end overvoltage protection, threshold, common mode rejection,
and word error rate.
BIT
15(MSB) RESERVED
DESCRIPTION
14
13
12
11
10
9
RAM PARITY ERROR
REGISTER AND MEMORY ADDRESSING
The software interface of the Enhanced Mini-ACE/µ-ACE to the
host processor consists of 24 internal operational registers for
normal operation, an additional 24 test registers, plus 64K words
of shared memory address space. The Enhanced Mini-ACE/µ-
ACE's 4K X 16 or 64K X 17 internal RAM resides in this address
space.
BC/RT TRANSMITTER TIMEOUT
BC/RT COMMAND STACK ROLLOVER
MT COMMAND STACK ROLLOVER
MT DATA STACK ROLLOVER
HANDSHAKE FAIL
8
BC RETRY
7
RT ADDRESS PARITY ERROR
TIME TAG ROLLOVER
For normal operation, the host processor only needs to access
the lower 32 register address locations (00-1F). The next 32
locations (20-3F) should be reserved, since many of these are
used for factory test.
6
5
RT CIRCULAR BUFFER ROLLOVER
BC CONTROL WORD/RT SUBADDRESS CONTROL WORD EOM
BC END OF FRAME
4
3
INTERNAL REGISTERS
The address mapping for the Enhanced Mini-ACE/µ-ACE regis-
2
FORMAT ERROR
ters is illustrated in TABLE 2.
1
BC STATUS SET/RT MODE CODE/MT PATTERN TRIGGER
0(LSB) END OF MESSAGE
TABLE 4. CONFIGURATION REGISTER #1
(READ/WRITE 01H)
BC FUNCTION (Bits
11-0 Enhanced Mode Only)
RT WITHOUT ALTERNATE
STATUS
RT WITH ALTERNATE
STATUS (Enhanced Only) (Enhanced mode only bits 12-0)
MONITOR FUNCTION
BIT
15 (MSB) RT/BC-MT (logic 0)
(logic 1)
(logic 1)
(logic 0)
14
13
12
MT/BC-RT (logic 0)
(logic 0)
(logic 0)
(logic 1)
CURRENT AREA B/A
MESSAGE STOP-ON-ERROR
CURRENT AREA B/A
CURRENT AREA B/A
CURRENT AREA B/A
MESSAGE MONITOR ENABLED
MESSAGE MONITOR ENABLED MESSAGE MONITOR
(MMT)
ENABLED
11
10
9
FRAME STOP-ON-ERROR
DYNAMIC BUS CONTROL
ACCEPTANCE
S10
TRIGGER WORD ENABLED
START-ON-TRIGGER
STATUS SET
STOP-ON-MESSAGE
BUSY
S09
S08
S07
STATUS SET
STOP-ON-FRAME
SERVICE REQUEST
SSFLAG
STOP-ON-TRIGGER
8
7
6
5
FRAME AUTO-REPEAT
NOT USED
EXTERNAL TRIGGER ENABLED RTFLAG (Enhanced Mode Only) S06
EXTERNAL TRIGGER ENABLED
NOT USED
INTERNAL TRIGGER ENABLED NOT USED
S05
S04
INTERMESSAGE GAP TIMER
ENABLED
NOT USED
NOT USED
4
3
2
1
RETRY ENABLED
NOT USED
NOT USED
NOT USED
NOT USED
S03
S02
S01
S00
NOT USED
DOUBLED/SINGLE RETRY
BC ENABLED (Read Only)
NOT USED
MONITOR ENABLED(Read Only)
BC FRAME IN PROGRESS
(Read Only)
MONITOR TRIGGERED
(Read Only)
0 (LSB)
BC MESSAGE IN PROGRESS
(Read Only)
RT MESSAGE IN PROGRESS
(Enhanced mode only,Read Only) PROGRESS (Read Only)
RT MESSAGE IN
MONITOR ACTIVE
(Read Only)
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TABLE 5. CONFIGURATION REGISTER #2
(READ/WRITE 02H)
TABLE 8. BC CONTROL WORD REGISTER
(READ/WRITE 04H)
BIT
DESCRIPTION
BIT
DESCRIPTION
TRANSMIT TIME TAG FOR SYNCHRONIZE MODE COM-
MAND
15(MSB) ENHANCED INTERRUPTS
15(MSB)
14
RAM PARITY ENABLE
14
MESSAGE ERROR MASK
SERVICE REQUEST BIT MASK
BUSY BIT MASK
13
BUSY LOOKUP TABLE ENABLE
RX SA DOUBLE BUFFER ENABLE
OVERWRITE INVALID DATA
13
12
12
11
11
SUBSYSTEM FLAG BIT MASK
TERMINAL FLAG BIT MASK
RESERVED BITS MASK
RETRY ENABLED
10
256-WORD BOUNDARY DISABLE
TIME TAG RESOLUTION 2
10
9
9
8
8
TIME TAG RESOLUTION 1
7
BUS CHANNEL A/B
7
TIME TAG RESOLUTION 0
6
OFF-LINE SELF-TEST
MASK BROADCAST BIT
EOM INTERRUPT ENABLE
1553A/B SELECT
6
CLEAR TIME TAG ON SYNCHRONIZE
LOAD TIME TAG ON SYNCHRONIZE
INTERRUPT STATUS AUTO CLEAR
LEVEL/PULSE INTERRUPT REQUEST
CLEAR SERVICE REQUEST
5
5
4
4
3
3
2
MODE CODE FORMAT
BROADCAST FORMAT
RT-to-RT FORMAT
2
1
1
ENHANCED RT MEMORY MANAGEMENT
SEPARATE BROADCAST DATA
0(LSB)
0(LSB)
TABLE 9. RT SUBADDRESS CONTROL WORD
(READ/WRITE 04H)
TABLE 6. START/RESET REGISTER
(WRITE 03H)
BIT
DESCRIPTION
BIT
DESCRIPTION
15(MSB) RX: DOUBLE BUFFER ENABLE
15(MSB) RESERVED
14
TX: EOM INT
14
13
12
11
10
9
RESERVED
13
TX: CIRC BUF INT
RESERVED
12
TX: MEMORY MANAGEMENT 2 (MM2)
TX: MEMORY MANAGEMENT 1 (MM1)
TX: MEMORY MANAGEMENT 0 (MM0)
RX: EOM INT
RESERVED
11
CLEAR RT HALT
10
9
CLEAR SELF-TEST REGISTER
INITIATE RAM SELF-TEST
RESERVED
8
RX: CIRC BUF INT
7
RX: MEMORY MANAGEMENT 2 (MM2)
RX: MEMORY MANAGEMENT 1 (MM1)
RX: MEMORY MANAGEMENT 0 (MM0)
BCST: EOM INT
8
6
7
INITIATE PROTOCOL SELF-TEST
BC/MT STOP-ON-MESSAGE
BC STOP-ON-FRAME
TIME TAG TEST CLOCK
TIME TAG RESET
5
6
4
5
3
BCST: CIRC BUF INT
4
2
BCST: MEMORY MANAGEMENT 2 (MM2)
BCST: MEMORY MANAGEMENT 1 (MM1)
BCST: MEMORY MANAGEMENT 0 (MM0)
3
1
0(LSB)
2
INTERRUPT RESET
BC/MT START
1
0(LSB) RESET
TABLE 7. BC/RT COMMAND STACK POINTER REG.
(READ 03H)
TABLE 10. TIME TAG REGISTER
(READ/WRITE 05H)
DESCRIPTION
BIT
DESCRIPTION
BIT
15(MSB) COMMAND STACK POINTER 15
15(MSB) TIME TAG 15
•
•
•
•
•
•
•
•
•
•
•
•
0(LSB)
COMMAND STACK POINTER 0
0(LSB)
TIME TAG 0
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TABLE 11. INTERRUPT STATUS REGISTER #1
(READ 06H)
TABLE 13. CONFIGURATION REGISTER #4
(READ/WRITE 08H)
BIT
DESCRIPTION
BIT
DESCRIPTION
15(MSB) MASTER INTERRUPT
15(MSB) EXTERNAL BIT WORD ENABLE
14
13
12
11
10
9
RAM PARITY ERROR
14
INHIBIT BIT WORD IF BUSY
TRANSMITTER TIMEOUT
13
MODE COMMAND OVERRIDE BUSY
EXPANDED BC CONTROL WORD ENABLE
BROADCAST MASK ENA/XOR
RETRY IF -A AND M.E.
12
BC/RT COMMAND STACK ROLLOVER
MT COMMAND STACK ROLLOVER
MT DATA STACK ROLLOVER
HANDSHAKE FAIL
11
10
9
RETRY IF STATUS SET
8
1ST RETRY ALT/SAME BUS
2ND RETRY ALT/SAME BUS
VALID M.E./NO DATA
8
BC RETRY
7
7
RT ADDRESS PARITY ERROR
TIME TAG ROLLOVER
6
6
5
VALID BUSY/NO DATA
5
RT CIRCULAR BUFFER ROLLOVER
BC CONTROL WORD/RT SUBADDRESS CONTROL WORD EOM
BC END OF FRAME
4
MT TAG GAP OPTION
4
3
LATCH RT ADDRESS WITH CONFIG #5
TEST MODE 2
3
2
FORMAT ERROR
2
BC STATUS SET / RT MODE CODE /
MT PATTERN TRIGGER
1
TEST MODE 1
1
0(LSB)
TEST MODE 0
0(LSB)
END OF MESSAGE
TABLE 14. CONFIGURATION REGISTER #5
(READ/WRITE 09H)
TABLE 12. CONFIGURATION REGISTER #3
(READ/WRITE 07H)
BIT
DESCRIPTION
BIT
DESCRIPTION
15(MSB) ENHANCED MODE ENABLE
15(MSB) 12 / 16 MHZ CLOCK SELECT
14
BC/RT COMMAND STACK SIZE 1
BC/RT COMMAND STACK SIZE 0
MT COMMAND STACK SIZE 1
MT COMMAND STACK SIZE 0
MT DATA STACK SIZE 2
14
SINGLE-ENDED SELECT
13
13
EXTERNAL TX INHIBIT A
EXTERNAL TX INHIBIT B
EXPANDED CROSSING ENABLED
RESPONSE TIMEOUT SELECT 1
RESPONSE TIMEOUT SELECT 0
GAP CHECK ENABLED
BROADCAST DISABLED
RT ADDRESS LATCH/TRANSPARENT
RT ADDRESS 4
12
12
11
11
10
10
9
MT DATA STACK SIZE 1
9
8
MT DATA STACK SIZE 0
8
7
ILLEGALIZATION DISABLED
OVERRIDE MODE T/R ERROR
ALTERNATE STATUS WORD ENABLE
ILLEGAL RX TRANSFER DISABLE
BUSY RX TRANSFER DISABLE
RTFAIL / RTFLAG WRAP ENABLE
1553A MODE CODES ENABLE
ENHANCED MODE CODE HANDLING
7
6
6
5
5
4
4
RT ADDRESS 3
3
3
RT ADDRESS 2
2
2
RT ADDRESS 1
1
1
RT ADDRESS 0
0(LSB)
0(LSB)
RT ADDRESS PARITY
TABLE 15. RT / MONITOR DATA STACK ADDRESS
REGISTER
(READ/WRITE 0AH)
BIT
DESCRIPTION
15(MSB) RT / MONITOR DATA STACK ADDRESS 15
•
•
•
•
•
•
0(LSB)
RT / MONITOR DATA STACK ADDRESS 0
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TABLE 16. BC FRAME TIME REMAINING REGISTER
(READ/WRITE 0BH)
TABLE 20. RT BIT WORD REGISTER
(READ 0FH)
BIT
DESCRIPTION
BIT
DESCRIPTION
TRANSMITTER TIMEOUT
15(MSB) BC FRAME TIME REMAINING 15
15(MSB)
14
LOOP TEST FAILURE B
•
•
13
LOOP TEST FAILURE A
•
•
12
HANDSHAKE FAILURE
•
•
11
TRANSMITTER SHUTDOWN B
TRANSMITTER SHUTDOWN A
TERMINAL FLAG INHIBITED
BIT TEST FAIL
0(LSB)
BC FRAME TIME REMAINING 0
10
Note: resolution = 100 µs per LSB
9
TABLE 17. BC MESSAGE TIME REMAINING
REGISTER
8
7
HIGH WORD COUNT
(READ/WRITE 0CH)
6
LOW WORD COUNT
BIT
DESCRIPTION
5
INCORRECT SYNC RECEIVED
PARITY / MANCHESTER ERROR RECEIVED
RT-to-RT GAP / SYNCH / ADDRESS ERROR
RT-to-RT NO RESPONSE ERROR
RT-to-RT 2ND COMMAND WORD ERROR
COMMAND WORD CONTENTS ERROR
15(MSB) BC MESSAGE TIME REMAINING 15
4
•
•
3
•
•
2
•
•
1
0(LSB)
BC MESSAGE TIME REMAINING 0
0(LSB)
Note: resolution = 1 µs per LSB
TABLE 18. BC FRAME TIME / RT LAST COMMAND /
MT TRIGGER REGISTER (READ/WRITE 0DH)
TABLE 21. CONFIGURATION REGISTER #6
(READ/WRITE 18H)
BIT
DESCRIPTION
BIT
DESCRIPTION
ENHANCED BUS CONTROLLER
ENHANCED CPU ACCESS
15(MSB) BIT 15
15(MSB)
14
•
•
COMMAND STACK POINTER INCREMENT ON EOM
(RT, MT)
•
•
•
13
•
12
11
10
9
GLOBAL CIRCULAR BUFFER ENABLE
GLOBAL CIRCULAR BUFFER SIZE 2
GLOBAL CIRCULAR BUFFER SIZE 1
GLOBAL CIRCULAR BUFFER SIZE 0
0(LSB)
BIT 0
TABLE 19. RT STATUS WORD REGISTER
(READ/WRITE 0EH)
DISABLE INVALID MESSAGES TO INTERRUPT STATUS
QUEUE
BIT
DESCRIPTION
8
7
15(MSB) LOGIC “0”
DISABLE VALID MESSAGES TO INTERRUPT STATUS
QUEUE
14
LOGIC “0”
13
LOGIC “0”
6
INTERRUPT STATUS QUEUE ENABLE
RT ADDRESS SOURCE
ENHANCED MESSAGE MONITOR
RESERVED
12
LOGIC “0”
5
11
LOGIC “0”
4
10
MESSAGE ERROR
INSTRUMENTATION
SERVICE REQUEST
RESERVED
3
9
2
64-WORD REGISTER SPACE
CLOCK SELECT 1
8
1
7
0(LSB)
CLOCK SELECT 0
6
RESERVED
5
RESERVED
4
BROADCAST COMMAND RECEIVED
BUSY
3
2
SSFLAG
1
DYNAMIC BUS CONTROL ACCEPT
TERMINAL FLAG
0(LSB)
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TABLE 22. CONFIGURATION REGISTER #7
(READ/WRITE 19H)
TABLE 24. BC GENERAL PURPOSE FLAG REGISTER
(WRITE 1BH)
BIT
DESCRIPTION
MEMORY MANAGEMENT BASE ADDRESS 15
MEMORY MANAGEMENT BASE ADDRESS 14
MEMORY MANAGEMENT BASE ADDRESS 13
MEMORY MANAGEMENT BASE ADDRESS 12
MEMORY MANAGEMENT BASE ADDRESS 11
MEMORY MANAGEMENT BASE ADDRESS 10
RESERVED
BIT
DESCRIPTION
15(MSB)
15(MSB) CLEAR GENERAL PURPOSE FLAG 7
14
14
CLEAR GENERAL PURPOSE FLAG 6
CLEAR GENERAL PURPOSE FLAG 5
CLEAR GENERAL PURPOSE FLAG 4
CLEAR GENERAL PURPOSE FLAG 3
CLEAR GENERAL PURPOSE FLAG 2
CLEAR GENERAL PURPOSE FLAG 1
CLEAR GENERAL PURPOSE FLAG 0
SET GENERAL PURPOSE FLAG 7
SET GENERAL PURPOSE FLAG 6
SET GENERAL PURPOSE FLAG 5
SET GENERAL PURPOSE FLAG 4
SET GENERAL PURPOSE FLAG 3
SET GENERAL PURPOSE FLAG 2
SET GENERAL PURPOSE FLAG 1
SET GENERAL PURPOSE FLAG 0
13
13
12
12
11
11
10
10
9
9
8
RESERVED
8
7
7
RESERVED
6
6
RESERVED
5
5
RESERVED
4
4
RT HALT ENABLE
3
3
1553B RESPONSE TIME
2
2
ENHANCED TIMETAG SYNCHRONIZE
ENHANCED BC WATCHDOG TIMER ENABLED
MODE CODE RESET / INCMD SELECT
1
1
0(LSB)
0(LSB)
TABLE 23. BC CONDITION REGISTER
(READ 1BH)
TABLE 25. BIT TEST STATUS FLAG REGISTER
(READ 1CH)
BIT
DESCRIPTION
BIT
DESCRIPTION
15(MSB) LOGIC “1”
15(MSB) PROTOCOL BUILT-IN TEST COMPLETE
14
RETRY 1
14
PROTOCOL BUILT-IN TEST IN-PROGRESS
13
RETRY 0
13
PROTOCOL BUILT-IN TEST PASSED
12
BAD MESSAGE
12
PROTOCOL BUILT-IN TEST ABORT
11
MESSAGE STATUS SET
GOOD BLOCK TRANSFER
FORMAT ERROR
11
PROTOCOL BUILT-IN-TEST COMPLETE / IN-PROGRESS
10
10
LOGIC “0”
9
LOGIC “0”
9
8
LOGIC “0”
8
NO RESPONSE
7
GENERAL PURPOSE FLAG 7
GENERAL PURPOSE FLAG 6
GENERAL PURPOSE FLAG 5
GENERAL PURPOSE FLAG 4
GENERAL PURPOSE FLAG 3
GENERAL PURPOSE FLAG 2
EQUAL FLAG / GENERAL PURPOSE FLAG 1
LESS THAN FLAG / GENERAL PURPOSE FLAG 1
7
RAM BUILT-IN TEST COMPLETE
RAM BUILT-IN TEST IN-PROGRESS
RAM BUILT-IN TEST IN-PASSED
LOGIC “0”
6
6
5
5
4
4
3
3
LOGIC “0”
2
2
LOGIC “0”
1
1
LOGIC “0”
0(LSB)
0(LSB)
LOGIC “0”
Note: If the Enhanced Mini-ACE is not online in enhanced BC mode (i.e., pro-
cessing instructions), the BC condition code register will always return a value of
0000.
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TABLE 28. BC GENERAL PURPOSE QUEUE
POINTER REGISTER
TABLE 26. INTERRUPT MASK REGISTER #2
(READ/WRITE 1DH)
RT, MT INTERRUPT STATUS QUEUE POINTER
REGISTER
BIT
15(MSB) NOT USED
DESCRIPTION
(READ/WRITE1FH)
14
13
BC OP CODE PARITY ERROR
BIT
DESCRIPTION
RT ILLEGAL COMMAND/MESSAGE MT MESSAGE
RECEIVED
15(MSB) QUEUE POINTER BASE ADDRESS 15
14
13
12
11
10
9
QUEUE POINTER BASE ADDRESS 14
QUEUE POINTER BASE ADDRESS 13
QUEUE POINTER BASE ADDRESS 12
QUEUE POINTER BASE ADDRESS 11
QUEUE POINTER BASE ADDRESS 10
QUEUE POINTER BASE ADDRESS 9
GENERAL PURPOSE QUEUE /
INTERRUPT STATUS QUEUE ROLLOVER
12
11
CALL STACK POINTER REGISTER ERROR
BC TRAP OP CODE
10
9
RT COMMAND STACK 50% ROLLOVER
RT CIRCULAR BUFFER 50% ROLLOVER
MONITOR COMMAND STACK 50% ROLLOVER
MONITOR DATA STACK 50% ROLLOVER
ENHANCED BC IRQ3
8
7
8
QUEUE POINTER BASE ADDRESS 8
QUEUE POINTER BASE ADDRESS 7
QUEUE POINTER BASE ADDRESS 6
QUEUE POINTER ADDRESS 5
QUEUE POINTER ADDRESS 4
QUEUE POINTER ADDRESS 3
QUEUE POINTER ADDRESS 2
QUEUE POINTER ADDRESS 1
QUEUE POINTER ADDRESS 0
6
7
5
6
4
ENHANCED BC IRQ2
5
3
ENHANCED BC IRQ1
4
2
ENHANCED BC IRQ0
3
1
BIT TEST COMPLETE
2
0(LSB)
NOT USED
1
0(LSB)
TABLE 27. INTERRUPT STATUS REGISTER #2
(READ 1EH)
BIT
DESCRIPTION
15(MSB) MASTER INTERRUPT
14
13
BC OP CODE PARITY ERROR
RT ILLEGAL COMMAND/MESSAGE MT MESSAGE
RECEIVED
GENERAL PURPOSE QUEUE /
INTERRUPT STATUS QUEUE ROLLOVER
12
11
CALL STACK POINTER REGISTER ERROR
BC TRAP OP CODE
10
9
RT COMMAND STACK 50% ROLLOVER
RT CIRCULAR BUFFER 50% ROLLOVER
MONITOR COMMAND STACK 50% ROLLOVER
MONITOR DATA STACK 50% ROLLOVER
ENHANCED BC IRQ3
8
7
6
5
4
ENHANCED BC IRQ2
3
ENHANCED BC IRQ1
2
ENHANCED BC IRQ0
1
BIT TEST COMPLETE
0(LSB)
INTERRUPT CHAIN BIT
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NOTE: TABLES 29 TO 35 ARE NOT REGISTERS, BUT THEY ARE WORDS STORED IN RAM.
TABLE 29. BC MODE BLOCK STATUS WORD
TABLE 31. 1553 COMMAND WORD
BIT
DESCRIPTION
BIT
DESCRIPTION
EOM
15(MSB)
15(MSB) REMOTE TERMINAL ADDRESS BIT 4
14
SOM
14
REMOTE TERMINAL ADDRESS BIT 3
REMOTE TERMINAL ADDRESS BIT 2
REMOTE TERMINAL ADDRESS BIT 1
REMOTE TERMINAL ADDRESS BIT 0
TRANSMIT / RECEIVE
13
CHANNEL B/A
ERROR FLAG
STATUS SET
FORMAT ERROR
13
12
12
11
11
10
10
9
NO RESPONSE TIMEOUT
LOOP TEST FAIL
9
SUBADDRESS / MODE BIT 4
8
8
SUBADDRESS / MODE BIT 3
7
MASKED STATUS SET
RETRY COUNT 1
7
SUBADDRESS / MODE BIT 2
6
6
SUBADDRESS / MODE BIT 1
5
RETRY COUNT 0
5
SUBADDRESS / MODE BIT 0
4
GOOD DATA BLOCK TRANSFER
WRONG STATUS ADDRESS / NO GAP
WORD COUNT ERROR
INCORRECT SYNC TYPE
INVALID WORD
4
DATA WORD COUNT / MODE CODE BIT 4
DATA WORD COUNT / MODE CODE BIT 3
DATA WORD COUNT / MODE CODE BIT 2
DATA WORD COUNT / MODE CODE BIT 1
DATA WORD COUNT / MODE CODE BIT 0
3
3
2
2
1
1
0(LSB)
0(LSB)
TABLE 30. RT MODE BLOCK STATUS WORD
TABLE 32. WORD MONITOR IDENTIFICATION
WORD
BIT
DESCRIPTION
BIT
15(MSB) GAP TIME (MSB)
DESCRIPTION
EOM
15(MSB)
14
SOM
•
•
•
•
13
CHANNEL B/A
ERROR FLAG
RT-to-RT FORMAT
FORMAT ERROR
•
12
•
11
8
7
6
5
4
3
2
1
GAP TIME (LSB)
WORD FLAG
THIS RT
10
9
NO RESPONSE TIMEOUT
LOOP TEST FAIL
8
BROADCAST
ERROR
7
DATA STACK ROLLOVER
6
ILLEGAL COMMAND WORD
WORD COUNT ERROR
COMMAND / DATA
CHANNEL B/A
5
4
INCORRECT DATA SYNC
INVALID WORD
CONTIGUOUS DATA / GAP
MODE_CODE
3
0(LSB)
2
RT-to-RT GAP / SYNC / ADDRESS ERROR
RT-to-RT 2ND COMMAND ERROR
COMMAND WORD CONTENTS ERROR
1
0(LSB)
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TABLE 33. MESSAGE MONITOR MODE BLOCK
STATUS WORD
TABLE 35. 1553B STATUS WORD
BIT
DESCRIPTION
BIT
DESCRIPTION
EOM
15(MSB)
15(MSB) REMOTE TERMINAL ADDRESS BIT 4
14
SOM
14
REMOTE TERMINAL ADDRESS BIT 3
REMOTE TERMINAL ADDRESS BIT 2
REMOTE TERMINAL ADDRESS BIT 1
REMOTE TERMINAL ADDRESS BIT 0
MESSAGE ERROR
13
CHANNEL B/A
ERROR FLAG
RT-to-RT TRANSFER
FORMAT ERROR
13
12
12
11
11
10
10
9
NO RESPONSE TIMEOUT
GOOD DATA BLOCK TRANSFER
DATA STACK ROLLOVER
RESERVED
9
INSTRUMENTATION
8
8
SERVICE REQUEST
7
7
RESERVED
6
6
RESERVED
5
WORD COUNT ERROR
5
RESERVED
4
INCORRECT SYNC
4
BROADCAST COMMAND RECEIVED
BUSY
3
INVALID WORD
3
2
RT-to-RT GAP / SYNC / ADDRESS ERROR
RT-to-RT 2ND COMMAND ERROR
COMMAND WORD CONTENTS ERROR
2
SSFLAG
1
1
DYNAMIC BUS CONTROL ACCEPTANCE
TERMINAL FLAG
0(LSB)
0(LSB)
TABLE 34. RT/MONITOR INTERRUPT STATUS WORD
(FOR INTERRUPT STATUS QUEUE)
NON-TEST REGISTER FUNCTION SUMMARY
DEFINITION FOR
NON-MESSAGE
INTERRUPT EVENT
DEFINITION FOR MESSAGE
A summary of the Enhanced Mini-ACE/µ-ACE's 24 non-test reg-
isters follows.
BIT
INTERRUPT EVENT
15
14
TRANSMITTER TIMEOUT
ILLEGAL COMMAND
NOT USED
NOT USED
INTERRUPT MASK REGISTERS #1 AND #2
Interrupt Mask Registers #1 and #2 are used to enable and dis-
able interrupt requests for various events and conditions.
MONITOR DATA STACK 50%
ROLLOVER
13
12
11
10
NOT USED
NOT USED
NOT USED
NOT USED
MONITOR DATA STACK
ROLLOVER
NOTE: Please see Appendix “F” of the Enhanced Mini-ACE
User’s Guide for important information applicable only to RT
MODE operation, enabling of the interrupt status queue and
use of specific non-message interrupts.
RT CIRCULAR BUFFER 50%
ROLLOVER
RT CIRCULAR BUFFER
ROLLOVER
MONITOR COMMAND
(DESCRIPTOR) STACK 50%
ROLLOVER
9
8
NOT USED
NOT USED
CONFIGURATION REGISTERS #1 AND #2
Configuration Registers #1 and #2 are used to select the Mini-
ACE Mark3’s mode of operation, and for software control of RT
Status Word bits, Active Memory Area, BC Stop-On-Error, RT
Memory Management mode selection, and control of the Time
Tag operation.
MONITOR COMMAND
(DESCRIPTOR) STACK
ROLLOVER
RT COMMAND (DESCRIPTOR)
STACK 50% ROLLOVER
7
6
NOT USED
NOT USED
RT COMMAND (DESCRIPTOR)
STACK ROLLOVER
START/RESET REGISTER
5
4
HANDSHAKE FAIL
FORMAT ERROR
NOT USED
The Start/Reset Register is used for "command" type functions
such as software reset, BC/MT Start, Interrupt reset, Time Tag
Reset, Time Tag Register Test, Initiate protocol self-test, Initiate
RAM self-test, Clear self-test register, and Clear RT Halt. The
Start/Reset Register also includes provisions for stopping the BC
in its auto-repeat mode, either at the end of the current message
or at the end of the current BC frame.
TIME TAG ROLLOVER
RT ADDRESS PARITY
ERROR
3
MODE CODE INTERRUPT
SUBADDRESS CONTROL
WORD EOM
PROTOCOL SELF-TEST
COMPLETE
2
1
0
END-OF-MESSAGE (EOM)
RAM PARITY ERROR
“1” FOR MESSAGE INTERRUPT EVENT
“0” FOR NON-MESSAGE INTERRUPT EVENT
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BC/RT COMMAND STACK REGISTER
The BC/RT Command Stack Register allows the host CPU to
determine the pointer location for the current or most recent
message.
vidual receive (broadcast) subaddresses, and the alternate (fully
software programmable) RT Status Word. For MT mode, use of
the Enhanced Mode enables the Selective Message Monitor, the
combined RT/Selective Monitor modes, and the monitor trigger-
ing capability.
BC INSTRUCTION LIST POINTER REGISTER
The BC Instruction List Pointer Register may be read to deter-
mine the current location of the Instruction List Pointer for the
Enhanced BC mode.
RT/MONITOR DATA STACK ADDRESS REGISTER
The RT/Monitor Data Stack Address Register provides a
read/writable indication of the last data word stored for RT or
Monitor modes.
BC CONTROL WORD/RT SUBADDRESS CONTROL
WORD REGISTER
BC FRAME TIME REMAINING REGISTER
In BC mode, the BC Control Word/RT Subaddress Control Word
Register allows host access to the current word or most recent
BC Control Word. The BC Control Word contains bits that select
the active bus and message format, enable off-line self-test,
masking of Status Word bits, enable retries and interrupts, and
specify MIL-STD-1553A or -1553B error handling. In RT mode,
this register allows host access to the current or most recent
Subaddress Control Word. The Subaddress Control Word is
used to select the memory management scheme and enable
interrupts for the current message.
The BC Frame Time Remaining Register provides a read-only
indication of the time remaining in the current BC frame. In the
enhanced BC mode, this timer may be used for minor or major
frame control, or as a watchdog timer for the BC message
sequence control processor. The resolution of this register is
100 µs/LSB.
BC TIME REMAINING TO NEXT MESSAGE REGISTER
The BC Time Remaining to Next Message Register provides a
read-only indication of the time remaining before the start of the
next message in a BC frame. In the enhanced BC mode, this
timer may also be used for the BC message sequence control
processor's Delay (DLY) instruction, or for minor or major frame
control. The resolution of this register is 1 µs/LSB.
TIME TAG REGISTER
The Time Tag Register maintains the value of a real-time clock.
The resolution of this register is programmable from among 2, 4,
8, 16, 32, and 64 µs/LSB. The Start-of-Message (SOM) and
End-of-Message (EOM) sequences in BC, RT, and Message
Monitor modes cause a write of the current value of the Time Tag
Register to the stack area of the RAM.
BC FRAME TIME/ RT LAST COMMAND /MT TRIGGER
WORD REGISTER
In BC mode, this register is used to program the BC frame time,
for use in the frame auto-repeat mode. The resolution of this reg-
ister is 100 µs/LS, with a range up to 6.55 seconds. In RT mode,
this register stores the current (or most previous) 1553
Command Word processed by the Mini-ACE Mark3 RT. In the
Word Monitor mode, this register is used to specify a 16-bit
Trigger (Command) Word. The Trigger Word may be used to
start or stop the monitor, or to generate interrupts.
INTERRUPT STATUS REGISTERS #1 AND #2
Interrupt Status Registers #1 and #2 allow the host processor to
determine the cause of an interrupt request by means of one or
two read accesses. The interrupt events of the two Interrupt
Status Registers are mapped to correspond to the respective bit
positions in the two Interrupt Mask Registers. Interrupt Status
Register #2 contains an INTERRUPT CHAIN bit, used to indi-
cate an interrupt event from Interrupt Status Register #1.
BC INITIAL INSTRUCTION LIST POINTER REGISTER
The BC Initial Instruction List Pointer Register enables the host
to assign the starting address for the enhanced BC Instruction
List.
CONFIGURATION REGISTERS #3, #4, AND #5
Configuration Registers #3, #4, and #5 are used to enable many
of the Mini-ACE Mark3’s advanced features that were imple-
mented by the prior generation products, the ACE and Mini-ACE
(Plus). For BC, RT, and MT modes, use of the Enhanced Mode
enables the various read-only bits in Configuration Register #1.
For BC mode, Enhanced Mode features include the expanded
BC Control Word and BC Block Status Word, additional Stop-On-
Error and Stop-On-Status Set functions, frame auto-repeat, pro-
grammable intermessage gap times, automatic retries, expand-
ed Status Word Masking, and the capability to generate inter-
rupts following the completion of any selected message. For RT
mode, the Enhanced Mode features include the expanded RT
Block Status Word, combined RT/Selective Message Monitor
mode, automatic setting of the TERMINAL FLAG Status Word bit
following a loop test failure; the double buffering scheme for indi-
RT STATUS WORD REGISTER AND BIT WORD
REGISTERS
The RT Status Word Register and BIT Word Registers provide
read-only indications of the RT Status and BIT Words.
CONFIGURATION REGISTERS #6 AND #7
Configuration Registers #6 and #7 are used to enable the Mini-
ACE Mark3 features that extend beyond the architecture of the
ACE/Mini-ACE (Plus). These include the Enhanced BC mode;
RT Global Circular Buffer (including buffer size); the RT/MT
Interrupt Status Queue, including valid/invalid message filtering;
enabling a software-assigned RT address; clock frequency
selection; a base address for the "non-data" portion of Mini-ACE
15
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Mark3 memory; LSB filtering for the Synchronize (with data) time
tag operations; and enabling a watchdog timer for the Enhanced
BC message sequence control engine.
determine the current location of the Interrupt Status Queue
pointer, which is incremented by the RT/MT message processor.
BUS CONTROLLER (BC) ARCHITECTURE
NOTE: Please see Appendix “F” of the Enhanced Mini-ACE
User’s Guide for important information applicable only to RT
MODE operation, enabling of the interrupt status queue and
use of specific non-message interrupts.
The BC functionality for the Enhanced Mini-ACE/µ-ACE includes
two separate architectures: (1) the older, non-Enhanced Mode,
which provides complete compatibility with the previous ACE
and Mini-ACE (Plus) generation products; and (2) the newer,
Enhanced BC mode.The Enhanced BC mode offers several new
powerful architectural features. These include the incorporation
of a highly autonomous BC message sequence control engine,
which greatly serves to offload the operation of the host CPU.
BC CONDITION CODE REGISTER
The BC Condition Code Register is used to enable the host
processor to read the current value of the Enhanced BC
Message Sequence Control Engine's condition flags.
The Enhanced BC's message sequence control engine provides
a high degree of flexibility for implementing major and minor
frame scheduling; capabilities for inserting asynchronous mes-
sages in the middle of a frame; to separate 1553 message data
from control/status data for the purpose of implementing double
buffering and performing bulk data transfers; for implementing
message retry schemes, including the capability for automatic
bus channel switchover for failed messages; and for reporting
various conditions to the host processor by means of 4 user-
defined interrupts and a general purpose queue.
BC GENERAL PURPOSE FLAG REGISTER
The BC General Purpose Flag Register allows the host processor
to be able to set, clear, or toggle any of the Enhanced BC Message
Sequence Control Engine's General Purpose condition flags.
BIT TEST STATUS REGISTER
The BIT Test Status Register is used to provide read-only access
to the status of the protocol and RAM built-in self-tests (BIT).
BC GENERAL PURPOSE QUEUE POINTER
The BC General Purpose Queue Pointer provides a means for
initializing the pointer for the General Purpose Queue, for the
Enhanced BC mode. In addition, this register enables the host to
determine the current location of the General Purpose Queue
pointer, which is incremented internally by the Enhanced BC
message sequence control engine.
In both the non-Enhanced and Enhanced BC modes, the
Enhanced Mini-ACE/µ-ACE BC implements all MIL-STD-1553B
message formats. Message format is programmable on a mes-
sage-by-message basis by means of the BC Control Word and
the T/R bit of the Command Word for the respective message.
The BC Control Word allows 1553 message format, 1553A/B
type RT, bus channel, self-test, and Status Word masking to be
specified on an individual message basis. In addition, automatic
retries and/or interrupt requests may be enabled or disabled for
individual messages. The BC performs all error checking
required by MIL-STD-1553B. This includes validation of
response time, sync type and sync encoding, Manchester II
encoding, parity, bit count, word count, Status Word RT Address
field, and various RT-to-RT transfer errors. The Enhanced Mini-
ACE/µ-ACE BC response timeout value is programmable with
choices of 18, 22, 50, and 130 µs. The longer response timeout
values allow for operation over long buses and/or the use of
repeaters.
RT/MT INTERRUPT STATUS QUEUE POINTER
The RT/MT Interrupt Status Queue Pointer provides a means for
initializing the pointer for the Interrupt Status Queue, for RT, MT,
and RT/MT modes. In addition, this register enables the host to
BC INSTRUCTION
LIST
MESSAGE
CONTROL/STATUS
BC INSTRUCTION
LIST POINTER REGISTER
OP CODE
BLOCK
BC CONTROL
WORD
PARAMETER
(POINTER)
INITIALITIZE BY REGISTER
0D (RD/WR); READ CURRENT
VALUE VIA REGISTER 03
(RD ONLY)
COMMAND WORD
(Rx Command for
RT-to-RT transfer)
DATA BLOCK POINTER
TIME-TO-NEXT MESSAGE
TIME TAG WORD
In its non-Enhanced Mode, the Enhanced Mini-ACE/µ-ACE may
be programmed to process BC frames of up to 512 messages
with no processor intervention. In the Enhanced BC mode, there
is no explicit limit to the number of messages that may be
processed in a frame. In both modes, it is possible to program for
either single frame or frame auto-repeat operation. In the auto-
repeat mode, the frame repetition rate may be controlled either
internally, using a programmable BC frame timer, or from an
external trigger input.
DATA BLOCK
BLOCK STATUS WORD
LOOPBACK WORD
RT STATUS WORD
2nd (Tx) COMMAND WORD
(for RT-to-RT transfer)
2nd RT STATUS WORD
(for RT-to-RT transfer)
FIGURE 2. BC MESSAGE SEQUENCE CONTROL
ENHANCED BC MODE: MESSAGE SEQUENCE CONTROL
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One of the major new architectural features of the Enhanced
Mini-ACE/µ-ACE series is its advanced capability for BC mes-
sage sequence control. The Enhanced Mini-ACE/µ-ACE sup-
ports highly autonomous BC operation, which greatly offloads
the operation of the host processor.
GP Flag Bits (FLG) instruction; and (3) GP0 and GP1 only (but
none of the others) may be set or cleared by means of the BC
message sequence control processor's Compare Frame Timer
(CFT) or Compare Message Timer (CMT) instructions.
The host processor also has read-only access to the BC condi-
tion codes by means of the BC CONDITION CODE REGISTER.
The operation of the Enhanced Mini-ACE/µ-ACE's message
sequence control engine is illustrated in FIGURE 2. The BC mes-
sage sequence control involves an instruction list pointer register;
an instruction list which contains multiple 2-word entries; a mes-
sage control/status stack, which contains multiple 8-word or 10-
word descriptors; and data blocks for individual messages.
Note that four (4) instructions are unconditional. These are
Compare to Frame Timer (CFT), Compare to Message Timer
(CMT), GP Flag Bits (FLG), and Execute and Flip (XQF). For
these instructions, the Condition Code Field is "don't care". That
is, these instructions are always executed, regardless of the
result of the condition code test.
The initial value of the instruction list pointer register is initialized
by the host processor (via Register 0D), and is incremented by
the BC message sequence processor (host readable via
Register 03). During operation, the message sequence control
processor fetches the operation referenced by the instruction list
pointer register from the instruction list.
All of the other instructions are conditional.That is, they will only be
executed if the condition code specified by the condition code field
in the op code word tests true. If the condition code field tests false,
the instruction list pointer will skip down to the next instruction.
Note that the pointer parameter referencing the first word of a
message's control/status block (the BC Control Word) must con-
tain an address value that is modulo 8. Also, note that if the
message is an RT-to-RT transfer, the pointer parameter must
contain an address value that is modulo 16.
As shown in TABLE 36, many of the operations include a single-
word parameter. For an XEQ (execute message) operation, the
parameter is a pointer to the start of the message’s Control /
Status block. For other operations, the parameter may be an
address, a time value, an interrupt pattern, a mechanism to set
or clear general purpose flag bits, or an immediate value. For
several op codes, the parameter is "don't care" (not used).
OP CODES
The instruction list pointer register references a pair of words in
the BC instruction list: an op code word, followed by a parameter
word. The format of the op code word, which is illustrated in FIG-
URE 3, includes a 5-bit op code field and a 5-bit condition code
field. The op code identifies the instruction to be executed by the
BC message sequence controller.
As described above, some of the op codes will cause the mes-
sage sequence control processor to execute messages. In this
case, the parameter references the first word of a message
Control/Status block. With the exception of RT-to-RT transfer
messages, all message status/control blocks are eight words
long: a block control word, time-to-next-message parameter,
data block pointer, command word, status word, loopback word,
block status word, and time tag word.
Most of the operations are conditional, with execution dependent
on the contents of the condition code field. Bits 3-0 of the condi-
tion code field identifies a particular condition. Bit 4 of the condi-
tion code field identifies the logic sense ("1" or "0") of the select-
ed condition code on which the conditional execution is depen-
dent. TABLE 36 lists all the op codes, along with their respective
mnemonic, code value, parameter, and description. TABLE 37
defines all the condition codes.
In the case of an RT-to-RT transfer message, the size of the message
control/status block increases to 16 words. However, in this case, the
last six words are not used; the ninth and tenth words are for the sec-
ond command word and second status word.
The third word in the message control/status block is a pointer
that references the first word of the message's data word block.
Note that the data word block stores only data words, which are
to be either transmitted or received by the BC. By segregating
data words from command words, status words, and other con-
trol and "housekeeping" functions, this architecture enables the
use of convenient, usable data structures, such as circular
buffers and double buffers.
Eight of the condition codes (8 through F) are set or cleared as the
result of the most recent message. The other eight are defined as
"General Purpose" condition codes GP0 through GP7. There are
three mechanisms for programming the values of the General
Purpose Condition Code bits: (1) They may be set, cleared, or tog-
gled by the host processor, by means of the BC GENERAL PUR-
POSE FLAG REGISTER; (2) they may be set, cleared, or toggled
by the BC message sequence control processor, by means of the
15
14
13
12
11
10
9
0
8
1
7
0
6
1
5
0
4
3
2
1
0
Odd Parity
OpCode Field
Condition Code Field
FIGURE 3. BC OP CODE FORMAT
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TABLE 36. BC OPERATIONS FOR MESSAGE SEQUENCE CONTROL
CONDITIONAL
OP CODE
(HEX)
INSTRUCTION MNEMONIC
PARAMETER
OR
DESCRIPTION
UNCONDITIONAL
Execute
Message
XEQ
0001
Message Control /
Status Block
Address
Conditional
(See Note)
Executes the message at the specified Message Control/Status
Block Address if the condition flag tests TRUE, otherwise con-
tinue execution at the next OpCode in the instruction list.
Jump
JMP
CAL
0002
0003
Instruction List
Address
Conditional
Conditional
Jump to the OpCode specified in the Instruction List if the con-
dition flag tests TRUE, otherwise continue execution at the next
OpCode in the instruction list.
Subroutine
Call
Instruction List
Address
Jump to the OpCode specified by the Instruction List Address
and push the Address of the Next OpCode on the Call Stack if
the condition flag tests TRUE, otherwise continue execution at
the next OpCode in the instruction list. Note that the maximum
depth of the subroutine call stack is four.
Subroutine
Return
RTN
IRQ
0004
0006
Not Used
(Don’t Care)
Conditional
Conditional
Return to the OpCode popped off the Call Stack if the condition
flag tests TRUE, otherwise continue execution at the next
OpCode in the instruction list.
Interrupt
Request
Interrupt
Bit Pattern
in 4 LS bits
Generate an interrupt if the condition flag tests TRUE, otherwise
continue execution at the next OpCode in the instruction list.
The passed parameter (Interrupt Bit Pattern) specifies which of
the ENHANCED BC IRQ bit(s) (bits 5-2) will be set in Interrupt
Status Register #2. Only the four LSBs of the passed parameter
are used. A parameter where the four LSBs are logic "0" will
not generate an interrupt.
Halt
HLT
DLY
WFT
CFT
0007
0008
0009
000A
Not Used
(Don’t Care)
Conditional
Conditional
Conditional
Unconditional
Stop execution of the Message Sequence Control Program until
a new BC Start is issued by the host if the condition flag tests
TRUE, otherwise continue execution at the next OpCode in the
instruction list.
Delay
Delay Time Value
(Resolution = 1µS
/ LSB)
Delay the time specified by the Time parameter before execut-
ing the next OpCode if the condition flag tests TRUE, otherwise
continue execution at the next OpCode without delay. The delay
generated will use the Time to Next Message Timer.
Wait Until
Frame Timer
= 0
Not Used
(Don’t Care)
Wait until Frame Time counter is equal to Zero before continu-
ing execution of the Message Sequence Control Program if the
condition flag tests TRUE, otherwise continue execution at the
next OpCode without delay.
Compare to
Frame Timer
Delay Time Value
(Resolution
= 100µS / LSB)
Compare Time Value to Frame Time Counter. The LT/GP0 and
EQ/GP1 flag bits are set or cleared based on the results of the
compare. If the value of the CFT's parameter is less than the
value of the frame time counter, then the LT/GP0 and NE/GP1
flags will be set, while the GT-EQ/GP0 and EQ/GP1 flags will
be cleared. If the value of the CFT's parameter is equal to the
value of the frame time counter, then the GT-EQ/GP0 and
EQ/GP1 flags will be set, while the LT/GP0 and NE/GP1 flags
will be cleared. If the value of the CFT's parameter is greater
than the current value of the frame time counter, then the GT-
EQ/GP0 and NE/GP1 flags will be set, while the LT/GP0 and
EQ/GP1 flags will be cleared.
Compare to
Message
Timer
CMT
000B
Delay Time Value
(Resolution
= 1µS / LSB)
Unconditional
Compare Time Value to Message Time Counter. The LT/GP0 and
EQ/GP1 flag bits are set or cleared based on the results of the
compare. If the value of the CMT's parameter is less than the value
of the message time counter, then the LT/GP0 and NE/GP1 flags
will be set, while the GT-EQ/GP0 and EQ/GP1 flags will be cleared.
If the value of the CMT's parameter is equal to the value of the mes-
sage time counter, then the GT-EQ/GP0 and EQ/GP1 flags will be
set, while the LT/GP0 and NE/GP1 flags will be cleared. If the value
of the CMT's parameter is greater than the current value of the
message time counter, then the GT-EQ/GP0 and NE/GP1 flags will
be set, while the LT/GP0 and EQ/GP1 flags will be cleared.
NOTE: While the XEQ (Execute Message) instruction is conditional, not all condition codes may be used to enable its use. The ALWAYS and NEVER condition codes
may be used. The eight general purpose flag bits, GP0 through GP7, may also be used. However, if GP0 through GP7 are used, it is imperative that the host processor
not modify the value of the specific general purpose flag bit that enabled a particular message while that message is being processed. Similarly, the LT, GT-EQ, EQ, and
NE flags, which the BC only updates by means of the CFT and CMT instructions, may also be used. However, these two flags are dual use. Therefore, if these are used, it
is imperative that the host processor not modify the value of the specific flag (GP0 or GP1) that enabled a particular message while that message is being processed. The
NORESP, FMT ERR, GD BLK XFER, MASKED STATUS SET, BAD MESSAGE, RETRY0, and RETRY1 condition codes are not available for use with the XEQ instruction
and should not be used to enable its execution.
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TABLE 36. BC OPERATIONS FOR MESSAGE SEQUENCE CONTROL (CONT.)
CONDITIONAL
OP CODE
(HEX)
INSTRUCTION MNEMONIC
PARAMETER
OR
DESCRIPTION
UNCONDITIONAL
GP Flag Bits
FLG
000C
Used to set,
clear, or toggle
GP
Unconditional
Used to set, toggle, or clear any or all of the eight general
purpose flags. The table below illustrates the use of the GP
Flag Bits instruction for the case of GP0 (General Purpose
Flag 0). Bits 1 and 9 of the parameter byte affect flag GP1,
bits 2 and 10 effect GP2, etc., according to the following
rules:
(General
Purpose)
Flag bits
(See descrip-
tion)
Bit 8
Bit 0
Effect on GP0
0
0
1
1
0
1
0
1
No Change
Set Flag
Clear Flag
Toggle Flag
Load Time Tag
Counter
LTT
000D
Time Value.
Resolution
(µs/LSB) is
Conditional
Load Time Tag Counter with Time Value if the condition flag
tests TRUE, otherwise continue execution at the next
OpCode in the instruction list.
defined by bits 9,
8, and 7 of
Configuration
Register #2.
Load Frame
Timer
LFT
SFT
PTT
000E
000F
0010
Time Value
(resolution =
100 µs/LSB)
Conditional
Conditional
Conditional
Load Frame Timer Register with the Time Value parameter
if the condition flag tests TRUE, otherwise continue execu-
tion at the next OpCode in the instruction list.
Start Frame
Timer
Not Used
(Don't Care)
Start Frame Time Counter with Time Value in Time Frame
register if the condition flag tests TRUE, otherwise continue
execution at the next OpCode in the instruction list.
Push Time Tag
Register
Not Used
(Don't Care)
Push the value of the Time Tag Register on the General
Purpose Queue if the condition flag tests TRUE, otherwise
continue execution at the next OpCode in the instruction list.
Push Block
Status Word
PBS
0011
Not Used
(Don't Care)
Conditional
Push the Block Status Word for the most recent message on
the General Purpose Queue if the condition flag tests TRUE,
otherwise continue execution at the next OpCode in the
instruction list.
Push Immediate
Value
PSI
0012
0013
Immediate Value
Conditional
Conditional
Push Immediate data on the General Purpose Queue if the
condition flag tests TRUE, otherwise continue execution at
the next OpCode in the instruction list.
Push Indirect
PSM
Memory
Address
Push the data stored at the specified memory location on
the General Purpose Queue if the condition flag tests TRUE,
otherwise continue execution at the next OpCode in the
instruction list.
Wait for
External
Trigger
WTG
XQF
0014
0015
Not Used
(Don't Care)
Conditional
Wait for a logic "0"-to-logic "1" transition on the EXT_TRIG
input signal before proceeding to the next OpCode in the
instruction list if the condition flag tests TRUE, otherwise
continue execution at the next OpCode without delay.
Execute and
Flip
Message
Control /
Status Block
Address
Unconditional
Execute (unconditionally) the message referenced by the
Message Control/Status Block Address. Following the pro-
cessing of this message, if the condition flag tests TRUE,
the BC will toggle bit 4 in the Message Control/Status Block
Address, and store the new Message Block Address as the
updated value of the parameter following the XQF instruc-
tion code. As a result, the next time that this line in the
instruction list is executed, the Message Control/Status
Block at the updated address (old address XOR 0010h),
rather than the old address, will be processed. If the condi-
tion flag tests FALSE, the value of the Message
Control/Status Block Address parameter will not change.
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TABLE 37. BC CONDITION CODES
BIT
CODE
NAME
(BIT 4 = 0)
INVERSE
(BIT 4 = 1)
FUNCTIONAL DESCRIPTION
0
LT/GP0
GT-EQ/
GP0
Less than or GP0 flag. This bit is set or cleared based on the results of the compare. If the value of the
CMT's parameter is less than the value of the message time counter, then the LT/GP0 and NE/GP1
flags will be set, while the GT-EQ/GP0 and EQ/GP1 flags will be cleared. If the value of the CMT's
parameter is equal to the value of the message time counter, then the GT-EQ/GP0 and EQ/GP1 flags
will be set, while the LT/GP0 and NE/GP1 flags will be cleared. If the value of the CMT's parameter is
greater than the current value of the message time counter, then the GT-EQ/GP0 and NE/GP1 flags will
be set , while the LT/GP0 and EQ/GP1 flags will be cleared. Also, General Purpose Flag 1 may be also
be set or cleared by a FLG operation.
1
EQ/GP1
NE/GP1
Equal Flag. This bit is set or cleared after CFT or CMT operation. If the value of the CMT's parameter is
equal to the value of the message time counter, then the EQ/GP1 flag will be set and the NE/GP1 bit
will be cleared. If the value of the CMT's parameter is not equal to the value of the message time
counter, then the NE/GP1 flag will be set and the EQ/GP1bit will be cleared. Also, General Purpose
Flag 1 may be also be set or cleared by a FLG operation.
2
3
4
5
6
7
GP2
GP3
GP4
GP5
GP6
GP7
GP2
GP3
GP4
GP5
GP6
GP7
General Purpose Flags may be set, cleared, or toggled by a FLG operation. The host processor can
set, clear, or toggle these flags in the same way as the FLG instruction by means of the BC GENERAL
PURPOSE FLAG REGISTER.
8
NORESP
RESP
NORESP indicates that an RT has either not responded or has responded later than the BC No
Response Timeout time. The Enhanced Mini-ACE's/µ-ACE’s No Response Timeout Time is defined per
MIL-STD-1553B as the time from the mid-bit crossing of the parity bit of the last word transmitted by
the BC to the mid-sync crossing of the RT Status Word. The value of the No Response Timeout value
is programmable from among the nominal values 18.5, 22.5, 50.5, and 130 µs (±1 µs) by means of bits
10 and 9 of Configuration Register #5.
9
FMT ERR
FMT ERR FMT ERR indicates that the received portion of the most recent message contained one or more viola-
tions of the 1553 message validation criteria (sync, encoding, parity, bit count, word count, etc.), or the
RT's status word received from a responding RT contained an incorrect RT address field.
A
GD BLK
XFER
GD BLK
XFER
For the most recent message, GD BLK XFER will be set to logic "1" following completion of a valid
(error-free) RT-to-BC transfer, RT-to-RT transfer, or transmit mode code with data message. This bit is
set to logic "0" following an invalid message. GOOD DATA BLOCK TRANSFER is always logic "0" fol-
lowing a BC-to-RT transfer, a mode code with data, or a mode code without data. The Loop Test has
no effect on GOOD DATA BLOCK TRANSFER. GOOD DATA BLOCK TRANSFER may be used to
determine if the transmitting portion of an RT-to-RT transfer was error free.
B
MASKED
STATUS
BIT
MASKED Indicates that one or both of the following conditions have occurred for the most recent message: (1) If
STATUS
BIT
one (or more) of the Status Mask bits (14 through 9) in the BC Control Word is logic "0" and the corre-
sponding bit(s) is (are) set (logic "1") in the received RT Status Word. In the case of the RESERVED
BITS MASK (bit 9) set to logic "0", any or all of the 3 Reserved Status Word bits being set will result in
a MASKED STATUS SET condition; and/or (2) If BROADCAST MASK ENABLED/XOR (bit 11 of
Configuration Register #4) is logic "1" and the MASK BROADCAST bit of the message's BC Control
Word is logic "0" and the BROADCAST COMMAND RECEIVED bit in the received RT Status Word is
logic "1".
C
BAD
GOOD
BAD MESSAGE indicates either a format error, loop test fail, or no response error for the most recent
MESSAGE
MESSAGE message. Note that a "Status Set" condition has no effect on the "BAD MESSAGE/GOOD MESSAGE"
condition code.
D
E
RETRY0
RETRY1
RETRY0
RETRY1
These two bits reflect the retry status of the most recent message. The number of times that the mes-
sage was retried is delineated by these two bits as shown below:
RETRY COUNT 1
RETRY COUNT 0
Number of
(bit 14)
(bit 13)
Message Retries
0
0
1
1
0
1
0
1
0
1
N/A
2
F
ALWAYS
NEVER
The ALWAYS bit should be set (bit 4 = 0) to designate an instruction as unconditional. The NEVER bit
(bit 4 = 0) can be used to implement an NOP or “skip” instruction.
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Other operations support program flow control; i.e., jump and call
capability.The call capability includes maintenance of a call stack
which supports a maximum of four (4) entries; there is also a
return instruction. In the case of a call stack overrun or underrun,
the BC will issue a CALL STACK POINTER REGISTER ERROR
interrupt, if enabled.
message sequence control processor fetches an undefined op
code word, an op code word with even parity, or bits 9-5 of an op
code word do not have a binary pattern of 01010, the message
sequence control processor will immediately halt the BC's oper-
ation. In addition, if enabled, a BC TRAP OP CODE interrupt will
be issued. Also, if enabled, a parity error will result in an OP
CODE PARITY ERROR interrupt. TABLE 37 describes the
Condition Codes.
Other op codes may be used to delay for a specified time; start a new
BC frame; wait for an external trigger to start a new frame; perform
comparisons based on frame time and time-to-next message; load
the time tag or frame time registers; halt; and issue host interrupts. In
the case of host interrupts, the message control processor passes a
4-bit user-defined interrupt vector to the host, by means of the
Enhanced Mini-ACE/µ-ACE's Interrupt Status Register.
BC MESSAGE SEQUENCE CONTROL
The Enhanced Mini-ACE/µ-ACE BC message sequence control
capability enables a high degree of offloading of the host proces-
sor. This includes using the various timing functions to enable
autonomous structuring of major and minor frames. In addition,
by implementing conditional jumps and subroutine calls, the
message sequence control processor greatly simplifies the
insertion of asynchronous, or "out-of-band" messages.
The purpose of the FLG instruction is to enable the message
sequence controller to set, clear, or toggle the value(s) of any or
all of the eight general purpose condition flags.
Execute and Flip Operation. The Enhanced Mini-ACE/µ-ACE
BC's XQF, or "Execute and Flip" operation, provides some
unique capabilities. Following execution of this unconditional
instruction, if the condition code tests TRUE, the BC will modify
the value of the current XQF instruction's pointer parameter by
toggling bit 4 of the pointer. That is, if the selected condition flag
tests true, the value of the parameter will be updated to the
value = old address XOR 0010h. As a result, the next time that
this line in the instruction list is executed, the Message
Control/Status Block at the updated address (old address XOR
0010h) will be processed, rather than the one at the old address.
The operation of the XQF instruction is illustrated in FIGURE 4.
The op code parity bit encompasses all sixteen bits of the op
code word. This bit must be programmed for odd parity. If the
(part of) BC INSTRUCTION LIST
MESSAGE
CONTROL/STATUS
BLOCK 0
There are multiple ways of utilizing the "execute and flip" instruc-
tion. One is to facilitate the implementation of a double buffering
data scheme for individual messages. This allows the message
sequence control processor to "ping-pong" between a pair of
data buffers for a particular message. By doing so, the host
processor can access one of the two Data Word blocks, while the
BC reads or writes the alternate Data Word block.
XQF
POINTER
XX00h
POINTER
DATA BLOCK 0
A second application of the "execute and flip" capability is in con-
junction with message retries. This allows the BC to not only
switch buses when retrying a failed message, but to automati-
cally switch buses permanently for all future times that the same
message is to be processed. This not only provides a high
degree of autonomy from the host CPU, but saves BC band-
width, by eliminating the need for future attempts to process
messages on an RT's failed channel.
MESSAGE
CONTROL/STATUS
BLOCK 1
XX00h
DATA BLOCK 1
POINTER
FIGURE 4. EXECUTE and FLIP (XQF) OPERATION
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General Purpose Queue. The Enhanced Mini-ACE/µ-ACE BC
allows for the creation of a general purpose queue. This data
structure provides a means for the message sequence proces-
sor to convey information to the BC host. The BC op code
repertoire provides mechanisms to push various items on this
queue. These include the contents of the Time Tag Register,
the Block Status Word for the most recent message, an imme-
diate data value, or the contents of a specified memory
address.
address rolls over at a 64-word boundary.The rollover will always
occur at a modulo 64 address.
REMOTE TERMINAL (RT) ARCHITECTURE
The Enhanced Mini-ACE/µ-ACE's RT architecture builds upon
that of the ACE and Mini-ACE. The Enhanced Mini-ACE/µ-ACE
provides multiprotocol support, with full compliance to all of the
commonly used data bus standards, including MIL-STD-1553A,
MIL-STD-1553B Notice 2, STANAG 3838, General Dynamics
16PP303, and McAirA3818, A5232, and A5690. For the
Enhanced Mini-ACE/µ-ACE RT mode, there is programmable
flexibility enabling the RT to be configured to fulfill any set of sys-
tem requirements. This includes the capability to meet the MIL-
STD-1553A response time requirement of 2 to 5 µs, and multiple
options for mode code subaddresses, mode codes, RT status
word, and RT BIT word.
FIGURE 5 illustrates the operation of the BC General Purpose
Queue. Note that the BC General Purpose Queue Pointer
Register will always point to the next address location (modulo
64); that is, the location following the last location written by the
BC message sequence control engine.
If enabled, a BC GENERAL PURPOSE QUEUE ROLLOVER
interrupt will be issued when the value of the queue pointer
BC GENERAL
PURPOSE QUEUE
(64 Locations)
LAST LOCATION
NEXT LOCATION
BC GENERAL
PURPOSE QUEUE
POINTER
REGISTER
FIGURE 5. BC GENERAL PURPOSE QUEUE
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The Enhanced Mini-ACE/µ-ACE RT protocol design implements
all of the MIL-STD-1553B message formats and dual redundant
mode codes. The design has passed validation testing for MIL-
STD-1553B compliance.The Enhanced Mini-ACE/µ-ACE RT per-
forms comprehensive error checking including word and format
validation, and checks for various RT-to-RT transfer errors. One of
the main features of the Enhanced Mini-ACE/µ-ACE RT is its
choice of memory management options. These include single
buffering by subaddress, double buffering for individual receive
subaddresses, circular buffering by individual subaddresses, and
global circular buffering for multiple (or all) subaddresses.
(hex) for the Area A Stack Pointer and address 0104 for the Area
B Stack Pointer. In addition to the Stack Pointer, there are sever-
al other areas of the shared RAM address space that are desig-
nated as fixed locations (all shown in bold). These are for the
Area A and Area B lookup tables, the illegalization lookup table,
the busy lookup table, and the mode code data tables.
The RT lookup tables (reference TABLE 39) provide a mecha-
nism for allocating data blocks for individual transmit, receive, or
broadcast subaddresses. The RT lookup tables include subad-
dress control words as well as the individual data block pointers.
If command illegalization is used, address range 0300-03FF is
used for command illegalizing.The descriptor stack RAM area, as
well as the individual data blocks, may be located in any of the
non-fixed areas in the shared RAM address space.
Other features of the Enhanced Mini-ACE/µ-ACE RT include a
set of interrupt conditions, a flexible status queue with filtering
based on valid and/or invalid messages, flexible command ille-
galization, programmable busy by subaddress, multiple options
on time tagging, and an "auto-boot" feature which allows the RT
to initialize as an online RT with the busy bit set following power
turn-on.
Note that in TABLE 38, there is no area allocated for "Stack B".
This is shown for purpose of simplicity of illustration. Also, note
that in TABLE 38, the allocated area for the RT command stack is
256 words. However, larger stack sizes are possible. That is, the
RT command stack size may be programmed for 256 words (64
messages), 512, 1024, or 2048 words (512 messages) by means
of bits 14 and 13 of Configuration Register 3.
RT MEMORY ORGANIZATION
TABLE 38 illustrates a typical memory map for an Enhanced Mini-
ACE/µ-ACE RT with 4K RAM. The two Stack Pointers reside in
fixed locations in the shared RAM address space: address 0100
TABLE 38. TYPICAL RT MEMORY MAP (SHOWN
FOR 4K RAM)
ADDRESS
DESCRIPTION
(HEX)
0000-00FF
0100
Stack A
Stack Pointer A
Global Circular Buffer A Pointer
RESERVED
0101
TABLE 39. RT LOOK-UP TABLES
0102-0103
0104
Stack Pointer B
Global Circular Buffer B Pointer
RESERVED
AREA A
AREA B
DESCRIPTION
COMMENT
0105
0140
•
•
•
01C0
•
•
•
Rx(/Bcst) SA0
Receive
(/Broadcast)
Lookup Pointer
Table
•
•
•
0106-0107
0108-010F
0110-013F
0140-01BF
01C0-023F
0240-0247
0248-025F
0260-027F
0280-02FF
0300-03FF
0400-041F
0420-043F
•
Mode Code Selective Interrupt Table
Mode Code Data
Lookup Table A
Lookup Table B
Busy Bit Lookup Table
(not used)
015F
01DF
Rx(/Bcst) SA31
0160
•
•
•
01E0
•
•
•
Tx SA0
Transmit
Lookup Pointer
Table
•
•
•
017F
01FF
Tx SA31
Data Block 0
0180
•
•
•
0200
•
•
•
Bcst SA0
Broadcast
Lookup Pointer
Table
Data Block 1-4
•
•
•
Command Illegalizing Table
Data Block 5
(Optional)
019F
021F
Bcst SA31
Data Block 6
01A0
•
•
•
0220
•
•
•
SACW SA0
Subaddress
Control Word
Lookup Table
(Optional)
•
•
•
•
•
•
•
•
01BF
023F
SACW SA31
0FE0-0FFF
Data Block 100
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RT MEMORY MANAGEMENT
End-of-message interrupts may be enabled either globally (fol-
lowing all messages), following error messages, on a
transmit/receive/broadcast subaddress or mode code basis, or
when a circular buffer reaches its midpoint (50% boundary) or
lower (100%) boundary. A pair of interrupt status registers allow
the host processor to determine the cause of all interrupts by
means of a single read operation.
The Enhanced Mini-ACE/µ-ACE provides a variety of RT memo-
ry management capabilities. As with the ACE and Mini-ACE, the
choice of memory management scheme is fully programmable
on a transmit/receive/broadcast subaddress basis.
In compliance with MIL-STD-1553B Notice 2, received data from
broadcast messages may be optionally separated from non-
broadcast received data. For each transmit, receive or broadcast
subaddress, either a single-message data block, a double
buffered configuration (two alternating Data Word blocks), or a
variable-sized (128 to 8192 words) subaddress circular buffer
may be allocated for data storage. The memory management
scheme for individual subaddresses is designated by means of
the subaddress control word (reference TABLE 40).
SINGLE BUFFERED MODE
The operation of the single buffered RT mode is illustrated in
FIGURE 6. In the single buffered mode, the respective lookup
table entry must be written by the host processor. Received data
words are written to, or transmitted data words are read from the
data word block with starting address referenced by the lookup
table pointer. In the single buffered mode, the current lookup
table pointer is not updated by the Enhanced Mini-ACE/µ-ACE
memory management logic.Therefore, if a subsequent message
is received for the same subaddress, the same Data Word block
will be overwritten or overread.
For received data, there is also a global circular buffer mode. In
this configuration, the data words received from multiple (or all)
subaddresses are stored in a common circular buffer structure.
Like the subaddress circular buffer, the size of the global circular
buffer is programmable, with a range of 128 to 8192 data words.
SUBADDRESS DOUBLE BUFFERING MODE
The Enhanced Mini-ACE/µ-ACE provides a double buffering
mechanism for received data, that may be selected on an individ-
ual subaddress basis for any or all receive (and/or broadcast) sub-
addresses. This is illustrated in FIGURE 7. It should be noted that
the Subaddress Double Buffering mode is applicable for receive
data only, not for transmit data. Double buffering of transmit mes-
sages may be easily implemented by software techniques.
The double buffering feature provides a means for the host
processor to easily access the most recent, complete received
block of valid Data Words for any given subaddress. In addition
to helping ensure data sample consistency, the circular buffer
options provide a means for greatly reducing host processor
overhead for multi-message bulk data transfer applications.
TABLE 40. RT SUBADDRESS CONTROL WORD - MEMORY MANAGEMENT OPTIONS
DOUBLE-BUFFERED OR
GLOBAL CIRCULAR BUFFER
(bit 15)
SUBADDRESS CONTROL WORD BITS
MEMORY MANAGEMENT SUBADDRESS
BUFFER SCHEME DESCRIPTION
MM2
MM1
MM0
0
0
0
0
Single Message
For Receive or Broadcast:
Double Buffered
1
0
0
0
For Transmit: Single Message
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
128-Word
256-Word
512-Word
Subaddress -
specific circular buffer
of specified size.
1024-Word
2048-Word
4096-Word
8192-Word
(for receive and / or broadcast subaddresses only)
Global Circular Buffer: The buffer size is specified by
Configuration Register #6, bits 11-9. The pointer to the global
circular buffer is stored at address 0101 (for Area A) or address
0105 (for Area B)
1
1
1
1
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The purpose of the subaddress double buffering mode is to pro-
vide data sample consistency to the host processor. This is
accomplished by allocating two 32-word data word blocks for
each individual receive (and/or broadcast receive) subaddress.
At any given time, one of the blocks will be designated as the
"active" 1553 block while the other will be considered as "inac-
tive". The data words for the next receive command to that sub-
address will be stored in the active block. Following receipt of a
valid message, the Enhanced Mini-ACE/µ-ACE will automatical-
ly switch the active and inactive blocks for that subaddress. As a
result, the latest, valid, complete data block is always accessible
to the host processor.
In general, the location after the last data word written or read
(modulo the circular buffer size) during the message is written to
the respective lookup table location during the end-of-message
sequence. By so doing, data for the next message for the respec-
tive transmit, receive(/broadcast), or broadcast subaddress will
be accessed from the next lower contiguous block of locations in
the circular buffer.
For the case of a receive (or broadcast receive) message with a
data word error, there is an option such that the lookup table
pointer will only be updated following receipt of a valid message.
That is, the pointer will not be updated following receipt of a
message with an error in a data word. This allows failed mes-
sages in a bulk data transfer to be retried without disrupting the
circular buffer data structure, and without intervention by the
RT's host processor.
CIRCULAR BUFFER MODE
The operation of the Enhanced Mini-ACE/µ-ACE's circular buffer
RT memory management mode is illustrated in FIGURE 8. As in
the single buffered and double buffered modes, the individual
lookup table entries are initially loaded by the host processor. At
the start of each message, the lookup table entry is stored in the
third position of the respective message block descriptor in the
descriptor stack area of RAM. Receive or transmit data words
are transferred to (from) the circular buffer, starting at the loca-
tion referenced by the lookup table pointer.
GLOBAL CIRCULAR BUFFER
Beyond the programmable choice of single buffer mode, double
buffer mode, or circular buffer mode, programmable on an indi-
vidual subaddress basis, the Enhanced Mini-ACE/µ-ACE RT
architecture provides an additional option, a variable sized glob-
al circular buffer.The Enhanced Mini-ACE/µ-ACE RT allows for a
LOOK-UP TABLE
(DATA BLOCK ADDR)
DESCRIPTOR
STACKS
CONFIGURATION
REGISTER
STACK
POINTERS
DATA
BLOCKS
15 13
0
CURRENT
AREA B/A
BLOCK STATUS WORD
TIME TAG WORD
LOOK-UP
TABLE ADDR
DATA BLOCK
DATA BLOCK
DATA BLOCK POINTER
(See note)
RECEIVED COMMAND
WORD
Note: Lookup table is not used for mode commands when enhanced mode codes are enabled.
FIGURE 6. RT SINGLE BUFFERED MODE
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mix of single buffered, double buffered, and individually circular
buffered subaddresses, along with the use of the global double
buffer for any arbitrary group of receive(/broadcast) or broadcast
subaddresses.
The pointer to the Global Circular Buffer will be stored in location
0101 (for Area A), or location 0105 (for Area B).
The global circular buffer option provides a highly efficient
method for storing received message data. It allows for frequent-
ly used subaddresses to be mapped to individual data blocks,
while also providing a method for asynchronously received mes-
sages to infrequently used subaddresses to be logged to a com-
mon area. Alternatively, the global circular buffer provides an effi-
cient means for storing the received data words for all subad-
dresses. Under this method, all received data words are stored
chronologically, regardless of subaddress.
In the global circular buffer mode, the data for multiple receive
subaddresses is stored in the same circular buffer data structure.
The size of the global circular buffer may be programmed for 128,
256, 512, 1024, 2048, 4096, or 8192 words, by means of bits 11,
10, and 9 of Configuration Register #6. As shown in TABLE 40,
individual subaddresses may be mapped to the global circular
buffer by means of their respective subaddress control words.
CONFIGURATION
REGISTER
STACK
POINTERS
DESCRIPTOR
STACK
LOOK-UP
TABLES
15
13
0
DATA
BLOCKS
CURRENT
AREA B/A
BLOCK STATUS WORD
TIME TAG WORD
X..X 0 YYYYY
DATA
BLOCK 0
DATA BLOCK POINTER
DATA BLOCK POINTER
X..X 1 YYYYY
RECEIVED COMMAND
WORD
DATA
BLOCK 1
RECEIVE DOUBLE
BUFFER ENABLE
MSB
SUBADDRESS
CONTROL WORD
FIGURE 7. RT DOUBLE BUFFERED MODE
CIRCULAR
DATA
CONFIGURATION
REGISTER
STACK
POINTERS
DESCRIPTOR
STACK
LOOK-UP TABLES
BUFFER
15
13
0
CURRENT
AREA B/A
BLOCK STATUS WORD
TIME TAG WORD
POINTER TO
CURRENT
DATA BLOCK
LOOK-UP
TABLE
ADDRESS
DATA BLOCK POINTER
128,
256
LOOK-UP TABLE
ENTRY
RECEIVED COMMAND
WORD
RECEIVED
(TRANSMITTED)
MESSAGE
POINTER TO
NEXT DATA
BLOCK
*
DATA
8192
WORDS
(NEXT LOCATION)
Notes:
CIRCULAR
BUFFER
ROLLOVER
1. TX/RS/BCST_SA look-up table entry is updated following valid receive (broadcast) message
or following completion of transit message
2. For the Global Circular Buffer Mode, the pointer is read from and re-written to Address 0101 (for Area A)
or Address 0105 (for Area B).
FIGURE 8. RT CIRCULAR BUFFERED MODE
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RT DESCRIPTOR STACK
(3) Monitor command (descriptor) stack; and
(4) Monitor data stack.
The descriptor stack provides a chronology of all messages
processed by the Enhanced Mini-ACE/µ-ACE RT. Reference
FIGURES 6, 7, and 8. Similar to BC mode, there is a four-word
block descriptor in the Stack for each message processed. The
four entries to each block descriptor are the Block Status Word,
Time Tag Word, the pointer to the start of the message's data
block, and the 16-bit received Command Word.
The 50% rollover interrupt is beneficial for performing bulk data
transfers. For example, when using circular buffering for a partic-
ular receive subaddress, the 50% rollover interrupt will inform the
host processor when the circular buffer is half full. At that time,
the host may proceed to read the received data words in the
upper half of the buffer, while the Enhanced Mini-ACE/µ-ACE RT
writes received data words to the lower half of the circular buffer.
Later, when the RT issues a 100% circular buffer rollover inter-
rupt, the host can proceed to read the received data from the
lower half of the buffer, while the Enhanced Mini-ACE RT contin-
ues to write received data words to the upper half of the buffer.
The RT Block Status Word includes indications of whether a par-
ticular message is ongoing or has been completed, what bus
channel it was received on, indications of illegal commands, and
flags denoting various message error conditions. For the double
buffering, subaddress circular buffering, and global circular
buffering modes, the data block pointer may be used for locating
the data blocks for specific messages. Note that for mode code
commands, there is an option to store the transmitted or
received data word as the third word of the descriptor, in place of
the data block pointer.
Interrupt status queue. The Enhanced Mini-ACE/µ-ACE RT,
Monitor, and combined RT/Monitor modes include the capability
for generating an interrupt status queue. As illustrated in FIGURE
10, this provides a chronological history of interrupt generating
events and conditions. In addition to the Interrupt Mask Register,
the Interrupt Status Queue provides additional filtering capability,
such that only valid messages and/or only invalid messages may
result in the creation of an entry to the Interrupt Status Queue.
Queue entries for invalid and/or valid messages may be disabled
by means of bits 8 and 7 of configuration register #6.
The Time Tag Word provides a 16-bit indication of relative time
for individual messages. The resolution of the Enhanced Mini-
ACE/µ-ACE's time tag is programmable from among 2, 4, 8, 16,
32, or 64 µs/LSB. There is also a provision for using an external
clock input for the time tag (consult factory). If enabled, there is
a time tag rollover interrupt, which is issued when the value of
the time tag rolls over from FFFF(hex) to 0. Other time tag
options include the capabilities to clear the time tag register fol-
lowing receipt of a Synchronize (without data) mode command
and/or to set the time tag following receipt of a Synchronize (with
data) mode command. For the latter, there is an added option to
filter the "set" capability based on the LSB of the received data
word being equal to logic "0".
The interrupt status queue is 64 words deep, providing the capa-
bility to store entries for up to 32 messages.These events and con-
ditions include both message-related and non-message related
events. Note that the Interrupt Vector Queue Pointer Register will
always point to the next location (modulo 64) following the last vec-
tor/pointer pair written by the Enhanced Mini-ACE/µ-ACE RT.
The pointer to the Interrupt Status Queue is stored in the
INTERRUPT VECTOR QUEUE POINTER REGISTER (register
address 1F). This register must be initialized by the host, and is
subsequently incremented by the RT message processor. The
interrupt status queue is 64 words deep, providing the capability
to store entries for up to 32 messages.
RT INTERRUPTS
The Enhanced Mini-ACE/µ-ACE offers a great deal of flexibility in
terms of RT interrupt processing. By means of the Enhanced Mini-
ACE/µ-ACE’s two Interrupt Mask Registers, the RT may be pro-
grammed to issue interrupt requests for the following events/con-
ditions: End-of-(every)Message, Message Error, Selected (trans-
mit or receive) Subaddress, 100% Circular Buffer Rollover, 50%
Circular Buffer Rollover, 100% Descriptor Stack Rollover, 50%
Descriptor Stack Rollover, Selected Mode Code, Transmitter
Timeout, Illegal Command, and Interrupt Status Queue Rollover.
The queue rolls over at addresses of modulo 64. The events that
result in queue entries include both message-related and non-
message-related events. Note that the Interrupt Vector Queue
Pointer Register will always point to the next location (modulo 64)
following the last vector/pointer pair written by the Enhanced
Mini-ACE/µ-ACE RT, Monitor, or RT/Monitor.
Interrupts for 50% Rollovers of Stacks and Circular Buffers.
The Enhanced Mini-ACE/µ-ACE RT and Monitor are capable of
issuing host interrupts when a subaddress circular buffer pointer
or stack pointer crosses its mid-point boundary. For RT circular
buffers, this is applicable for both transmit and receive subad-
dresses. Reference FIGURE 9. There are four interrupt mask
and interrupt status register bits associated with the 50% rollover
function:
Each event that causes an interrupt results in a two-word entry
to be written to the queue. The first word of the entry is the inter-
rupt vector. The vector indicates which interrupt event(s)/condi-
tion(s) caused the interrupt.
The interrupt events are classified into two categories: message
interrupt events and non-message interrupt events. Message-
based interrupt events include End-of-Message, Selected mode
(1) RT circular buffer;
(2) RT command (descriptor) stack;
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code, Format error, Subaddress control word interrupt, RT
Circular buffer Rollover, Handshake failure, RT Command stack
rollover, transmitter timeout, MT Data Stack rollover,
MT Command Stack rollover, RT Command Stack 50% rollover,
MT Data Stack 50% rollover, MT Command Stack 50% rollover,
and RT Circular buffer 50% rollover. Non-message interrupt
events/conditions include time tag rollover, RT address parity
error, RAM parity error, and BIT completed.
possible for one entry on the queue to indicate both a message
interrupt and a non-message interrupt.
As illustrated in FIGURE 10, for a message interrupt event, the para-
meter word is a pointer.The pointer will reference the first word of the
RT or MT command stack descriptor (i.e., the Block Status Word).
For a RAM Parity Error non-message interrupt, the parameter
will be the RAM address where the parity check failed. For the
RT address Parity Error, Protocol Self-test Complete, and Time
Tag rollover non-message interrupts, the parameter is not used;
it will have a value of 0000.
Bit 0 of the interrupt vector (interrupt status) word indicates
whether the entry is for a message interrupt event (if bit 0 is logic
"1") or a non-message interrupt event (if bit 0 is logic "0"). It is not
CIRCULAR
BUFFER*
(128,256,...8192 WORDS)
DESCRIPTOR STACK
BLOCK STATUS WORD
TIME TAG WORD
LOOK-UP TABLE
DATA BLOCK POINTER
DATA POINTER
RECEIVED COMMAND WORD
RECEIVED
(TRANSMITTED)
MESSAGE DATA
50%
ROLLOVER
50%
INTERRUPT
Note
100%
ROLLOVER
INTERRUPT
The example shown is for an RT Subaddress Circular Buffer.
The 50% and 100% Rollover Interrupts are also applicable to
the RT Global Circulat Buffer, RT Command Stack,
Monitor Command Stack, and Monitor Data Stack.
100%
FIGURE 9. 50% and 100% ROLLOVER INTERRUPTS
INTERRUPT STATUS QUEUE
(64 Locations)
DESCRIPTOR
STACK
INTERRUPT
VECTOR
PARAMETER
(POINTER)
BLOCK STATUS WORD
INTERRUPT VECTOR
TIME TAG
QUEUE POINTER
REGISTER (IF)
NEXT
VECTOR
DATA BLOCK POINTER
RECEIVED COMMAND
DATA WORD
BLOCK
FIGURE 10. RT (and MONITOR) INTERRUPT STATUS QUEUE
(shown for message Interrupt event)
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If enabled, an INTERRUPT STATUS QUEUE ROLLOVER inter-
rupt will be issued when the value of the queue pointer address
rolls over at a 64-word address boundary.
ibility, allowing any subset of the 4096 possible combinations of
broadcast/own address, T/R bit, subaddress, and word
count/mode code to be illegalized.
The address map of the Enhanced Mini-ACE/µ-ACE's illegalizing
table is illustrated in TABLE 41.
NOTE: Please see Appendix “F” of the Enhanced Mini-ACE
User’s Guide for important information applicable only to RT
MODE operation, enabling of the interrupt status queue and
use of specific non-message interrupts.
BUSY BIT
The Enhanced Mini-ACE/µ-ACE RT provides two different meth-
ods for setting the Busy status word bit: (1) globally, by means of
Configuration Register #1; or (2) on a T/R-bit/subaddress basis,
by means of a RAM lookup table. If the host CPU asserts the
BUSY bit to logic ”0” in Configuration Register #1, the Enhanced
Mini-ACE/µ-ACE RT will respond to all non-broadcast com-
mands with the Busy bit set in its RT Status Word.
RT COMMAND ILLEGALIZATION
The Enhanced Mini-ACE/µ-ACE provides an internal mechanism
for RT Command Word illegalizing. By means of a 256-word area
in shared RAM, the host processor may designate that any mes-
sage be illegalized, based on the command word T/R bit, subad-
dress, and word count/mode code fields. The Enhanced Mini-
ACE/µ-ACE illegalization scheme provides the maximum in flex-
Alternatively, there is a Busy lookup table in the Enhanced Mini-
ACE/µ-ACE shared RAM. By means of this table, it is possible for the
TABLE 41. ILLEGALIZATION TABLE MEMORY MAP
ADDRESS
300
DESCRIPTION
Brdcst / Rx, SA 0. MC15-0
Brdcst / RX, SA 0. MC31-16
Brdcst / Rx, SA 1. WC15-0
Brdcst / Rx, SA 1. WC31-16
301
302
303
•
•
•
•
•
•
33F
340
341
342
Brdcst / Rx, SA 31. MC31-16
Brdcst / Tx, SA 0. MC15-0
Brdcst / Tx, SA 0.MC31-16
Brdcst / Tx, SA 1. WC15-0
•
•
•
•
•
•
37D
37E
37F
380
381
382
383
Brdcst / Tx, SA 30. WC31-16
Brdcst / Tx, SA 31. MC15-0
Brdcst / Tx, SA 31. MC31-16
Own Addr / Rx, SA 0. MC15-0
Own Addr / Rx, SA 0. MC31-16
Own Addr / Rx, SA 1. WC15-0
Own Addr / Rx, SA 1. WC31-16
•
•
•
•
•
•
3BE
3BF
3C0
3C1
3C2
3C3
Own Addr / Rx, SA 31. MC15-0
Own Addr / Rx, SA 31. MC31-16
Own Addr / Tx, SA 0. MC15-0
Own Addr / Tx, SA 0. MC31-16
Own Addr / Tx, SA 1. WC15-0
Own Addr / Tx, SA 1. WC31-16
•
•
•
•
•
•
3FC
3FD
3FE
3FF
Own Addr / Tx, SA 30. WC15-0
Own Addr / Tx, SA 30. WC31-16
Own Addr / Tx, SA 31. MC15-0
Own Addr / Tx, SA 31. MC31-16
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TABLE 42. RT BIT WORD
host processor to set the busy bit for any selectable subset of the 128
combinations of broadcast/own address, T/R bit, and subaddress.
BIT
DESCRIPTION
15(MSB) TRANSMITTER TIMEOUT
If the busy bit is set for a transmit command, the Enhanced Mini-
ACE/µ-ACE RT will respond with the busy bit set in the status
word, but will not transmit any data words. If the busy bit is set for
a receive command, the RT will also respond with the busy status
bit set. There are two programmable options regarding the recep-
tion of data words for a non-mode code receive command for
which the RT is busy: (1) to transfer the received data words to
shared RAM; or (2) to not transfer the data words to shared RAM.
14
LOOP TEST FAILURE B
13
LOOP TEST FAILURE A
12
HANDSHAKE FAILURE
11
TRANSMITTER SHUTDOWN B
TRANSMITTER SHUTDOWN A
TERMINAL FLAG INHIBITED
BIT TEST FAILURE
10
9
8
7
HIGH WORD COUNT
6
LOW WORD COUNT
RT ADDRESS
5
INCORRECT SYNC RECEIVED
PARITY / MANCHESTER ERROR RECEIVED
RT-to-RT GAP / SYNC ADDRESS ERROR
RT-to-RT NO RESPONSE ERROR
RT-to-RT 2ND COMMAND WORD ERROR
COMMAND WORD CONTENTS ERROR
The Enhanced Mini-ACE/µ-ACE offers several different options
for designating the Remote Terminal address. These include the
following: (1) hardwired, by means of the 5 RT ADDRESS inputs,
and the RT ADDRESS PARITY input; (2) by means of the RT
ADDRESS (and PARITY) inputs, but latched via hardware, on
the rising edge of the RT_AD_LAT input signal; (3) input by
means of the RT ADDRESS (and PARITY) inputs, but latched via
host software; and (4) software programmable, by means of an
internal register. In all four configurations, the RT address is
readable by the host processor.
4
3
2
1
0(LSB)
For new applications, it is recommended that the selective mes-
sage monitor mode be used, rather than the word monitor mode.
Besides providing monitor filtering based on RT address, T/R bit,
and subaddress, the message monitor eliminates the need to
determine the start and end of messages by software.
RT BUILT-IN-TEST (BIT) WORD
The bit map for the Enhanced Mini-ACE/µ-ACE's internal RT
Built-in-Test (BIT) Word is indicated in TABLE 42.
WORD MONITOR MODE
In the Word Monitor Terminal mode, the Enhanced Mini-ACE/µ-
ACE monitors both 1553 buses. After the software initialization
and Monitor Start sequences, the Enhanced Mini-ACE/µ-ACE
stores all Command, Status, and Data Words received from both
buses. For each word received from either bus, a pair of words is
stored to the Enhanced Mini-ACE/µ-ACE's shared RAM.The first
word is the word received from the 1553 bus. The second word
is the Monitor Identification (ID), or "Tag" word. The ID word con-
tains information relating to bus channel, word validity, and inter-
word time gaps. The data and ID words are stored in a circular
buffer in the shared RAM address space.
RT AUTO-BOOT OPTION
If utilized, the RT pin-programmable auto-boot option allows the
Enhanced Mini-ACE/µ-ACE RT to automatically initialize as an
active remote terminal with the Busy status word bit set to logic "1"
immediately following power turn-on.This is a useful feature for MIL-
STD-1760 applications, in which the RT is required to be respond-
ing within 150 ms after power-up. This feature is available for ver-
sions of the Enhanced Mini-ACE/µ-ACE with 4K words of RAM.
OTHER RT FEATURES
The Enhanced Mini-ACE/µ-ACE includes options for the
Terminal flag status word bit to be set either under software con-
trol and/or automatically following a failure of the loopback self-
test. Other software programmable RT options include software
programmable RT status and RT BIT words, automatic clearing
of the Service Request bit following receipt of a Transmit vector
word mode command, options regarding Data Word transfers for
the Busy and Message error (illegal) Status word bits, and
options for the handling of 1553A and reserved mode codes.
WORD MONITOR MEMORY MAP
A typical word monitor memory map is illustrated in TABLE 43.
TABLE 43 assumes a 64K address space for the Enhanced Mini-
ACE/µ-ACE's monitor. The Active Area Stack pointer provides
the address where the first monitored word is stored. In the
example, it is assumed that the Active Area Stack Pointer for
Area A (location 0100) is initialized to 0000. The first received
data word is stored in location 0000, the ID word for the first word
is stored in location 0001, etc.
MONITOR ARCHITECTURE
The Enhanced Mini-ACE/µ-ACE includes three monitor modes:
The current Monitor address is maintained by means of a
counter register. This value may be read by the CPU by means
of the Data Stack Address Register. It is important to note that
when the counter reaches the Stack Pointer address of 0100 or
0104, the initial pointer value stored in this shared RAM location
will be overwritten by the monitored data and ID Words. When
the internal counter reaches an address of FFFF (or 0FFF, for an
(1) A Word Monitor mode
(2) A selective message monitor mode
(3) A combined RT/message monitor mode
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TABLE 44. MONITOR SELECTION TABLE LOOKUP
ADDRESS
TABLE 43. TYPICAL WORD MONITOR MEMORY
MAP
BIT
DESCRIPTION
HEX
FUNCTION
ADDRESS
15(MSB)
Logic “0”
Logic “0”
0000
0001
0002
0003
0004
005
First Received 1553 Word
First Identification Word
14
13
Logic “0”
Second Received 1553 Word
Second Identification Word
Third Received 1553 Word
Third Identification Word
12
Logic “0”
11
Logic “0”
10
Logic “0”
9
Logic “1”
•
•
•
•
•
•
8
Logic “0”
7
Logic “1”
6
RTAD_4
Stack Pointer
(Fixed Location - gets overwritten)
0100
5
RTAD_3
•
•
•
•
•
•
4
RTAD_2
3
RTAD_1
FFFF
Received 1553 Words and Identification Word
2
RTAD_0
1
TRANSMIT / RECEIVE
SUBADDRESS 4
0(LSB)
Enhanced Mini-ACE/µ-ACE with 4K RAM), the counter rolls over
to 0000.
tive monitor lookup table to determine if the particular command
is enabled. The address for this location in the table is deter-
mined by means of an offset based on the RT Address, T/R bit,
and Subaddress bit 4 of the current command word, and con-
catenating it to the monitor lookup table base address of 0280
(hex). The bit location within this word is determined by subad-
dress bits 3-0 of the current command word.
WORD MONITOR TRIGGER
In the Word Monitor mode, there is a pattern recognition trigger
and a pattern recognition interrupt. The 16-bit compare word for
both the trigger and the interrupt is stored in the Monitor Trigger
Word Register. The pattern recognition interrupt is enabled by set-
ting the MT Pattern Trigger bit in Interrupt Mask Register #1. The
pattern recognition trigger is enabled by setting the Trigger Enable
bit in Configuration Register #1 and selecting either the Start-on-
trigger or the Stop-on-trigger bit in Configuration Register #1. The
Word Monitor may also be started by means of a low-to-high
transition on the EXT_TRIG input signal.
If the specified bit in the lookup table is logic "0", the command
is not enabled, and the Enhanced Mini-ACE/µ-ACE will ignore
this command. If this bit is logic "1", the command is enabled and
the Enhanced Mini-ACE/µ-ACE will create an entry in the moni-
tor command descriptor stack (based on the monitor command
stack pointer), and store the data and status words associated
with the command into sequential locations in the monitor data
stack. In addition, for an RT-to-RT transfer in which the receive
command is selected, the second command word (the transmit
command) is stored in the monitor data stack.
SELECTIVE MESSAGE MONITOR MODE
The Enhanced Mini-ACE/µ-ACE Selective Message Monitor pro-
vides monitoring of 1553 messages with filtering based on RT
address, T/R bit, and subaddress with no host processor interven-
tion. By autonomously distinguishing between 1553 command and
status words, the Message Monitor determines when messages
begin and end, and stores the messages into RAM, based on a
programmable filter of RT address, T/R bit, and subaddress.
The address definition for the Selective Monitor Lookup TABLE
is illustrated in TABLE 44.
SELECTIVE MESSAGE MONITOR MEMORY
ORGANIZATION
The selective monitor may be configured as just a monitor, or as a
combined RT/Monitor. In the combined RT/Monitor mode, the
Enhanced Mini-ACE/µ-ACE functions as an RT for one RT address
(including broadcast messages), and as a selective message mon-
itor for the other 30 RT addresses.The Enhanced Mini-ACE/µ-ACE
Message Monitor contains two stacks, a command stack and a
data stack, that are independent from the RT command stack. The
pointers for these stacks are located at fixed locations in RAM.
A typical memory map for the Enhanced Mini-ACE/µ-ACE in the
Selective Message Monitor mode, assuming a 4K RAM space, is
illustrated in TABLE 45. This mode of operation defines several
fixed locations in the RAM. These locations are allocated in a
way in which none of them overlap with the fixed RT locations.
This allows for the combined RT/Selective Message Monitor
mode.
MONITOR SELECTION FUNCTION
Following receipt of a valid command word in Selective Monitor
mode, the Enhanced Mini-ACE/µ-ACE will reference the selec-
The fixed memory map consists of two Monitor Command Stack
Pointers (locations 102 and 106 hex), two Monitor Data Stack
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TABLE 45. TYPICAL SELECTIVE MESSAGE
MONITOR MEMORY MAP (shown for 4K RAM for
“Monitor only” mode)
half of the respective stack, while the Enhanced Mini-ACE/µ-ACE
monitor writes messages to the lower half of the stack. Later, when
the monitor issues a 100% stack rollover interrupt, the host can pro-
ceed to read the received data from the lower half of the stack,
while the Enhanced Mini-ACE/µ-ACE monitor continues to write
received data words to the upper half of the stack.
ADDRESS
DESCRIPTION
(HEX)
Not Used
Monitor Command Stack Pointer A (fixed location)
Monitor Data Stack Pointer A (fixed location)
Not Used
0000-0101
0102
INTERRUPT STATUS QUEUE
0103
Like the Enhanced Mini-ACE/µ-ACE RT, the Selective Monitor
mode includes the capability for generating an interrupt status
queue. As illustrated in FIGURE 10, this provides a chronological
history of interrupt generating events. Besides the two Interrupt
Mask Registers, the Interrupt Status Queue provides additional
filtering capability, such that only valid messages and/or only
invalid messages may result in entries to the Interrupt Status
Queue. The interrupt status queue is 64 words deep, providing
the capability to store entries for up to 32 monitored messages.
0104-0105
0106
Monitor Command Stack Pointer B (fixed location)
Monitor Data Stack Pointer B (fixed location)
Not Used
0107
0108-027F
0280-02FF
0300-03FF
0400-07FF
0800-0FFF
Selective Monitor Lookup Table (fixed location)
Not Used
Monitor Command Stack A
Monitor Data Stack A
Pointers (locations 103 and 107 hex), and a Selective Message
Monitor Lookup Table (locations 0280 through 02FF hex).
For this example, the Monitor Command Stack size is assumed
to be 1K words, and the Monitor Data Stack size is assumed to
be 2K words.
MISCELLANEOUS
CLOCK INPUT
The Enhanced Mini-ACE/µ-ACE decoder is capable of operating
from a 10, 12, 16, or 20 MHz clock input. Depending on the con-
figuration of the specific model Enhanced Mini-ACE/µ-ACE ter-
minal, the selection of the clock input frequency may be chosen
by one of either two methods. For all versions, the clock fre-
quency may be specified by means of the host processor writing
to Configuration Register #6. With the second method, which is
applicable only for the versions incorporating 4K (but not 64K)
words of internal RAM, the clock frequency may be specified by
means of the input signals that are otherwise used as the A15
and A14 address lines.
FIGURE 11 illustrates the Selective Message Monitor operation.
Upon receipt of a valid Command Word, the Enhanced Mini-
ACE/µ-ACE will reference the Selective Monitor Lookup Table to
determine if the current command is enabled. If the current com-
mand is disabled, the Enhanced Mini-ACE/µ-ACE monitor will
ignore (and not store) the current message. If the command is
enabled, the monitor will create an entry in the Monitor Command
Stack at the address location referenced by the Monitor Command
Stack Pointer, and an entry in the monitor data stack starting at the
location referenced by the Monitor Data Stack Pointer.
ENCODER/DECODERS
The format of the information in the data stack depends on the
format of the message that was processed. For example, for a
BC-to-RT transfer (receive command), the monitor will store the
command word in the monitor command descriptor stack, with
the data words and the receiving RT's status word stored in the
monitor data stack.
For the selected clock frequency, there is internal logic to derive
the necessary clocks for the Manchester encoder and decoders.
For all clock frequencies, the decoders sample the receiver out-
puts on both edges of the input clock. By in effect doubling the
decoders' sampling frequency, this serves to widen the tolerance
to zero-crossing distortion, and reduce the bit error rate.
The size of the monitor command stack is programmable, with
choices of 256, 1K, 4K, or 16K words. The monitor data stack
size is programmable with choices of 512, 1K, 2K, 4K, 8K, 16K,
32K or 64K words.
For interfacing to fiber optic transceivers (e.g., for MIL-STD-1773
applications), the decoders are capable of operating with single-
ended, rather than double-ended, input signals. For applications
involving the use of single-ended transceivers, it is suggested
that you contact the factory at DDC regarding a transceiverless
version of the Enhanced Mini-ACE.
MONITOR INTERRUPTS
Selective monitor interrupts may be issued for End-of-message and
for conditions relating to the monitor command stack pointer and
monitor data stack pointer. The latter, which are shown in FIGURE
9, include Command Stack 50% Rollover, Command Stack 100%
Rollover, Data Stack 50% Rollover, and Data Stack 100% Rollover.
TIME TAG
The Enhanced Mini-ACE/µ-ACE includes an internal
read/writable Time Tag Register. This register is a CPU
read/writable 16-bit counter with a programmable resolution of
either 2, 4, 8, 16, 32, or 64 µs per LSB. Another option allows
software controlled incrementing of the Time Tag Register. This
supports self-test for the Time Tag Register. For each message
processed, the value of the Time Tag Register is loaded into the
The 50% rollover interrupts may be used to inform the host proces-
sor when the command stack or data stack is half full. At that time,
the host may proceed to read the received messages in the upper
32
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second location of the respective descriptor stack entry ("TIME
TAG WORD") for both the BC and RT modes.
interrupt by reading the two Interrupt Status Registers, which
provide the current state of interrupt events and conditions. The
Interrupt Status Registers may be updated in two ways. In one
interrupt handling mode, a particular bit in Interrupt Status
Register #1 or #2 will be updated only if the event occurs and the
corresponding bit in Interrupt Mask Register #1 or #2 is enabled.
In the enhanced interrupt handling mode, a particular bit in one
of the Interrupt Status Registers will be updated if the event/con-
dition occurs regardless of the value of the corresponding
Interrupt Mask Register bit. In either case, the respective
Interrupt Mask Register (#1 or #2) bit is used to enable an inter-
rupt for a particular event/condition.
The functionality involving the Time Tag Register that's compati-
ble with ACE/Mini-ACE (Plus) includes: the capability to issue an
interrupt request and set a bit in the Interrupt Status Register
when the Time Tag Register rolls over FFFF to 0000; for RT
mode, the capability to automatically clear the Time Tag Register
following reception of a Synchronize (without data) mode com-
mand, or to load the Time Tag Register following a Synchronize
(with data) mode command.
Additional time tag features supported by the Enhanced Mini-
ACE/µ-ACE include the capability for the BC to transmit the con-
tents of the Time Tag Register as the data word for a
Synchronize (with data) mode command; the capability for the
RT to "filter" the data word for the Synchronize with data mode
command, by only loading the Time Tag Register if the LSB of
the received data word is "0"; an instruction enabling the BC
Message Sequence Control engine to load the Time Tag
Register with a specified value; and an instruction enabling the
BC Message Sequence Control engine to write the value of the
Time Tag Register to the General Purpose Queue.
The Enhanced Mini-ACE/µ-ACE supports all the interrupt events
from ACE/Mini-ACE (Plus), including RAM Parity Error, Transmitter
Timeout, BC/RT Command Stack Rollover, MT Command Stack
and Data Stack Rollover, Handshake Error, BC Retry, RT Address
Parity Error, Time Tag Rollover, RT Circular Buffer Rollover, BC
Message, RT Subaddress, BC End-of-Frame, Format Error, BC
Status Set, RT Mode Code, MT Trigger, and End-of-Message.
For the Enhanced Mini-ACE/µ-ACE's Enhanced BC mode, there
are four user-defined interrupt bits. The BC Message Sequence
Control Engine includes an instruction enabling it to issue these
interrupts at any time.
INTERRUPTS
The Enhanced Mini-ACE/µ-ACE series terminals provide many
programmable options for interrupt generation and handling.
The interrupt output pin (INT) has three software programmable
modes of operation: a pulse, a level output cleared under soft-
ware control, or a level output automatically cleared following a
read of the Interrupt Status Register (#1 or #2).
For RT and Monitor modes, the Enhanced Mini-ACE/µ-ACE archi-
tecture includes an Interrupt Status Queue. This provides a mech-
anism for logging messages that result in interrupt requests.
Entries to the Interrupt Status Queue may be filtered such that only
valid and/or invalid messages will result in entries on the queue.
Individual interrupts are enabled by the two Interrupt Mask
Registers. The host processor may determine the cause of the
The Enhanced Mini-ACE/µ-ACE incorporates additional interrupt
conditions beyond ACE/Mini-ACE (Plus), based on the addition
CONFIGURATION
REGISTER #1
MONITOR COMMAND
STACK POINTERS
MONITOR
COMMAND STACKS
MONITOR DATA
STACKS
15
13
0
CURRENT
AREA B/A
BLOCK STATUS WORD
TIME TAG WORD
MONITOR DATA
BLOCK #N
CURRENT
COMMAND WORD
DATA BLOCK POINTER
MONITOR DATA
BLOCK #N + 1
RECEIVED COMMAND
WORD
MONITOR DATA
STACK POINTERS
NOTE
IF THIS BIT IS "0" (NOT SELECTED)
NO WORDS ARE STORED IN EITHER
THE COMMAND STACK OR DATA STACK.
IN ADDITION, THE COMMAND AND DATA
STACK POINTERS WILL NOT BE UPDATED.
SELECTIVE MONITOR
LOOKUP TABLES
OFFSET BASED ON
RTA4-RTA0, T/R, SA4
SELECTIVE MONITOR
ENABLE
(SEE NOTE)
FIGURE 11. SELECTIVE MESSAGE MONITOR MEMORY MANAGEMENT
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of Interrupt Mask Register #2 and Interrupt Status Register #2.
This is accomplished by chaining the two Interrupt Status
Registers using the INTERRUPT CHAIN BIT (bit 0) in Interrupt
Status Register #2 to indicate that an interrupt has occurred in
Interrupt Status Register #1. Additional interrupts include "Self-
Test Completed", masking bits for the Enhanced BC Control
Interrupts, 50% Rollover interrupts for RT Command Stack, RT
Circular Buffers, MT Command Stack, and MT Data Stack; BC
Op Code Parity Error, (RT) Illegal Command, (BC) General
Purpose Queue or (RT/MT) Interrupt Status Queue Rollover,
Call Stack Pointer Register Error, BC Trap Op Code, and the four
User-Defined interrupts for the Enhanced BC mode.
If there is a failure of the protocol self-test, it is possible to access
information about the first failed vector.This may be done by means
of the Enhanced Mini-ACE/µ-ACE's upper registers (register
addresses 32 through 63).Through these registers, it is possible to
determine the self-test ROM address of the first failed vector, the
expected response data pattern (from the ROM), the register or
memory address, and the actual (incorrect) data value read from
register or memory. The on-chip self-test ROM is 4K X 24.
Note that the RAM self-test is destructive. That is, following the
RAM self-test, regardless of whether the test passes or fails, the
shared RAM is not restored to its state prior to this test. Following
a failed RAM self-test, the host may read the internal RAM to
determine which location(s) failed the walking pattern test.
BUILT-IN TEST
A salient feature of the Enhanced Mini-ACE/µ-ACE is its highly
autonomous self-test capability. This includes both protocol and
RAM self-tests. Either or both of these self-tests may be initiated
by command(s) from the host processor.
RAM PARITY
The BC/RT/MT version of the Enhanced Mini-ACE/µ-ACE is avail-
able with options of 4K or 64K words of internal RAM. For the 64K
option, the RAM is 17 bits wide.The 64K X 17 internal RAM allows
for parity generation for RAM write accesses, and parity checking
for RAM read accesses.This includes host RAM accesses, as well
as accesses by the Enhanced Mini-ACE’s/µ-ACE’s internal logic.
When the Enhanced Mini-ACE/µ-ACE detects a RAM parity error,
it reports it to the host processor by means of an interrupt and a
register bit. Also, for the RT and Selective Message Monitor
modes, the RAM address where a parity error was detected will be
stored on the Interrupt Status Queue (if enabled).
The protocol test consists of a comprehensive toggle test of the
terminal's logic. The test includes testing of all registers,
Manchester decoders, protocol logic, and memory management
logs.This test is completed in approximately 32,000 clock cycles.
That is, about 1.6 ms with a 20 MHz clock, 2.0 ms at 16 MHz, 2.7
ms at 12 MHz, and 3.2 ms at 10 MHz.
There is also a separate built-in test for the Enhanced Mini-ACE/µ-
ACE's 4K X 16 or 64K X 16 shared RAM.This test consists of writing
and then reading/verifying the two walking patterns "data = address"
and "data = address inverted". This test takes 10 clock cycles per
word. For an Enhanced Mini-ACE/µ-ACE with 4K words of RAM, this
is about 2.0 ms with a 20 MHz clock, 2.6 ms at 16 MHz, 3.4 ms at 12
MHz, or 4.1 ms at 10 MHz. For an Enhanced Mini-ACE/µ-ACE with
64K words of RAM, this test takes about 32.8 ms with a 20 MHz clock,
40.1 ms at 16 MHz, 54.6 ms at 12 MHz, or 65.6 ms at 10 MHz.
RELOCATABLE MEMORY MANAGEMENT LOCATIONS
In the Enhanced Mini-ACE/µ-ACE's default configuration, there is
a fixed area of shared RAM addresses, 0000h-03FF, that is allo-
cated for storage of the BC's or RT's pointers, counters, tables,
and other "non-message" data structures. As a means of reduc-
ing the overall memory address space for using multiple
Enhanced Mini-ACE/µ-ACE’s in a given system (e.g., for use with
the DMA interface configuration), the Enhanced Mini-ACE/µ-ACE
allows this area of RAM to be relocated by means of 6 configura-
tion register bits. To provide backwards compatibility to ACE and
Mini-ACE, the default for this RAM area is 0000h-03FFh.
The Enhanced Mini-ACE/µ-ACE built-in protocol test is performed
automatically at power-up. In addition, the protocol or RAM self-
tests may be initiated by a command from the host processor, via
the START/REST REGISTER. For RT mode, this may include the
host processor invoking self-test following receipt of an Initiate
self-test mode command. The results of the self-test are host
accessible by means of the BIT status register. For RT mode, the
result of the self-test may be communicated to the bus controller
via bit 8 of the RT BIT word ("0" = pass, "1" = fail).
HOST PROCESSOR INTERFACE
The Enhanced Mini-ACE/µ-ACE supports a wide variety of proces-
sor interface configurations. These include shared RAM and DMA
configurations, straightforward interfacing for 16-bit and 8-bit buses,
support for both non-multiplexed and multiplexed address/data
buses, non-zero wait mode for interfacing to a processor
address/data buses, and zero wait mode for interfacing (for example)
to microcontroller I/O ports. In addition, with respect to the ACE/Mini-
ACE, the Enhanced Mini-ACE provides two major improvements: (1)
reduced maximum host access time for shared RAM mode; and (2)
increased maximum DMA grant time for the transparent/DMA mode.
Assuming that the protocol self-test passes, all of the register
and shared RAM locations will be restored to their state prior to
the self-test, with the exception of the 60 RAM address locations
0342-037D and the TIME TAG REGISTER. Note that for RT
mode, these locations map to the illegalization lookup table for
"broadcast transmit subaddresses 1 through 30" (non-mode
code subaddresses). Since MIL-STD-1553 does not define
these as valid command words, this section of the illegalization
lookup table is normally not used during RT operation. The TIME
TAG REGISTER will continue to increment during the self-test.
The Enhanced Mini-ACE/µ-ACE's maximum host holdoff time
(time prior to the assertion of the READYD handshake signal)
has been significantly reduced. For ACE/Mini-ACE, this maxi-
mum holdoff time is 17 internal word transfer cycles, resulting in
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an overall holdoff time of approximately 4.6 µs, using a 16 MHz
clock. By comparison, using the Enhanced Mini-ACE/µ-ACE's
ENHANCED CPU ACCESS feature, this worst-case holdoff time
is reduced significantly, to a single internal transfer cycle. For
example, when operating the Enhanced Mini-ACE/µ-ACE in its
16-bit buffered, non-zero wait configuration with a 16 MHz clock
input, this results in a maximum overall host transfer cycle time
of 632 ns for a read cycle, or 570 ns for a write cycle.
By far, the most commonly used processor interface configura-
tion is the 16-bit buffered, non-zero wait mode.This configuration
may be used to interface between 16-bit or 32-bit microproces-
sors and an Enhanced Mini-ACE/µ-ACE. In this mode, only the
Enhanced Mini-ACE/µ-ACE's internal 4K or 64K words of inter-
nal RAM are used for storing 1553 message data and associat-
ed "housekeeping" functions. That is, in this configuration, the
Enhanced Mini-ACE/µ-ACE will never attempt to access memo-
ry on the host bus.
In addition, when using the ACE or Mini-ACE in the transpar-
ent/DMA configuration, the maximum request-to-grant time,
which occurs prior to an RT start-of-message sequence, is 4.0
µs with a 16 MHz clock, or 3.5 µs with a 12 MHz clock. For the
Enhanced Mini-ACE/µ-ACE functioning as a MIL-STD-1553B
RT, this time has been increased to 8.5 µs at 10 MHz, 9 µs at 12 MHz,
10 µs at 16 MHz, and 10.5 µs at 20MHz. This provides greater
flexibility, particularly for systems in which a host has to arbitrate
among multiple DMA requestors.
FIGURE 12 illustrates a generic connection diagram between a
16-bit (or 32-bit) microprocessor and an Enhanced Mini-ACE/µ-
ACE for the 16-bit buffered configuration, while FIGURES 13 and
14, and associated tables illustrate the processor read and write
timing respectively.
+5V (3.3V)
(NOTE 5)
CLK IN
CLOCK
OSCILLATOR
D15-D0
55 Ω
TX/RXA
N/C
A15-A12
CH. A
TX/RXA
A11-A0
55 Ω
ADDR_LAT
CPU ADDRESS LATCH (NOTE 1)
TRANSPARENT/BUFFERED
+5V
16/8_BIT
55 Ω
TRIGGER_SEL
+5V
TX/RXB
TX/RXB
N/C
N/C
MSB/LSB
CH. B
(NOTE 2)
POLARITY_SEL
Enhanced
Mini-ACE/
µ-ACE
(NOTE 3)
ZERO_WAIT
HOST
55 Ω
SELECT
ADDRESS
DECODER
MEM/REG
RD/WR
RD/WR
STRBD
CPU STROBE
RTAD4-RTAD0
RT
ADDRESS,
PARITY
CPU ACKNOWLEDGE
READYD
TAG_CLK
(NOTE 4)
RTADP
+5V
RESET
MSTCLR
SSFLAG/EXT_TRIG
INT
CPU INTERRUPT REQUEST
NOTES:
1. CPU ADDRESS LATCH SIGNAL PROVIDED BY
3. ZERO_WAIT SHOULD BE STRAPPED TO
LOGIC "1" FOR NON-ZERO WAIT INTERFACE
AND TO LOGIC "0" FOR ZERO WAIT INTERFACE.
4. CPU ACKNOWLEDGE PROCESSOR INPUT ONLY
FOR NON-ZERO WAIT TYPE OF INTERFACE.
PROCESSORS WITH MULTIPLEXED ADDRESS/DATA
BUSES. FOR PROCESSORS WITH NON-MULTIPLEXED
ADDRESS AND DATA BUSSES, ADDR_LAT SHOULD BE
CONNECTED TO +5V.
2. IF POLARITY_SEL = "1", RD/WR IS HIGH TO READ,
LOW TO WRITE.
5. +3.3V POWER FOR BU-61743 / 61843 / 61864 ONLY
IF POLARITY_SEL = "0", RD/WR IS LOW TO READ,
HIGH TO WRITE.
FIGURE 12. HOST PROCESSOR INTERFACE - 16-BIT BUFFERED CONFIGURATION
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t5
CLOCK IN
t1
SELECT
(Note 2,7)
t6
t2
t18
t14
STRBD
(Note 2)
VALID
MEM/REG
(Note 3,4,7)
t7
t8
t3
RD/WR
(Note 4,5)
t11
IOEN
(Note 2,6)
t15
t13
READYD
t4
(Note 6)
t12
t9
t19
t10
VALID
A15-A0
(Note 7,8,9)
t16
VALID
D15-D0
(Note 6)
t17
FIGURE 13. CPU READING RAM / REGISTER (16-BIT BUFFERED, NONZERO WAIT)
NOTES:
1. For the 16-bit buffered nonzero wait configuration, TRANSPARENT/BUFFERED must be connected to logic "0". ZERO_WAIT and DTREQ / 16/8
must be connected to logic "1". The inputs TRIGGER_SEL and MSB/LSB may be connected to either +5V or ground.
2. SELECT and STRBD may be tied together. IOEN goes low on the first rising CLK edge when SELECT • STRBD is sampled low (satisfying t1)
and the Enhanced Mini-ACE/µ-ACE's protocol/memory management logic is not accessing the internal RAM. When this occurs, IOEN goes low,
starting the transfer cycle. After IOEN goes low, SELECT may be released high.
3. MEM/REG must be presented high for memory access, low for register access.
4. MEM/REG and RD/WR are buffered transparently until the first falling edge of CLK after IOEN goes low. After this CLK edge, MEM/REG and
RD/WR become latched internally.
5. The logic sense for RD/WR in the diagram assumes that POLARITY_SEL is connected to logic "1". If POLARITY_SEL is connected to logic "0",
RD/WR must be asserted low to read.
6. The timing for IOEN, READYD and D15-D0 assumes a 50 pf load. For loading above 50 pf, the validity of IOEN, READYD, and D15-D0 is delayed
by an additional 0.14 ns/pf typ, 0.28 ns/pf max.
7. The timing for A15-A0, MEM/REG and SELECT assumes that ADDR-LAT is connected to logic "1". Refer to Address Latch timing for additional
details.
8. The address bus A15-A0 is internally buffered transparently until the first rising edge of CLK after IOEN goes low. After this CLK edge, A15-A0
become latched internally.
9. Setup time given for use in worst case timing calculations. None of the Enhanced Mini-ACE/µ-ACE input signals are required to be synchronized
to the system clock. When SELECT and STRBD do not meet the setup time of t1, but occur during the setup window of an internal flip-flop, an
additional clock cycle will be inserted between the falling clock edge that latches MEM/REG and RD/WR and the rising clock edge that latches
the Address (A15-A0). When this occurs, the delay from IOEN falling to READYD falling (t11) increases by one clock cycle and the address hold
time (t10) must be increased be one clock cycle.
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TABLE FOR FIGURE 13. CPU READING RAM OR REGISTERS
(SHOWN FOR 16-BIT, BUFFERED, NONZERO WAIT MODE)
5V LOGIC
3.3V LOGIC
UNITS
REF
DESCRIPTION
NOTES
MIN TYP MAX MIN TYP MAX
t1 SELECT and STRBD low setup time prior to clock rising edge
2, 9
10
15
ns
t2
SELECT and STRBD low to IOEN low (uncontended access @ 20 MHz)
2, 6
2, 6
2, 6
2, 6
2, 6
2, 6
2, 6
2, 6
2, 6
2, 6
2, 6
2, 6
100
3.6
105
2.2
ns
µs
ns
ns
µs
ns
ns
µs
ns
ns
µs
ns
(contended access, with ENHANCED CPU ACCESS = “0” @ 20 MHz)
(contended access, with ENHANCED CPU ACCESS = “1” @ 20 MHz)
(uncontended access @ 16 MHz)
350
112
4.6
355
117
2.8
(contended access, with ENHANCED CPU ACCESS = “0” @ 16 MHz)
(contended access, with ENHANCED CPU ACCESS = “1” s @ 16 MHz)
(uncontended access @ 12 MHz)
425
133
6.0
430
138
3.7
(contended access, with ENHANCED CPU ACCESS = “0” @ 12 MHz)
(contended access, with ENHANCED CPU ACCESS = “1” @ 12 MHz)
(uncontended access @ 10 MHz)
550
150
7.2
555
155
4.4
(contended access, with ENHANCED CPU ACCESS = “0” @ 10 MHz)
(contended access, with ENHANCED CPU ACCESS = “1” @ 10 MHz)
650
655
t3
Time for MEM/REG and RD/WR to become valid following SELECT and STRBD
low(@ 20 MHz)
3, 4, 5, 7
3, 4, 5, 7
3, 4, 5, 7
3, 4, 5, 7
15
21
32
40
10
16
27
35
ns
ns
ns
ns
@ 16 MHz
@ 12 MHz
@ 10 MHz
t4
Time for Address to become valid following SELECT and STRBD low (@ 20 MHz)
17
30
50
67
12
25
45
62
ns
ns
ns
ns
@ 16 MHz
@ 12 MHz
@ 10 MHz
t5 CLOCK IN rising edge delay to IOEN falling edge
t6 SELECT hold time following IOEN falling
6
2
40
40
ns
ns
ns
ns
ns
ns
0
0
t7 MEM/REG, RD/WR setup time prior to CLOCK IN falling edge
t8 MEM/REG, RD/WR hold time following CLOCK IN falling edge
t9 Address valid setup time prior to CLOCK IN rising edge
t10 Address hold time following CLOCK IN rising edge
3, 4, 5, 7 10
3, 4, 5, 7 30
15
30
35
30
7, 8
30
30
7, 8, 9
t11
IOEN falling delay to READYD falling (@ 20 MHz)
6, 9
6, 9
6, 9
6, 9
135 150 165 135 150 165
170 187.5 205 170 187.5 205
235 250 265 235 250 265
285 300 315 285 300 315
ns
ns
ns
ns
@ 16 MHz
@ 12 MHz
@ 10 MHz
t12
Output Data valid prior to READYD falling (@ 20 MHz)
6
6
6
6
21
33
54
71
11
23
44
61
ns
ns
ns
ns
@ 16 MHz
@ 12 MHz
@ 10 MHz
t13 CLOCK IN rising edge delay to READYD falling
t14 READYD falling to STRBD rising release time
t15 STRBD rising edge delay to IOEN rising edge and READYD rising edge
t16 Output Data hold time following STRBD rising edge
t17 STRBD rising delay to output data tri-state
6
40
∞
40
∞
ns
ns
ns
ns
ns
ns
ns
6
30
40
0
0
0
0
40
40
40
t18 STRBD high hold time from READYD rising
t19 CLOCK IN rising edge delay to output data valid
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t6
CLOCK IN
t1
SELECT
(Note 2,7)
t7
t16
t2
t18
STRBD
(Note 2)
VALID
MEM/REG
(Note 3,4,7)
t8
t9
t3
RD/WR
(Note 4,5)
t14
IOEN
(Note 2,6)
t15
t17
READYD
t4
t5
(Note 6)
t10
t12
t13
VALID
A15-A0
(Note 7,8,9,10)
t11
VALID
D15-D0
(Note 9,10)
FIGURE 14. CPU WRITING RAM / REGISTER (16-BIT BUFFERED, NONZERO WAIT)
NOTES:
1. For the 16-bit buffered nonzero wait configuration TRANSPARENT/BUFFERED must be connected to logic "0", ZERO_WAIT and DTREG / 16/8
must be connected to logic "1". The inputs TRIGGER_SEL and MSB/LSB may be connected to either +5V or ground.
2. SELECT and STRBD may be tied together. IOEN goes low on the first rising CLK edge when SELECT • STRBD is sampled low (satisfying t1)
and the Enhanced Mini-ACE/µ-ACE's protocol/memory management logic is not accessing the internal RAM. When this occurs, IOEN goes low,
starting the transfer cycle. After IOEN goes low, SELECT may be released high.
3. MEM/REG must be presented high for memory access, low for register access.
4. MEM/REG and RD/WR are buffered transparently until the first falling edge of CLK after IOEN goes low. After this CLK edge, MEM/REG and
RD/WR become latched internally.
5. The logic sense for RD/WR in the diagram assumes that POLARITY_SEL is connected to logic "1". If POLARITY_SEL is connected to logic "0",
RD/WR must be asserted high to write.
6. The timing for the IOEN and READYD outputs assume a 50 pf load. For loading above 50 pf, the validity of IOEN and READYD is delayed by an
additional 0.14 ns/pf typ, 0.28 ns/pf max.
7. The timing for A15-A0, MEM/REG, and SELECT assumes that ADDR-LAT is connected to logic "1". Refer to Address Latch timing for additional
details.
9. The address bus A15-A0 and data bus D15-D0 are internally buffered transparently until the first rising edge of CLK after IOEN goes low. After
this CLK edge, A15-A0 and D15-D0 become latched internally.
10 Setup time given for use in worst case timing calculations. None of the Enhanced Mini-ACE/µ-ACE input signals are required to be synchronized
to the system clock. When SELECT and STRBD do not meet the setup time of t1, but occur during the setup time of an internal flip-flop, an addi-
tional clock cycle may be inserted between the falling clock edge that latches MEM/REG and RD/WR and the rising clock edge that latches the
address (A15-A0) and data (D15-D0). When this occurs, the delay from IOEN falling to READYD falling (t14) increases by one clock cycle and the
address and data hold time (t12 and t13) must be increased by one clock.
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TABLE FOR FIGURE 14. CPU WRITING RAM OR REGISTERS
(SHOWN FOR 16-BIT, BUFFERED, NONZERO WAIT MODE)
5V LOGIC
3.3V LOGIC
REF
DESCRIPTION
NOTES
UNITS
MIN TYP MAX MIN TYP MAX
t1 SELECT and STRBD low setup time prior to clock rising edge
2, 10
10
15
ns
t2
SELECT and STRBD low to IOEN low (uncontended access @ 20 MHz)
2, 6
2, 6
2, 6
2, 6
2, 6
2, 6
2, 6
2, 6
2, 6
2, 6
2, 6
2, 6
100
3.6
105
2.2
ns
µs
ns
ns
µs
ns
ns
µs
ns
ns
µs
ns
(contended access, with ENHANCED CPU ACCESS = “0” @ 20 MHz)
(contended access, with ENHANCED CPU ACCESS = “1” @ 20 MHz)
(uncontended access @ 16 MHz)
350
112
4.6
355
117
2.8
(contended access, with ENHANCED CPU ACCESS = “0” @ 16 MHz)
(contended access, with ENHANCED CPU ACCESS = “1” @ 16 MHz)
(uncontended access @ 12 MHz)
425
133
6.0
430
138
3.7
(contended access, with ENHANCED CPU ACCESS = “0” @ 12 MHz)
(contended access, with ENHANCED CPU ACCESS = “1” @ 12 MHz)
(uncontended access @ 10 MHz)
550
150
7.2
555
155
4.4
(contended access, with ENHANCED CPU ACCESS = “0” @ 10 MHz)
(contended access, with ENHANCED CPU ACCESS = “1” @ 10 MHz)
650
655
t3
Time for MEM/REG and RD/WR to become valid following SELECT and STRBD
low(@ 20 MHz)
3, 4, 5, 7
3, 4, 5, 7
3, 4, 5, 7
3, 4, 5, 7
15
21
32
40
10
16
27
35
ns
ns
ns
ns
@ 16 MHz
@ 12 MHz
@ 10 MHz
t4
Time for Address to become valid following SELECT and STRBD low (@ 20 MHz)
17
30
50
67
12
25
45
62
ns
ns
ns
ns
@ 16 MHz
@ 12 MHz
@ 10 MHz
t5
Time for data to become valid following SELECT and STRBD low (@ 20 MHz)
37
50
70
87
40
32
45
65
82
40
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
@ 16 MHz
@ 12 MHz
@ 10 MHz
t6 CLOCK IN rising edge delay to IOEN falling edge
t7 SELECT hold time following IOEN falling
t8 MEM/REG, RD/WR setup time prior to CLOCK IN falling edge
t9 MEM/REG, RD/WR setup time following CLOCK IN falling edge
t10 Address valid setup time prior to CLOCK IN rising edge
t11 Data valid setup time prior to CLOCK IN rising edge
t12 Address valid hold time prior to CLOCK IN rising edge
t13 Data valid hold time following CLOCK IN rising edge
6
2
0
0
3, 4, 5, 7
3, 4, 5, 7
7, 8
10
30
30
10
30
10
15
35
35
15
30
15
7, 8, 9
9
t14
IOEN falling delay to READYD falling @ 20 MHz
6, 9
6, 9
6, 9
6, 9
6
85
100 115 85 100 115
ns
ns
ns
ns
ns
ns
ns
ns
@ 16 MHz
110 125 140 110 125 140
152 167 182 152 167 182
185 200 215 185 200 215
@ 12 MHz
@ 10 MHz
t15 CLOCK IN rising edge delay to READYD falling
t16 READYD falling to STRBD rising release time
t17 STRBD rising delay to IOEN rising edge and READYD rising edge
t18 STRBD high hold time from READYD rising
40
∞
40
∞
6
30
40
10
10
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INTERFACE TO MIL-STD-1553 BUS
FIGURE 15 illustrates the interface between the various versions
of the Enhanced Mini-ACE/µ-ACE series and a MIL-STD-1553
bus. Connections for both direct (short stub) and transformer
(long stub) coupling, as well as the nominal peak-to-peak voltage
levels at various points (when transmitting), are indicated in the
diagram.
DATA
BUS
Z0
SHORT STUB
(DIRECT COUPLED)
(1:2.5)
1 FT MAX
55 Ω
TX/RX
11.2 Vpp
TX/RX
7 Vpp
28 Vpp
Enhanced
Mini-ACE/µ-ACE
55 Ω
ISOLATION
TRANSFORMER
LONG STUB
(TRANSFORMER
COUPLED)
OR
(1:1.79)
(1:1.41)
0.75 Z0
28 Vpp
20 FT MAX
20 Vpp
11.2 Vpp
7 Vpp
Enhanced
Mini-ACE/µ-ACE
0.75 Z0
COUPLING
TRANSFORMER
ISOLATION
TRANSFORMER
Z0
NOTES: 1. Z 0 = 70 TO 85 OHMS
2. NOMINAL VOLTAGE
LEVELS SHOWN
FIGURE 15. ENHANCED MINIATURE ADVANCED COMMUNICATIONS
ENGINE INTERFACE TO MIL-STD-1553 BUS
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TRANSFORMERS
winding. This inductance must be less than 6.0 µH. Similarly, if
the other side of the primary is shorted to the primary center-tap,
the inductance measured across the “secondary” (stub side)
winding must also be less than 6.0 µH.
In selecting isolation transformers to be used with the Enhanced
Mini-ACE/µ-ACE, there is a limitation on the maximum amount of
leakage inductance. If this limit is exceeded, the transmitter rise
and fall times may increase, possibly causing the bus amplitude
to fall below the minimum level required by MIL-STD-1553. In
addition, an excessive leakage imbalance may result in a trans-
former dynamic offset that exceeds 1553 specifications.
The difference between these two measurements is the
“differential” leakage inductance.This value must be less than 1.0 µH.
Beta Transformer Technology Corporation (BTTC), a subsidiary
of DDC, manufactures transformers in a variety of mechanical
configurations with the required turns ratios of 1:2.5 direct cou-
pled, and 1:1.79 transformer coupled. TABLE 46 provides a list-
ing of many of these transformers.
The maximum allowable leakage inductance is 6.0 µH, and
is measured as follows:
The side of the transformer that connects to the Enhanced
Mini-ACE/µ-ACE is defined as the “primary” winding. If one side
of the primary is shorted to the primary center-tap, the induc-
tance should be measured across the “secondary” (stub side)
For further information, contact BTTC at 631-244-7393 or at
www.bttc-beta.com.
TABLE 46. BTTC TRANSFORMERS FOR USE WITH ENHANCED MINI-ACE
TRANSFORMER CONFIGURATION
BTTC PART NO.
B-3067
B-3226
Single epoxy transformer, through-hole, 0.625" X 0.625", 0.250" max height
Single epoxy transformer, through-hole, 0.625" X 0.625", 0.220" max height.
May be used with BU-6XXXXX4 versions of the Enhanced Mini-ACE.
B-3818
Single epoxy transformer, flat pack, 0.625" X 0.625", 0.275" max height
Single epoxy transformer, surface mount, 0.625" X 0.625", 0.275" max height
B-3231
B-3227
Single epoxy transformer, surface mount, hi-temp solder, 0.625" X 0.625", 0.220" max height.
May be used with BU-6XXXXX4 versions of the Enhanced Mini-ACE
B-3819
Single epoxy transformer, flat pack, 0.625" X 0.625", 0.150" max height
Single epoxy transformer, surface mount, 0.625" X 0.625", 0.150" max height
LPB-5014
LPB-5015
B-3229
Single epoxy transformer, through hole, transformer coupled only, 0.500" X 0.350", 0.250" max height
Dual epoxy transformer, twin stacked, 0.625" X 0.625", 0.280" max height
TST-9007
TST-9017
TST-9027
B-3300
Dual epoxy transformer, twin stacked, surface mount, 0.625" X 0.625", 0.280" max height
Dual epoxy transformer, twin stacked, flat pack, 0.625" X 0.625", 0.280" max height
Dual epoxy transformer, side by side, through-hole, 0.930" X 0.630", 0.155" max height
Dual epoxy transformer, side by side, flat pack, 0.930" X 0.630", 0.155" max height
Dual epoxy transformer, side by side, surface mount, 0.930" X 0.630", 0.155" max height
Dual epoxy transformer, side by side, surface mount, 1.410" X 0.750", 0.130" max height
Single metal transformer, hermetically sealed, flat pack, 0.630" X 0.630", 0.175" max height
Single metal transformer, hermetically sealed, surface mount, 0.630" X 0.630", 0.175" max height
B-3261
B-3310
DLP-7115 (see note 3)
HLP-6014
HLP-6015
DLP-7014
SLP-8007
SLP-8024
NOT RECOMMENDED
Notes:
1. For the BU-6XXXXX4 versions of the Enhanced Mini-ACE, which include the McAir-compatible transceivers, only the B-3818 or B-3819 transformers (shown in bold
in the table) may be used.
2. For the BU-6XXXXX3 versions of the Enhanced Mini-ACE/µ-ACE with -1553B transceivers, any of the transformers listed in the table may be used.
3. DLP-7115 operates to +85°C max. All other transformers listed operate to +130°C max.
Data Device Corporation
www.ddc-web.com
BU-6174X/6184X/6186X
web rev G2-03/03-0
41
THERMAL AND MECHANICAL MANAGEMENT FOR
µ-ACE (BGA PACKAGE)
through thermal vias as shown in FIGURE 17. Operation without
an adequate ground/thermal plane is not recommended and
extended exposure to these conditions may affect device relia-
bility.
Ball Grid Array (BGA) components necessitate that thermal
management issues be considered early in the design stage for
MIL-STD-1553 terminals. This is especially true if high transmit-
ter duty cycles are expected.The temperature range specified for
DDC's µ-ACE device refers to the temperature at the ball, not the
case.
The purpose of this ground/thermal plane is to conduct the heat
being generated by the transceivers within the package and con-
duct this heat away from the µ-ACE. In general, the circuit ground
and thermal (chassis) ground are not the same ground plane. It
is acceptable for these six balls to be directly soldered to a
ground plane but it must be located in close physical and thermal
proximity ("0.003" pre-preg layer recommended) to the thermal
plane (See FIGURE 17).
All µ-ACE devices incorporate six package connections (E2, F2,
G2, U13, U14, and U15), which perform the dual function of cir-
cuit ground and thermal heat sink. Refer to FIGURE 16 for con-
nection locations. It is mandatory that these six balls be con-
nected to a circuit ground plane (a circuit trace is insufficient)
18
17
16
15
14
13
12
11
10
9
(USA)
8
7
6
S/N
D/C
5
4
3
2
1
V
U T R P N M L K J H G F E D C B A
ESD and Pin 1 Identifier
BOTTOM VIEW
TOP VIEW
Notes:
1) E2, F2, G2, U13, U14 and U15 must be connected
to a thermal plane to maintain recommended operating temperature.
FIGURE 16. THERMAL BALL LOCATIONS FOR µ-ACE (BGA PACKAGES)
Thermal Balls
(Two groups: E2, F2, G2;
and U13, U14, U15)
µ-ACE
Detail A
(BGA Package)
Top (component)
Layer
Detail A
Signal Layer
0.0394"
Pitch
0.022"
dia.
PC Board
Thermal Vias
Prepreg,
Approx. 0.003" thick
Signal Ground
Plane
Thermal Plane
FIGURE 17. THERMAL DESIGN FOR µ-ACE (BGA PACKAGES)
Data Device Corporation
www.ddc-web.com
BU-6174X/6184X/6186X
web rev G2-03/03-0
42
SIGNAL DESCRIPTIONS BY FUNCTIONAL GROUPS
TABLE 47. POWER AND GROUND
BU-6186XFX/GX
BU-6184XFX/GX
BU-6174XFX/GX
BU-61860BX
BU-61840BX
BU-61740BX
SIGNAL NAME
DESCRIPTION
PIN
72
BALL
+5V Vcc CH A
+5V Vcc CH B
E1, F1, G1
V13, V14, V15
Channel A transceiver power.
Channel B transceiver power.
20
+5V / +3.3V Logic
37
A8, A16, B8, L1, Logic power. For BU-61864/61843/61743, this pin must be connected to +3.3V.
L2, L17, L18, B16 For BU-61865/61845/61745, this pin must be connected to +5V.
For BU-61740/61840/61860BX, these eight balls may connect to either +5V or +3.3V.
Refer to VDD_LOW (ball V2) signal information to determine voltage selection options.
+5V RAM
26
(BU-6186XFX/GX
only)
U3, V3
(BU-61860BX
only)
For BU-61864FX/GX, BU-61865FX/GX, and BU-61860BX this pin must be connected
to +5V.
Note: for BU-6184XFX/GX and BU-6174XFX/GX, this pin assumes the function
UPADDREN.
Note: for BU-61740BX and BU-61840BX, these two balls are not connected (N/C).
Ground
17, 18, 19, 65, 67 A9, B9, C17, C18, Ground.
K17, K18, U4, U9,
V1, V4
Ground/Thermal
VDD_LOW (I)
-
-
E2, F2, G2, U13, Ground/Thermal connections. See Thermal and Mechanical Management Section for
U14, U15
important user information.
V2
Input that selects logic threshold voltage. Set to logic "0" for 3.3V threshold and to +5V
(logic "1") for 5V threshold. Must match “+5V/+3V Logic” input voltage.
TABLE 48. 1553 ISOLATION TRANSFORMER
BU-6186XFX/GX
BU-6184XFX/GX
BU-6174XFX/GX
BU-61860BX
BU-61840BX
BU-61740BX
SIGNAL NAME
DESCRIPTION
PIN
5
BALL
D1, D2
TX/RX-A (I/O)
TX/RX-A (I/O)
TX/RX-B (I/O)
TX/RX-B (I/O)
Analog Transmit/Receive Input/Outputs. Connect directly to 1553 isolation transformers.
7
H1, H2
13
16
U12, V12
U16, V16
Data Device Corporation
www.ddc-web.com
BU-6174X/6184X/6186X
web rev G2-03/03-0
43
TABLE 49. DATA BUS
BU-6186XFX/GX
BU-6184XFX/GX
BU-6174XFX/GX
BU-61860BX
BU-61840BX
BU-61740BX
SIGNAL NAME
DESCRIPTION
PIN
53
50
48
49
52
54
51
46
47
36
45
39
44
43
38
42
BALL
D17
D18
J17
D15 (MSB)
D14
D13
D12
D11
D10
D9
16-bit bi-directional data bus. This bus interfaces the host processor to the Enhanced
Mini-ACE/µ-ACE's internal registers and internal RAM. In addition, in transparent
mode, this bus allows data transfers to take place between the internal protocol/memo-
ry management logic and up to 64K x 16 of external RAM. Most of the time, the out-
puts for D15 through D0 are in the high impedance state. They drive outward in the
buffered or transparent mode when the host CPU reads the internal RAM or registers.
E18
E17
N17
N18
F18
F17
J18
Also, in the transparent mode, D15-D0 will drive outward (towards the host) when the
protocol/management logic is accessing (either reading or writing) internal RAM, or
writing to external RAM. In the transparent mode, D15-D0 drives inward when the CPU
writes internal registers or RAM, or when the protocol/memory management logic
reads external RAM.
D8
D7
D6
D5
H17
M18
G17
G18
M17
H18
D4
D3
D2
D1
D0 (LSB)
Data Device Corporation
BU-6174X/6184X/6186X
www.ddc-web.com
44
web rev G2-03/03-0
TABLE 50. PROCESSOR ADDRESS BUS
BU-6186XFX/GX
BU-6184XFX/GX
BU-6174XFX/GX
BU-61860BX
BU-61840BX
BU-61740BX
SIGNAL NAME
DESCRIPTION
64K RAM
4K RAM
PIN
BALL
A15
A15 / CLK_SEL_1
66
A11
For BU-6186X (64K RAM versions), this signal is always config-
ured as address line A15 (MSB). Refer to the description for A11-
A0 below.
For BU-6184X/6174X (4K RAM versions), if UPADDREN is con-
nected to logic "1", this signal operates as address line A15.
For BU-6184X/6174X (4K RAM versions), if UPADDREN is con-
nected to logic "0", this signal operates as CLK_SEL_1. In this
case, A15/CLK_SEL_1 and A14/CLK_SEL_0 are used to select
the Enhanced Mini-ACE/µ-ACE's clock frequency, as follows:
Clock
CLK_SEL_1 CLK_SEL_0
Frequency
10 MHz
20 MHz
12 MHz
16 MHz
0
0
1
1
0
1
0
1
A14
A14 / CLK_SEL_0
8
B10
For BU-6186X (64K RAM versions), this signal is always config-
ured as address line A14. Refer to the description of A11-A0
below.
For BU-6184X/6174X (4K RAM versions), if UPADDREN is con-
nected to logic "1", this signal operates as A14.
For BU-6184X/6174X (4K RAM versions), if UPADDREN is con-
nected to logic "0", then this signal operates as CLK_SEL_1. In
this case, CLK_SEL_1 and CLK_SEL_0 are used to select the
Enhanced Mini-ACE/µ-ACE's clock frequency, as defined in the
description for A15/CLK_SEL1 above.
A13
A13 / Vcc -LOGIC
71
A10
For BU-6186X (64K RAM versions), this signal is always config-
ured as address line A13. Refer to the description for A11-A0
below.
For BU-6184X/6174X (4K RAM versions), if UPADDREN is con-
nected to logic "1", this signal operates as A13.
For BU-6184X/6174X (4K RAM versions), if UPADDREN is con-
nected to logic "0", then this signal MUST be connected to
+5V/+3.3V-LOGIC (logic "1").
Data Device Corporation
www.ddc-web.com
BU-6174X/6184X/6186X
web rev G2-03/03-0
45
TABLE 50. PROCESSOR ADDRESS BUS (CONT.)
BU-6186XFX/GX
BU-6184XFX/GX
BU-6174XFX/GX
BU-61860BX
BU-61840BX
BU-61740BX
SIGNAL NAME
DESCRIPTION
64K RAM
4K RAM
PIN
BALL
A12
A12 / RTBOOT
70
A7
For BU-6186X (64K RAM versions), this signal is always config-
ured as address line A12. Refer to the description for A11-A0
below.
For BU-6184X/6174X (4K RAM versions), if UPADDREN is con-
nected to logic "1", this signal operates as A12.
For BU-6184X/6174X (4K RAM versions), if UPADDREN is con-
nected to logic "0", then this signal functions as RTBOOT. If
RTBOOT is connected to logic "0", the Enhanced Mini-ACE/µ-ACE
will initialize in RT mode with the Busy status word bit set following
power turn-on. If RTBOOT hardwired to logic "1", the Enhanced
Mini-ACE/µ-ACE will initialize in either Idle mode (for an RT-only
part), or in BC mode (for a BC/RT/MT part).
Lower 12 bits of 16-bit bi-directional address bus. In both the
buffered and transparent modes, the host CPU accesses the
Enhanced Mini-ACE/µ-ACE registers and internal RAM by means
of A11 - A0 (4K version). For the 64K versions, A15 - A12 are also
used for this purpose.
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
3
B7
A6
B6
B5
A5
A4
B4
A3
B3
A2
B1
4
69
6
11
22
68
9
In buffered mode, A12-A0 (or A15-A0) are inputs only. In the trans-
parent mode, A12-A0 (or A15-A0) are inputs during CPU accesses
and become outputs, driving outward (towards the CPU) when the
1553 protocol/memory management logic accesses up to 64K
words of external RAM.
10
12
27
In transparent mode, the address bus is driven outward only when
the signal DTACK is low (indicating that the Enhanced Mini-ACE/µ-
ACE has control of the RAM interface bus) and IOEN is high, indi-
cating a non-host access. Most of the time, including immediately
after power turn-on, A12-A0 (or A15-A0) will be in high impedance
(input) state.
A0 (LSB)
A0 (LSB)
15
A1
Data Device Corporation
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web rev G2-03/03-0
46
TABLE 51. PROCESSOR INTERFACE CONTROL
BU-6186XFX/GX
BU-6184XFX/GX
BU-6174XFX/GX
BU-61860BX
BU-61840BX
BU-61740BX
SIGNAL NAME
DESCRIPTION
PIN
BALL
SELECT (I)
STRBD (I)
61
B12
Generally connected to a CPU address decoder output to select the Enhanced Mini-
ACE/µ-ACE for a transfer to/from either RAM or register.
62
63
B14
A12
Strobe Data. Used in conjunction with SELECT to initiate and control the data transfer
cycle between the host processor and the Enhanced Mini-ACE/µ-ACE. STRBD must
be asserted low through the full duration of the transfer cycle.
RD / WR
Read/Write. For a host processor access, RD/WR selects between reading and writing.
In the 16-bit buffered mode, if POL_SEL is logic "0, then RD/WR should be low (logic
“0") for read accesses and high (logic "1") for write accesses. If POL_SEL is logic "1",
or the interface is configured for a mode other than 16-bit buffered mode, then RD/WR
is high (logic "1") for read accesses and low (logic "0") for write accesses.
ADDR_LAT(I) /
MEMOE (O)
14
V8
Memory Output Enable or Address Latch.
In buffered mode, the ADDR_LAT input is used to configure the buffers for A15-A0,
SELECT, MEM/REG, and MSB/LSB (for 8-bit mode only) in latched mode (when low)
or transparent mode (when high). That is, the Enhanced Mini-ACE/µ-ACE's internal
transparent latches will track the values on A15-A0, SELECT, MEM/REG, and
MSB/LSB when ADDR_LAT is high, and latch the values when ADDR_LAT goes low.
In general, for interfacing to processors with a non-multiplexed address/data bus,
ADDR_LAT should be hardwired to logic "1". For interfacing to processors with a multi-
plexed address/data bus, ADDR_LAT should be connected to a signal that indicates a
valid address when ADDR_LAT is logic "1".
In transparent mode, MEMOE output signal is used to enable data outputs for external
RAM read cycles (normally connected to the OE input signal on external RAM chips).
ZEROWAIT (I) /
MEMWR (O)
23
U8
Memory Write or Zero Wait. In buffered mode, input signal (ZEROWAIT) used to select
between the zero wait mode (ZEROWAIT = “0") and the non-zero wait mode
(ZEROWAIT = "1").
In transparent mode, active low output signal (MEMWR) asserted low during memory
write transfers to strobe data into external RAM (normally connected to the WR input
signal on external RAM chips).
16 / 8 (I) /
DTREQ (O)
24
64
V7
U6
Data Transfer Request or Data Bus Select. In buffered mode, input signal 16/8 used to
select between the 16 bit data transfer mode (16/8= "1") and the 8-bit data transfer
mode (16/8 = "0").
In transparent mode (16-bit only), active low level output signal DTREQ used to
request access to the processor/RAM interface bus (address and data buses).
MSB / LSB (I) /
DTGRT (I)
Data Transfer Grant or Most Significant Byte/Least Significant Byte.
In 8-bit buffered mode, input signal (MSB/LSB) used to indicate which byte is currently
being transferred (MSB or LSB). The logic sense of MSB/LSB is controlled by the
POL_SEL input. MSB/LSB is not used in the 16-bit buffered mode.
In transparent mode, active low input signal (DTGRT) asserted in response to the
DTREQ output to indicate that control of the external processor/RAM bus has been
transferred from the host processor to the Enhanced Mini-ACE/µ-ACE.
Data Device Corporation
BU-6174X/6184X/6186X
www.ddc-web.com
47
web rev G2-03/03-0
TABLE 51. PROCESSOR INTERFACE CONTROL (CONT.)
BU-6186XFX/GX
BU-6184XFX/GX
BU-6174XFX/GX
BU-61860BX
BU-61840BX
BU-61740BX
SIGNAL NAME
DESCRIPTION
PIN
BALL
POL_SEL (I) /
DTACK (O)
29
U7
Data Transfer Acknowledge or Polarity Select. In 16-bit buffered mode, if POL_SEL is
connected to logic "1", RD/WR should be asserted high (logic "1") for a read operation
and low (logic "0") for a write operation. In 16-bit buffered mode, if POL_SEL is con-
nected to logic "0", RD/WR should be asserted low (logic "0") for a read operation and
high (logic "1") for a write operation.
In 8-bit buffered mode (TRANSPARENT/ BUFFERED = "0" and 16/8 = "0"), POL_SEL
input signal used to control the logic sense of the MSB/LSB signal. If POL_SEL is con-
nected to logic "0", MSB/LSB should be asserted low (logic "0") to indicate the transfer
of the least significant byte and high (logic "1") to indicate the transfer of the most sig-
nificant byte. If POL_SEL is connected to logic "1", MSB/LSB should be asserted high
(logic "1") to indicate the transfer of the least significant byte and low (logic "0") to indi-
cate the transfer of the most significant byte.
In transparent mode, active low output signal (DTACK) used to indicate acceptance of
the processor/RAM interface bus in response to a data transfer grant (DTGRT). The
Enhanced Mini-ACE/µ-ACE's RAM transfers over A15-A0 and D15-D0 will be framed
by the time that DTACK is asserted low.
TRIG_SEL (I) /
MEMENA_IN (I)
28
V6
Memory Enable or Trigger Select input. In 8-bit buffered mode, input signal (TRIG-SEL)
used to select the order in which byte pairs are transferred to or from the Enhanced
Mini-ACE/µ-ACE by the host processor. In the 8-bit buffered mode, TRIG_SEL should
be asserted high (logic 1) if the byte order for both read operations and write opera-
tions is MSB followed by LSB. TRIG_SEL should be asserted low (logic 0) if the byte
order for both read operations and write operations is LSB followed by MSB.
This signal has no operation in the 16-bit buffered mode (it does not need to be con-
nected).
In transparent mode, active low input MEMENA_IN, used as a Chip Select (CS) input to the
Enhanced Mini-ACE/µ-ACE's internal shared RAM. If only internal RAM is used, should be
connected directly to the output of a gate that is OR'ing the DTACK and IOEN output signals.
MEM / REG(I)
1
B13
T2
Memory/Register. Generally connected to either a CPU address line or address
decoder output. Selects between memory access (MEM/REG = "1") or register access
(MEM/REG = "0").
SSFLAG (I) /
EXT_TRIG(I)
32
Subsystem Flag (RT) or External Trigger (BC/Word Monitor) input. In RT mode, if this
input is asserted low, the Subsystem Flag bit will be set in the Enhanced Mini-ACE/µ-
ACE's RT Status Word. If the SSFLAG input is logic "0" while bit 8 of Configuration
Register #1 has been programmed to logic "1" (cleared), the Subsystem Flag RT
Status Word bit will become logic "1", but bit 8 of Configuration Register #1, SUBSYS-
TEM FLAG, will return logic "1" when read. That is, the sense on the SSFLAG input
has no effect on the SUBSYSTEM FLAG register bit.
In the non-enhanced BC mode, this signal operates as an External Trigger input. In BC
mode, if the external BC Start option is enabled (bit 7 of Configuration Register #1), a
low to high transition on this input will issue a BC Start command, starting execution of
the current BC frame.
In the enhanced BC mode, during the execution of a Wait for External Trigger (WTG)
instruction, the Enhanced Mini-ACE/µ-ACE BC will wait for a low-to-high transition on
EXT_TRIG before proceeding to the next instruction.
In the Word Monitor mode, if the external trigger is enabled (bit 7 of Configuration
Register #1), a low to high transition on this input will initiate a monitor start.
This input has no effect in Message Monitor mode.
Data Device Corporation
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web rev G2-03/03-0
48
TABLE 51. PROCESSOR INTERFACE CONTROL (CONT.)
BU-6186XFX/GX BU-61860BX
BU-6184XFX/GX BU-61840BX
BU-6174XFX/GX BU-61740BX
SIGNAL NAME
DESCRIPTION
PIN
BALL
TRANSPARENT
/BUFFERED
Used to select between the buffered mode (when strapped to logic “0”) and transparent/DMA
mode (when strapped to logic "1") for the host processor interface.
55
B17
READYD
56
B15
Handshake output to host processor. For a nonzero wait state read access, READYD is assert-
ed at the end of a host transfer cycle to indicate that data is available to be read on D15
through D0 when asserted (low). For a nonzero wait state write cycle, READYD is asserted at
the end of the cycle to indicate that data has been transferred to a register or RAM location.
For both nonzero wait reads and writes, the host must assert STRBD low until READYD is
asserted low.
In the (buffered) zero wait state mode, this output is normally logic "1", indicating that the Enhanced
Mini-ACE/µ-ACE is in a state ready to accept a subsequent host transfer cycle. In zero wait mode,
READYD will transition from high to low during (or just after) a host transfer cycle, when the
Enhanced Mini-ACE/µ-ACE initiates its internal transfer to or from registers or internal RAM. When
the Enhanced Mini-ACE/µ-ACE completes its internal transfer, READYD returns to logic "1", indicat-
ing it is ready for the host to initiate a subsequent transfer cycle.
I/O Enable. Tri-state control for external address and data buffers. Generally not used in
buffered mode. When low, indicates that the Enhanced Mini-ACE is currently performing a host
access to an internal register, or internal or (for transparent mode) external RAM. In transparent
mode, IOEN (low) should be used to enable external address and data bus tri-state buffers.
IOEN(O)
58
A17
TABLE 52. RT ADDRESS
BU-6186XFX/GX BU-61860BX
BU-6184XFX/GX BU-61840BX
BU-6174XFX/GX BU-61740BX
SIGNAL NAME
DESCRIPTION
PIN
BALL
RT Address inputs. If bit 5 of Configuration Register #6, RT ADDRESS SOURCE, is pro-
grammed to logic "0" (default), then the Enhanced Mini-ACE/µ-ACE's RT address is provided
by means of these 5 input signals. In addition, if RT ADDRESS SOURCE is logic "0", the
source of RT address parity is RTADP.
RTAD4 (MSB) (I)
RTAD3 (I)
35
T17
34
21
41
U18
U17
V18
RTAD2 (I)
There are many methods for using these input signals for designating the Enhanced Mini-
ACE/µ-ACE's RT address. For details, refer to the description of RT_AD_LAT.
RTAD1 (I)
If RT ADDRESS SOURCE is programmed to logic "1", then the Enhanced Mini-ACE/µ-ACE's
source for its RT address and parity is under software control, via data lines D5-D0. In this
case, the RTAD4-RTAD0 and RTADP signals are not used.
RTAD0 (LSB) (I)
RTADP
33
40
V17
T18
Remote Terminal Address Parity. This input signal must provide an odd parity sum with RTAD4-
RTAD0 in order for the RT to respond to non-broadcast commands. That is, there must be an
odd number of logic "1"s from among RTAD-4-RTAD0 and RTADP.
RT_AD_LAT (I)
31
P18
RT Address Latch. Input signal used to control the Enhanced MINI-ACE/µ-ACE's internal RT
address latch. If RT_AD_LAT is connected to logic "0", then the Enhanced Mini-ACE/µ-ACE RT
is configured to accept a hardwired (transparent) RT address from RTAD4-RTAD) and RTADP.
If RT_AD_LAT is initially logic "0", and then transitions to logic "1", the values presented on
RTAD4-RTAD0 and RTADP will be latched internally on the rising edge of RT_AD_LAT.
If RT_AD_LAT is connected to logic "1", then the Enhanced Mini-ACE/µ-ACE's RT address is
latchable under host processor control. In this case, there are two possibilities: (1) If bit 5 of
Configuration Register #6, RT ADDRESS SOURCE, is programmed to logic "0" (default), then
the source of the RT Address is the RTAD4-RTAD0 and RTADP input signals; (2) If RT
ADDRESS SOURCE is programmed to logic "1", then the source of the RT Address is the
lower 6 bits of the processor data bus, D5-D1 (for RTAD4-0) and D0 (for RTADP).
In either of these two cases (with RT_AD_LAT = "1"), the processor will cause the RT address
to be latched by: (1) writing bit 15 of Configuration Register #3, ENHANCED MODE, to logic
"1"; (2) writing bit 3 of Configuration Register #4, LATCH RT ADDRESS WITH CONFIGURA-
TION REGISTER #5, to logic "1"; and (3) writing to Configuration Register #5. In the case of
RT ADDRESS SOURCE = "1", then the values of RT address and RT address parity must be
written to the lower 6 bits of Configuration Register #5, via D5-D0. In the case where RT
ADDRESS SOURCE = "0", the bit values presented on D5-D0 become "don't care" .
Data Device Corporation
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49
web rev G2-03/03-0
TABLE 53. MISCELLANEOUS
BU-6186XFX/GX
BU-6184XFX/GX
BU-6174XFX/GX
BU-61860BX
BU-61840BX
BU-61740BX
SIGNAL NAME
DESCRIPTION
BU-6186XFX/GX
BU-61860BX
BU-61840BX
BU-61740BX
BU-6184XFX/GX
BU-6174XFX/GX
PIN
BALL
UPADDREN
(BU-6174X,
UPADDREN
26
N2
For BU-61864/61865FX/GX, this pin signal is +5V-RAM and
MUST be connected to +5V.
BU-6184X only)
For the 61860BX, this signal must be connected to logic "1".
For BU-6174X and 6184X, this signal is used to control the func-
tion of the upper 4 address inputs (A15-A12). For these versions of
Enhanced Mini-ACE/µ-ACE, if UPADDREN is connected to logic
"1", then these four signals operate as address lines A15-A12.
For BU-6184X/6174X, if UPADDREN is connected to logic "0",
then A15 and A14 function as CLK_SEL_1 and CLK_SEL_0
respectively; A13 MUST be connected to Vcc-LOGIC (+5V or
+3.3V); and A12 functions as RTBOOT.
INCMD (O) /
MCRST (O)
-
25
-
In-command or Mode Code Reset. The function of this pin is con-
trolled by bit 0 of Configuration Register #7, MODE CODE
RESET/INCMD SELECT.
If this register bit is logic "0" (default), INCMD will be active on this
pin. For BC, RT, or Selective Message Monitor modes, INCMD is
asserted low whenever a message is being processed by the
Enhanced Mini-ACE. In Word Monitor mode, INCMD will be assert-
ed low for as long as the monitor is online.
For RT mode, if MODE CODE RESET/INCMD SELECT is pro-
grammed to logic "1", MCRST will be active. In this case, MCRST
will be asserted low for two clock cycles following receipt of a
Reset remote terminal mode command.
In BC or Monitor modes, if MODE CODE RESET/INCMD SELECT
is logic "1", this signal is inoperative; i.e., in this case, it will always
output a value of logic "1".
-
INCMD (O)
-
M1
For BC, RT, or Selective Message Monitor modes, INCMD is
asserted low whenever a message is being processed by the
µ-ACE. In Word Monitor mode, INCMD will be asserted low for as
long as the monitor is online.
-
MCRST (O)
INT (O)
-
A13
A18
For RT mode MCRST will be asserted low for two clock cycles fol-
lowing receipt of a Reset remote terminal mode command.
INT (O)
57
Interrupt Request output. If the LEVEL/PULSE interrupt bit (bit 3)
of Configuration Register #2 is logic "0", a negative pulse of
approximately 500ns in width is output on INT to signal an inter-
rupt request.
If LEVEL/PULSE is high, a low level interrupt request output will
be asserted on INT. The level interrupt will be cleared (high) after
either: (1) The processor writes a value of logic "1" to INTERRUPT
RESET, bit 2 of the Start/Reset Register; or (2) If bit 4 of
Configuration Register #2, INTERRUPT STATUS AUTO-CLEAR is
logic "1", then it will only be necessary to read the Interrupt Status
Register (#1 and/or #2) that is requesting an interrupt that has
been enabled by the corresponding Interrupt Mask Register.
However, for the case where both Interrupt Status Register #1 and
Interrupt Status Register #2 have bits set reflecting interrupt
events, it will be necessary to read both interrupt status registers
in order to clear INT.
Data Device Corporation
www.ddc-web.com
BU-6174X/6184X/6186X
web rev G2-03/03-0
50
TABLE 53. MISCELLANEOUS (CONT.)
BU-6186XFX/GX
BU-6184XFX/GX
BU-6174XFX/GX
BU-61860BX
BU-61840BX
BU-61740BX
SIGNAL NAME
DESCRIPTION
BU-6186XFX/GX
BU-61860BX
BU-61840BX
BU-61740BX
BU-6184XFX/GX
BU-6174XFX/GX
PIN
BALL
CLOCK_IN (I)
CLOCK_IN (I)
30
V9
20 MHz, 16 MHz, 12 MHz, or 10 MHz clock input.
Transmitter inhibit inputs for the Channel A and Channel B MIL-
STD-1553 transmitters. For normal operation, these inputs should
be connected to logic "0". To force a shutdown of Channel A
and/or Channel B, a value of logic "1" should be applied to the
respective TX_INH input.
TX_INH_A (I)
TX_INH_A (I)
59
A14
TX_INH_B (I)
MSTCLR(I)
TX_INH_B (I)
MSTCLR(I)
60
2
A15
B11
Master Clear. Negative true Reset input, normally asserted low fol-
lowing power turn-on.
-
-
TAG_CLK (I)
RSTBITEN (I)
-
-
B18
P17
Time Tag Clock - External clock that may be used to increment the
Time Tag Register. This option is selected by setting Bits 7,8 and 9
of Configuration Register # 2 to Logic "1".
If this input is set to logic "1", the Built-In-Self-Test (BIST) will be
enabled after hardware reset (for example, following power-up). A
logic "0" input disables power-up BIST.
TABLE 54. NO USER CONNECTIONS
BU-6186XFX/GX
BU-6184XFX/GX
BU-6174XFX/GX
BU-61860BX
BU-61840BX
BU-61740BX
SIGNAL NAME
DESCRIPTION
BU-6186XFX/GX
BU-6184XFX/GX
BU-6174XFX/GX
BU-61860BX
BU-61840BX
BU-61740BX
PAD (*)
BALL
NC
NC
P1, P2, P3,
P4, P5, P6
B2, C1, C2, J1, No user connection
J2, K1, K2, M2,
N1, P1, P2, R1,
R2, R17, R18, T1,
U1, U2, U5, U10
U11, V5, V10, V11
(*) Note that the Test Output pins are recessed pads located on the bottom of the package.
Data Device Corporation
www.ddc-web.com
BU-6174X/6184X/6186X
web rev G2-03/03-0
51
PIN FUNCTIONS
TABLE 55. ENHANCED MINI-ACE (FLAT PACK AND GULL WING PACKAGE) PINOUTS
BU-61843(5)
BC / RT / MT, (4K RAM)
BU-61743(5)
BU-61843(5)
BC / RT / MT, (4K RAM)
BU-61743(5)
BU-61864(5)
BC / RT / MT
(64K RAM)
BU-61864(5)
BC / RT / MT
(64K RAM)
PIN
PIN
RT ONLY, (4K RAM)
RT ONLY, (4K RAM)
1
MEM/REG
MEM/REG
MSTCLR
A11
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
D1
D4
D1
D4
2
MSTCLR
3
A11
RTADP
RTAD1
D0
RTADP
RTAD1
D0
4
A10
TX/RX_A
A8
A10
5
TX/RX_A
A8
6
D2
D2
7
TX/RX_A
A14
TX/RX_A
A14/CLK_SEL_0
A4
D3
D3
8
D5
D5
9
A4
D8
D8
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
A3
A3
D7
D7
A7
A7
D13
D12
D14
D9
D13
D12
D14
D9
A2
A2
TX/RX_B
ADDR_LAT/MEMOE
A0
TX/RX_B
ADDR_LAT/MEMOE
A0
D11
D15
D10
D11
D15
D10
TX/RX-B
LOGIC GND
LOGIC GND
LOGIC GND
+5V Vcc-CH. B
RTAD2
TX/RX-B
LOGIC GND
LOGIC GND
LOGIC GND
+5V Vcc-CH. B
RTAD2
TRANSPARENT/
BUFFERED
TRANSPARENT/
BUFFERED
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
READYD
INT
READYD
INT
A6
A6
IOEN
IOEN
ZEROWAIT/MEMWR
8/16-BIT/DTREQ
INCMD/MCRST
+5V RAM
A1
ZEROWAIT/MEMWR
8/16-BIT/DTREQ
INCMD/MCRST
UPADDREN
A1
TX_INH_A
TX_INH_B
SELECT
STRBD
TX_INH_A
TX_INH_B
SELECT
STRBD
RD / WR
MSB/LSB/DTGRT
LOGIC GND
A15
RD / WR
TRIG_SEL/MEMENA_IN TRIG_SEL/MEMENA_IN
MSB/LSB/DTGRT
LOGIC GND
A15/CLK_SEL_1
LOGIC GND
A5
POL_SEL/DTACK
CLOCK_IN
RT_AD_LAT
SSFLAG/ EXT_TRIG
RTAD0
POL_SEL/DTACK
CLOCK_IN
RT_AD_LAT
SSFLAG/ EXT_TRIG
RTAD0
LOGIC GND
A5
A9
A9
RTAD3
RTAD3
A12
A12/RTBOOT
A13/+5V/3.3V LOGIC
+5V Vcc-CH. A
RTAD4
RTAD4
A13
D6
D6
+5V Vcc-CH. A
+5V/3.3V LOGIC
+5V/3.3V LOGIC
Data Device Corporation
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BU-6174X/6184X/6186X
web rev G2-03/03-0
52
TABLE 56. ENHANCED MINI-ACE (FLAT PACK AND
GULL WING) NO USER CONNECTIONS
BU-6186XFX/GX
BU-6184XFX/GX
BU-6174XFX/GX
PAD (*)
P1
P2
P3
P4
P5
P6
NC
NC
NC
NC
NC
NC
* Note that the Test Output pins on the flat pack are pads located on the
bottom of the package.
TABLE 57. µ-ACE (BGA PACKAGE) “DAISY CHAIN”
MECHANICAL SAMPLE CONNECTIONS
BALL PAIRS WIRED
TOGETHER
BALL PAIRS WIRED
TOGETHER
BALL PAIRS WIRED
TOGETHER
BALL PAIRS WIRED
TOGETHER
A1-A2
A3-A4
B15-B16
B17-B18
C1-C2
K1-K2
K17-K18
L1-L2
U5-U6
U7-U8
A5-A6
U9-U10
U11-U12
U13-U14
U15-U16
U17-U18
V1-V2
A7-A8
C17-C18
D1-D2
L17-L18
M1-M2
M17-M18
N1-N2
A9-A10
A11-A12
A13-A14
A15-A16
A17-A18
B1-B2
D17-D18
E1-E2
E17-E18
F1-F2
N17-N18
P1-P2
V3-V4
F17-F18
G1-G2
P17-P18
R1-R2
V5-V6
B3-B4
V7-V8
B5-B6
G17-G18
H1-H2
R17-R18
T1-T2
V9-V10
V11-V12
V13-V14
V15-V16
V17-V18
B7-B8
B9-B10
B11-B12
B13-B14
H17-H18
J1-J2
T17-T18
U1-U2
J17-J18
U3-U4
Data Device Corporation
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BU-6174X/6184X/6186X
web rev G2-03/03-0
53
TABLE 58. µ-ACE (BGA PACKAGE) PINOUTS
BALL
SIGNAL
BALL
E1
SIGNAL
BALL
T1
SIGNAL
NC
A1
A2
A0
+5V_A
A2
E2
GND/THERMAL*
T2
SSFLAG/EXT_TRIG
RTAD4
A3
A4
E17
E18
F1
D11
T17
T18
U1
A4
A6
D12
RTADP
A5
A7
+5V_A
NC
A6
A10
F2
GND/THERMAL*
U2
NC
A7
A12** or A12/RTBOOT***
F17
F18
G1
D7
U3
VDD_RAM ( +5V)
GND
A8
+5V/3.3V LOGIC
D8
U4
A9
GND
+5V_A
U5
NC
A10
A11
A12
A13
A14
A15
A16
A17
A18
B1
A13** or A13/Vcc_LOGIC***
G2
GND/THERMAL*
U6
MSB/LSB/DTGRT
POL_SEL/DTACK
ZEROWAIT/MEMWR
GND
A15** or A15/CLK_SEL_1***
G17
G18
H1
D3
U7
RD/WR
D2
U8
MCRST
TX/RX_A
U9
TX_INH_A
H2
TX/RX_A
U10
U11
U12
U13
U14
U15
U16
U17
U18
V1
NC
TX_INH_B
H17
H18
J1
D5
NC
+5V/3.3V LOGIC
D0
TX/RX_B
GND/THERMAL*
GND/THERMAL*
GND/THERMAL*
TX/RX_B
RTAD2
IOEN
NC
INT
J2
NC
A1
J17
J18
K1
D13
B2
NC
D6
B3
A3
NC
B4
A5
K2
NC
RTAD3
B5
A8
K17
K18
L1
GND
GND
B6
A9
A11
GND
V2
VDD_LOW
VDD_RAM (+5V)
GND
B7
+5V/3.3V LOGIC
V3
B8
+5V/3.3V LOGIC
GND
L2
+5V/3.3V LOGIC
V4
L17
L18
M1
+5V/3.3V LOGIC
V5
NC
B9
+5V/3.3V LOGIC
V6
TRIG_SEL/MEMENA_IN
16/8 / DTREQ
ADDR_LAT/MEMOE
CLOCK IN
NC
B10
B11
B12
B13
B14
B15
B16
B17
B18
C1
A14** or A14/CLK_SEL_0***
MSTCLR
SELECT
INCMD
V7
M2
NC
V8
M17
M18
N1
D1
V9
MEM/REG
STROBE
READY
D4
V10
V11
V12
V13
V14
V15
V16
V17
V18
NC
NC
N2
UPADDRENA
TX/RX_B
+5V_B
+5V/3.3V LOGIC
TRANS/BUFFERED
TAG_CLK
NC
N17
N18
P1
D10
D9
NC
+5V_B
+5V_B
P2
NC
TX/RX_B
RTAD0
C2
NC
P17
P18
R1
RSTBITEN
RT_AD_LAT
NC
C17
C18
D1
GND
RTAD1
GND
TX/RX_A
TX/RX_A
D15
R2
NC
D2
R17
R18
NC
D17
D18
NC
D14
* See Thermal Management Section for important user information.
** Applicable for 64K RAM option.
*** Applicable for 4K RAM option.
Data Device Corporation
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BU-6174X/6184X/6186X
web rev G2-03/03-0
54
2.000 ±0.015
(50.800 ±0.381)
1.000 SQ ±0.010
(25.400 ±0.254)
0.500 ±0.005
(12.70 ±0.127)
0.200 ±0.005
(5.080 ±0.127)
0.100 DIA.
(2.540) (see note 4)
P6
P5
P2
P4
P1
P3
72
1
INDEX DENOTES
PIN NO. 1
0.018 ±0.002 0.050 ±0.005
(1.270 ±0.127)
(0.457 ±0.051)
VIEW "B"
VIEW "A"
VIEW "B"
0.850 ±0.008
(21.590 ±0.203)
BOTTOM VIEW
0.010 ±0.002
(0.254 ±0.051)
0.130 MAX
(3.30)
0.050 ±0.005
(1.270 ±0.127)
0.040 ±0.004
1.024 ±0.014 NOM.
(26.010 ±0.356)
0.035 ±0.005
(0.889 ±0.127)
(1.016 ±0.102)
VIEW "A"
0.090 ±0.010
(2.286 ±0.254)
SIDE VIEW
Notes:
1) Dimensions are in inches (mm).
2) Package Material: Alumina (AL O )
2
3
3) Lead Material: Kovar, Plated by 50µ in. minimum nickel under 60µ in. minimum gold.
4) There are 6 test pads located on the bottom of the package. These pads are recessed
so as not to interfere when mounting the hybrid. There are no user connections to these pads.
FIGURE 18. MECHANICAL OUTLINE DRAWING FOR ENHANCED MINI-ACE 72-LEAD FLAT PACK
Data Device Corporation
www.ddc-web.com
BU-6174X/6184X/6186X
web rev G2-03/03-0
55
1.38 ±0.02
(35.05 ±0.51)
1.00 SQ ±0.01
(25.40 ±0.25)
0.19 Ref
(4.83 Ref)
0.100 DIA.
(2.540) (see note 4)
P6
P5
P2
P4
P1
P3
72
1
VIEW "B"
0.850 ±0.008
(21.590 ±0.203)
0.018 ±0.002 0.050 ±0.005
(1.270 ±0.127)
(0.457 ±0.051)
VIEW "B"
BOTTOM VIEW
0.08 MIN FLAT
(2.03)
INDEX DENOTES
PIN NO. 1
0.012 R. MAX
(0.305 R.)
0.130 MAX
(3.30)
0.050 ±0.005
(1.27 ±0.127)
0.010 ±0.002
(0.254 ±0.051)
0.05 MIN FLAT
(1.27)
1.024 ±0.014 NOM.
(26.010 ±0.356)
0.006 -0.004,+0.010
(0.152 -0.100,+ 0.254)
VIEW "A"
0.075 MAX FLAT
(1.91)
VIEW "A"
SIDE VIEW
0.19 Ref
(4.83 Ref)
Notes:
1) Dimensions are in inches (mm).
2) Package Material: Alumina (AL O )
2 3
3) Lead Material: Kovar, Plated by 50µ in.
minimum nickel under 60µ in. minimum gold.
4) There are 6 test pads located on the bottom of
the package. These pads are recessed so as
not to interfere when mounting the hybrid.
There are no user connections to these pads.
FIGURE 19. MECHANICAL OUTLINE DRAWING FOR ENHANCED MINI-ACE 72-PIN GULL WING PACKAGE
Data Device Corporation
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BU-6174X/6184X/6186X
web rev G2-03/03-0
56
.815 [20.70]
(MAX)
SQUARE
.670 [17.02]
(TYP)
18
17
16
15
14
13
12
11
10
9
17 EQ.SP.
.0394 [1.00] = .670 [17.02]
(TOL NONCUM)
(TYP)
8
7
6
5
4
3
2
1
V
U T R P N M L K J H G F E D C B A
.065 [1.65]
(TYP)
.0394 [1.00]
(TYP)
Triangle denotes
Ball A1
.065 [1.65]
(TYP)
BOTTOM VIEW
Cover Material
Diallyl Phthalate (DAP)
0.140 [3.58]
(MAX)
.032 [0.81]
(REF)
.022 [0.559] DIA
Sn/Pb BALL
FR4 P.C. Board
(128 PLACES)
SIDE VIEW
Notes:
1) Dimensions are in inches (mm).
2) Cover material: Diallyl Phthalate (DAP).
3) Base material: FR4 PC board.
4) Ball material: SnPb.
5) Solder Ball Cluster to be centralized within ±.010 of outline dimensions.
6) The copper pads (128 places) on the bottom of the BGA package are .025" (0.635 mm)
in diameter prior to processing. Final ball size is .022" (0.559 mm) after processing (typical).
FIGURE 20. MECHANICAL OUTLINE DRAWING FOR µ-ACE 128-BALL BGA PACKAGE
Data Device Corporation
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BU-6174X/6184X/6186X
web rev G2-03/03-0
57
ORDERING INFORMATION FOR ENHANCED MINI-ACE (FLAT PACK AND “GULL WING” PACKAGES)
BU-61XXXXX-XXXX
Supplemental Process Requirements:
S = Pre-Cap Source Inspection
L = Pull Test
Q = Pull Test and Pre-Cap Inspection
K = One Lot Date Code
W = One Lot Date Code and PreCap Source
Y = One Lot Date Code and 100% Pull Test
Z = One Lot Date Code, PreCap Source and 100% Pull Test
Blank = None of the Above
Test Criteria:
0 = Standard Testing
2 = MIL-STD-1760 Amplitude Compliant (not available with Voltage/Transceiver Option 4 “McAir compatible”)
Process Requirements:
0 = Standard DDC practices, no Burn-In
1 = MIL-PRF-38534 Compliant
2 = B*
3 = MIL-PRF-38534 Compliant with PIND Testing
4 = MIL-PRF-38534 Compliant with Solder Dip
5 = MIL-PRF-38534 Compliant with PIND Testing and Solder Dip
6 = B* with PIND Testing
7 = B* with Solder Dip
8 = B* with PIND Testing and Solder Dip
9 = Standard DDC Processing with Solder Dip, no Burn-In
Temperature Range** / Data Requirements:
1 = -55°C to +125°C
2 = -40°C to +85°C
3 = 0°C to +70°C
4 = -55°C to +125°C with Variables Test Data
5 = -40°C to +85°C with Variables Test Data
6 = Custom Part (Reserved)
7 = Custom Part (Reserved)
8 = 0°C to +70°C with Variables Test Data
Voltage / Transceiver Option:
3 = +5 Volts rise/fall times = 100 to 300 ns (-1553B)
4 = +5 Volts rise/fall times = 200 to 300 ns (-1553B and McAir compatible)(not available with
Test Criteria option 2 “MIL-STD-1760 Amplitude Compliant”)
Package Type:
F = 72-Lead Enhanced Mini-ACE Flat Pack
G = 72-Lead Enhanced Mini-ACE “Gull Wing” (Formed Lead)
Logic / RAM Voltage (for BU-6186X versions, 64K x 17K RAM voltage is always 5V)
3 = 3.3 Volt (Applicable only for BU-61743 and BU-61843)
4 = 3.3 and 5 Volt (Applicable only for BU-61864)
5 = 5 Volt
Product Type:
BU-6174 = RT only with 4K x 16 RAM
BU-6184 = BC / RT / MT with 4K x 16 RAM
BU-6186 = BC / RT / MT with 64K x 17 RAM
* Standard DDC processing with burn-in and full temperature test. See Standard DDC Processing table.
** Temperature Range applies to case temperature.
Data Device Corporation
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BU-6174X/6184X/6186X
web rev G2-03/03-0
58
ORDERING INFORMATION FOR µ-ACE (BGA PACKAGE)
BU-61XX0B3-202
Test Criteria:
2 = MIL-STD-1760 Amplitude Compliant
Process Requirements:
0 = Standard DDC practices, no Burn-In
Temperature Range** / Data Requirements:
2 = -40°C to +85°C
Voltage / Transceiver Option:
3 = +5 Volts rise / fall times = 100 to 300 ns (-1553B)
Package Type:
B = 128-Ball BGA Package
Logic / RAM Voltage (for BU-61860 version, 64K x 17K RAM voltage is always 5V)
0 = 3.3 or 5 Volt logic
Product Type:
BU-6174 = RT only with 4K x 16 RAM
BU-6184 = BC / RT / MT with 4K x 16 RAM
BU-6186 = BC / RT / MT with 64K x 17 RAM
** Temperature Range applies to ball temperature.
BU-61860B3-601
µ-ACE (128-ball BGA) mechanical sample, with “daisy chain” connections
of alternating balls, for use in environmental (mechanical / thermal)
integrity testing.
STANDARD DDC PROCESSING
MIL-STD-883
TEST
METHOD(S)
CONDITION(S)
INSPECTION
SEAL
2009, 2010, 2017, and 2032
—
1014
1010
A and C
TEMPERATURE CYCLE
CONSTANT ACCELERATION
BURN-IN
C
A
2001
1015, Table 1
—
Data Device Corporation
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BU-6174X/6184X/6186X
web rev G2-03/03-0
59
The information in this data sheet is believed to be accurate; however, no responsibility is
assumed by Data Device Corporation for its use, and no license or rights are
granted by implication or otherwise in connection therewith.
Specifications are subject to change without notice.
Please visit our web site at www.ddc-web.com for the latest information.
105 Wilbur Place, Bohemia, New York, U.S.A. 11716-2482
For Technical Support - 1-800-DDC-5757 ext. 7234
Headquarters, N.Y., U.S.A. - Tel: (631) 567-5600, Fax: (631) 567-7358
Southeast, U.S.A. - Tel: (703) 450-7900, Fax: (703) 450-6610
West Coast, U.S.A. - Tel: (714) 895-9777, Fax: (714) 895-4988
United Kingdom - Tel: +44-(0)1635-811140, Fax: +44-(0)1635-32264
Ireland - Tel: +353-21-341065, Fax: +353-21-341568
France - Tel: +33-(0)1-41-16-3424, Fax: +33-(0)1-41-16-3425
Germany - Tel: +49-(0)8141-349-087, Fax: +49-(0)8141-349-089
Japan - Tel: +81-(0)3-3814-7688, Fax: +81-(0)3-3814-7689
World Wide Web - http://www.ddc-web.com
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DATA DEVICE CORPORATION
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