BUS-61553-12L [ETC]
Controller Miscellaneous - Datasheet Reference ; 控制器杂项 - 数据表参考\n型号: | BUS-61553-12L |
厂家: | ETC |
描述: | Controller Miscellaneous - Datasheet Reference
|
文件: | 总4页 (文件大小:52K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
BUS -6 1 5 5 3
MIL-S TD-1 5 5 3 ADVANCED INTEGRATED
(
)
MUX AIM HYBRID
DESCRIPTION
FEATURES
• Fully Intergrated Terminal
Including:
–Dual Transceiver
–BC/RT/MT Protocol
–Memory Management Unit
–Processor lnterface Logic
–8K x 16 RAM
DDC’s
Integrated Mux (AIM) Hybrid is a maximum design flexibility, memory
complete MIL-STD-1553 Bus control lines are provided for attach-
Controller (BC), Remote Terminal ing external RAM to the BUS-61553
Unit (RTU), and Bus Monitor (MT) address and data buses and for dis-
device. Packaged in a single 78-pin abling internal memory; the total
DIP package, the BUS-61553 con- combined memory space can be
tains dual low-power transceivers, expanded to 64K x 16. All 1553 trans-
complete BC/RT/MT protocol logic, a fers are entirely memory-mapped;
MIL-STD-1553-to-host interface unit thus the CPU interface requires
BUS-61553
Advanced shared 8K x 16 RAM. To ensure
• CMOS and Bipolar Technologies
and 8K x 16 RAM.
minimal hardware and/or software
support.
• Internal Interrupt Status and Time
Tag Registers
Using an industry standard dual
transceiver and standard status and The BUS-61553 operates over the
control signals, the BUS-61553 sim- full military -55°C to +125°C temper-
plifies system integration at both the ature range. Available screened to
MIL-STD-1553 and host processor MIL-PRF-38534, the BUS-61553 is
• High Reliability
• 883B Processing Available
interface levels.
ideal for demanding military and
industrial microprocessor-to-1553
interface applications.
All 1553 operations are controlled
through the CPU access to the
BUS-25679
TRANSCEIVER A
8
1
TX INH
CLOCK IN
DATA
2
BUS A
3
4
MSTRCLR
SELECT
STRBD
TX
CHANNEL A
ENCODER/
DECODER
MEMORY
TIMING
TRANSFORMER A
RX
READYD
CPU
RD/WR
TIMING
RX
MEM/REG
EXTEN
EXTLD
CONTENTION
RESOLVER
PROTOCOL
CONTROLLER
INTERRUPT
GENERATOR
INT
768 µs
TIME OUT
A15-A00
BUS-25679
D15-D00
1
2
8
TX INH
TX
DATA
BUS B
4
3
CHANNEL B
ENCODER/
DECODER
8K x 16
SHARED RAM
RTAD0
RTAD1
TRANSFORMER B
RX
PARITY
CHECKER
RTAD2
RTAD3
RTAD4
RTAD P
RT ADDR
RAM
RX
TRANSCEIVER B
RTPARERR
FIGURE 1. BU-61553 BLOCK DIAGRAM
© 1987, 1999 Data Device Corporation
ORDERING INFORMATION
BUS-615XX- XX0X
Supplemental Process Requirements:
S = Pre-Cap Source Inspection
L = Pull Test
Q = Pull Test and Pre-Cap Inspection
K = One Lot Date Code
W = One Lot Date Code and PreCap Source
Y = One Lot Date Code and 100% Pull Test
Z = One Lot Date Code, PreCap Source and 100% Pull Test
Blank = None of the Above
Process Requirements:
(
)
0 = Standard DDC Processing, no Burn-In See Page 13.
1 = MIL-PRF-38534 Compliant
2 = B*
3 = MIL-PRF-38534 Compliant with PIND Testing
4 = MIL-PRF-38534 Compliant with Solder Dip
5 = MIL-PRF-38534 Compliant with PIND Testing and Solder Dip
6 = B* with PIND Testing
7 = B* with Solder Dip
8 = B* with PIND Testing and Solder Dip
(
)
9 = Standard DDC Processing with Solder Dip, no Burn-In See Page 13.
Temperature Grade/Data Requirements:
1 = -55°C to +125°C
2 = -40°C to +85°C
3 = 0°C to +70°C
4 = -55°C to +125°C with Variables Test Data
5 = -40°C to +85°C with Variables Test Data
8 = 0°C to +70°C with Variables Test Data
Power Supply
3 = -15 V Transceivers
4 = -12 V Transceivers
5 = +5 V Transceivers–Call Factory
6 = Transceivers–Use with BUS-63102II–Call Factory
Packaging
5 = DDIP
6 = Flat Pack
2
NOTES
3
The information in this data sheet is believed to be accurate; however, no responsibility is
assumed by Data Device Corporation for its use, and no license or rights are
granted by implication or otherwise in connection therewith.
Specifications are subject to change without notice.
105 Wilbur Place, Bohemia, New York 11716-2482
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Headquarters - Tel: (631) 567-5600 ext. 7257 or 7381, Fax: (631) 567-7358
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World Wide Web - http://www.ddc-web.com
ILC DATA DEVICE CORPORATION
REGISTERED TO ISO 9001
FILE NO. A5976
L - DSN
PRINTED IN THE U.S.A.
4
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