BW4104X [ETC]
BW4104X LVDS Receiver|Data Sheet ; BW4104X LVDS接收器|数据表\n
| 型号： | BW4104X |
| 厂家： | 
ETC |
| 描述： | BW4104X LVDS Receiver|Data Sheet
|
| 文件： | 总7页 (文件大小：106K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LVDS Receiver
BW4104X
DECEMBER 1998. Ver1.0
Features
General Description
The BW4104X receiver converts the LVDS data
streams
• 20 to 65MHz shift clock support
• 28:4 Data Channel Compression at up to
455Megabits/sec on each LVDS channel
• Single 3.3V supply
back into 28bits of CMOS/TTL data. At a transmit clock
frequency of 65MHz, 24 bits of RGB data and 4bits of
LCD timing data and control data are transmitted at a
rate of 455Mbps per LVDS data channel. Using a
65MHz clock the throughput is 227Mbytes/sec. Devices
are offered with falling edge clocks for convenient
interface with a varity of graphics and LCD panel
controllers. This receiver is an ideal means to solve
EMI and cable size problems associated with wide high
speed TTL
• Low Power CMOS Design
• Power-down mode
• Single pixel per clock XGA(1024x768) ready
• Supports VGA,SVGA,XGA and higher
addressability
• Up to 227 Megabytes/sec bandwidth
• Narrow bus reduces cable size and cost
• PLL requires no external components
• Low profile 56 lead TSSOP package
• Falling edge data strobe Receiver
interfaces.
Block Diagram
Serial/Parallel
LVDS input buffer
Data transfer
RAN
RAP
RXOUT<0:6>
RXOUT<7:13>
outbuffer x 7
outbuffer x 7
outbuffer x 7
For channel A
RBN
RBP
For channel B
For channel C
RCN
RCP
RXOUT<14:20>
RXOUT<21:27>
RDN
RDP
For channel D
outbuffer x 7
RCLKN
RCLKP
CLKOUT
PLL
PDWNN
Figure1 . LVDS Block Diagram
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0.35um LVDS Receiver
BW4104X
Absolute Maximum Ratings
Supply Voltage (Vcc)
-0.3V to +4V
CMOS/TTL Input Voltage
CMOS/TTL output Voltage
LVDS Receiver Input Voltage
Storage Temperature
-0.3V to (Vcc+0.3V)
-0.3V to (Vcc+0.3V)
-0.3V to (Vcc+0.3V)
°
°
C
-45 C to 125
Note: "Absolute Maximum Ratings" are thise values beyond which the safety of the device cannot guaranteed.
They are not to imply that the device should be operated at these limits. The tables of "Electrical
Characteristics" specify conditions for device operation.
Recommended Operating Conditions
Parameter
Min
Typ
3.3
25
Max
Units
Supply Voltage (Vcc)
3.0
3.6
V
Operating Temperature
Receiver Input Range
-10
0
70
2.4
V
Electrical Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Units
CMOS/TTL DC SPECIFICATIONS
VIH
VIL
High Level Input Voltage
2
Vcc
0.8
V
V
V
V
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
GND
2.4
VOH
VOL
IOH=-4mA
IOL=4mA
0.4
±
IIN
Input Current
0V VIN VCC
10
A
m
£
£
IOS
Output Short Circuit Current
VOUT=0V
-50
mA
LVDS DC SPECIFICATIONS
VTH
VTL
IIN
Differential Input High Threshold
VOM=1.2V
+100
mV
mV
Differential Input Low Threshold
Input Current
-100
±
VIN=+2.4V/0V
VCC=3.6V
10
A
m
IRCC
Dynamic Current
CL=8pF, f=65MHz
16 Gray Scale
34
43
mA
IRCCS
Power Down Current
PDWNN=Low
10
A
m
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SEC ASIC
ANALOG
0.35um LVDS Receiver
BW4104X
Switching Characteristics
Symbol
tRCP
tRCH
tRCL
Parameter
Min
Typ
T
Max
Units
ns
CLKOUT Period
15.4
50
CLKOUT High Time
4T/7
3T/7
ns
CLKOUT Low Time
ns
tRS
TTL Data Setup to CLKOUT
TTL Dat Hold from CLKOUT
RCLKP/- to CLKOUT Delay
TTL Low to High Transition Time
TTL High to Low Transition Time
LVDS Channel to Channel Skew
Phase Lock Loop Lock Time
2.5
4.0
ns
tRH
ns
tRCD
tTLH
4T/7
ns
3
2
5
5
ns
tTHL
ns
tRSK
500
5.2
ps
tRPLL
s
m
SEC ASIC
3 / 7
ANALOG
0.35um LVDS Receiver
AC Timing Diagrams
BW4104X
RA6
RA5
RA4
RB4
RA3
RB3
RA2
RB2
RA1
RB1
RA0
RB0
RAP/N
RBP/N
RCP/N
RB5
RC5
RB6
RC6
RD6
RC4
RC3
RC2
RD2
RC1
RD1
RC0
RD5
RD4
RD3
RD0
RDP/N
Vdiff=0V
tRCD
RCLKP/N
tRSK
tRCH
tRCL
2.0V
0.8V
2.0V
tRS
2.0V
CLKOUT
0.8V
0.8V
tRCP
tRH
2.0V
2.0V
0.8V
DATA VALID
RXOUT0-RXOUT6
0.8V
DATA VALID
DATA VALID
DATA VALID
RXOUT7-RXOUT13
RXOUT14-RXOUT20
RXOUT21-RXOUT27
Note:
tRSK measured between eariest and latest initial LVDS edges.
Vdiff = (RAP)-(RAN),(RBP)-(RBN),(RCP)-(RCN),(RDP)-(RDN),(RCLKP)-(RCLKN)
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SEC ASIC
ANALOG
0.35um LVDS Receiver
BW4104X
LVDS input setup/hold time
The skew margin is represented by setup time and hold time. Setup time and hold time are
defined in below timing diagram. Setup time represents "+skew" margin and hold time
represents "-skew" margin. Ideal strobe position is virtual strobe.
Ideal strobe position
RAP,RBP,RCP,RDP
RAN,RBN,RCN,RDN
Vdiff=0
setup
hold
+Skew
RAP,RBP,RCP,RDP
RAN,RBN,RCN,RDN
RAP,RBP,RCP,RDP
RAN,RBN,RCN,RDN
-Skew
Note : Vdiff=(RAP-RAN,RBP-RBN,RCP-RCN,RDP-RDN)
unit:ps
Frequency
"1" data
"0" data
setup
130
hold
-80
setup
hold
-90
65MHz
32MHz
70
140
-160
190
-150
Ideal Strobe position for LVDS input
RCLKP
RCLKN
RAP or RAN..etc
Rx1
Rx0
Rx4
Rx3
Rx6
Rx5
Rx2
RAN or RAP..etc
0.5/7T
1.5/7T
2.5/7T
3.5/7T
4.5/7T
5.5/7T
6.5/7T
Note: LVDS Input(RAP/RAN,RBP/RBN..etc) is 7bit data stream
SEC ASIC
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ANALOG
0.35um LVDS Receiver
BW4104X
Pin Descriptions & Configurations
Pin Name
I/O
Description
Configuration
RAP
RBP
RCP
RDP
I
Positive LVDS differential data inputs
Vcc
RXOUT22
RXOUT23
RXOUT24
GND
1
56
55
54
53
52
51
504
9
RXOUT21
RXOUT20
RXOUT19
GND
2
3
4
RAN
RBN
RCN
RDN
RXOUT25
RXOUT26
RXOUT27
LVDS GND
RAN
5
I
Negative LVDS differential data inputs
RXOUT18
RXOUT17
RXOUT16
Vcc
6
7
8
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
9
RCLKP
RCLKN
PDWNN
CLKOUT
I
I
Positive LVDS differential clock inputs
Negative LVDS differential clock input
Power down signal. Active Low
RXOUT15
RXOUT14
RXOUT13
GND
RAP
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
RBN
RBP
I
LVDS Vcc
LVDS GND
RCN
RXOUT12
RXOUT11
RXOUT10
Vcc
O
TTL level clock output. The falling
edge acts as data strobe.
RCP
RXOUT<0:6>
RXOUT<7:13>
RXOUT<14:20>
RXOUT<21:27>
RCLKN
RCLKP
RDN
O
TTL level data outputs. This include
8 Red, 8 Green, 8 Blue and 4
control lines.
RXOUT9
RXOUT8
RXOUT7
GND
RDP
LVDS GND
PLL GND
PLL Vcc
PLL GND
PDWNN
CLKOUT
RXOUT0
GND
RXOUT6
RXOUT5
RXOUT4
RXOUT3
Vcc
VCC
P
G
P
G
P
G
Power supply pins for TTL outputs
Ground pins for TTL outputs
Power supply for PLL
GND
PLL VCC
PLL GND
LVDS VCC
LVDS GND
RXOUT2
RXOUT1
Ground pin for PLL
Power Supply pin for LVDS inputs
Ground pins for LVDS inputs
SEC ASIC
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ANALOG
0.35um LVDS Receiver
Test Method
BW4104X
Following figures are LVDS receiver test methods. Low frequency test case is shown in Figure 1 and
high frequency test case is shown in Figure 2. For exampl, in low frequency test case LVDS input
data(RAP/N,RBP/N,etc) are input to receiver chip(Rx chip) at 65MHz, and Rx chip
outputs(RXOUT<0:6>,etc) at 20MHz.
RAP
RAN
RBP
RBN
7
7
RXOUT<0:6>
RXOUT<7:1
65MHz
input
7
7
3>
20MHz
output
RCP
RCN
RDP
RDN
BW4104X
RXOUT<14:2
0>
RXOUT<21:2
7
7>
CLKOUT
20MHz
input
RCLKP
RCLKN
PDWNN
Figure 1. Low Frequency Test Case
In high frequency test case, Transmitter chip(Tx Chip) is needed. For example, Test data input to Tx
chip at 65MHz,Rx chip is received LVDS data at 455MHz each channels. Test data and expectation
value using this test are made from slow frequency test result.
RAP
7
7
RAN
RXOUT<0:6>
TA<0:6>
RBP
RBN
RCP
RCN
RDP
RDN
7
7
7
7
7
7
RXOUT<7:13>
RXOUT<14:20>
TB<0:6>
TC<0:6>
65MHz
output
65MHz
input
BW4104X
Tx Chip
RXOUT<21:2
TD<0:6>
CLKIN
7
7>
CLKOUT
7
RCLKP
RCLKN
PDWNN
Figure 2. High Frequency Test Case
SEC ASIC
ANALOG
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