CBM2093 [ETC]
Chipsbank U盘控制芯片; 芯邦微电子ü盘控制芯片
| 型号： | CBM2093 |
| 厂家： | 
ETC |
| 描述： | Chipsbank U盘控制芯片 |
| 文件： | 总15页 (文件大小：254K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CBM2093
USB 2.0 Flash Disk Controller
Datasheet
Rev 1.0
Chipsbank Technologies (Shenzhen) Co.,Ltd.
7/F,Building No.12,Keji Central Road 2,
Software Park, High-Tech Industrial Park, Shenzhen,
P.R.China 518057
Tel: 0755-86169650-808
Fax: 0755-86169690
Email: info@chipsbank.com
URL: http://www.chipsbank.com
Contained herein
Copyright by Chipsbank Technologies (Shenzhen) Co.,Ltd all rights reserved.
CBM2093 Datasheet
- 1 -
05/12/2009
Revision History
Date
2009-05-12
Rev No
Descrption
Initial release
1.0
CBM2093 Datasheet
- 2 -
05/12/2009
Contents
1
2
3
4
DESCRIPTION........................................................................................................................................ 4
FEATURES.............................................................................................................................................. 4
BLOCK DIAGRAM................................................................................................................................. 6
PIN ASSIGNMENT................................................................................................................................. 7
4.1 TQFP48 (TOP SIDE).............................................................................................................................. 7
5
6
PIN DESCRIPTION ................................................................................................................................ 8
ELECTRICAL CHARACTERISTICS..................................................................................................11
6.1 ABSOLUTE MAXIMUM RATINGS.....................................................................................................11
6.2 RECOMMENDED OPERATING CONDITIONS................................................................................11
6.3 STATIC CHARACTERISTICS .............................................................................................................11
6.4 DYNAMIC CHARACTERISTICS.........................................................................................................12
7
MECHANICAL DIMENSIONS .............................................................................................................14
7.1 48-PIN CBM2093 PACKAGE OUTLINE DIMENSION....................................................................14
COPYRIGHT NOTICE ..........................................................................................................................15
8
CBM2093 Datasheet
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05/12/2009
1 Description
Fastest & Securest USB 2.0 Flash Disk Controller with dedicated 32-bit
microprocessor
The CBM2093 is the USB 2.0 Flash Disk controller with the fastest transfer speed on the market.
CBM2093 can reach theoretical flash access speed limit of over 32MByte/s for read and
20MByte/s for write.
The on-the-fly ECC engine is capable of correcting up to 8/15bits per 512 bytes page . For data
security, CBM2093 is designed with both hardware and software data protection technology to
prevent data corruption even if it is powered off or unplugged during data transfer.
The CBM2093 supports all 8 /16 bit BUS wide NAND flash memory available in the market. New
flash can be supported by software re-configuration.
The CBM2093 has both a) 5V to 3.3V LDO and b) power on reset circuits integrated. Thus greatly
reduced BOM cost and eased layout burden.
The CBM2093 runs smoothly with all available hosts and PC platforms. Complied with USB
specification rev. 2.0, the CBM2093 can be supported without additional driver under Win XP, Win
2000, Windows Me, Mac OS and Linux OS. With device driver installed, it can support Win
98/98SE as well. Comprehensive applications, such as PC boot up, disk partitions, password
check for security disk, are available as part of our standard mass production software package.
The CBM2093 is available in 48-pin TQFP and 64-pin LQFP package, which are thinnest and
smallest on the market. The 48-pin CBM2093 supports up to 4 flash chips and the 64-pin
CBM2093 supports up to 8 flash chips. Customers can choose different packages to meet their
design requirement.
2 Features
USB Interface
High-speed USB 2.0 interface;
Fastest data transfer rate on the market
Dual-channel mode: 32MB/s for Read, 20MB/s for Write
Single-channel mode: 26MB/s for Read, 20MB/s for Write
Fastest file copy rate on the market.
On-the-fly ECC built-in Hardware enhances reliability
ECC for SLC NAND flash: 8 bit per page (1 page = 512 bytes)
ECC for MLC NAND flash: 8/15 bit per page
Special wear leveling algorithm to improve the flash life-time
Hardware & Software Data Protection Technology
Prevent data corruption even if it is powered off or unplugged during data transfer.
CBM2093 Datasheet
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05/12/2009
NAND, SLC/MLC Flash Interface
Support 4k page flash parallel mode.
Support 8-bit and 16-bit Samsung SLC and MLC NAND flash.
Support 8-bit and 16-bit Toshiba SLC and MLC NAND flash.
Support 8-bit and 16-bit Hynix SLC and MLC NAND flash.
Support 8-bit and 16-bit Micron/Intel SLC and MLC NAND flash.
Support 8-bit and 16-bit ST/Numony SLC and MLC NAND flash.
Support 8-bit and 16-bit Infineon SLC and MLC NAND flash.
Support 8-bit and 16-bit Sandisk SLC and MLC NAND flash.
Support PowerChip SLC & MLC Nand Flash
Support Spansion 3.3V MirrorBit-Quad Flash
Support SMIC Double Density Flash
Support Actrans Nand Flash
Software configuration to support various new flash memories
Supports up to 8 flash chips.
Proprietary 32-bit CISC microprocessor feature
Proprietary 32-bit CISC processor for USB protocol processing and flash access.
Single cycle instruction period
Integrated 5v to 3.3v voltage regulator
Disk partitions and password check for security disk available
PC boot up as USB Zip Disk, USB Hard Disk or USB CDROM
Auto run function
Low power dissipation
Operating current 50mA (Bus power compatible)
Build-in LDO
Output maximum current up to 300mA
Leading 0.18um CMOS technology
48-pin TQFP /64-pin LQFP package
48-pin CBM2093 supports up to 4 Flash Chips
Windows, Mac and Linux compatible
CBM2093 Datasheet
- 5 -
05/12/2009
3 Block Diagram
CBM2093 Datasheet
- 6 -
05/12/2009
4 Pin Assignment
4.1 TQFP48 (Top Side)
CBM2093 Datasheet
- 7 -
05/12/2009
5 Pin Description
Brief CBM2093 pin functions are shown in the following tables.
I: Input signal
O: Output signal
I/O:
Bi-direction signal
Power signal
Ground signal
pull up
PWR:
GND:
PU:
PD:
pull down
CBM2093 TQFP48 Pin Description
TQFP48
Pin No.
Pin Name
VDD50
VDD33
VDD18_OUT
VDD18_IN
REXT
VDD33
DP
Type
PWR
PWR
PWR
PWR
I
Description
1
Regulator5V Power Input
Regulator 3.3V Power OUT
Regulator 1.8V Out
2
3
4
CORE 1.8V in
5
Connect External Resister for current reference
Padring 3.3V Power
USB Data D+
6
PWR
I/O
7
8
DM
I/O
USB Data D-
9
VSS
GND
I
Padring 3.3V / Logic 1.8V Ground
Crystal Input (12 MHz)
Crystal Output
10
11
12
13
XI
XO
O
VSSU
VDDU
GND
PWR
Analog 1.8V Ground
Analog 1.8V Power
Test Mode Enable Pin
When high , test mode
When low , normal mode
Group 1 Flash Data Bus - bit 7
General I/O port 15
I
14
15
TEST_MODE
PD
FDATA1_7
GPIO15
I/O
PU
CBM2093 Datasheet
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05/12/2009
When select spi mode ,as spi chip select .
(configure as GPIO and clear pin_64( detail in
spi_ctl[13] .when select master mode , configure output ,
otherwise, configure as input.).
Group 1 Flash Data Bus - bit 6
General I/O port 14
FDATA1_6
GPIO14
I/O
PU
16
When select spi mode, as clock out support ligh-tun sensor
(configure as GPIO and clear pin_64( detail in
spi_ctl[13] .when select ligh-tun mode , configure output).
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
VSS
GND
Padring 3.3V / Logic 1.8V Ground
FDATA1_5
GPIO13
FDATA1_4
GPIO12
FDATA1_3
GPIO11
FDATA1_2
GPIO10
FDATA1_1
GPIO9
FDATA1_0
GPIO8
I/O
PU
I/O
PU
I/O
PU
I/O
PU
I/O
PU
I/O
PU
Group 1 Flash Data Bus - bit 5
General I/O port 13
Group 1 Flash Data Bus - bit 4
General I/O port 12
Group 1 Flash Data Bus - bit 3
General I/O port 11
Group 1 Flash Data Bus - bit 2
General I/O port 10
Group 1 Flash Data Bus - bit 1
General I/O port 9
Group 1 Flash Data Bus - bit 0
General I/O port 8
When TEST_MODE =1, as scan clock input.
When TEST_MODE =0, as LED Indication
X_LED
I/O
O
FWRN
FALE
Group Flash Write Enable (active low)
Group Flash Address Latch Enable
O
WP
I
Write Protect Switch Input
FCLE
Group Flash Command Latch Enable
O
VDD33
CLKOFF
FCEN0
FRDN
PWR
Padring 3.3V Power
I
Clock input switch. CLK_OFF=1, select external test clock.
Flash Chip Enable - Chip 0 (active low)
PD
O
O
Group Flash Read Enable (active low)
Group Flash Ready_Busy
1, when select flash_rb1 mode, as
Group Flash
FRB1
/INTR
33
I
Ready_Busy1 signal input(detail in soft_flag [25]).
2, when select intr mode, as external interrupt input
signal(detail in soft_flag [25]).
1, When select test-mode, as scan-chain output
2, When select i2c , as sck
3, When select chip select2/3 mode, as CE3 output
1, When select test_mode, As scan-chain input
2, when select chip select2/3 mode, as CE2 output .(active
when disable test_mode)
/SCK(I2c)
FCEN3
34
35
O
FCEN2
I/O
PU
CBM2093 Datasheet
- 9 -
05/12/2009
1, When select clock input mode
(1), X_CLK_OFF=1, as external input test clock.
2, When select chip select1 mode or spi master mode, as
X_CLK_OUT
/FCEN1
output. ( only active when
de-slect spi slve mode)
(1), select chip select1 mode
[28]/[25]), as CE1 output
X_CLK_OFF =0 or
I/O
PU
36
(detail in soft_flag
(2), otherwise, as normal clock_out ,which defined at
config_r[20].
37
38
39
40
41
42
43
44
45
FRB0
I
Group Flash Ready_Busy0
FDATA0_0
GPIO0
FDATA0_1
GPIO1
FDATA0_2
GPIO2
FDATA0_3
GPIO3
FDATA0_4
GPIO4
FDATA0_5
GPIO5
FDATA0_6
GPIO6
FDATA0_7
GPIO7
I/O
PU
I/O
PU
I/O
PU
I/O
PU
I/O
PU
I/O
PU
I/O
PU
I/O
PU
Group 0 Flash Data Bus - bit 0
General I/O port 0
Group 0 Flash Data Bus - bit 1
General I/O port 1
Group 0 Flash Data Bus - bit 2
General I/O port 2
Group 0 Flash Data Bus - bit 3
General I/O port 3
Group 0 Flash Data Bus - bit 4
General I/O port 4
Group 0 Flash Data Bus - bit 5
General I/O port 5
Group 0 Flash Data Bus - bit 6
General I/O port 6
Group 0 Flash Data Bus - bit 7
General I/O port 7
Chip reset output/ External device reset signal
Low active pulse output
Should connect with RESET pad
46
RST_OUT
O
47
48
RESET
VSSA
I
Reset Sign (active low)
Analog 3.3V Ground
GND
CBM2093 Datasheet
- 10 -
05/12/2009
6 Electrical Characteristics
6.1 Absolute maximum ratings
In accordance with the Absolute Maximum Rating System (IEC 60134).
symbol
VDD33
VDD18
VDD50
parameter
analog supply voltage
digital supply voltage
input voltage
conditions
min
-0.5
max
5.5
unit
v
v
v
-0.5
4.5
-0.5
5.5
DP, DM and
GND pins
-4000
-2000
-40
+4000
+2000
+125
electrostatic
discharge voltage[1]
ILI <
1 A
Vesd
Tstg
v
other pins
storage temperature
ꢀ℃
[1] Equivalent to discharging a 100 pF capacitor via a 1.5 kꢀresistor (Human Body
Model).
6.2 Recommended operating conditions
symbol
VDD33
VDD18
VDD50
Parameter
analog supply voltage
digital supply voltage
input voltage
conditions
min
3.0
1.62
4.5
0
Typ
3.3
1.8
5
max
3.6
1.98
5.5
3.6
-
Unit
V
V
V
Low/Full speed
High speed
3.3
400
-
V
input voltage on analog
I/O pins DP DM
VI(AI/O)
Tamb
0
mV
℃
ambient temperature
0
+70
6.3 Static characteristics
All parameters are measured at VCCA = VCCD = 3.0 to 3.6 V; VAGND = VDGND = 0 V;
Tamb = 40 to 85 ℃;
symbol
ICC
Parameter
Conditions
min
Type max
Unit
mA
Full-speed transmitting and
receiving;
high-speed transmitting and
receiving
-
-
-
29.5
50
-
operating
supply current
suspend
supply current
ICC(susp)
in suspend mode
500
ꢀuA
CBM2093 Datasheet
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05/12/2009
6.4 Dynamic characteristics
All parameters are measured at VCCA = VCCD = 3.0 to 3.6 V; VAGND = VDGND = 0 V;
Tamb = -40 to 85 ℃ ;
symbol
Ts(FDATA*)
Th(FDATA*)
Ts (FCLE*)
Th (FCLE*)
Ts (FALE*)
Th (FALE*)
Ts (FCEN*)
Tpw (FWRN*)
Thh (FWRN*)
Parameter
conditions
min
8
Typ max Unit
FDATA* setup time relative
to rising FWRN* edge
FDATA* hold time relative to
falling FWRN* edge
FCLE* setup time relative to
falling FWRN* edge
FCLE* hold time relative to
rising FWRN* edge
FALE* setup time relative to
falling FWRN* edge
Configured
by firmware
Configured
by firmware
Configured
by firmware
Configured
by firmware
Configured
by firmware
Configured
by firmware
Configured
by firmware
Configured
by firmware
Configured
by firmware
33
33
16
16
16
16
99
33
33
75
75
25
75
25
75
ns
ns
ns
ns
ns
ns
ns
ns
ns
8
8
10
8
FALE* hold time relative to
rising FWRN* edge
FCEN* setup time relative
to falling FWRN* edge
10
-
FWRN* Pulse Width
8
75
75
FWRN* high hold time
8
FDATA* access time
relative to falling FRDN*
edge
Ta(FDATA*)
-5
0
5
ns
Configured
by firmware
Configured
by firmware
Tpw (FRDN*)
Thh (FRDN*)
FWRN* Pulse Width
8
8
33
33
75
75
ns
ns
FWRN* high hold time
Timing diagram for Writing of Data
CBM2093 Datasheet
- 12 -
05/12/2009
Timing diagram for Reading of Data
CBM2093 Datasheet
- 13 -
05/12/2009
7 Mechanical Dimensions
7.1 48-Pin CBM2093 Package Outline Dimension
CBM2093 Datasheet
- 14 -
05/12/2009
8 Copyright Notice
Copyright by Chipsbank Technologies (Shenzhen) Co. Ltd. All Rights Reserved.
Right to make changes —Chipsbank Technologies (Shenzhen) Co., Ltd reserves the right to make
changes in the products - including circuits, standard cells, and/or software - described or contained
herein in order to improve design and/or performance. The information contained in this manual is
provided for the general use by our customers. Our customers should be aware that the personal
computer field is the subject of many patents. Our customers should ensure that they take
appropriate action so that their use of our products does not infringe upon any patents. It is the
policy of Chipsbank Technologies (Shenzhen) Co., Ltd. to respect the valid patent rights of third
parties and not to infringe upon or assist others to infringe upon such rights.
This manual is copyrighted by Chipsbank Technologies (Shenzhen) Co., Ltd. You may not
reproduce, transmit, transcribe, store in a retrieval system, or translate into any language, in any
form or by any means, electronic, mechanical, magnetic, optical, chemical, manual, or otherwise,
any part of this publication without the expressly written permission from Chipsbank Technologies
(Shenzhen) Co.,Ltd
CBM2093 Datasheet
- 15 -
05/12/2009
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