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CL10K50VBI356-3 [ETC]

FPGA ; FPGA产品将打
CL10K50VBI356-3
型号： CL10K50VBI356-3
厂家： ETC    ETC
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FPGA
FPGA产品将打
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LIBERATOR  
CL10K30A  
u Fully Compatible To The Altera® FLEX® 10KA Family  
u Prototype Your System With Altera FPGAs  
u Seamlessly Migrate Production To Clear Logic  
Key Features  
u No ASIC Engineering, No NRE, And No Test Vector  
Development  
u Very Fast, Dense Signal Routing Using Vertical Link  
Interconnect  
u "Gate Array" Option Eliminates Configuration EPROMs  
u Fabricated Using 0.35 Micron CMOS Process  
u Very Low Power Consumption (Active And Standby)  
u High Density  
-
-
-
-
30,000 Usable Gates  
1,728 Logic Elements  
12,288 RAM Bits  
189 Maximum User I/O Pins  
CL10KA Product Family Overview  
Parameter  
CL10K30A  
CL10K50V  
CL10K100A  
Typical Gates  
(Logic and RAM)  
30,000  
50,000  
100,000  
Maximum System Gates  
69,000  
1,728  
216  
116,000  
2,880  
158,000  
4,992  
624  
Logic Elements  
Logic Blocks  
360  
Embedded Array Blocks  
Total RAMBits  
6
10  
12  
12,288  
189  
20,480  
274  
24,576  
406  
Max User I/O Pins  
Speed Grades  
-1, -2, -3  
-1, -2, -3, -4  
-1, -2, -3  
240-pin PQFP  
240-pin RQFP  
356-pin SBGA  
484-pin FBGA  
600-pin SBGA  
144-pin TQFP  
208-pin PQFP  
240-pin PQFP  
256-pin FBGA  
240-pin PQFP  
240-pin RQFP  
356-pin SBGA  
Packages  
10KA tbl 01A  
March 2001  
Page 1  
LIBERATOR CL10K30A  
™
The LIBERATOR CL10KA family offers you all of the time-to-  
market benefits of designing with programmable logic. Simply  
use Altera FLEX 10KA FPGAs to prototype and verify the  
design. Then, take five minutes to submit the bitstream using  
Clear Logic's web site! Within eight weeks, your system can be  
in volume production using compatible Clear Logic devices.  
Description  
LIBERATOR technology frees you to completely design,  
prototype, and verify your custom logic using Altera FLEX 10KA  
products. Clear Logic's innovative technology eliminates NRE  
costs, test vector development, ordering minimums, and long lead  
times. No re-simulation or re-layout is required, because Clear  
Logic offers an architecture that is exactly compatible to the  
functionality of the FPGA prototype. Clear Logic's NoFault® test  
technology ensures complete test coverage through the use of  
special scan test registers.  
The LIBERATOR family is based upon an array of logic  
elements. Each logic element contains a configurable look-up  
table for combinatorial functions and a register for sequential  
operations. Eight logic elements in a group form a block. Logic  
functions and signal routing are defined by Clear Logic's  
proprietary vertical metal links.  
Laser-based configuration allows quick-turn prototyping and  
eliminates NRE costs for photomasks. Inherent CL10KA family  
performance benefits include extremely consistent propagation  
delays, reduced power consumption, and improved immunity to  
noise and upset events.  
Configuration  
The "Gate Array" configuration mode eliminates the need for  
external EPROMs or software configuration. The LIBERATOR  
device is already factory-configured when it is shipped. When  
using the device in the "Gate Array" mode, it powers up fully  
configured. In this mode, if the customer selects INIT_DONE  
option, this pin will always be high.  
Page 2  
LIBERATOR CL10K30A  
Additional  
Information  
For further information on designing with the LIBERATOR  
family, please refer to these documents:  
u AN-01: Requesting a First Article. This document provides  
instructions on how to request first articles by submitting a  
bitstream file to Clear Logic's web site.  
u AN-02: Clear Logic Packaging Guide. This document provides  
specifications and drawings for packages used by the CL10K  
family and other Clear Logic devices.  
u AN-13: LIBERATOR -- A New Way To Design. This document  
describes the most efficient path for custom logic designs up  
to 200K gates using FPGA design techniques and going to  
production with Clear Logic.  
u AN-14: CL10K Technology White Paper. This document  
outlines the technologies employed by the LIBERATOR  
family.  
u AN-15: LIBERATOR System Configuration. This document  
contains a detailed discussion of all aspects of configuring  
CL10K-based systems.  
u AN-16: Introduction to the Clear Logic Verilog Model  
Generator. Clear Logic now has Verilog models of your FPGA  
converted design. Learn what it is and how it can help you.  
u AN-17: Clear Logic LIBERATOR Design Models. This  
document outlines the capabilities and freedom available in  
the Clear Logic Verilog and VHDL design models.  
u AN-18: Debugging Designs Using Clear Logic Models. This  
document shows the enhanced troubleshooting capabilities  
that the Clear Logic LIBERATOR Verilog/VHDL design  
models bring to the system debugging process.  
Page 3  
LIBERATOR CL10K30A  
Block Diagram  
Embedded Array Block (EAB)  
I/O Element  
(IOE)  
IOE IOE IOE IOE  
IOE IOE  
IOE IOE  
IOE  
IOE  
IOE  
IOE  
IOE  
IOE  
Logic Array  
Column  
Interconnect  
EAB  
Logic Building  
Block (LBB)  
IOE  
IOE  
Logic Element (LE)  
IOE  
IOE  
EAB  
Row  
Local Interconnect  
Interconnect  
Logic  
Array  
10KA drw 01  
IOE IOE  
IOE IOE  
IOE IOE  
IOE IOE IOE IOE  
Logical Memory Array (LMA)  
Page 4  
LIBERATOR CL10K30A  
Pin Configuration  
240-Pin  
Pin Name  
144-Pin TQFP  
208-Pin PQFP  
PQFP/RQFP  
256-Pin FBGA  
MSEL0  
77  
108  
124  
P1  
MSEL1  
nSTATUS  
nCONFIG  
DCLK  
76  
107  
52  
123  
60  
R1  
T16  
N4  
35  
74  
105  
155  
2
121  
179  
2
107  
2
B2  
CONF_DONE  
INIT_DONE  
nCE  
C15  
G16  
B1  
14  
19  
26  
106  
3
154  
3
178  
3
nCEO  
nWS  
B16  
B14  
C14  
A16  
A15  
G14  
D15  
B5  
142  
141  
144  
143  
11  
206  
204  
208  
207  
16  
238  
236  
240  
239  
23  
nRS  
nCS  
CS  
RDYnBSY  
CLKUSR  
DATA7  
DATA6  
DATA5  
DATA4  
DATA3  
DATA2  
DATA1  
DATA0  
TDI  
7
10  
11  
116  
114  
113  
112  
111  
110  
109  
108  
105  
4
166  
164  
162  
161  
159  
158  
157  
156  
153  
4
190  
188  
186  
185  
183  
182  
181  
180  
177  
4
D4  
A4  
B4  
C3  
A2  
B3  
A1  
C2  
TDO  
C16  
B15  
P15  
R16  
TCK  
1
1
1
TMS  
34  
50  
58  
TRST  
51  
59  
Dedicated Inputs  
54, 56, 124, 126  
78, 80, 182, 184  
90, 92, 210, 212  
B9, E8, M9, R8  
10K30A tbl 01A  
Page 5  
LIBERATOR CL10K30A  
Pin Configuration  
240-Pin  
PQFP/RQFP  
91, 211  
Pin Name  
144-Pin TQFP  
208-Pin PQFP  
256-Pin FBGA  
Dedicated Clock Pins  
55, 125  
79, 183  
A9, L8  
DEV_CLRn  
DEV_OE  
122  
180  
186  
209  
D8  
128  
213  
C9  
6, 23, 35, 43, 76, 77,  
106, 109, 117, 137,  
145, 181  
5, 16, 27, 37, 47, 57,  
77, 89, 96, 112, 122, H6, H7, H10, J7, J10,  
130, 140, 150, 160,  
E11, F5, F7, F9, F12,  
6, 25, 52, 53, 75, 93,  
123  
VCCINT  
J11, K9, L5, L7, L9,  
5, 22, 34, 42, 66, 84,  
98, 110, 118, 138, 146,  
165, 178, 194  
D12, E6, F8, F10, G6,  
G8, G11, H11, J6, K6,  
K8, K11, L10, M6, N12  
5, 24, 45, 61, 71, 94,  
115, 134  
VCCIO  
-
10, 22, 32, 42, 52, 69, E5, E12, F6, F11, G7,  
85, 93, 104, 125, 135, G9, G10, H8, H9, J8,  
16, 57, 58, 84, 103, 21, 33, 49, 81, 82, 123,  
GNDINT  
GNDIO  
127  
129, 151, 185  
145, 155, 165, 176,  
J9, K7, K10, L6, L11,  
20, 32, 48, 89, 72, 91,  
124, 130, 152, 171,  
188, 201  
15, 40, 50, 66, 85, 104,  
129, 139  
-
-
No connect  
-
-
-
-
Total user I/O Pins  
102  
147  
189  
191  
10K30A tbl 01B  
Page 6  
LIBERATOR CL10K30A  
DC Electrical Specifications  
Absolute Maximum Ratings  
Symbol  
Parameter  
Conditions  
Min  
-0.5  
-2.0  
-25  
Max  
4.6  
Unit  
V
VCC  
Supply Voltage  
DC Input Voltage[1]  
V
I
5.75  
25  
V
IOUT  
TSTG  
TAMB  
TJ  
DC Output Current, per Pin  
Storage Temperature  
Ambient Temperature  
Junction Temperature  
mA  
°C  
°C  
°C  
No Bias  
-65  
150  
135  
135  
Under Bias  
Under Bias  
-65  
10KA tbl 02  
[2]  
Recommended Operating Conditions  
Symbol  
Parameter  
Conditions  
Min  
Max  
Unit  
VCCINT  
Supply Voltage, Internal Logic and Input Buffers  
Commercial Grade Devices  
3.00  
3.00  
3.60  
3.60  
V
V
Industrial Grade Devices  
VCCIO  
DC Input Voltage for 3.3VOperation  
Commercial Grade Devices  
Industrial Grade Devices  
3.00  
3.00  
3.60  
3.60  
V
V
VCCIO  
DC Input Voltage for 2.5VOperation  
Commercial Grade Devices  
Industrial Grade Devices  
2.30  
2.30  
2.70  
2.70  
V
V
V
Input Voltage  
-0.5  
0
5.75  
V
V
I
VO  
TA  
Output Voltage  
VCCIO  
Operating Temperature  
Commercial Temperature Range  
Industrial Temperature Range  
0
-40  
70  
85  
°C  
°C  
tR  
tF  
Input Signal Rise Time  
Input Signal Fall Time  
40  
40  
ns  
ns  
10KA tbl 03B  
Page 7  
LIBERATOR CL10K30A  
DC Electrical Specifications cont.  
DC Electrical Characteristics (over the operating range)  
Typ[3]  
Symbol  
Parameter  
Input HIGH Voltage  
Input LOW Voltage  
Conditions  
Min  
Max  
5.75  
Unit  
Lower of  
1.7 or 0.5  
x VCCINT  
V
IH  
V
V
IL  
-0.5  
2.4  
0.3 x VCCINT  
V
V
3.3-VHigh-Level TTL Output  
Voltage  
3.3-VHigh-Level CMOS  
Output Voltage  
3.3-VHigh-Level PCI Output  
Voltage  
IOH = -8 mADC, VCCIO = 3.00 V  
IOH = -0.1 mADC, VCCIO = 3.00 V  
VCCIO-0.2  
V
V
V
V
V
V
V
V
V
V
V
IOH = -0.5 mADC, VCCIO = 3 to 3.60 V 0.9 x VCCIO  
VOH  
IOH = -0.1 mADC, VCCIO = 2.30 V  
IOH = -1 mADC, VCCIO = 2.30 V  
IOH = -2 mADC, VCCIO = 2.30 V  
IOL = 9 mADC, VCCIO = 3.00 V  
IOL = 0.1 mADC, VCCIO = 3.00 V  
IOL = 1.5 mADC, VCCIO = 3 to 3.60 V  
IOL = 0.1 mADC, VCCIO = 2.30 V  
IOL = 1 mADC, VCCIO = 2.30 V  
IOL = 2 mADC, VCCIO = 2.30 V  
2.1  
2.0  
1.7  
2.5-VHigh-Level Output  
Voltage  
3.3-VLow-Level TTL Output  
Voltage  
3.3-VLow-Level CMOS  
Output Voltage  
3.3-VLow-Level PCI Output  
Voltage  
0.45  
0.2  
0.1 x VCCIO  
0.2  
VOL  
2.5-VLow-Level Output  
Voltage  
0.4  
0.7  
IIN  
IOZ  
Input Leakage Current  
Output Leakage Current  
Standby Current  
V = 5.3Vto -0.3V  
-10  
-10  
10  
10  
10  
µA  
µA  
I
VO = 5.3Vto -0.3V  
ICC0  
V = GND, no load  
I
0.3  
mA  
10KA tbl 04B  
Capacitance[4]  
Symbol  
CIN  
Parameter  
Input Capacitance  
Output Capacitance  
Conditions  
Min  
Max  
Unit  
pF  
V = 0 V, f = 1.0 MHz  
8
8
IN  
COUT  
VOUT = 0 V, f = 1.0 MHz  
pF  
10K tbl 05B  
Page 8  
LIBERATOR CL10K30A  
AC Electrical Specifications  
I/O Element Timing Parameters [5]  
Speed: -1  
Speed: -2  
Speed: -3  
Symbol  
tIOD  
Parameter  
Min  
Max  
Min  
Max  
2.6  
Min  
Max Unit  
IOE Register Data Delay  
2.2  
0.3  
0.2  
0.5  
3.4  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tIOC  
IOE Register Control Signal Delay  
IOE Register Clock to Output Delay  
0.3  
0.5  
0.3  
0.8  
tIOCO  
0.2  
tIOCOMB IOE Combinatorial Delay  
tIOSU IOE Register Setup Time Before Clock  
tIOH  
0.6  
1.4  
0.9  
1.7  
1.1  
2.2  
1.4  
IOE Register Hold Time After Clock  
IOE Register Clear Delay  
tIOCLR  
0.7  
1.9  
0.8  
2.2  
1.0  
2.9  
Output Buffer and Pad Delay  
tOD1  
tOD2  
tOD3  
ns  
ns  
ns  
Slow Slew Rate = off, VCCIO = VCCINT  
Output Buffer and Pad Delay  
Slow Slew Rate = off, VCCIO = Low Voltage  
4.8  
7.0  
5.6  
8.2  
7.3  
Output Duffer and Pad Delay  
Slow Slew Rate = on  
10.8  
[6]  
tZX  
2.2  
2.2  
2.6  
2.6  
3.4  
3.4  
ns  
ns  
Output Buffer Disable Delay  
Output Buffer Disable Delay  
tZX1  
[6]  
Slow Slew Rate = off, VCCIO = VCCINT  
Output Buffer Disable Delay  
Slow Slew Rate = off, VCCIO = Low  
tZX2  
5.1  
7.3  
6.0  
8.6  
7.8  
ns  
ns  
Voltage[6]  
Output Buffer Disable Delay  
Slow Slew Rate = on[6]  
tZX3  
11.3  
IOE Input Pad and Buffer to IOE Register  
Delay  
tINREG  
tIOFD  
4.4  
3.8  
3.8  
5.2  
4.5  
4.5  
6.8  
5.9  
5.9  
ns  
ns  
ns  
IOE Register Feedback Delay  
IOE Input Pad and Buffer to Interconnect  
Delay  
tINCOMB  
10KA tbl 06C  
Page 9  
LIBERATOR CL10K30A  
AC Electrical Specifications cont.  
External Timing Parameters[4]  
Speed: -1  
Speed: -2  
Speed: -3  
Symbol  
Parameter  
Min  
Max  
Min  
Max  
Min  
Max Unit  
Register to Register Delay via Four LEs,  
Three Row Interconnects, and Four Local  
Interconnects  
tDRR  
11.0  
13.0  
17.0  
ns  
ns  
Setup Time with Global Clock at IOE  
Register  
tINSU  
2.5  
3.1  
3.9  
tINH  
Hold time with Global Clock at IOE Register  
0.0  
2.0  
0.0  
2.0  
0.0  
2.0  
ns  
ns  
tOUTCO Output Data Hold Time After Clock  
5.4  
6.2  
8.3  
10KA tbl 07C  
Logic Element Timing Parameters[5]  
Speed: -1  
Speed: -2  
Speed: -3  
Symbol  
tLUT  
Parameter  
Look-up Table Delay for Data-in  
Look-up Table Delay for Carry-in  
Min  
Max  
0.8  
Min  
Max  
1.1  
Min  
Max Unit  
1.5  
1.0  
ns  
ns  
tCLUT  
0.6  
0.7  
Look-up Table Delay for LE Register  
Feedback  
tRLUT  
1.2  
1.5  
2.0  
ns  
tPACKED Data-in to Packed Register Delay  
0.6  
1.3  
0.2  
0.8  
0.6  
0.9  
1.1  
0.4  
0.6  
0.6  
1.5  
0.3  
1.0  
0.8  
1.1  
1.3  
0.6  
0.7  
1.0  
2.0  
0.4  
1.3  
1.0  
1.4  
1.7  
0.7  
0.9  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tEN  
LE Register Enable Delay  
Carry-in to Carry-out Delay  
Data-in to Carry-out Delay  
tCICO  
tCGEN  
tCGENR LE Register Feedback to Carry-out Delay  
tCASC  
tC  
Cascade Chain Routing Ddelay  
LE Register Control Signal Delay  
LE Register Clock-to-output Delay  
Combinatorial Delay  
tCO  
tCOMB  
tSU  
LE Register Setup Time Before Clock  
LE Register Hold Time After Clock  
LE Register Preset Delay  
LE Register Clear Delay  
0.9  
1.1  
0.9  
1.3  
1.4  
1.4  
tH  
tPRE  
tCLR  
tCH  
0.5  
0.5  
0.6  
0.6  
0.8  
0.8  
Clock High Time  
3.0  
3.0  
3.5  
3.5  
4.0  
4.0  
tCL  
Clock Low Time  
10KA tbl 08C  
Page 10  
LIBERATOR CL10K30A  
AC Electrical Specifications cont.  
Interconnect Timing Parameters[5]  
Speed: -1  
Speed: -2  
Speed: -3  
Symbol  
Parameter  
Min  
Max  
Min  
Max  
Min  
Max Unit  
Delay from Dedicated Input Pin to IOE  
Control Input  
tDIN2IOE  
3.9  
1.2  
3.2  
3.0  
1.2  
0.1  
4.4  
5.1  
ns  
ns  
ns  
ns  
ns  
ns  
Delay from Dedicated Input Pin to LE or EAB  
Control Input  
tDIN2LE  
1.5  
3.6  
3.5  
1.5  
0.1  
1.9  
4.5  
4.6  
1.9  
0.2  
Delay from Dedicated Input or Clock Pin to  
LE or EAB Data  
tDIN2DATA  
tDCLK2IOE Delay from Dedicated Clock Pin to IOE Clock  
Delay from Dedicated Clock Pin to LE or EAB  
tDCLK2LE  
Clock  
tSAMELAB Delay from an LE to LE in Same LAB  
Delay for Driving a Row IOE, LE or EAB to a  
tSAMEROW  
2.3  
2.4  
2.7  
ns  
Row IOE, LE or EAB in the Same Row  
Delay from an LE to IOE in the Same  
t
1.3  
3.6  
5.9  
3.5  
0.3  
1.4  
3.8  
6.2  
3.8  
0.4  
1.9  
4.6  
7.3  
4.1  
0.5  
ns  
ns  
ns  
ns  
ns  
SAMECOLUMN Column  
Delay for Driving a Column IOE, LE or EAB to  
an LE or EAB in a Different Row  
tDIFFROW  
tTWOROWS  
tLEPERIPH  
tLABCARRY  
Delay for Driving a Row IOE or EAB to an LE  
or EAB in a Different Row  
Delay from an LE to IOE Control Signal via  
the Peripheral Dontol Bus  
Delay from an LE Carry-out Signal to an LE  
Carry-in Signal in a Different LAB  
Delay from an LE Cascade-out Signal to an  
LE Cascade-in Signal in a Different LAB  
tLABCASC  
0.9  
1.1  
1.4  
ns  
10KA tbl 09C  
Page 11  
LIBERATOR CL10K30A  
AC Electrical Specifications cont.  
EAB Timing Parameters[5]  
Speed: -1  
Speed: -2  
Speed: -3  
Symbol  
Parameter  
Min  
Max  
Min  
Max  
Min  
Max Unit  
Delay from Data or Address to EAB for  
Combinatorial Input  
tEABDATA1  
5.5  
1.1  
2.4  
2.1  
6.5  
1.3  
2.8  
2.5  
8.5  
ns  
ns  
ns  
ns  
Delay from Data or Address to EAB for  
Registered Input  
tEABDATA2  
1.8  
3.7  
3.2  
tEABWE1 WE Delay to EAB for Combinatorial Input  
tEABWE2 WE Delay to EAB for Registered Input  
tEABCLK EAB Register Clock Delay  
tEABCO EAB Register Clock-to-output Delay  
tEABBYPASS Bypass Register Delay  
0.0  
1.7  
0.0  
0.0  
2.0  
0.0  
0.2  
2.6  
0.3  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tEABSU  
tEABH  
tAA  
EAB Register Setup Time  
EAB Register Hold Time  
Address Access Delay  
Write Pulse Width  
1.2  
0.1  
1.4  
0.1  
1.9  
0.3  
4.2  
5.0  
6.5  
tWP  
3.8  
0.1  
4.5  
0.1  
5.9  
0.2  
Data Setup Time Before Falling Edge of  
Write Pulse  
tWDSU  
tWDH  
tWASU  
tWAH  
ns  
ns  
ns  
ns  
Data Hold Time After Falling Edge of Write  
Pulse  
0.1  
0.1  
0.1  
0.1  
0.1  
0.1  
0.2  
0.2  
0.2  
Address Setup Time Before Rising Edge of  
Write Pulse  
Address Hold After Falling Edge of Write  
Pulse  
tWO  
tDD  
Write Enable to Date Output Delay  
Data-in to Date-out Delay  
3.7  
3.7  
0.0  
4.4  
4.4  
0.1  
6.4  
6.4  
0.6  
ns  
ns  
ns  
ns  
ns  
tEABOUT Data-out Delay  
tEABCH  
tEABCL  
Clock High Time  
Clock Low Time  
3.0  
3.8  
3.5  
4.5  
4.0  
5.9  
10KA tbl 10C  
Page 12  
LIBERATOR CL10K30A  
AC Electrical Specifications cont.  
EAB Timing Parameters[5]  
Speed: -1  
Speed: -2  
Speed: -3  
Symbol  
Parameter  
Min  
Max  
Min  
Max  
Min  
Max Unit  
tEABAA  
EAB Address Access Delay  
9.7  
11.6  
16.2  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tEABRCCOMB EAB Asynchronous Read Cycle Time  
tEABRCREG EAB Synchronous Read Cycle Time  
tEABWP EAB Write Pulse Width  
9.7  
5.9  
3.8  
4.0  
9.8  
11.6  
7.1  
16.2  
9.7  
4.5  
5.9  
tEABWCCOMB EAB Asynchronous Write Cycle Time  
tEABWCREG EAB Synchronous Write Cycle Time  
4.7  
6.3  
11.6  
16.6  
tEABDD  
EAB Data-in to Data-out Delay  
9.2  
1.7  
11.0  
2.1  
16.1  
3.4  
EAB Clock-to-output Delay Using Output  
Registers  
tEABDATACO  
ns  
ns  
ns  
ns  
ns  
EAB Data/Address Setup Time Using Input  
Register  
tEABDATASU  
2.3  
0.0  
3.3  
0.0  
2.7  
0.0  
3.9  
0.0  
3.5  
0.0  
4.9  
0.0  
EAB Data/Address Hold Time Using Input  
Register  
tEABDATAH  
tEABWESU EAB WE Setup When Using Input Register  
EAB WE Hold Time When Using Input  
Register  
tEABWESH  
EAB Data Setup Time to Falling Edge of  
tEABWDSU  
3.2  
0.0  
3.7  
0.0  
3.8  
0.0  
4.4  
0.0  
5.0  
0.0  
5.1  
0.0  
ns  
ns  
ns  
Write Pulse When Not Using Input Registers  
EAB Data Hold Time After Falling Edge of  
tEABWDH  
Write Pulse When Not Using Input Registers  
EAB Address Setup Time to Rising Edge of  
tEABWASU  
Write Pulse When Not Using Input Registers  
EAB Address Hold Time After Falling Edge  
tEABWAH of Write Pulse When Not Using Input  
Registers  
ns  
ns  
tEABWO EAB WE to Data Output Delay  
6.1  
7.3  
11.3  
10KA tbl 11C  
Page 13  
LIBERATOR CL10K30A  
AC Electrical Specifications cont.  
External Bi-Directional Timing Parameters[5]  
Speed: -1  
Speed: -2  
Speed: -3  
Symbol  
Parameter  
Min  
Max  
Min  
Max  
Min  
Max Unit  
Setup for Bi-directional Pins with Global  
Clock at Adjacent LE Registers  
tINSUBIDIR  
4.2  
4.9  
0.0  
2.0  
6.8  
0.0  
2.0  
ns  
Hold Time for Bi-directional Pins with Global  
Glock at Adjacent LE Registers  
tINHBIDIR  
tOUTCOBIDIR  
tXZBIDIR  
0.0  
2.0  
ns  
Clock-to-output Delay for Bi-directional Pins  
with Global Clock at IOE Register  
5.4  
6.2  
6.2  
6.2  
7.5  
7.5  
8.3  
9.8  
9.8  
ns  
ns  
ns  
Synchronous IOE Output Buffer Disable  
Delay  
Synchronous IOE Output Buffer Disable  
Delay, Slow Slew Rate = off  
tZXBIDIR  
10KA tbl 12C  
AC Test Conditions  
(A)  
(B)  
All Input Pulses  
703 Ω  
703 Ω  
VCCIO  
VCCIO  
3.0V  
90%  
10%  
90%  
OUTPUT  
OUTPUT  
10%  
35 pF  
8.06k Ω  
5 pF  
8.06k Ω  
GND  
Includes jig  
capacitance  
Includes jig  
capacitance  
≤ 3ns  
≤ 3ns  
10KA drw 02  
A: Test fixture set-up A is for general testing.  
B: Test fixture set-up B is for high Z testing (tZX#).  
Notes to Tables  
1. During transitions, inputs may undershoot to -2.0V or overshoot to 5.75V for  
periods shorter than 20ns. Otherwise, minimum DC input voltage is -0.5V.  
2. Device inputs may be driven before VCCINT and VCCIO are powered.  
3. Typical values are at VCC of 3.3 volts and ambient temperature of 25 ºC.  
4. Guaranteed but not tested. Characterized initially, and after any design changes  
which may affect these parameters.  
5. Internal timing delays are based on characterization, and cannot be explicitly  
tested. Internal timing parameters should be used for performance estimation  
only.  
6. Use AC Test Conditions set-up B for these parameters.  
Revision History  
20 Apr. 2000:  
01 Dec. 2000:  
04 Jan. 2001:  
29 Mar. 2001:  
Created new document  
Updated package availability and additional literature available  
Corrected table on AC Electrical Specifications  
Added Pin Configuration for the FBGA 256-pin package  
Page 14  
LIBERATOR CL10K30A  
Ordering Information  
Part Number  
CL10K30ATC144-3  
CL10K30ATC144-2  
CL10K30ATC144-1  
CL10K30ATI144-3  
CL10K30AQC208-3  
CL10K30AQC208-2  
CL10K30AQC208-1  
CL10K30AQI208-3  
CL10K30AQC240-3  
CL10K30AQC240-2  
CL10K30AQC240-1  
CL10K30AQI240-3  
CL10K30AFC256-3  
CL10K30AFC256-2  
CL10K30AFC256-1  
CL10K50VBC356-3  
CL10K50VBC356-2  
CL10K50VBC356-1  
CL10K50VBI356-3  
Temperature Range  
Package Type  
Speed  
Altera Equivalent  
EPF10K30ATC144-3  
EPF10K30ATC144-2  
EPF10K30ATC144-1  
EPF10K30ATI144-3  
EPF10K30AQC208-3  
EPF10K30AQC208-2  
EPF10K30AQC208-1  
EPF10K30AQI208-3  
EPF10K30AQC240-3  
EPF10K30AQC240-2  
EPF10K30AQC240-1  
EPF10K30AQI240-3  
EPF10K30AFC256-3  
EPF10K30AFC256-2  
EPF10K30AFC256-1  
EPF10K30ABC356-3  
EPF10K30ABC356-2  
EPF10K30ABC356-1  
Commercial  
144-pin TQFP  
-3  
-2  
-1  
-3  
-3  
-2  
-1  
-3  
-3  
-2  
-1  
-3  
-3  
-2  
-1  
-3  
-2  
-1  
-3  
Industrial  
Commercial  
208-pin Plastic QFP  
240-pin Plastic QFP  
256-pin FBGA  
Industrial  
Commercial  
Industrial  
Commercial  
Commercial  
356-pin SBGA  
Use CL10K50VBC356*  
Industrial  
EPF10K30ABI356-3  
10K30A tbl 02  
* The SBGA is not offered for the CL10K30A. Use the CL10K50V. This can be done by locking the I/Os in  
MAX+PLUS® II and recompiling to a CL10K50V. Test the part on your board with an Altera FLEX® EPF10K50V  
and then submit the bitstream to Clear Logic for production.  
Page 15  
LIBERATOR CL10K30A  
Page 16  

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