CLC440AJP [ETC]
IC-HI-SPD VOLT FBK OP-AMP ; IC- HI- SPD FBK VOLT OP- AMP\n
| 型号： | CLC440AJP |
| 厂家： | 
ETC |
| 描述： | IC-HI-SPD VOLT FBK OP-AMP
|
| 文件： | 总8页 (文件大小：363K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
August 1996
N
Comlinear CLC440
High-Speed, Low-Power, Voltage Feedback Op Amp
General Description
Features
■
Unity-gain stable
The Comlinear CLC440 is a wideband, low-power, voltage feedback
op amp that offers 750MHz unity-gain bandwidth, 1500V/µs slew
rate, and 90mA output current. For video applications, the CLC440
sets new standards for voltage feedback monolithics by offering
the impressive combination of 0.015% differential gain and
0.025° differential phase errors while dissipating a mere 70mW.
■
High unity-gain bandwidth: 750MHz
Ultra-low differential gain: 0.015%
Very low differential phase: 0.025°
Low power: 70mW
Extremely fast slew rate: 1500V/µs
High output current: 90mA
■
■
■
■
■
■
■
Low noise: 3.5nV/√Hz
Dual ±2.5V to ±6V or single 5V to 12V supplies
The CLC440 incorporates the proven properties of Comlinear’s
current feedback amplifiers (high bandwidth, fast slewing, etc.) into a
“classical” voltage feedback architecture. This amplifier possesses
truly differential and fully symmetrical inputs both having a high
900kΩ impedance with matched low input bias currents.
Furthermore, since the CLC440 incorporates voltage feedback, a
specific R is not required for stability. This flexibility in choosing R
Applications
■
Professional video
■
Graphics workstations
■
Test equipment
■
■
■
■
■
■
Video switching & routing
Communications
Medical imaging
A/D drivers
Photo diode transimpedance amplifiers
Improved replacement for CLC420 or OPA620
f
f
allows for numerous applications in wideband filtering and integration.
Unlike several other high-speed voltage feedback op amps, the
CLC440 operates with a wide range of dual or single supplies
allowing for use in a multitude of applications with limited supply
availability. The CLC440’s low 3.5nV/√Hz(e ) and 2.5pA/√Hz(i )
Frequency Response (AV = +2V/V)
n
n
noise sets a very low noise floor.
Generator Waveforms
Typical Application
10MHz to 40MHz Square and Triangular Wave Generator
Pinout
DIP & SOIC
© 1996 National Semiconductor Corporation
Printed in the U.S.A.
http://www.national.com
(A = +2, R = R = 250Ω: Vcc = + 5V, RL = 100Ω unless specified)
CLC440 Electrical Characteristics
V
f
g
PARAMETERS
CONDITIONS
TYP
MIN/MAX RATINGS
0 to 70˚C -40 to 85˚C
UNITS
NOTES
Ambient Temperature
CLC440
+25˚C
+25˚C
FREQUENCY DOMAIN RESPONSE
-3dB bandwidth AV =+2
Vout < 0.2Vpp
out < 4.0Vpp
Vout < 0.2Vpp
out < 0.2Vpp
260
190
750
230
0.05
0.8
165
150
165
135
135
130
MHz
MHz
MHz
MHz
dB
deg
%
B
V
-3dB bandwidth AV =+1
gain bandwidth product
gain flatness
linear phase deviation
differential gain
V
V
V
< 2.0V DC to 75MHz
< 2.0V DC to 75MHz
0.15
1.2
0.03
0.05
0.20
1.5
0.04
0.06
0.20
1.5
0.04
0.06
out
pp
4o.4u3t MHz, pRpL=150Ω
4.43MHz, RL=150Ω
0.015
0.025
differential phase
deg
TIME DOMAIN RESPONSE
rise and fall time
2V step
4V step
2V step
4V step
1.5
3.2
10
2.0
4.2
14
2.2
4.5
16
2.5
5.0
16
ns
ns
ns
settling time to 0.05%
overshoot
7
13
13
13
%
slew rate
4V step, ±0.5V crossing
1500
900
750
600
V/µs
DISTORTION AND NOISE RESPONSE
2nd harmonic distortion
2Vpp, 5MHz
-64
-52
-70
-51
-59
-46
-65
-45
-59
-46
-64
-43
-59
-46
-64
-43
dBc
dBc
dBc
dBc
2Vpp, 20MHz
2Vpp, 5MHz
2Vpp, 20MHz
B
B
3rd harmonic distortion
equivalent input noise
voltage
>1MHz
>1MHz
3.5
2.5
4.5
3.5
5.0
4.0
5.0
4.0
nV/√Hz
pA/√Hz
current
STATIC DC PERFORMANCE
input offset voltage
average drift
input bias current
average drift
1.0
5.0
10
3.0
30
3.5
10
35
50
4.0
10
40
60
mV
µV/°C
µA
A
A
30
nA/°C
input offset current
average drift
power supply rejection ratio
common-mode rejection ratio
supply current
0.5
3.0
65
80
7.0
2.0
2.0
10
58
60
8.0
3.0
10
58
60
8.0
µA
nA/°C
dB
dB
mA
A
A
A
DC
DC
RL= ∞
58
65
7.5
MISCELLANEOUS PERFORMANCE
input resistance
input capacitance
common-mode
900
1.2
0.5
±3.0
±2.5
±3.0
±90
500
2.0
1.0
±2.8
±2.3
±2.8
±80
400
2.0
1.0
±2.7
±2.2
±2.7
±65
300
2.0
1.0
±2.7
±2.2
±2.7
±45
kΩ
pF
pF
V
V
V
common-mode
differential-mode
common-mode
RL= 100Ω
input voltage range
output voltage range
output voltage range
output current
RL= ∞
mA
Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are
determined from tested parameters.
Absolute Maximum Ratings
voltage supply
Ordering Information
±6V
Model
Temperature Range
Description
Iout is short circuit protected to ground
common-mode input voltage
CLC440AJP
CLC440AJE
CLC440ALC
CLC440A8B
-40 C to +85 C
8-pin PDIP
8-pin SOIC
dice
8-pin hermetic CerDIP,
MIL-STD-883
dice, MIL-STD-883
˚
˚
±
Vcc
-40 C to +85 C
˚
˚
maximum junction temperature
storage temperature range
+175 C
˚
-40 C to +85 C
˚
˚
-55 C to +125 C
-65 C to +150 C
˚
˚
˚
˚
lead temperature (soldering 10 sec)
+300 C
˚
CLC440AMC
Contact factory for SMD number.
-55 C to +125 C
˚ ˚
Package Thermal Resistance
Notes
Package
θjc
θja
A) J-level: spec is 100% tested at +25 C, sample tested at +85 C.
LC/MC-level: spec is 100% wafer probed at +25 C.
B) J-level: spec is sample tested at +25 C.
˚
˚
Plastic (AJP)
Surface Mount (AJE)
CerDip
90 /W
105 /W
˚
˚
˚
110 /W
130 /W
˚
˚
40 /W
130 /W
˚
˚
˚
http://www.national.com
2
(A = +2, R = 250Ω: Vcc = + 5V, RL = 100Ω unless specified)
CLC440 Typical Performance Characteristics
V
f
Non-Inverting Frequency Response
Inverting Frequency Response
Frequency Response vs. Load
AV = 1(Rf = 0)
AV = -1
RL=1K
Gain
Gain
Gain
AV = 2
AV = -2
RL=100
AV = -10
AV = 5
(Rf = 500Ω)
RL=50
AV = 10
AV = -5
AV = 2
AV -1
RL=1K
Phase
Phase
Phase
RL=50
0
-180
-225
-270
-315
-360
0
AV = 1
-45
-90
-135
-180
-45
-90
-135
-180
AV = 10
AV -10
AV = 5
AV -5
A
V -2
RL=100
100
1
10
100
1000
1
10
100
1000
1
10
1000
Frequency (MHz)
Frequency (MHz)
Frequency (MHz)
Frequency Response vs. Vout
Frequency Response vs. Capacitive Load
Gain Flatness and Linear Phase
CL = 10pF
Vout = 200mVpp
Vout = 2Vpp
R
s = 50
Gain
Gain
Gain
CL = 100pF
s = 30
CL = 1000pF
Rs = 5
R
Vout = 5Vpp
Vout = 2Vpp
CL = 10pF
CL = 100pF
Phase
Phase
0
0
Phase
CL = 1000pF
-45
-90
-135
-180
-45
-90
-135
-180
Vout = 5Vpp
+
Rs
-
CL 1k
Vout = 200mVpp
1
10
100
1000
1
10
100
1000
0
75
Frequency (MHz)
Frequency (MHz)
BW vs. Gain for Transimpedance Configuration
Frequency (7.5MHz/div)
Open Loop Gain and Phase
Equivalent Input Noise
80
60
40
20
0
0
4
400
320
240
160
80
10
10
Gain
C
= 1pF
d
Cf
Example
Cf
Rf
BW
123
0
8
Voltage = 3.5nV/√Hz
Current = 2.5pA/√Hz
C
d
= 5pF
1000
1.6
Phase
See dashed lines
-90
-180
-270
12
16
C
= 20pF
d
BW
1000
-20
20
0
1
100M
1
10k
100k
1M
1k
10M
100M
100
10000
100
1k
10k
100k
1M
10M
Frequency (Hz)
Rf
Frequency (Hz)
Harmonic Distortion vs. Frequency
PSRR, CMRR, and Closed Loop Rout
1dB Compression
45
35
25
15
5
100
-45
-55
-65
-75
-85
-95
Vo = 2Vpp
5MHz
CMRR
PSRR
80
60
40
20
20MHz
50MHz
2nd RL = 100
+
-
Pout
50Ω
100MHz
3rd RL = 100
2nd RL = 1k
3rd RL = 1k
50Ω
250Ω
250Ω
Rout
0
0.1
1
10
50
10k
1M
10M
-4
0
4
8
12
16
100k
100M
Frequency (MHz)
Frequency (Hz)
Output Power (Pout
)
2-Tone, 3rd Order Intermodulation Intercept
Input and Output VSWR
Differential Gain and Phase
50
Input
2.2
1.8
1.4
1.0
+
50Ω
0.12
0.08
0.04
0
Phase
Positive Sync
40
30
20
10
0
50Ω
-
250Ω
50Ω
Output
Gain
Negative Sync
Output
Input
+
50Ω
50Ω
Pout
Phase
Negative Sync
-
250Ω
250Ω
Gain
Positive Sync
1
10
100
0
40
80
120
160
200
1
2
3
4
Frequency (MHz)
Frequency (20MHz/div)
Number of 150Ω Loads
3
http://www.national.com
(A = +2, R = 250Ω: Vcc = + 5V, RL = 100Ω unless specified)
CLC440 Typical Performance Characteristics
V
f
Pulse Response
Typical DC Errors vs. Temperature
0.05% Settling Time vs. Capacitive Load
2.0
1.0
0
0.4
6
80
60
55
45
Rs
AV = +2
0
2
los
-0.4
-0.8
-1.2
-2
-6
-10
+
Rs
40
20
0
35
25
15
-
CL 1k
lb
Vio
-1.0
-2.0
AV = -2
Ts
-1.6
-14
Time (5ns/div)
-60
-20
20
60
140
10
100
100
1000
Temperature (C°)
Load Capacitance CL (pF)
Short Term Settling Time
Long Term Settling Time
Ib and Ios vs. Common-Mode Voltage
0.2
0.2
20
10
0
2.0
0.1
0
0.1
0
1.0
0
Ib
los
-10
-20
-1.0
-2.0
-0.1
-0.2
-0.1
-0.2
0
20
40
60
80
100
10-9 10-8 10-7 10-6 10-5 10-4 10-3 10-2 10-1 100
-4.0
-2.4
-0.8
0.8
2.4
4.0
Time (ns)
Time (s)
Common-Mode Input Voltage (V)
APPLICATION INFORMATION
General Design Equations
Output Drive and Settling Time Performance
The CLC440 is a unity gain stable voltage feedback
amplifier. The matched input bias currents track well over
temperature. This allows the DC offset to be minimized
by matching the impedance seen by both inputs.
The CLC440 has large output current capability. The
90mA of output current makes the CLC440 an excellent
choice for applications such as:
Video Line Drivers
Distribution Amplifiers
•
•
Gain
The non-inverting and inverting gain equations for the
CLC440 are as follows:
When driving a capacitive load or coaxial cable, include
a series resistance R to back match or improve settling
s
time. Refer to the “Settling Time vs. Capacitive Load”
plot in the typical performance section to determine the
recommended resistance for various capacitive loads.
R
f
Non-inverting Gain: 1+
R
g
R
R
f
When driving resistive loads of under 500Ω, settling time
performance diminishes. This degradation occurs
because a small change in voltage on the output causes
a large change of current in the power supplies. This
current creates ringing on the power supplies. A small
resistor will dampen this effect if placed in series with the
6.8µF bypass capacitor.
−
Inverting Gain:
g
Gain Bandwidth Product
The CLC440 is a voltage feedback amplifier, whose
closed-loop bandwidth is approximately equal to the
gain-bandwidth product (GBP) divided by the gain (Av).
For gains greater than 5, Av sets the closed-loop band-
width of the CLC440.
Noise Figure
Noise Figure (NF) is a measure of noise degradation
caused by an amplifier.
GBP
Closed Loop Bandwidth =
A
v
2
R +R
S /N
e
ni
(
)
g
f
i
i
NF = 10LOG
= 10LOG
A =
v
2
S /N
e
R
o
o
t
g
where,
GBP = 230MHz
e = Total Equivalent Input Noise Density
ni
Due to the Amplifier
e = Thermal Voltage Noise (
For gains less than 5, refer to the frequency response
plots to determine maximum bandwidth.
)
seq
t
4kTR
http://www.national.com
4
Noise Figure vs. Source Resistance
Figure 1 shows the noise model for the non-inverting
amplifier configuration. The model includes all of the
following noise sources:
25
R (Ω) NF Unterminated NF Terminated
s
50
12.03dB
3.13dB
17.90dB
6.15dB
20
15
10
5
R
OPT
Input voltage noise (e )
•
n
Input current noise (i = i = i )
Terminated
•
n
n+
n-
Thermal Voltage Noise (e ) associated with each
external resistor
•
t
Ropt = 2800Ω
Unterminated
en
+
*
CLC440
Rseq
in+
*
*
Ropt = 1400Ω
1k
-
0
4kTR
10
100
10k
100k
seq
*
Rf
Source Resistance (Ω)
*
4kTR
in-
f
Rg
4kTR
Figure 2: Noise Figure vs. Source Resistance
These boards were laid out for optimum, high-speed
performance. The ground plane was removed near the
input and output pins to reduce parasitic capacitance.
And all trace lengths were minimized to reduce series
inductances.
g
*
Rseq = Rs for Unterminated Systems
seq = Rs II RT for Terminated Systems
R
Figure 1: Non-inverting Amplifier Noise Model
Supply bypassing is required for the amplifiers
performance. The bypass capacitors provide a low
impedance return current path at the supply pins. They
also provide high frequency filtering on the power supply
traces. 6.8µF tantalum, 0.01µF ceramic, and 500pF
ceramic capacitors are recommended on both supplies.
Place the 6.8µF capacitors within 0.75 inches of the
power pins, and the 0.01µF and 500pF capacitors less
than 0.1 inches from the power pins.
The total equivalent input noise density is calculated
by using the noise model shown. Equations 1 and 2
represent the noise equation and the resulting equation
for noise figure.
2
2
eni
=
en2 +in Rseq2 + R IIR
+ 4kTRseq + 4kT R IIR
(
)
(
)
g
g
f
f
Equation 1: Noise Equation
2
Dip sockets add parasitic capacitance and inductance
which can cause peaking in the frequency response and
overshoot in the time domain response. If sockets are
necessary, flush-mount socket pins are recommended.
The device holes in the 730055 evaluation board are
sized for Cambion P/N 450-2598 socket pins, or their
functional equivalent.
2
2
2
e
+ i
R
+ R IIR
+ 4kTR
+ 4kT R IIR
(
)
(
)
n
n
seq
g
seq
g
f
f
NF = 10LOG
4kTR
seq
Equation 2: Noise Figure Equation
The noise figure is related to the equivalent source
resistance (R ) and the parallel combination of R and
seq
f
R
To minimize noise figure, the following steps are
g.
Applications Circuits
recommended:
Transimpedance Amplifier
Minimize R IIR
Choose the optimum R (R
•
•
f
g
The low 2.5pA/√Hz input current noise and unity gain
stability make the CLC440 an excellent choice for
transimpedance applications. Figure 3 illustrates a
low noise transimpedance amplifier that is commonly
implemented with photo diodes. R sets the transimped-
ance gain. The photo diode current multiplied by R
)
s
OPT
R
is the point at which the NF curve reaches a
minimum and is approximated by:
OPT
e
i
n
f
R
OPT
n
f
determines the output voltage.
Figure 2 is a plot of NF vs R with R = 0, R = ∞ (A = +1).
s
f
g
v
The NF curves for both Unterminated and Terminated
systems are shown. The Terminated curve assumes R
Cf
s
= R . The table indicates the NF for various source resis-
T
Rf
tances including R = R
.
Photo Diode
s
OPT
Representation
-
Layout Considerations
Vout
CLC440
Cd
A proper printed circuit layout is essential for achieving
high frequency performance. Comlinear provides
evaluation boards for the CLC440 (730055-DIP, 730060-
SOIC) and suggests their use as a guide for high
frequency layout and as an aid in device testing and
characterization.
Iin
+
Vout = -Iin Rf
*
Figure 3: Transimpedance Amplifier Configuration
5
http://www.national.com
The capacitances are defined as:
Rectifier
The large bandwidth of the CLC440 allows for high speed
rectification. A common rectifier topology is shown in
C = Internal Input Capacitance of the CLC440
•
in
(typ 1.2pF)
Figure 6. R and R set the gain of the rectifier. V for
1
2
out
C = Equivalent Diode Capacitance
•
d
a 5MHz, 2V sinusoidal input is shown in Figure 7.
pp
C = Feedback Capacitance
•
f
D1
The transimpedance plot in the typical performance
section provides the recommended C and expected
f
D2
Vout
R2
bandwidth for different gains and diode capacitances.
The feedback capacitances indicated on the plot
give optimum gain flatness and stability. If a smaller
capacitance is used, then peaking will occur. The
frequency response shown in Figure 4 illustrates the
influence of the feedback capacitance on gain flatness.
R1
Vin
-
CLC440
+
Transimpedance Amplifier
Frequency Response
Figure 6: Rectifier Topology
80
Cf = 0
70
Rectifier Output
Cf = 1pF
2.0
Cf = 2pF
60
1.6
1.2
0.8
0.4
0
Cf = 2.5pF
50
Cf = 5pF
Cf
40
1k
-
CLC440
+
30
-0.4
-0.8
5pF
Iin
100Ω
20
-1.2
-1.6
-2.0
10k
100k
1M
10M
100M
1G
Frequency (Hz)
0
100
200
300
400
500
Figure 4
Time (ns)
The total input current noise density (i ) for the basic
ni
Figure 7: Rectifier Output
transimpedance configuration is shown in Equation 3.
The plot of current noise density versus feedback
resistance is shown in Figure 5.
Tunable Low Pass Filter
The center frequency of the low pass filter (LPF) can be
adjusted by varying the CLC522 gain control voltage, V .
g
Current Noise Density vs.
Feedback Resistance
40
Ra
Rf
-
35
30
Rg
RT
CLC522
+
(Total)
ini
20Ω
25
20
15
Vg
C2
C1
en
Rf
R
R1
-
if
R2
Vin
-
CLC440
+
10
5
Rin
Vout
CLC440
in
+
0
0.1
1.0
10
V
RC2
R1R2C1C2
Rf
in (max)
k
Q =
k
Rg
=
Av (max) = k =1.85
ωo
=
Feedback Resistance (kΩ)
R1R2C1C2
1.8mA
Rg
Figure 5
Figure 8: Tunable Low Pass Filter
2
e
2
f
4kT
n
i
= i +
+
n
ni
R
R
f
Equation 3: Total Equivalent Input Referred Current
Noise Density
http://www.national.com
6
This page intentionally left blank.
7
http://www.national.com
Customer Design Applications Support
National Semiconductor is committed to design excellence. For sales, literature and technical support, call the
National Semiconductor Customer Response Group at 1-800-272-9959 or fax 1-800-737-7018.
Life Support Policy
National’s products are not authorized for use as critical components in life support devices or systems without the express written approval
of the president of National Semiconductor Corporation. As used herein:
1. Life support devices or systems are devices or systems which, a) are intended for surgical implant into the body, or b) support or
sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to
cause the failure of the life support device or system, or to affect its safety or effectiveness.
National Semiconductor
Corporation
National Semiconductor
Europe
National Semiconductor
Hong Kong Ltd.
National Semiconductor
Japan Ltd.
1111 West Bardin Road
Arlington, TX 76017
Tel: 1(800) 272-9959
Fax: 1(800) 737-7018
Fax: (+49) 0-180-530 85 86
E-mail: europe.support.nsc.com
Deutsch Tel: (+49) 0-180-530 85 85
English Tel: (+49) 0-180-532 78 32
Francais Tel: (+49) 0-180-532 93 58
Italiano Tel: (+49) 0-180-534 16 80
13th Floor, Straight Block
Ocean Centre, 5 Canton Road
Tsimshatsui, Kowloon
Hong Kong
Tel: (852) 2737-1600
Fax: (852) 2736-9960
Tel: 81-043-299-2309
Fax: 81-043-299-2408
N
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said
circuitry and specifications.
http://www.national.com
8
Lit #150440-003
相关型号：
CLC446AJE-TR13
Operational Amplifier, 1 Func, 11000uV Offset-Max, BIPolar, PDSO8, 0.150 INCH, PLASTIC, SOIC-8
ROCHESTER
©2020 ICPDF网 联系我们和版权申明