COLDFIRE2UMAD [ETC]
Version 2/2M ColdFire Core Processor User＇s Manual Addendum ; 版本2 / 2M ColdFire内核处理器用户手册附录\n
| 型号： | COLDFIRE2UMAD |
| 厂家： | 
ETC |
| 描述： | Version 2/2M ColdFire Core Processor User＇s Manual Addendum
|
| 文件： | 总6页 (文件大小：305K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Freescale Semiconductor, Inc.
Consumer Systems Group
ColdFire
2/2M
Addendum to
ColdFire 2/2M
User Manual
April 14, 1998
This addendum to the ColdFire 2/2M UserÕs Manual provides corrections to the original text, plus additional
information not included in the original. This document and other information on this product is maintained on
the World Wide Web at http://sps.motorola.com/coldfire.
Instruction Set Architecture
The Instruction Set Summary shown on pages 1-19 through 1-23 should be replaced with the follow-
ing :
Notational Conventions
OPCODE WILDCARDS
cc
Logical Condition (example: NE for not equal)
REGISTER OPERANDS
An
Ay,Ax
Dn
Any Address Register n (example: A3 is address register 3)
Source and destination address registers, respectively
Any Data Register n (example: D5 is data register 5)
Source and destination data registers, respectively
Any Address or Data Register
Dy,Dx
Rn
Ry,Rx
Rw
Any source and destination registers, respectively
Any second destination register
Rc
Any Control Register (example VBR is the vector base register)
REGISTER/PORT NAMES
MAC Accumulator
ACC
DDATA
CCR
Debug Data Port
Condition Code Register (lower byte of status register)
MAC Status Register
Mask Register
MACSR
MASK
PC
Program Counter
PST
Processor Status Port
Status Register
SR
MISCELLANEOUS OPERANDS
Immediate data following the instruction word(s)
Effective Address
#<data>
<ea>
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
SEMICONDUCTOR PRODUCT INFORMATION
Ó 1998 Motorola, Inc. All Rights Reserved.
Revision 0.0
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Notational Conventions (Continued)
<ea>y,<ea>x
<label>
Source and Destination Effective Addresses, respectively
Assembly Program Label
<list>
List of registers (example: D3ÐD0)
<size>
Operand data size: Byte (B), Word (W), Longword (L)
OPERATIONS
Arithmetic addition or postincrement indicator
Arithmetic subtraction or predecrement indicator
Arithmetic multiplication
+
Ð
x
/
Arithmetic division
~
Invert; operand is logically complemented
Logical AND
&
|
Logical OR
~
Logical exclusive OR
<<
>>
Shift left (example: D0 << 3 is shift D0 left 3 bits)
Shift right (example: D0 >> 3 is shift D0 right 3 bits)
Source operand is moved to destination operand
Two operands are exchanged
®
¨
sign-extended
All bits of the upper portion are made equal to the high-order bit of the lower portion
If <condition>
Test the condition. If true, the operations after ÔthenÕ are performed. If the condition is false and the optional ÔelseÕ clause
is present, the operations after ÔelseÕ are performed. If the condition is false and else is omitted, the instruction performs no
operation. Refer to the Bcc instruction description as an example.
then <operations>
else <operations>
SUBFIELDS AND QUALIFIERS
Optional Operation
{}
()
Identifies an indirect address
d
Displacement Value, n-Bits Wide (example: d is a 16-bit displacement)
16
n
Address
Bit
Calculated Effective Address (pointer)
Bit Selection (example: Bit 3 of D0)
Least Significant Bit (example: MSB of D0)
Least Significant Word
LSB
LSW
MSB
MSW
Most Significant Bit
Most Significant Word
CONDITION CODE REGISTER BIT NAMES
Branch Prediction Bit in CCR
Carry Bit in CCR
P
C
N
V
X
Z
Negative Bit in CCR
Overflow Bit in CCR
Extend Bit in CCR
Zero Bit in CCR
2
COLDFIRE 2/2M USERÕS MANUAL ADDENDUM
MOTOROLA
For More Information On This Product,
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Freescale Semiconductor, Inc.
Instruction Set Summary
INSTRUCTION
OPERAND SYNTAX
OPERAND SIZE
OPERATION
ADD
Dy,<ea>x
<ea>y,Dx
32
32
Source + Destination
®
Destination
Destination
ADDA
ADDI
ADDQ
ADDX
AND
<ea>y,Ax
#<data>,Dx
#<data>,<ea>x
Dy,Dx
32
32
32
32
Source + Destination
®
Immediate Data + Destination
Immediate Data + Destination
®
®
Destination
Destination
Source + Destination + X
®
Destination
Dy,<ea>x
<ea>y,Dx
32
32
Source & Destination ® Destination
ANDI
ASL
#<data>,Dx
32
Immediate Data & Destination
®
Destination
Dx,Dy
#<data>,Dx
32
32
X/C
X/C
¬
(Dy << Dx)
¬
0
¬
(Dy << #<data>)
¬
0
ASR
Dx,Dy
<data>,Dx
32
32
MSB
MSB
®
(Dy >> Dx)
®
X/C
® X/C
®
(Dy >> #<data>)
Bcc
<label>
8,16
If Condition True, Then PC + d
®
®
PC
Z,
n
BCHG
Dy,<ea>x
8,32
8,32
~(<Bit Number> of Destination)
Bit of Destination
#<data>,<ea>x
BCLR
Dy,<ea>x
8,32
8,32
~(<Bit Number> of Destination)
®
Z;
#<data>,<ea>x
0
®
Bit of Destination
BRA
<label>
8,16
PC + d ® PC
n
BSET
Dy,<ea>x
8,32
8,32
~(<Bit Number> of Destination)
®
Z;
#<data>,<ea>x
1® Bit of Destination
BSR
<label>
8,16
SP Ð 4
®
SP; next sequential PC® (SP); PC + d ® PC
n
BTST
Dy,<ea>x
8,32
8,32
~(<Bit Number> of Destination) ® Z
#<data>,<ea>x
CLR
CMPI
CMP
<ea>x
#<data>,Dx
<ea>y,Dx
<ea>y,Ax
(An)
8,16,32
32
0 ® Destination
Destination Ð Immediate Data
Destination Ð Source
32
CMPA
CPUSH
DIVS
32
Destination - Source
32
Push and Invalidate Cache Line
<ea>y,Dx
16
32
Dx / <ea>y
® Dx {16-bit Remainder; 16-bit Quotient}
Dx / <ea>y
®
Dx {32-bit Quotient}
Signed operation
DIVU
<ea>y,Dx
16
Dx / <ea>y
®
Dx {16-bit Remainder; 16-bit Quotient}
Dx / <ea>y
® Dx {32-bit Quotient}
Unsigned operation
EOR
EORI
EXT
Dy,<ea>x
32
32
Source ~ Destination
®
Destination
Destination
#<data>,Dx
Immediate Data ~ Destination ®
Dx
Dx
8
®
®
16
32
Sign-Extended Destination Destination
®
16
EXTB
HALT
JMP
JSR
Dx
none
8
®
32
Sign-Extended Destination ® Destination
none
none
32
Enter Halted State
Address of <ea> PC
SP; next sequential PC (SP); <ea>
<ea>
®
<ea>
SPÐ 4
®
®
®
®
PC
SP
LEA
<ea>y,Ax
Ax,#<data>
32
<ea>
®
Ax
LINK
LSL
16
SP Ð 4
®
SP; Ax
®
(SP); SP
®
Ax; SP + d16
Dx,Dy
32
32
X/C
¬
(Dy << Dx)
¬
0
#<data>,Dx
X/C
0
¬
®
(Dx << #<data>)
¬
0
LSR
Dx,Dy
32
32
(Dy >> Dx)
®
X/C
X/C
#<data>,Dx
0
®
(Dx >> #<data>)
®
MOTOROLA
COLDFIRE 2/2M USERÕS MANUAL ADDENDUM
3
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Instruction Set Summary (Continued)
INSTRUCTION
OPERAND SYNTAX
OPERAND SIZE
OPERATION
Rx){<< 1 | >> 1}
Rx){<< 1 | >> 1} ACC; (<ea>y{&MASK})
ACC + (Ry Rx){<< 1 | >> 1} ACC
Rx){<< 1 | >> 1}
<ea>y
MAC
Ry,Rx <shift>
Ry,Rx<shift>,<ea>y,Rw
16
´
16
32
+
®
32
32
32
®
32
ACC + (Ry
´
® ACC
ACC + (Ry
ACC + (Ry
´
®
®
®
Rw
Rw
MACL
Ry,Rx<shift>
Ry,Rx,<shift>,<ea>y,Rw
32
´
32
32
+
®
®
32
32
´
®
´
®
®
ACC; (<ea>y{&MASK})
MOVE
<ea>y,<ea>x
ACC,Rx
Dx
8,16,32
32
<ea>x
MOVE from ACC
MOVE from CCR
ACC
CCR
®
Rx
Dx
16
®
MOVE from MACSR
MACSR,Rx
MACSR,CCR
32
8
MACSR
MACSR
® Rx
®
CCR
MOVE from MASK
MOVE from SR
MASK,Rx
Dx
32
16
MASK
SR
Ry
#<data>
Dy
#<data>
Ry
#<data>
Ry
#<data>
Source
®
Rx
®
Dx
MOVE to ACC
Ry,ACC
<#<data>,ACC
32
32
®
ACC
®
ACC
MOVE to CCR
MOVE to MACSR
MOVE to MASK
MOVE to SR
Dy,CCR
#<data>,CCR
8
®
CCR
®
CCR
Ry,MACSR
#<data>,MACSR
32
®
MACSR
® MACSR
Ry,MASK
#<data>,MASK
32
32
®
MASK
MASK
SR
®
Dy,SR
#<data>,SR
16
®
MOVEA
MOVEC
MOVEM
<ea>y,Ax
Ry,Rc
16,32
®
32
Source
Ry
Listed Registers ®
®
Destination
Rc
Destination
32
®
list,<ea>x
<ea>y,list
32
32
Source Listed Registers
®
MOVEQ
MSAC
#<data>,Dx
8
®
32
Sign-extended Immediate Data Destination
ACC - (Ry Rx){<< 1 | >> 1} ACC
Rx){<< 1 | >> 1} ACC, (<ea>y{&MASK})
ACC - (Rw Rx){<< 1 | >> 1} ACC
Rx){<< 1 | >> 1} ACC; (<ea>y{&MASK})
Destination Destination
®
Ry,Rx<shift>
Ry,Rx<shift>,<ea>y,Rw
32 - 16
32
´
16
®
32
32
´
®
®
32
ACC - (Ry
ACC - (Rw
´
´
®
®
®
Rw
Rw
MSACL
Ry,Rx<shift>
Ry,Rx<shift>,<ea>y,Rw
32 - 32
32
´
®
32
®
32
´
®
®
MULS
MULU
<ea>y,Dx
16 x 16
32 x 32
®
®
32
32
Source
Source
´
´
®
Signed operation
Destination Destination
<ea>y,Dx
16 x 16
32 x 32
®
®
32
32
®
Unsigned operation
Destination
Destination
PC; Synchronize Pipelines
~ Destination Destination
Source Destination
NEG
NEGX
NOP
NOT
OR
<ea>x
<ea>x
none
32
0 Ð Destination
0 Ð DestinationÐ X
PC + 2
®
32
none
32
®
®
<ea>
®
Dy,<ea>x
<ea>y,Dx
32
|
®
Destination
ORI
PEA
#<data>,Dx
<ea>
32
32
Immediate Data
|
Destination
®
Destination
(SP)
SP Ð 4
®
SP; Address of <ea>
Set PST= $4
®
PULSE
REMS
none
none
32
<ea>y,Dx:Dw
Dx/<ea>y
®
Dw {32-bit Remainder}
Signed operation
Dw {32-bit Remainder}
Unsigned operation
SP; (SP) PC; SP + FormatField
PC; SP + 4 SP
If Condition True, Then 1's Destination;
Else 0's Destination
Immediate Data SR; Enter Stopped State
REMU
<ea>y,Dx:Dw
32
Dx/<ea>y
®
RTE
RTS
Scc
none
none
Dx
none
none
8
(SP+2)
®
SR; SP+4
®
®
® SP
(SP)
®
®
®
®
STOP
#<data>
16
®
4
COLDFIRE 2/2M USERÕS MANUAL ADDENDUM
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Instruction Set Summary (Continued)
INSTRUCTION
OPERAND SYNTAX
OPERAND SIZE
OPERATION
SUB
Dy,<ea>x
<ea>y,Dx
32
32
Destination - Source
®
Destination
SUBA
SUBI
<ea>y,Ax
#<data>,Dx
#<data>,<ea>x
Dy,Dx
32
32
Destination - Source
®
Destination
Destination Ð Immediate Data
Destination - Immediate data
®
®
Destination
Destination
SUBQ
SUBX
SWAP
TRAP
32
32
Destination Ð Source Ð X
® Destination
Dn
16
MSW of Dn ¨ LSW of Dn
none
none
SP Ð 4
SP Ð 2
®
®
SP;PC
SP;SR
®
®
(SP);
(SP);
SP Ð 2
®
SP; Format
®
(SP);
Vector Address
® PC
TRAPF
none
none
16
PC + 2
®
®
®
PC
#<data>
PC + 4
PC
32
PC + 6
PC
TST
<ea>y
Ax
8,16,32
32
Set Condition Codes
SP; (SP) Ax; SP + 4
<ea>y DDATA port
<ea>y Debug Module
UNLK
Ax
®
®
® SP
WDDATA
WDEBUG
<ea>y
<ea>y
8,16,32
2 x 32
®
®
MOTOROLA
COLDFIRE 2/2M USERÕS MANUAL ADDENDUM
5
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
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