COP87L88RKV-XE_技术文档

September 1999

COP87L88EK/RK Family

8-Bit CMOS OTP Microcontrollers with 8k or 32k

Memory, Comparator, and Single-slope A/D Capability

Family features include an 8-bit memory mapped architec-

ture, 10 MHz CKI (-XE = crystal oscillator) with 1 µs instruc-

tion cycle, three multi-function 16-bit timer/counters with

General Description

The COP87L88EK/RK Family OTP (One Time Program-

™

mable) microcontrollers are highly integrated COP8 Fea-

ture core devices with 16k or 32k memory and advanced

™

PWM, MICROWIRE/PLUS serial I/O, one analog com-

parator with seven input multiplexor, an analog current

source and V_CC/2 reference, two power saving HALT/IDLE

modes, idle timer, MIWU, high current outputs, software se-

features including

a

Multi-Input Comparator and

Single-slope A/D capability. These multi-chip CMOS devices

are suited for applications requiring a full featured, low EMI

controller with an analog comparator, current source, and

voltage reference, and as pre-production devices for a

masked ROM design. Lower cost pin and software compat-

ible 8k ROM versions (COP888EK) are available for use with

a range of COP8 software and hardware development tools.

™

lectable I/O options, WATCHDOG timer and Clock Monitor,

2.7V to 5.5V operation and 28/40/44 pin packages.

Devices included in this datasheet are:

Device

Memory (bytes)

16k OTP EPROM

32k OTP EPROM

RAM (bytes)

I/O Pins

24

Packages

28 DIP/SOIC

Temperature

-40 to +85˚C

COP87L84EK

COP87L88EK

COP87L84RK

COP87L88RK

256

36/40

24

40 DIP, 44 PLCC

28 DIP/SOIC

36/40

40 DIP, 44 PLCC

n Schmitt trigger inputs on Port G and L

Key Features

n Analog function block with

CPU/Instruction Set Feature

n 1 µs instruction cycle time

n Twelve multi-source vectored interrupts servicing

— External Interrupt with selectable edge

— Idle Timer T0

— Three Timers (Each with 2 interrupts)

— MICROWIRE/PLUS

— Analog comparator with seven input multiplexor

— Constant current source and V_CC/2 reference

n Three 16-bit timers, each with two 16-bit registers

supporting:

— Processor Independent PWM mode

— External Event counter mode

— Input Capture mode

— Multi-Input Wake Up

— Software Trap

n 8 or 32 kbytes on-board EPROM with security feature

n 256 bytes on-board RAM

— Default VIS (default interrupt)

n Versatile and easy to use instruction set

n 8-bit Stack Pointer (SP)—stack in RAM

n Two 8-bit Register Indirect Data Memory Pointers

(B, X)

Additional Peripheral Features

n Idle Timer

n Multi-Input Wake Up (MIWU) with optional interrupts (8)

n WATCHDOG and Clock Monitor logic

n MICROWIRE/PLUS serial I/O

Fully Static CMOS

n Two power saving modes: HALT and IDLE

n Single supply operation: 2.7V to 5.5V

n Temperature ranges: −40˚C to +85˚C

I/O Features

™

n Software selectable I/O options ( TRI-STATE Output,

Push-Pull Output, Weak Pull-Up Input, High Impedance

Input)

n Packages:

— 44 PLCC with 40 I/O pins

— 40 DIP with 36 I/O pins

— 28 DIP/SO with 24 I/O pins

Development Support

n Emulation devices for the COP888EK/COP884EK

n Real time emulation and full program debug offered by

MetaLink Development System

™

COP8 is a trademark of National Semiconductor Corporation.

™

MICROWIRE/PLUS is a trademark of National Semiconductor Corporation.

TRI-STATE^®is a registered trademark of National Semiconductor Corporation.

™

WATCHDOG is a trademark of National Semiconductor Corporation.

™

iceMASTER is a trademark of MetaLink Corporation.

DS101133

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Block Diagram

DS101133-1

FIGURE 1. Block Diagram

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2

Connection Diagrams

Plastic Chip Carrier

Dual-In-Line Package

DS101133-2

Top View

Order Number COP87L88EKV-XE or COP87L88RKV-XE

See NS Plastic Chip Package Number V44A

DS101133-3

Top View

Order Number COP87L84EKN-XE or COP87L84RKN-XE

See NS Molded Package Number N40A

Dual-In-Line Package

DS101133-4

Top View

Order Number COP87L84EKN-XE or COP87L84RKN-XE

See NS Molded Package Number N28B

Order Number COP87L84EKM-XE or COP87L84RKM-XE

See NS Molded Package Number M28B

Note: -X Crystal Oscillator

-E Halt Mode Enabled

FIGURE 2. Connection Diagrams

3

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Connection Diagrams (Continued)

Pinouts for 28-, 40-, and 44-Pin Packages

28-Pin

Pack.

11

12

13

14

15

16

17

18

25

26

27

28

1

40-Pin

Pack.

17

18

19

20

21

22

23

24

35

36

37

38

3

44-Pin

Pack.

17

18

19

20

25

26

27

28

39

40

41

42

3

Port

Type

I/O

Alt. Fun

L0

L1

L2

L3

L4

L5

L6

L7

MIWU

INT

I/O

WDOUT

I/O

I

T2A

T2B

T3A

T3B

G0

G1

G2

G3

G4

G5

G6

G7

D0

D1

D2

D3

I0

T1B

T1A

SO

SK

2

4

SI

3

5

I/CKO

O

HALT Restart

4

6

19

20

21

22

7

25

26

27

28

9

29

30

31

32

9

O

I

COMPIN1+

I1

I

COMPIN−/Current

Source Out

8

10

I2

I

COMPIN0+

9

11

12

13

14

15

16

29

30

31

32

39

40

1

11

12

13

14

15

16

33

34

35

36

43

44

1

I3

I

COMPOUT/COMPIN2+

COMPIN3+

10

I4

I

I5

I

COMPIN4+

I6

I

COMPIN5+

I7

I

COMPOUT

D4

D5

D6

D7

C0

C1

C2

C3

C4

C5

C6

C7

V_CC

GND

CKI

RESET

O

I/O

2

21

22

23

24

8

6

23

5

8

33

7

37

7

24

34

38

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4

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

Total Current into V_CCPin (Source)

Total Current out of GND Pin (Sink)

Storage Temperature Range

Note 1: Absolute maximum ratings indicate limits beyond which damage to

the device may occur. DC and AC electrical specifications are not ensured

when operating the device at absolute maximum ratings.

100 mA

110 mA

−65˚C to +140˚C

Supply Voltage (V_CC

Voltage at Any Pin

)

7V

−0.3V to V_CC+ 0.3V

DC Electrical Characteristics

−40˚C ≤ T_A≤ +85˚C unless otherwise specified

Parameter

Conditions

Min

Typ

Max

5.5

Units

Operating Voltage

2.7

V

Power Supply Ripple (Note 3)

Supply Current (Note 4)

CKI = 10 MHz

Peak-to-Peak

0.1 V_CC

V_CC= 5.5V, t_c= 1 µs

16.5

6.5

12

mA

µA

CKI = 4 MHz

V_CC= 4.0V, t_c= 2.5 µs

V_CC= 5.5V, CKI = 0 MHz

V_CC= 4.0V, CKI = 0 MHz

HALT Current (Note 5)

8

µA

IDLE Current (Note 4)

CKI = 10 MHz

V_CC= 5.5V, t_c= 1 µs

V_CC= 4.0V, t_c= 10 µs

3.5

0.7

mA

CKI = 4 MHz

Input Levels (V_IH, V_IL)

RESET

Logic High

0.8 V_CC

0.7 V_CC

V

Logic Low

0.2 V_CC

CKI, All Other Inputs

Logic High

V

Logic Low

0.2 V_CC

+2

Hi-Z Input Leakage

Input Pullup Current

G and L Port Input Hysteresis (Note 8)

Output Current Levels

D Outputs

V_CC= 5.5V

−2

µA

V

V_CC= 5.5V, V_IN= 0V

−40

−250

0.35 V_CC

Source

V_CC= 4.5V, V_OH= 3.3V

V_CC= 4.5V, V_OL= 1V

−0.4

10

mA

Sink

All Others

Source (Weak Pull-Up Mode)

Source (Push-Pull Mode)

Sink (Push-Pull Mode)

TRI-STATE Leakage

Allowable Sink/Source Current per Pin

(Note 8)

V_CC= 4.5V, V_OH= 2.7V

V_CC= 4.5V, V_OH= 3.3V

V_CC= 4.5V, V_OL= 0.4V

V_CC= 6.0V

−10

−0.4

1.6

−110

+2

µA

mA

µA

−2

D Outputs (Sink)

All others

15

3

mA

±

Maximum Input Current

without Latchup (Note 6)

RAM Retention Voltage, V_r

Room Temp

200

500 ns Rise

2

V

and Fall Time (min)

Input Capacitance

7

pF

Load Capacitance on D2

1000

5

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AC Electrical Characteristics

−40˚C ≤ T_A≤ +85˚C unless otherwise specified

Parameter

Instruction Cycle Time (t_c)

Crystal, Resonator,

R/C Oscillator

Conditions

Min

Typ

Max

Units

4.5V ≤ V_CC≤ 5.5V

1.0

3.0

DC

µs

Inputs

t_SETUP

4.5V ≤ V_CC≤ 5.5V

R_L= 2.2k, C_L= 100 pF

200

60

ns

t_HOLD

Output Propagation Delay (Note 7)

t_PD1, t_PD0

SO, SK

4.5V ≤ V_CC≤ 5.5V

4.50V ≤ V_CC≤ 5.5V

V_CC≥ 4.5V

0.7

1.0

µs

ns

All Others

MICROWIRE Setup Time (t_UWS) (Note 7)

MICROWIRE Hold Time (t_UWH) (Note 7)

MICROWIRE Output Propagation Delay (t_UPD

Input Pulse Width (Note 8)

Interrupt Input High Time

Interrupt Input Low Time

20

56

V_CC≥ 4.5V

)

V_CC≥ 4.5V

220

1.0

t_c

Timer 1, 2, 3 Input High Time

Timer 1, 2, 3 Input Low Time

Reset Pulse Width

t_c

µs

Note 2: t = Instruction Cycle Time

c

<

Note 3: Maximum rate of voltage change must be 0.5 V/ms.

Note 4: Supply and IDLE currents are measured with CKI driven with a square wave Oscillator, CKO driven 180˚ out of phase with CKI, inputs connected to V

CC

and outputs driven low but not connected to a load.

Note 5: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Measurement of I HALT is done with device neither sourcing nor

DD

sinking current; with L, C, G0, and G2–G5 programmed as low outputs and not driving a load; all outputs programmed low and not driving a load; all inputs tied to

V

CC

; clock monitor and comparator disabled. Parameter refers to HALT mode entered via setting bit 7 of the G Port data register. Part will pull up CKI during HALT

in crystal clock mode.

>

Note 6: Pins G6 and RESET are designed with a high voltage input network. These pins allow input voltages

V

and the pins will have sink current to V when

CC CC

>

biased at voltages

V

(the pins do not have source current when biased at a voltage below V ). The effective resistance to V

pins will not latch up. The voltage at the pins must be limited to 14V. WARNING: Voltages in excess of 14V will cause damage to the pins. This warning ex-

is 750Ω (typical). These two

CC

<

cludes ESD transients.

Note 7: The output propagation delay is referenced to the end of the instruction cycle where the output change occurs.

Note 8: Parameter characterized but not tested.

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6

Analog Function Block AC and DC Characteristics

V_CC= 5.0V, −40˚C ≤ T_A≤ +85˚C

Parameter

Input Offset Voltage

Conditions

Min

Typ

Max

Units

mV

V

<

±

25

0.4V V_INV_CC− 1.5V

10

Input Common Mode Voltage Range

(Note 10)

0.4

V_CC− 1.5

<

V

_CC/2 Reference

4.5V V_CC5.5V

0.5 V_CC− 0.04

0.5 V_CC

0.5 V_CC+ 0.04

250

V

DC Supply Current for

Comparator (when enabled)

DC Supply Current for

µA

V_CC= 5.5V

50

80

200

40

µA

V_CC= 5.5V

V_CC/2 Reference (when enabled)

DC Supply Current for

Constant Current Source (when enabled)

Constant Current Source

<

4.5V V_CC5.5V

10

20

µA

<

±

2

Current Source Variation over

Common Mode Range

4.5V V_CC5.5V

Temp = Constant

Current Source Enable Time

Comparator Response Time

1.5

2

µs

100 mV Overdrive,

100 pF Load

1

Note 9: While performance characteristics are given at V

= 5.0V, the analog function block will operate over the entire 2.5V–6.0V V

range. Accuracy of the

CC

V /2 reference and the constant current source is not guaranteed beyond the specified limits.

CC

Note 10: The device is capable of operating over a common mode voltage range of 0 to V − 1.5V, however increased offset voltage will be observed between 0V

CC

and 0.4V.

DS101133-18

FIGURE 3. MICROWIRE/PLUS Timing

Typical Performance Characteristics (−55˚C ≤ T_A= +125˚C)

DS101133-19

DS101133-20

7

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Typical Performance Characteristics (−55˚C ≤ T_A= +125˚C) (Continued)

DS101133-21

DS101133-22

DS101133-27

DS101133-29

DS101133-23

DS101133-28

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8

Typical Performance Characteristics (−55˚C ≤ T_A= +125˚C) (Continued)

DS101133-30

The Port L has the following alternate features:

Pin Descriptions

V_CCand GND are the power supply pins. All V_CCand GND

pins must be connected.

L7 MIWU or T3B

L6 MIWU or T3A

L5 MIWU or T2B

L4 MIWU or T2A

L3 MIWU

CKI is the clock input. This can come from an R/C generated

oscillator, or a crystal oscillator (in conjunction with CKO).

See Oscillator Description section.

RESET is the master reset input. See Reset Description sec-

tion.

L2 MIWU

L1 MIWU

The device contains three bidirectional 8-bit I/O ports (C, G

and L), where each individual bit may be independently con-

figured as an input (Schmitt Trigger inputs on ports L and G),

output or TRI-STATE under program control. Three data

memory address locations are allocated for each of these

I/O ports. Each I/O port has two associated 8-bit memory

mapped registers, the CONFIGURATION register and the

output DATA register. A memory mapped address is also re-

served for the input pins of each I/O port. (See the memory

map for the various addresses associated with the I/O ports.)

Figure 4 shows the I/O port configurations. The DATA and

CONFIGURATION registers allow for each port bit to be in-

dividually configured under software control as shown below:

L0 MIWU

Port G is an 8-bit port with 5 I/O pins (G0, G2–G5), an input

pin (G6), and a dedicated output pin (G7). Pins G0 and

G2–G6 all have Schmitt Triggers on their inputs. Pin G1

serves as the dedicated WDOUT WATCHDOG output, while

pin G7 is either input or output depending on the oscillator

mask option selected. With the crystal oscillator option se-

lected, G7 serves as the dedicated output pin for the CKO

clock output. With the single-pin R/C oscillator mask option

selected, G7 serves as a general purpose input pin but is

also used to bring the device out of HALT mode with a low to

high transition on G7. There are two registers associated

with the G Port, a data register and a configuration register.

Therefore, each of the 5 I/O bits (G0, G2–G5) can be indi-

vidually configured under software control.

CONFIGURA-

TION

DATA

Port Set-Up

Since G6 is an input only pin and G7 is the dedicated CKO

clock output pin (crystal clock option) or general purpose in-

put (R/C clock option), the associated bits in the data and

configuration registers for G6 and G7 are used for special

purpose functions as outlined on the next page. Reading the

G6 and G7 data bits will return zeros.

Register

0

Register

0

Hi-Z Input

(TRI-STATE Output)

Input with Weak Pull-Up

Push-Pull Zero Output

Push-Pull One Output

0

1

0

1

PORT L is an 8-bit I/O port. All L-pins have Schmitt triggers

on the inputs.

The Port L supports Multi-Input Wake Up on all eight pins. L4

and L5 are used for the timer input functions T2A and T2B.

L6 and L7 are used for the timer input functions T3A and

T3B.

9

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Pin Descriptions (Continued)

DS101133-5

FIGURE 4. I/O Port Configurations

Note that the chip will be placed in the HALT mode by writing

a “1” to bit 7 of the Port G Data Register. Similarly the chip

will be placed in the IDLE mode by writing a “1” to bit 6 of the

Port G Data Register.

I5 COMPIN4+ (Comparator Positive Input 4)

I4 COMPIN3+ (Comparator Positive Input 3)

I3 COMPOUT/COMPIN2+

(Comparator

Output/

Comparator Positive Input 2))

Writing a “1” to bit 6 of the Port G Configuration Register en-

ables the MICROWIRE/PLUS to operate with the alternate

phase of the SK clock. The G7 configuration bit, if set high,

enables the clock start up delay after HALT when the R/C

clock configuration is used.

I2 COMPIN0+ (Comparator Positive Input 0)

I1 COMPIN− (Comparator Negative Input/Current

Source Out)

I0 COMPIN1+ (Comparator Positive Input 1)

Port D is an 8-bit output port that is preset high when RESET

goes low. The user can tie two or more D port outputs (ex-

cept D2) together in order to get a higher drive.

Config Reg.

CLKDLY

Alternate SK

Data Reg.

HALT

IDLE

G7

G6

Note: Care must be exercised with the D2 pin operation. At RESET, the ex-

ternal loads on this pin must ensure that the output voltages stay

Port G has the following alternate features:

G6 SI (MICROWIRE Serial Data Input)

G5 SK (MICROWIRE Serial Clock)

G4 SO (MICROWIRE Serial Data Output)

G3 T1A (Timer T1 I/O)

above 0.8 V

keep the external loading on D2 to 1000 pF.

to prevent the chip from entering special modes. Also

CC

<

Functional Description

The architecture of the device is modified Harvard architec-

ture. With the Harvard architecture, the control store pro-

gram memory (ROM) is separated from the data store

memory (RAM). Both ROM and RAM have their own sepa-

rate addressing space with separate address buses. The ar-

chitecture, though based on Harvard architecture, permits

transfer of data from ROM to RAM.

G2 T1B (Timer T1 Capture Input)

G0 INTR (External Interrupt Input)

Port G has the following dedicated functions:

G7 CKO Oscillator dedicated output or general purpose

input

G1 WDOUT WATCHDOG and/or Clock Monitor dedi-

cated output

CPU REGISTERS

The CPU can do an 8-bit addition, subtraction, logical or shift

operation in one instruction (t_c) cycle time.

Port C is an 8-bit I/O port. The 40-pin device does not have

a full complement of Port C pins. The unavailable pins are

not terminated. A read operation for these unterminated pins

will return unpredicatable values.

There are six CPU registers:

A is the 8-bit Accumulator Register

PORT I is an eight-bit Hi-Z input port. The 28-pin device does

not have a full complement of Port I pins. The unavailable

pins are not terminated i.e., they are floating. A read opera-

tion for these unterminated pins will return unpredictable val-

ues. The user must ensure that the software takes this into

account by either masking or restricting the accesses to bit

operations. The unterminated Port I pins will draw power

only when addressed.

PC is the 15-bit Program Counter Register

PU is the upper 7 bits of the program counter (PC)

PL is the lower 8 bits of the program counter (PC)

B is an 8-bit RAM address pointer, which can be optionally

post auto incremented or decremented.

X is an 8-bit alternate RAM address pointer, which can be

optionally post auto incremented or decremented.

Port I is an eight-bit Hi-Z input port.

SP is the 8-bit stack pointer, which points to the subroutine/

interrupt stack (in RAM). The SP is initialized to RAM ad-

dress 06F with reset.

Port I0–I7 are used for the analog function block.

The Port I has the following alternate features:

I7 COMPOUT (Comparator Output)

I6 COMPIN5+ (Comparator Positive Input 5)

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10

Functional Description (Continued)

Data Memory Segment RAM

Extension

Data memory address 0FF is used as a memory mapped lo-

cation for the Data Segment Address Register (S).

S is the 8-bit Data Segment Address Register used to extend

the lower half of the address range (00 to 7F) into 256 data

segments of 128 bytes each.

All the CPU registers are memory mapped with the excep-

tion of the Accumulator (A) and the Program Counter (PC).

The data store memory is either addressed directly by a

single byte address within the instruction, or indirectly rela-

tive to the reference of the B, X, or SP pointers (each con-

tains a single-byte address). This single-byte address allows

an addressing range of 256 locations from 00 to FF hex. The

upper bit of this single-byte address divides the data store

memory into two separate sections as outlined previously.

With the exception of the RAM register memory from ad-

dress locations 00F0 to 00FF, all RAM memory is memory

mapped with the upper bit of the single-byte address being

equal to zero. This allows the upper bit of the single-byte ad-

dress to determine whether or not the base address range

(from 0000 to 00FF) is extended. If this upper bit equals one

(representing address range 0080 to 00FF), then address

extension does not take place. Alternatively, if this upper bit

equals zero, then the data segment extension register S is

used to extend the base address range (from 0000 to 007F)

from XX00 to XX7F, where XX represents the 8 bits from the

S register. Thus the 128-byte data segment extensions are

located from addresses 0100 to 017F for data segment 1,

0200 to 027F for data segment 2, etc., up to FF00 to FF7F

for data segment 255. The base address range from 0000 to

007F represents data segment 0.

The device can be configured to inhibit external reads of the

program memory. This is done by programming the Security

Byte.

PROGRAM MEMORY

The program memory consists of 8192 bytes of OTP

EPROM. These bytes may hold program instructions or con-

stant data (data tables for the LAID instruction, jump vectors

for the JID instruction, and interrupt vectors for the VIS in-

struction). The program memory is addressed by the 15-bit

program counter (PC). All interrupts in the devices vector to

program memory location 0FF Hex.

The device can be configured to inhibit external reads of the

program memory. This is done by programming the Security

Byte.

SECURITY FEATURE

The program memory array has an associate Security Byte

that is located outside of the program address range. This

byte can be addressed only from programming mode by a

programmer tool.

Figure 5 illustrates how the S register data memory exten-

sion is used in extending the lower half of the base address

range (00 to 7F hex) into 256 data segments of 128 bytes

each, with a total addressing range of 32 kbytes from XX00

to XX7F. This organization allows a total of 256 data seg-

ments of 128 bytes each with an additional upper base seg-

ment of 128 bytes. Furthermore, all addressing modes are

available for all data segments. The S register must be

changed under program control to move from one data seg-

ment (128 bytes) to another. However, the upper base seg-

ment (containing the 16 memory registers, I/O registers,

control registers, etc.) is always available regardless of the

contents of the S register, since the upper base segment

(address range 0080 to 00FF) is independent of data seg-

ment extension.

Security is an optional feature and can only be asserted after

the memory array has been programmed and verified. A se-

cured part will read all 00(hex) by a programmer. The part

will fail Blank Check and will fail Verify operations. A Read

operation will fill the programmer’s memory with 00(hex).

The Security Byte itself is always readable with value of

00(hex) if unsecure and FF(hex) if secure.

DATA MEMORY

The data memory address space includes the on-chip RAM

and data registers, the I/O registers (Configuration, Data and

Pin), the control registers, the MICROWIRE/PLUS SIO shift

register, and the various registers, and counters associated

with the timers (with the exception of the IDLE timer). Data

memory is addressed directly by the instruction or indirectly

by the B, X, SP pointers and S register.

The instructions that utilize the stack pointer (SP) always ref-

erence the stack as part of the base segment (Segment 0),

regardless of the contents of the S register. The S register is

not changed by these instructions. Consequently, the stack

(used with subroutine linkage and interrupts) is always lo-

cated in the base segment. The stack pointer will be intitial-

ized to point at data memory location 006F as a result of re-

set.

The data memory consists of 256 bytes of RAM. Sixteen

bytes of RAM are mapped as “registers” at addresses 0F0 to

0FF Hex. These registers can be loaded immediately, and

also decremented and tested with the DRSZ (decrement

register and skip if zero) instruction. The memory pointer

registers X, SP, B and S are memory mapped into this space

at address locations 0FC to 0FF Hex respectively, with the

other registers being available for general usage.

The 128 bytes of RAM contained in the base segment are

split between the lower and upper base segments. The first

112 bytes of RAM are resident from address 0000 to 006F in

the lower base segment, while the remaining 16 bytes of

RAM represent the 16 data memory registers located at ad-

dresses 00F0 to 00FF of the upper base segment. No RAM

is located at the upper sixteen addresses (0070 to 007F) of

the lower base segment.

The instruction set permits any bit in memory to be set, reset

or tested. All I/O and registers (except A and PC) are

memory mapped; therefore, I/O bits and register bits can be

directly and individually set, reset and tested. The accumula-

tor (A) bits can also be directly and individually tested.

Note: RAM contents are undefined upon power-up.

Additional RAM beyond these initial 128 bytes, however, will

always be memory mapped in groups of 128 bytes (or less)

at the data segment address extensions (XX00 to XX7F) of

the lower base segment. The additional 128 bytes of RAM

are memory mapped at address locations 0100 to 017F hex.

11

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Data Memory Segment RAM

Extension ^(Continued)

DS101133-7

>

RC 5 x Power Supply Rise Time

FIGURE 6. Recommended Reset Circuit

Oscillator Circuits

The chip can be driven by a clock input on the CKI input pin

which can be between DC and 10 MHz. The CKO output

clock is on pin G7 (crystal configuration). The CKI input fre-

quency is divided down by 10 to produce the instruction

cycle clock (1/t_c).

Note: External clocks with frequencies above about 4 MHz require the user

to drive the CKO (G7) pin with a signal 180 degrees out of phase with

CKI.

DS101133-6

Figure 7 shows the Crystal and R/C oscillator diagrams.

*Reads as all ones.

FIGURE 5. RAM Organization

CRYSTAL OSCILLATOR

CKI and CKO can be connected to make a closed loop crys-

tal (or resonator) controlled oscillator.

Reset

The RESET input when pulled low initializes the microcon-

troller. Initialization will occur whenever the RESET input is

pulled low. Upon initialization, the data and configuration

registers for ports L, G and C are cleared, resulting in these

Ports being initialized to the TRI-STATE mode. Pin G1 of the

G Port is an exception (as noted below) since pin G1 is dedi-

cated as the WATCHDOG and/or Clock Monitor error output

pin. Port D is set high. The PC, PSW, ICNTRL, CNTRL,

T2CNTRL and T3CNTRL control registers are cleared. The

Comparator Select Register is cleared. The S register is ini-

tialized to zero. The Multi-Input Wakeup registers WKEN and

WKEDG are cleared. Wakeup register WKPND is unknown.

The stack pointer, SP, is initialized to 6F hex.

Table 1 shows the component values required for various

standard crystal values.

R/C OSCILLATOR

By selecting CKI as a single pin oscillator input, a single pin

R/C oscillator circuit can be connected to it. CKO is available

as a general purpose input, and/or HALT restart input.

Note: Use of the R/C oscillator option will result in higher electromagnetic

emissions.

Table 2 shows the variation in the oscillator frequencies as

functions of the component (R and C) values.

The device comes out of reset with both the WATCHDOG

logic and the Clock Monitor detector armed, with the

WATCHDOG service window bits set and the Clock Monitor

bit set. The WATCHDOG and Clock Monitor circuits are in-

hibited during reset. The WATCHDOG service window bits

being initialized high default to the maximum WATCHDOG

service window of 64k t_Cclock cycles. The Clock Monitor bit

being initialized high will cause a Clock Monitor error follow-

ing reset if the clock has not reached the minimum specified

frequency at the termination of reset. A Clock Monitor error

will cause an active low error output on pin G1. This error

output will continue until 16 t_C–32 t_Cclock cycles following

the clock frequency reaching the minimum specified value,

at which time the G1 output will enter the TRI-STATE mode.

DS101133-8

The external RC network shown in Figure 6 should be used

to ensure that the RESET pin is held low until the power sup-

ply to the chip stabilizes.

DS101133-9

FIGURE 7. Crystal and R/C Oscillator Diagrams

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12

flags. In addition to the SC and R/C instructions, ADC,

SUBC, RRC and RLC instructions affect the Carry and Half

Carry flags.

Oscillator Circuits (Continued)

TABLE 1. Crystal Oscillator Configuration, T_A= 25˚C

R1

R2

C1

C2

CKI Freq

(MHz)

10

ICNTRL Register (Address X'00E8)

Conditions

(kΩ) (MΩ) (pF)

(pF)

Rsvd

Bit 7

LPEN

T0PND

T0EN µWPND µWEN T1PNDB

T1ENB

Bit 0

0

1

30

30–36

V_CC= 5V

4

The ICNTRL register contains the following bits:

200 100–150

0.455

Rsvd

This bit is reserved and must be zero

LPEN

L Port Interrupt Enable (Multi-Input Wakeup/

Interrupt)

TABLE 2. RC Oscillator Configuration, T_A= 25˚C

T0PND

T0EN

Timer T0 Interrupt pending

R

C

CKI Freq

(MHz)

Instr. Cycle

(µs)

Conditions

Timer T0 Interrupt Enable (Bit 12 toggle)

(kΩ)

3.3

5.6

6.8

(pF)

82

µWPND MICROWIRE/PLUS interrupt pending

µWEN Enable MICROWIRE/PLUS interrupt

2.2 to 2.7

1.1 to 1.3

0.9 to 1.1

3.7 to 4.6

7.4 to 9.0

8.8 to 10.8

V_CC= 5V

100

T1PNDB Timer T1 Interrupt Pending Flag for T1B cap-

ture edge

Note 11: 3k ≤ R ≤ 200k

50 pF ≤ C ≤ 200 pF

T1ENB

Timer T1 Interrupt Enable for T1B Input capture

edge

T2CNTRL Register (Address X'00C6)

Control Registers

T2C3

Bit 7

T2C2

T2C1

T2C0

T2PNDA

T2ENA

T2PNDB

T2ENB

Bit 0

CNTRL Register (Address X'00EE)

T1C3 T1C2 T1C1 T1C0 MSEL IEDG

Bit 7

SL1

SL0

The T2CNTRL control register contains the following bits:

Bit 0

T2C3

T2C2

T2C1

T2C0

Timer T2 mode control bit

The Timer1 (T1) and MICROWIRE/PLUS control register

contains the following bits:

T1C3

T1C2

T1C1

T1C0

Timer T1 mode control bit

Timer T1 Start/Stop control in timer

Timer T2 Start/Stop control in timer

modes 1 and 2, T2 Underflow Interrupt Pend-

ing Flag in timer mode 3

T2PNDA Timer T2 Interrupt Pending Flag (Autoreload

RA in mode 1, T2 Underflow in mode 2, T2A

capture edge in mode 3)

modes 1 and 2, T1 Underflow Interrupt

Pending Flag in timer mode 3

T2ENA

Timer T2 Interrupt Enable for Timer Underflow

or T2A Input capture edge

MSEL

IEDG

Selects G5 and G4 as MICROWIRE/PLUS

signals SK and SO respectively

T2PNDB Timer T2 Interrupt Pending Flag for T2B cap-

ture edge

External interrupt edge polarity select

(0 = Rising edge, 1 = Falling edge)

T2ENB

Timer T2 Interrupt Enable for Timer Underflow

or T2B Input capture edge

SL1 & SL0 Select the MICROWIRE/PLUS clock divide

by (00 = 2, 01 = 4, 1x = 8)

T3CNTRL Register (Address X'00B6)

PSW Register (Address X'00EF)

T3C3

Bit 7

T3C2

T3C1

T3C0

T3PNDA

T3ENA

T3PNDB

T3ENB

Bit 0

HC

C

T1PNDA T1ENA EXPND BUSY EXEN GIE

Bit 0

Bit 7

The T3CNTRL control register contains the following bits:

The PSW register contains the following select bits:

T3C3

T3C2

T3C1

T3C0

Timer T3 mode control bit

HC

C

Half Carry Flag

Carry Flag

T1PNDA Timer T1 Interrupt Pending Flag (Autoreload

RA in mode 1, T1 Underflow in Mode 2, T1A

capture edge in mode 3)

Timer T3 Start/Stop control in timer

modes 1 and 2, T3 Underflow Interrupt Pend-

ing Flag in timer mode 3

T1ENA

Timer T1 Interrupt Enable for Timer Underflow

or T1A Input capture edge

T3PNDA Timer T3 Interrupt Pending Flag (Autoreload

RA in mode 1, T3 Underflow in mode 2, T3A

capture edge in mode 3)

EXPND External interrupt pending

BUSY

EXEN

GIE

MICROWIRE/PLUS busy shifting flag

T3ENA

Timer T3 Interrupt Enable for Timer Underflow

or T3A Input capture edge

Enable external interrupt

Global interrupt enable (enables interrupts)

T3PNDB Timer T3 Interrupt Pending Flag for T3B cap-

ture edge

The Half-Carry flag is also affected by all the instructions that

affect the Carry flag. The SC (Set Carry) and R/C (Reset

Carry) instructions will respectively set or clear both the carry

T3ENB

Timer T3 Interrupt Enable for Timer Underflow

or T3B Input capture edge

13

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The Tx Timer control bits, TxC3, TxC2 and TxC1 set up the

timer for PWM mode operation.

Timers

The device contains a very versatile set of timers (T0, T1,

T2, T3). All timers and associated autoreload/capture regis-

ters power up containing random data.

Figure 8 shows a block diagram of the timer in PWM mode.

The underflows can be programmed to toggle the TxA output

pin. The underflows can also be programmed to generate in-

terrupts.

TIMER T0 (IDLE TIMER)

Underflows from the timer are alternately latched into two

pending flags, TxPNDA and TxPNDB. The user must reset

these pending flags under software control. Two control en-

able flags, TxENA and TxENB, allow the interrupts from the

timer underflow to be enabled or disabled. Setting the timer

enable flag TxENA will cause an interrupt when a timer un-

derflow causes the RxA register to be reloaded into the timer.

Setting the timer enable flag TxENB will cause an interrupt

when a timer underflow causes the RxB register to be re-

loaded into the timer. Resetting the timer enable flags will

disable the associated interrupts.

The device supports applications that require maintaining

real time and low power with the IDLE mode. This IDLE

mode support is furnished by the IDLE timer T0, which is a

16-bit timer. The Timer T0 runs continuously at the fixed rate

of the instruction cycle clock, t_c. The user cannot read or

write to the IDLE Timer T0, which is a count down timer.

The Timer T0 supports the following functions:

j

Exit out of the Idle Mode (See Idle Mode description)

WATCHDOG logic (See WATCHDOG description)

Start up delay out of the HALT mode

Either or both of the timer underflow interrupts may be en-

abled. This gives the user the flexibility of interrupting once

per PWM period on either the rising or falling edge of the

PWM output. Alternatively, the user may choose to interrupt

on both edges of the PWM output.

The IDLE Timer T0 can generate an interrupt when the thir-

teenth bit toggles. This toggle is latched into the T0PND

pending flag, and will occur every 4 ms at the maximum

clock frequency (t_c= 1 µs). A control flag T0EN allows the in-

terrupt from the thirteenth bit of Timer T0 to be enabled or

disabled. Setting T0EN will enable the interrupt, while reset-

ting it will disable the interrupt.

TIMER T1, TIMER T2 AND TIMER T3

The device has a set of three powerful timer/counter blocks,

T1, T2 and T3. The associated features and functioning of a

timer block are described by referring to the timer block Tx.

Since the three timer blocks, T1, T2 and T3 are identical, all

comments are equally applicable to any of the three timer

blocks.

Each timer block consists of a 16-bit timer, Tx, and two sup-

porting 16-bit autoreload/capture registers, RxA and RxB.

Each timer block has two pins associated with it, TxA and

TxB. The pin TxA supports I/O required by the timer block,

while the pin TxB is an input to the timer block. The powerful

and flexible timer block allows the device to easily perform all

timer functions with minimal software overhead. The timer

block has three operating modes: Processor Independent

PWM mode, External Event Counter mode, and Input Cap-

ture mode.

DS101133-10

FIGURE 8. Timer in PWM Mode

Mode 2. External Event Counter Mode

This mode is quite similar to the processor independent

PWM mode described above. The main difference is that the

timer, Tx, is clocked by the input signal from the TxA pin. The

Tx timer control bits, TxC3, TxC2 and TxC1 allow the timer to

be clocked either on a positive or negative edge from the

TxA pin. Underflows from the timer are latched into the TxP-

NDA pending flag. Setting the TxENA control flag will cause

an interrupt when the timer underflows.

The control bits TxC3, TxC2, and TxC1 allow selection of the

different modes of operation.

Mode 1. Processor Independent PWM Mode

As the name suggests, this mode allows the device to gen-

erate a PWM signal with very minimal user intervention. The

user only has to define the parameters of the PWM signal

(ON time and OFF time). Once begun, the timer block will

continuously generate the PWM signal completely indepen-

dent of the microcontroller. The user software services the

timer block only when the PWM parameters require updat-

ing.

In this mode the input pin TxB can be used as an indepen-

dent positive edge sensitive interrupt input if the TxENB con-

trol flag is set. The occurrence of a positive edge on the TxB

input pin is latched into the TxPNDB flag.

Figure 9 shows a block diagram of the timer in External

Event Counter mode.

In this mode the timer Tx counts down at a fixed rate of t_c.

Upon every underflow the timer is alternately reloaded with

the contents of supporting registers, RxA and RxB. The very

first underflow of the timer causes the timer to reload from

the register RxA. Subsequent underflows cause the timer to

be reloaded from the registers alternately beginning with the

register RxB.

Note: The PWM output is not available in this mode since the TxA pin is being

used as the counter input clock.

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14

Timers (Continued)

DS101133-12

FIGURE 10. Timer in Input Capture Mode

DS101133-11

FIGURE 9. Timer in External Event Counter Mode

Mode 3. Input Capture Mode

TIMER CONTROL FLAGS

The control bits and their functions are summarized below.

The device can precisely measure external frequencies or

time external events by placing the timer block, Tx, in the in-

put capture mode.

TxC3

TxC2

TxC1

TxC0

Timer mode control

In this mode, the timer Tx is constantly running at the fixed t_c

rate. The two registers, RxA and RxB, act as capture regis-

ters. Each register acts in conjunction with a pin. The register

RxA acts in conjunction with the TxA pin and the register RxB

acts in conjunction with the TxB pin.

Timer Start/Stop control in Modes 1 and 2 (Pro-

cessor Independent PWM and External Event

Counter), where 1 = Start, 0 = Stop

Timer Underflow Interrupt Pending Flag in

Mode 3 (Input Capture)

The timer value gets copied over into the register when a

trigger event occurs on its corresponding pin. Control bits,

TxC3, TxC2 and TxC1, allow the trigger events to be speci-

fied either as a positive or a negative edge. The trigger con-

dition for each input pin can be specified independently.

TxPNDA Timer Interrupt Pending Flag

TxENA

Timer Interrupt Enable Flag

1 = Timer Interrupt Enabled

0 = Timer Interrupt Disabled

The trigger conditions can also be programmed to generate

interrupts. The occurrence of the specified trigger condition

on the TxA and TxB pins will be respectively latched into the

pending flags, TxPNDA and TxPNDB. The control flag Tx-

ENA allows the interrupt on TxA to be either enabled or dis-

abled. Setting the TxENA flag enables interrupts to be gener-

ated when the selected trigger condition occurs on the TxA

pin. Similarly, the flag TxENB controls the interrupts from the

TxB pin.

TxPNDB Timer Interrupt Pending Flag

TxENB

Timer Interrupt Enable Flag

1 = Timer Interrupt Enabled

0 = Timer Interrupt Disabled

T2 has additional flexibility because T2B can be internally

connected to the comparator output of the Analog Function

Block. This allows the user to capture the time of a compara-

tor event without using external pins.

Underflows from the timer can also be programmed to gen-

erate interrupts. Underflows are latched into the timer TxC0

pending flag (the TxC0 control bit serves as the timer under-

flow interrupt pending flag in the Input Capture mode). Con-

sequently, the TxC0 control bit should be reset when enter-

ing the Input Capture mode. The timer underflow interrupt is

enabled with the TxENA control flag. When a TxA interrupt

occurs in the Input Capture mode, the user must check both

the TxPNDA and TxC0 pending flags in order to determine

whether a TxA input capture or a timer underflow (or both)

caused the interrupt.

Figure 10 shows a block diagram of the timer in Input Cap-

ture mode.

15

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Timers (Continued)

The timer mode control bits (TxC3, TxC2 and TxC1) are detailed below:

Interrupt A

Source

Interrupt B

Source

Timer

Mode

TxC3

TxC2

TxC1

Description

Counts On

1

0

1

0

PWM: TxA Toggle

Autoreload RA

Autoreload RB

t_C

1

PWM: No TxA

Toggle

t_C

0

1

0

1

0

External Event

Counter

Timer

Underflow

Pos. TxB Edge

Pos. TxA

Edge

2

External Event

Counter

Timer

Underflow

Pos. TxA

Edge

Captures:

Pos. TxA Edge

or Timer

t_C

TxA Pos. Edge

TxB Pos. Edge

Captures:

Underflow

1

0

1

0

1

Pos. TxA

Neg. TxB

Edge

TxA Pos. Edge

TxB Neg. Edge

Captures:

Edge or Timer

Underflow

3

Neg. TxA

Neg. TxB

Edge

TxA Neg. Edge

TxB Neg. Edge

Captures:

Edge or Timer

Underflow

Neg. TxA

Neg. TxB

Edge

TxA Neg. Edge

TxB Neg. Edge

Edge or Timer

Underflow

resonators have a delayed start up time to reach full ampli-

tude and frequency stability. The IDLE timer is used to gen-

erate a fixed delay to ensure that the oscillator has indeed

stabilized before allowing instruction execution. In this case,

upon detecting a valid Wakeup signal, only the oscillator cir-

cuitry is enabled. The IDLE timer is loaded with a value of

256 and is clocked with the t_cinstruction cycle clock. The t_c

clock is derived by dividing the oscillator clock down by a fac-

tor of 10. The Schmitt trigger following the CKI inverter on

the chip ensures that the IDLE timer is clocked only when the

oscillator has a sufficiently large amplitude to meet the

Schmitt trigger specifications. This Schmitt trigger is not part

of the oscillator closed loop. The startup timeout from the

IDLE timer enables the clock signals to be routed to the rest

of the chip.

Power Save Modes

The device offers the user two power save modes of opera-

tion: HALT and IDLE. In the HALT mode, all microcontroller

activities are stopped. In the IDLE mode, the on-board oscil-

lator circuitry the WATCHDOG logic, the Clock Monitor and

timer T0 are active but all other microcontroller activities are

stopped. In either mode, all on-board RAM, registers, I/O

states, and timers (with the exception of T0) are unaltered.

HALT MODE

The device can be placed in the HALT mode by writing a “1”

to the HALT flag (G7 data bit). All microcontroller activities,

including the clock and timers, are stopped. The WATCH-

DOG logic is disabled during the HALT mode. However, the

clock monitor circuitry if enabled remains active and will

cause the WATCHDOG output pin (WDOUT) to go low. If the

HALT mode is used and the user does not want to activate

the WDOUT pin, the Clock Monitor should be disabled after

the device comes out of reset (resetting the Clock Monitor

control bit with the first write to the WDSVR register). In the

HALT mode, the power requirements of the device are mini-

mal and the applied voltage (V_CC) may be decreased to V_r

(V_r= 2.0V) without altering the state of the machine.

If an RC clock option is being used, the fixed delay is intro-

duced optionally. A control bit, CLKDLY, mapped as configu-

ration bit G7, controls whether the delay is to be introduced

or not. The delay is included if CLKDLY is set, and excluded

if CLKDLY is reset. The CLKDLY bit is cleared on reset.

The device has two mask options associated with the HALT

mode. The first mask option enables the HALT mode feature,

while the second mask option disables the HALT mode. With

the HALT mode enable mask option, the device will enter

and exit the HALT mode as described above. With the HALT

disable mask option, the device cannot be placed in the

HALT mode (writing a “1” to the HALT flag will have no effect,

the HALT flag will remain “0”).

The device supports three different ways of exiting the HALT

mode. The first method of exiting the HALT mode is with the

Multi-Input Wakeup feature on the L port. The second

method is with a low to high transition on the CKO (G7) pin.

This method precludes the use of the crystal clock configura-

tion (since CKO becomes a dedicated output), and so may

be used with an RC clock configuration. The third method of

exiting the HALT mode is by pulling the RESET pin low.

The WATCHDOG detector circuit is inhibited during the

HALT mode. However, the clock monitor circuit if enabled re-

mains active during HALT mode in order to ensure a clock

monitor error if the device inadvertently enters the HALT

mode as a result of a runaway program or power glitch.

Since a crystal or ceramic resonator may be selected as the

oscillator, the Wakeup signal is not allowed to start the chip

running immediately since crystal oscillators and ceramic

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16

device will first execute the Timer T0 interrupt service routine

and then return to the instruction following the “Enter Idle

Mode” instruction.

Power Save Modes (Continued)

IDLE MODE

The device is placed in the IDLE mode by writing a “1” to the

IDLE flag (G6 data bit). In this mode, all activities, except the

associated on-board oscillator circuitry, the WATCHDOG

logic, the clock monitor and the IDLE Timer T0, are stopped.

Alternatively, the user can enter the IDLE mode with the

IDLE Timer T0 interrupt disabled. In this case, the device will

resume normal operation with the instruction immediately

following the “Enter IDLE Mode” instruction.

Note: It is necessary to program two NOP instructions following both the set

HALT mode and set IDLE mode instructions. These NOP instructions

are necessary to allow clock resynchronization following the HALT or

IDLE modes.

As with the HALT mode, the device can be returned to nor-

mal operation with a reset, or with a Multi-Input Wakeup from

the L Port. Alternately, the microcontroller resumes normal

operation from the IDLE mode when the thirteenth bit (repre-

senting 4.096 ms at internal clock frequency of 1 MHz, t_c= 1

µs) of the IDLE Timer toggles.

Multi-Input Wakeup

The Multi-Input Wakeup feature is ued to return (wakeup) the

device from either the HALT or IDLE modes. Alternately

Multi-Input Wakeup/Interrupt feature may also be used to

generate up to 8 edge selectable external interrupts.

This toggle condition of the thirteenth bit of the IDLE Timer

T0 is latched into the T0PND pending flag.

The user has the option of being interrupted with a transition

on the thirteenth bit of the IDLE Timer T0. The interrupt can

be enabled or disabled via the T0EN control bit. Setting the

T0EN flag enables the interrupt and vice versa.

Figure 11 shows the Multi-Input Wakeup logic.

The user can enter the IDLE mode with the Timer T0 inter-

rupt enabled. In this case, when the T0PND bit gets set, the

DS101133-13

FIGURE 11. Multi-Input Wake Up Logic

The Multi-Input Wakeup feature utilizes the L Port. The user

selects which particular L port bit (or combination of L Port

bits) will cause the device to exit the HALT or IDLE modes.

The selection is done through the Reg: WKEN. The Reg:

WKEN is an 8-bit read/write register, which contains a con-

trol bit for every L port bit. Setting a particular WKEN bit en-

ables a Wakeup from the associated L port pin.

an edge select entails several steps in order to avoid a

pseudo Wakeup condition as a result of the edge change.

First, the associated WKEN bit should be reset, followed by

the edge select change in WKEDG. Next, the associated

WKPND bit should be cleared, followed by the associated

WKEN bit being re-enabled.

An example may serve to clarify this procedure. Suppose we

wish to change the edge select from positive (low going high)

to negative (high going low) for L Port bit 5, where bit 5 has

previously been enabled for an input interrupt. The program

would be as follows:

The user can select whether the trigger condition on the se-

lected L Port pin is going to be either a positive edge (low to

high transition) or a negative edge (high to low transition).

This selection is made via the Reg: WKEDG, which is an

8-bit control register with a bit assigned to each L Port pin.

Setting the control bit will select the trigger condition to be a

negative edge on that particular L Port pin. Resetting the bit

selects the trigger condition to be a positive edge. Changing

RBIT 5, WKEN ; Disable MIWU

SBIT 5, WKEDG ; Change edge polarity

RBIT 5, WKPND ; Reset pending flag

SBIT 5, WKEN ; Enable MIWU

17

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PORT L INTERRUPTS

Multi-Input Wakeup (Continued)

Port L provides the user with an additional eight fully select-

able, edge sensitive interrupts which are all vectored into the

same service subroutine.

If the L port bits have been used as outputs and then

changed to inputs with Multi-Input Wakeup/Interrupt, a safety

procedure should also be followed to avoid inherited pseudo

wakeup conditions. After the selected L port bits have been

changed from output to input but before the associated

WKEN bits are enabled, the associated edge select bits in

WKEDG should be set or reset for the desired edge selects,

followed by the associated WKPND bits being cleared.

The interrupt from Port L shares logic with the wake up cir-

cuitry. The register WKEN allows interrupts from Port L to be

individually enabled or disabled. The register WKEDG speci-

fies the trigger condition to be either a positive or a negative

edge. Finally, the register WKPND latches in the pending

trigger conditions.

This same procedure should be used following reset, since

the L port inputs are left floating as a result of reset.

The GIE (Global Interrupt Enable) bit enables the interrupt

function.

The occurrence of the selected trigger condition for

Multi-Input Wakeup is latched into a pending register called

WKPND. The respective bits of the WKPND register will be

set on the occurrence of the selected trigger edge on the cor-

responding Port L pin. The user has the responsibility of

clearing these pending flags. Since WKPND is a pending

register for the occurrence of selected wakeup conditions,

the device will not enter the HALT mode if any Wakeup bit is

both enabled and pending. Consequently, the user has the

responsibility of clearing the pending flags before attempting

to enter the HALT mode.

A control flag, LPEN, functions as a global interrupt enable

for Port L interrupts. Setting the LPEN flag will enable inter-

rupts and vice versa. A separate global pending flag is not

needed since the register WKPND is adequate.

Since Port L is also used for waking the device out of the

HALT or IDLE modes, the user can elect to exit the HALT or

IDLE modes either with or without the interrupt enabled. If he

elects to disable the interrupt, then the device will restart ex-

ecution from the instruction immediately following the in-

struction that placed the microcontroller in the HALT or IDLE

modes. In the other case, the device will first execute the in-

terrupt service routine and then revert to normal operation.

(See HALT MODE for clock option wakeup information.)

WKEN, WKPND and WKEDG are all read/write registers,

and are cleared at reset.

Analog Function Block

DS101133-14

FIGURE 12. COP888EK Analog Function Block

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18

nominal 20 µA constant current at the I1

pin. This current can be used to ensure a

linear charging rate on an external capaci-

tor. This bit has no affect and the current

source is disabled if the comparator is not

enabled (CMPEN = 0).

Analog Function Block (Continued)

This device contains an analog function block with the intent

to provide a function which allows for single slope, low cost,

A/D conversion of up to 6 channels.

CMPSL REGISTER (ADDRESS X’00B7)

CMPEN

Enable the comparator (“1” = enable).

CMPT2B CMPISEL2 CMPISEL1 CMPISEL0 CMPOE CSEN CMPEN CMPNEG

CMPNEG

Will drive I1 to a low level. This bit can be

used to discharge an external capacitor.

This bit is disabled if the comparator is not

enabled (CMPEN = 0).

Bit 7

Bit 0

The CMPSL register contains the following bits:

CMPT2B

Selects the timer T2B input to be driven di-

rectly by the comparator output. If the com-

The Comparator Select Register is cleared on RESET (the

comparator is disabled). To save power the program should

also disable the comparator before the µC enters the HALT/

IDLE modes. Disabling the comparator will turn off the con-

stant current source and the V_CC/2 reference, disconnect the

comparator output from the T2B input and pin I3 or I7 and re-

move the low on I1 caused by CMPNEG.

parator is disabled (CMPEN = 0), this func-

tion is disabled, i.e., the T2B input is

connected to Port L5.

CMPISEL0/1/2 Will select one of seven possible sources

(I0/I2/I3/I4/I5/I6/internal reference) as

a

positive input to the comparator (see Table

3 for more information.) Power savings can

be realized by deselecting the internal ref-

erence when it is not in actual use.

It is often useful for the user’s program to read the result of

a comparator operation. Since I1 is always selected to be

COMPIN− when the comparator is enabled (CMPEN = 1),

the comparator output can be read internally by reading bit 1

(CMPRD) of register PORTI (RAM address 0 x D7).

CMPOE

CSEN

Enables the comparator output to either pin

I3 or pin I7 (“1” = enable) depending on the

value of CMPISEL0/1/2.

The following table lists the comparator inputs and outputs

vs. the value of the CMPISEL0/1/2 bits. The output will only

be driven if the CMPOE bit is set to 1.

Enables the internal constant current

source. This current source provides a

TABLE 3. Comparator Input Selection

Comparator Input Source

Neg. Input Pos. Input

I2

Control Bit

Comparator

CMPISEL2 CMPISEL1 CMPISEL0

Output

0

1

0

1

0

1

0

1

0

1

0

1

0

1

I1

I3

I7

I2

I3

I0

I4

I5

I6

V

_CC/2 Ref.

RESET

Interrupts

The state of the Comparator Block immediately after RESET

is as follows:

Each device supports eleven vectored interrupts. Interrupt

sources include Timer 0, Timer 1, Timer 2, Timer 3, Port L

Wakeup, Software Trap, MICROWIRE/PLUS, and External

Input.

1. The CMPSL Register is set to all zeros

2. The Comparator is disabled

3. The Constant Current Source is disabled

4. CMPNEG is turned off

All interrupts force a branch to location 00FF Hex in program

memory. The VIS instruction may be used to vector to the

appropriate service routine from location 00FF Hex.

5. The Port I inputs are electrically isolated from the com-

parator

The Software trap has the highest priority while the default

VIS has the lowest priority.

6. The T2B input is as normally selected by the T2CNTRL

Register

Each of the 11 maskable inputs has a fixed arbitration rank-

ing and vector.

7. CMPISEL0–CMPISEL2 are set to zero

Figure 13 shows the Interrupt Block Diagram.

8. All Port I inputs are selected to the default digital input

mode

The comparator outputs have the same specification as

Ports L and G except that the rise and fall times are sym-

metrical.

19

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Interrupts (Continued)

DS101133-15

FIGURE 13. Interrupt Block Diagram

MASKABLE INTERRUPTS

edged until the start of the next normally executed instruction

is to be skipped, the skip is performed before the pending in-

terrupt is acknowledged.

All interrupts other than the Software Trap are maskable.

Each maskable interrupt has an associated enable bit and

pending flag bit. The pending bit is set to 1 when the interrupt

condition occurs. The state of the interrupt enable bit, com-

bined with the GIE bit determines whether an active pending

flag actually triggers an interrupt. All of the maskable inter-

rupt pending and enable bits are contained in mapped con-

trol registers, and thus can be controlled by the software.

At the start of interrupt acknowledgment, the following ac-

tions occur:

1. The GIE bit is automatically reset to zero, preventing any

subsequent maskable interrupt from interrupting the cur-

rent service routine. This feature prevents one maskable

interrupt from interrupting another one being serviced.

A maskable interrupt condition triggers an interrupt under the

following conditions:

2. The address of the instruction about to be executed is

pushed onto the stack.

1. The enable bit associated with that interrupt is set.

2. The GIE bit is set.

3. The program counter (PC) is loaded with 00FF Hex,

causing a jump to that program memory location.

3. The device is not processing a non-maskable interrupt.

The device requires seven instruction cycles to perform the

actions listed above.

(If

a non-maskable interrupt is being serviced, a

maskable interrupt must wait until that service routine is

completed.)

If the user wishes to allow nested interrupts, the interrupts

service routine may set the GIE bit to 1 by writing to the PSW

register, and thus allow other maskable interrupts to interrupt

the current service routine. If nested interrupts are allowed,

caution must be exercised. The user must write the program

in such a way as to prevent stack overflow, loss of saved

context information, and other unwanted conditions.

An interrupt is triggered only when all of these conditions are

met at the beginning of an instruction. If different maskable

interrupts meet these conditions simultaneously, the highest

priority interrupt will be serviced first, and the other pending

interrupts must wait.

Upon Reset, all pending bits, individual enable bits, and the

GIE bit are reset to zero. Thus, a maskable interrupt condi-

tion cannot trigger an interrupt until the program enables it by

setting both the GIE bit and the individual enable bit. When

enabling an interrupt, the user should consider whether or

not a previously activated (set) pending bit should be ac-

knowledged. If, at the time an interrupt is enabled, any pre-

vious occurrences of the interrupt should be ignored, the as-

sociated pending bit must be reset to zero prior to enabling

the interrupt. Otherwise, the interrupt may be simply en-

abled; if the pending bit is already set, it will immediately trig-

ger an interrupt. A maskable interrupt is active if its associ-

ated enable and pending bits are set.

The interrupt service routine stored at location 00FF Hex

should use the VIS instruction to determine the cause of the

interrupt, and jump to the interrupt handling routine corre-

sponding to the highest priority enabled and active interrupt.

Alternately, the user may choose to poll all interrupt pending

and enable bits to determine the source(s) of the interrupt. If

more than one interrupt is active, the user’s program must

decide which interrupt to service.

Within a specific interrupt service routine, the associated

pending bit should be cleared. This is typically done as early

as possible in the service routine in order to avoid missing

the next occurrence of the same type of interrupt event.

Thus, if the same event occurs a second time, even while the

first occurrence is still being serviced, the second occur-

rence will be serviced immediately upon return from the cur-

rent interrupt routine.

An interrupt is an asychronous event which may occur be-

fore, during, or after an instruction cycle. Any interrupt which

occurs during the execution of an instruction is not acknowl-

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20

The vector table should be filled by the user with the memory

locations of the specific interrupt service routines. For ex-

ample, if the Software Trap routine is located at 0310 Hex,

then the vector location 0yFE and -0yFF should contain the

data 03 and 10 Hex, respectively. When a Software Trap in-

terrupt occurs and the VIS instruction is executed, the pro-

gram jumps to the address specified in the vector table.

Interrupts (Continued)

An interrupt service routine typically ends with an RETI in-

struction. This instruction sets the GIE bit back to 1, pops the

address stored on the stack, and restores that address to the

program counter. Program execution then proceeds with the

next instruction that would have been executed had there

been no interrupt. If there are any valid interrupts pending,

the highest-priority interrupt is serviced immediately upon re-

turn from the previous interrupt.

The interrupt sources in the vector table are listed in order of

rank, from highest to lowest priority. If two or more enabled

and pending interrupts are detected at the same time, the

one with the highest priority is serviced first. Upon return

from the interrupt service routine, the next highest-level

pending interrupt is serviced.

VIS INSTRUCTION

The general interrupt service routine, which starts at address

00FF Hex, must be capable of handling all types of inter-

rupts. The VIS instruction, together with an interrupt vector

table, directs the device to the specific interrupt handling rou-

tine based on the cause of the interrupt.

If the VIS instruction is executed, but no interrupts are en-

abled and pending, the lowest-priority interrupt vector is

used, and a jump is made to the corresponding address in

the vector table. This is an unusual occurrence, and may be

the result of an error. It can legitimately result from a change

in the enable bits or pending flags prior to the execution of

the VIS instruction, such as executing a single cycle instruc-

tion which clears an enable flag at the same time that the

pending flag is set. It can also result, however, from inadvert-

ent execution of the VIS command outside of the context of

an interrupt.

VIS is a single-byte instruction, typically used at the very be-

ginning of the general interrupt service routine at address

00FF Hex, or shortly after that point, just after the code used

for context switching. The VIS instruction determines which

enabled and pending interrupt has the highest priority, and

causes an indirect jump to the address corresponding to that

interrupt source. The jump addresses (vectors) for all pos-

sible interrupts sources are stored in a vector table.

The default VIS interrupt vector can be useful for applica-

tions in which time critical interrupts can occur during the

servicing of another interrupt. Rather than restoring the pro-

gram context (A, B, X, etc.) and executing the RETI instruc-

tion, an interrupt service routine can be terminated by return-

ing to the VIS instruction. In this case, interrupts will be

serviced in turn until no further interrupts are pending and

the default VIS routine is started. After testing the GIE bit to

ensure that execution is not erroneous, the routine should

restore the program context and execute the RETI to return

to the interrupted program.

The vector table may be as long as 32 bytes (maximum of 16

vectors) and resides at the top of the 256-byte block contain-

ing the VIS instruction. However, if the VIS instruction is at

the very top of a 256-byte block (such as at 00FF Hex), the

vector table resides at the top of the next 256-byte block.

Thus, if the VIS instruction is located somewhere between

00FF and 01DF Hex (the usual case), the vector table is lo-

cated between addresses 01E0 and 01FF Hex. If the VIS in-

struction is located between 01FF and 02DF Hex, then the

vector table is located between addresses 02E0 and 02FF

Hex, and so on.

This technique can save up to fifty instruction cycles (t_c), or

more, (50µs at 10 MHz oscillator) of latency for pending in-

terrupts with a penalty of fewer than ten instruction cycles if

no further interrupts are pending.

Each vector is 15 bits long and points to the beginning of a

specific interrupt service routine somewhere in the 32 kbyte

memory space. Each vector occupies two bytes of the vector

table, with the higher-order byte at the lower address. The

vectors are arranged in order of interrupt priority. The vector

of the maskable interrupt with the lowest rank is located to

0yE0 (higher-order byte) and 0yE1 (lower-order byte). The

next priority interrupt is located at 0yE2 and 0yE3, and so

forth in increasing rank. The Software Trap has the highest

rank and its vector is always located at 0yFE and 0yFF. The

number of interrupts which can become active defines the

size of the table.

To ensure reliable operation, the user should always use the

VIS instruction to determine the source of an interrupt. Al-

though it is possible to poll the pending bits to detect the

source of an interrupt, this practice is not recommended. The

use of polling allows the standard arbitration ranking to be al-

tered, but the reliability of the interrupt system is compro-

mised. The polling routine must individually test the enable

and pending bits of each maskable interrupt. If a Software

Trap interrupt should occur, it will be serviced last, even

though it should have the highest priority. Under certain con-

ditions, a Software Trap could be triggered but not serviced,

resulting in an inadvertent “locking out” of all maskable inter-

rupts by the Software Trap pending flag. Problems such as

this can be avoided by using VIS instruction.

Table 4 shows the types of interrupts, the interrupt arbitration

ranking, and the locations of the corresponding vectors in

the vector table.

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Interrupts (Continued)

TABLE 4. Interrupt Vector Table

Arbitration

Ranking

Vector (Note 12)

Address

Source

Description

Hi-Low Byte

0yFE–0yFF

0yFC–0yFD

0yFA–0yFB

0yF8–0yF9

0yF6–0yF7

0yF4–0yF5

0yF2–0yF3

0yF0–0yF1

0yEE–0yEF

0yEC–0yED

0yEA–0yEB

0yE8–0yE9

0yE6–0yE7

0yE4–0yE5

0yE2–0yE3

0yE0–0yE1

(1) Highest

Software

Reserved

External

Timer T0

Timer T1

INTR Instruction

(2)

(3)

(4)

(5)

(6)

G0

Underflow

T1A/Underflow

T1B

MICROWIRE/PLUS BUSY Low

Reserved

(7)

(8)

(9)

Timer T2

Timer T3

Port L/Wakeup

Default

T2A/Underflow

(10)

T2B

(11)

T3A/Underflow

T3B

(12)

(13)

Port L Edge

VIS Instr. Execution

without Any Interrupts

(14) Lowest

Note 12: y is a variable which represents the VIS block. VIS and the vector table must be located in the same 256-byte block except if VIS is located at the last ad-

dress of a block. In this case, the table must be in the next block.

VIS Execution

vector of the active interrupt with the highest arbitration rank-

ing. This vector is read from program memory and placed

into the PC which is now pointed to the 1st instruction of the

service routine of the active interrupt with the highest arbitra-

tion ranking.

When the VIS instruction is executed it activates the arbitra-

tion logic. The arbitration logic generates an even number

between E0 and FE (E0, E2, E4, E6 etc...) depending on

which active interrupt has the highest arbitration ranking at

the time of the 1st cycle of VIS is executed. For example, if

the software trap interrupt is active, FE is generated. If the

external interrupt is active and the software trap interrupt is

not, then FA is generated and so forth. If the only active inter-

rupt is software trap, than E0 is generated. This number re-

places the lower byte of the PC. The upper byte of the PC re-

mains unchanged. The new PC is therefore pointing to the

Figure 14 illustrates the different steps performed by the VIS

instruction. Figure 15 shows a flowchart for the VIS instruc-

tion.

The non-maskable interrupt pending flag is cleared by the

RPND (Reset Non-Maskable Pending Bit) instruction (under

certain conditions) and upon RESET.

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22

Interrupts (Continued)

DS101133-34

FIGURE 14. VIS Operation

DS101133-33

FIGURE 15. VIS Flowchart

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Interrupts (Continued)

Programming Example: External Interrupt

PSW

CNTRL

RBIT

SBIT

JP

=00EF

=00EE

0,PORTGC

0,PORTGD

IEDG, CNTRL

EXEN, PSW

GIE, PSW

WAIT

; G0 pin configured Hi-Z

; Ext interrupt polarity; falling edge

; Enable the external interrupt

; Set the GIE bit

WAIT:

; Wait for external interrupt

.

.=0FF

VIS

; The interrupt causes a

; branch to address 0FF

; The VIS causes a branch to

;interrupt vector table

.

.=01FA

.ADDRW SERVICE

; Vector table (within 256 byte

; of VIS inst.) containing the ext

; interrupt service routine

.

INT_EXIT:

SERVICE:

RETI

.

RBIT

EXPND, PSW

; Interrupt Service Routine

; Reset ext interrupt pend. bit

.

JP

INT_EXIT

; Return, set the GIE bit

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24

flag; upon return to the first Software Trap routine, the

STPND flag will have the wrong state. This will allow

maskable interrupts to be acknowledged during the servicing

of the first Software Trap. To avoid problems such as this, the

user program should contain the Software Trap routine to

perform a recovery procedure rather than a return to normal

execution.

Interrupts (Continued)

NON-MASKABLE INTERRUPT

Pending Flag

There is a pending flag bit associated with the non-maskable

interrupt, called STPND. This pending flag is not memory-

mapped and cannot be accessed directly by the software.

Under normal conditions, the STPND flag is reset by a

RPND instruction in the Software Trap service routine. If a

programming error or hardware condition (brownout, power

supply glitch, etc.) sets the STPND flag without providing a

way for it to be cleared, all other interrupts will be locked out.

To alleviate this condition, the user can use extra RPND in-

structions in the main program and in the WATCHDOG ser-

vice routine (if present). There is no harm in executing extra

RPND instructions in these parts of the program.

The pending flag is reset to zero when a device Reset oc-

curs. When the non-maskable interrupt occurs, the associ-

ated pending bit is set to 1. The interrupt service routine

should contain an RPND instruction to reset the pending flag

to zero. The RPND instruction always resets the STPND

flag.

Software Trap

The Software Trap is a special kind of non-maskable inter-

rupt which occurs when the INTR instruction (used to ac-

knowledge interrupts) is fetched from program memory and

placed in the instruction register. This can happen in a vari-

ety of ways, usually because of an error condition. Some ex-

amples of causes are listed below.

PORT L INTERRUPTS

Port L provides the user with an additional eight fully select-

able, edge sensitive interrupts which are all vectored into the

same service subroutine.

The interrupt from Port L shares logic with the wake up cir-

cuitry. The register WKEN allows interrupts from Port L to be

individually enabled or disabled. The register WKEDG speci-

fies the trigger condition to be either a positive or a negative

edge. Finally, the register WKPND latches in the pending

trigger conditions.

If the program counter incorrectly points to a memory loca-

tion beyond the available program memory space, the non-

existent or unused memory location returns zeroes which is

interpreted as the INTR instruction.

If the stack is popped beyond the allowed limit (address 06F

Hex), a 7FFF will be loaded into the PC, if this last location in

program memory is unprogrammed or unavailable, a Soft-

ware Trap will be triggered.

The GIE (Global Interrupt Enable) bit enables the interrupt

function.

A control flag, LPEN, functions as a global interrupt enable

for Port L interrupts. Setting the LPEN flag will enable inter-

rupts and vice versa. A separate global pending flag is not

needed since the register WKPND is adequate.

A Software Trap can be triggered by a temporary hardware

condition such as a brownout or power supply glitch.

The Software Trap has the highest priority of all interrupts.

When a Software Trap occurs, the STPND bit is set. The GIE

bit is not affected and the pending bit (not accessible by the

user) is used to inhibit other interrupts and to direct the pro-

gram to the ST service routine with the VIS instruction. Noth-

ing can interrupt a Software Trap service routine except for

another Software Trap. The STPND can be reset only by the

RPND instruction or a chip Reset.

Since Port L is also used for waking the device out of the

HALT or IDLE modes, the user can elect to exit the HALT or

IDLE modes either with or without the interrupt enabled. If he

elects to disable the interrupt, then the device will restart ex-

ecution from the instruction immediately following the in-

struction that placed the microcontroller in the HALT or IDLE

modes. In the other case, the device will first execute the in-

terrupt service routine and then revert to normal operation.

(See HALT MODE for clock option wakeup information.)

The Software Trap indicates an unusual or unknown error

condition. Generally, returning to normal execution at the

point where the Software Trap occurred cannot be done re-

liably. Therefore, the Software Trap service routine should

reinitialize the stack pointer and perform a recovery proce-

dure that restarts the software at some known point, similar

to a device Reset, but not necessarily performing all the

same functions as a device Reset. The routine must also ex-

ecute the RPND instruction to reset the STPND flag. Other-

wise, all other interrupts will be locked out. To the extent pos-

sible, the interrupt routine should record or indicate the

context of the device so that the cause of the Software Trap

can be determined.

INTERRUPT SUMMARY

The device uses the following types of interrupts, listed be-

low in order of priority:

1. The Software Trap non-maskable interrupt, triggered by

the INTR (00 opcode) instruction. The Software Trap is

acknowledged immediately. This interrupt service rou-

tine can be interrupted only by another Software Trap.

The Software Trap should end with two RPND instruc-

tions followed by a restart procedure.

2. Maskable interrupts, triggered by an on-chip peripheral

block or an external device connected to the device. Un-

der ordinary conditions, a maskable interrupt will not in-

If the user wishes to return to normal execution from the

point at which the Software Trap was triggered, the user

must first execute RPND, followed by RETSK rather than

RETI or RET. This is because the return address stored on

the stack is the address of the INTR instruction that triggered

the interrupt. The program must skip that instruction in order

to proceed with the next one. Otherwise, an infinite loop of

Software Traps and returns will occur.

terrupt any other interrupt routine in progress.

maskable interrupt routine in progress can be inter-

rupted by the non-maskable interrupt request.

maskable interrupt routine should end with an RETI in-

struction or, prior to restoring context, should return to

execute the VIS instruction. This is particularly useful

when exiting long interrupt service routiness if the time

between interrupts is short. In this case the RETI instruc-

tion would only be executed when the default VIS rou-

tine is reached.

A

Programming a return to normal execution requires careful

consideration. If the Software Trap routine is interrupted by

another Software Trap, the RPND instruction in the service

routine for the second Software Trap will reset the STPND

25

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occur after coming out of reset, if the instruction cycle clock

frequency has not reached a minimum specified value, in-

cluding the case where the oscillator fails to start.

WATCHDOG

The device contains a WATCHDOG and clock monitor. The

WATCHDOG is designed to detect the user program getting

stuck in infinite loops resulting in loss of program control or

“runaway” programs. The Clock Monitor is used to detect the

absence of a clock or a very slow clock below a specified

rate on the CKI pin.

The WDSVR register can be written to only once after reset

and the key data (bits 5 through 1 of the WDSVR Register)

must match to be a valid write. This write to the WDSVR reg-

ister involves two irrevocable choices: (i) the selection of the

WATCHDOG service window (ii) enabling or disabling of the

Clock Monitor. Hence, the first write to WDSVR Register in-

volves selecting or deselecting the Clock Monitor, select the

WATCHDOG service window and match the WATCHDOG

key data. Subsequent writes to the WDSVR register will

compare the value being written by the user to the WATCH-

DOG service window value and the key data (bits 7 through

1) in the WDSVR Register. Table IV shows the sequence of

events that can occur.

The WATCHDOG consists of two independent logic blocks:

WD UPPER and WD LOWER. WD UPPER establishes the

upper limit on the service window and WD LOWER defines

the lower limit of the service window.

Servicing the WATCHDOG consists of writing a specific

value to a WATCHDOG Service Register named WDSVR

which is memory mapped in the RAM. This value is com-

posed of three fields, consisting of a 2-bit Window Select, a

5-bit Key Data field, and the 1-bit Clock Monitor Select field.

Table 5 shows the WDSVR register.

The user must service the WATCHDOG at least once before

the upper limit of the service window expires. The WATCH-

DOG may not be serviced more than once in every lower

limit of the service window. The user may service the

WATCHDOG as many times as wished in the time period be-

tween the lower and upper limits of the service window. The

first write to the WDSVR Register is also counted as a

WATCHDOG service.

TABLE 5. WATCHDOG Service Register (WDSVR)

Window

Select

Clock

Key Data

Monitor

X

7

X

6

0

5

1

4

1

3

0

2

0

1

Y

0

The WATCHDOG has an output pin associated with it. This

is the WDOUT pin, on pin 1 of the port G. WDOUT is active

low. The WDOUT pin is in the high impedance state in the in-

active state. Upon triggering the WATCHDOG, the logic will

pull the WDOUT (G1) pin low for an additional 16 t_c–32 t_c

cycles after the signal level on WDOUT pin goes below the

lower Schmitt trigger threshold. After this delay, the device

will stop forcing the WDOUT output low.

The lower limit of the service window is fixed at 2048 instruc-

tion cycles. Bits 7 and 6 of the WDSVR register allow the

user to pick an upper limit of the service window.

Table 6 shows the four possible combinations of lower and

upper limits for the WATCHDOG service window. This flex-

ibility in choosing the WATCHDOG service window prevents

any undue burden on the user software.

The WATCHDOG service window will restart when the

WDOUT pin goes high. It is recommended that the user tie

the WDOUT pin back to V_CCthrough a resistor in order to

pull WDOUT high.

Bits 5, 4, 3, 2 and 1 of the WDSVR register represent the

5-bit Key Data field. The key data is fixed at 01100. Bit 0 of

the WDSVR Register is the Clock Monitor Select bit.

A WATCHDOG service while the WDOUT signal is active will

be ignored. The state of the WDOUT pin is not guaranteed

on reset, but if it powers up low then the WATCHDOG will

time out and WDOUT will enter high impedance state.

TABLE 6. WATCHDOG Service Window Select

WDSVR WDSVR

Clock

Service Window

(Lower-Upper Limits)

2048–8k t_CCycles

Bit 7

Bit 6

Monitor

The Clock Monitor forces the G1 pin low upon detecting a

clock frequency error. The Clock Monitor error will continue

until the clock frequency has reached the minimum specified

value, after which the G1 output will enter the high imped-

ance TRI-STATE mode following 16 t_c–32 t_cclock cycles.

The Clock Monitor generates a continual Clock Monitor error

if the oscillator fails to start, or fails to reach the minimum

specified frequency. The specification for the Clock Monitor

is as follows:

0

1

x

0

1

0

1

x

0

1

2048–16k t_CCycles

2048–32k t_CCycles

2048–64k t_CCycles

Clock Monitor Disabled

Clock Monitor Enabled

>

1/t_c10 kHz—No clock rejection.

Clock Monitor

<

1/t_c10 Hz—Guaranteed clock rejection.

The Clock Monitor aboard the device can be selected or de-

selected under program control. The Clock Monitor is guar-

anteed not to reject the clock if the instruction cycle clock (1/

t_c) is greater or equal to 10 kHz. This equates to a clock input

rate on CKI of greater or equal to 100 kHz.

WATCHDOG AND CLOCK MONITOR SUMMARY

The following salient points regarding the WATCHDOG and

CLOCK MONITOR should be noted:

•

Both the WATCHDOG and CLOCK MONITOR detector

circuits are inhibited during RESET.

WATCHDOG Operation

•

Following RESET, the WATCHDOG and CLOCK MONI-

TOR are both enabled, with the WATCHDOG having he

maximum service window selected.

The WATCHDOG and Clock Monitor are disabled during re-

set. The device comes out of reset with the WATCHDOG

armed, the WATCHDOG Window Select bits (bits 6, 7 of the

WDSVR Register) set, and the Clock Monitor bit (bit 0 of the

WDSVR Register) enabled. Thus, a Clock Monitor error will

•

The WATCHDOG service window and CLOCK MONI-

TOR enable/disable option can only be changed once,

during the initial WATCHDOG service following RESET.

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26

The subroutine stack grows down for each call (jump to sub-

routine), interrupt, or PUSH, and grows up for each return or

POP. The stack pointer is initialized to RAM location 06F Hex

during reset. Consequently, if there are more returns than

calls, the stack pointer will point to addresses 070 and 071

Hex (which are undefined RAM). Undefined RAM from ad-

dresses 070 to 07F (Segment 0), 140 to 17F (Segment 1),

and all other segments (i.e., Segments 2 … etc.) is read as

all 1’s, which in turn will cause the program to return to ad-

dress 7FFF Hex. This is an undefined ROM location and the

instruction fetched (all 0’s) from this location will generate a

software interrupt signaling an illegal condition.

WATCHDOG Operation (Continued)

•

The initial WATCHDOG service must match the key data

value in the WATCHDOG Service register WDSVR in or-

der to avoid a WATCHDOG error.

Subsequent WATCHDOG services must match all three

data fields in WDSVR in order to avoid WATCHDOG er-

rors.

The correct key data value cannot be read from the

WATCHDOG Service register WDSVR. Any attempt to

read this key data value of 01100 from WDSVR will read

as key data value of all 0’s.

Thus, the chip can detect the following illegal conditions:

1. Executing from undefined ROM

•

The WATCHDOG detector circuit is inhibited during both

the HALT and IDLE modes.

2. Over “POP”ing the stack by having more returns than

calls.

The CLOCK MONITOR detector circuit is active during

both the HALT and IDLE modes. Consequently, the de-

vice inadvertently entering the HALT mode will be de-

tected as a CLOCK MONITOR error (provided that the

CLOCK MONITOR enable option has been selected by

the program).

When the software interrupt occurs, the user can re-initialize

the stack pointer and do a recovery procedure before restart-

ing (this recovery program is probably similar to that follow-

ing reset, but might not contain the same program initializa-

tion procedures). The recovery program should reset the

software interrupt pending bit using the RPND instruction.

•

With the single-pin R/C oscillator mask option selected

and the CLKDLY bit reset, the WATCHDOG service win-

dow will resume following HALT mode from where it left

off before entering the HALT mode.

MICROWIRE/PLUS

With the crystal oscillator mask option selected, or with

the single-pin R/C oscillator mask option selected and the

CLKDLY bit set, the WATCHDOG service window will be

set to its selected value from WDSVR following HALT.

Consequently, the WATCHDOG should not be serviced

for at least 2048 instruction cycles following HALT, but

must be serviced within the selected window to avoid a

WATCHDOG error.

MICROWIRE/PLUS is a serial synchronous communications

interface. The MICROWIRE/PLUS capability enables the de-

vice to interface with any of National Semiconductor’s MI-

CROWIRE peripherals (i.e. A/D converters, display drivers,

E²PROMs etc.) and with other microcontrollers which sup-

port the MICROWIRE interface. It consists of an 8-bit serial

shift register (SIO) with serial data input (SI), serial data out-

put (SO) and serial shift clock (SK). Figure 16 shows a block

diagram of the MICROWIRE/PLUS logic.

•

The IDLE timer T0 is not initialized with RESET.

The user can sync in to the IDLE counter cycle with an

IDLE counter (T0) interrupt or by monitoring the T0PND

flag. The T0PND flag is set whenever the thirteenth bit of

the IDLE counter toggles (every 4096 instruction cycles).

The user is responsible for resetting the T0PND flag.

•

A hardware WATCHDOG service occurs just as the de-

vice exits the IDLE mode. Consequently, the WATCH-

DOG should not be serviced for at least 2048 instruction

cycles following IDLE, but must be serviced within the se-

lected window to avoid a WATCHDOG error.

Following RESET, the initial WATCHDOG service (where

the service window and the CLOCK MONITOR enable/

disable must be selected) may be programmed any-

where within the maximum service window (65,536 in-

struction cycles) initialized by RESET. Note that this initial

WATCHDOG service may be programmed within the ini-

tial 2048 instruction cycles without causing a WATCH-

DOG error.

DS101133-16

FIGURE 16. MICROWIRE/PLUS Block Diagram

The shift clock can be selected from either an internal source

or an external source. Operating the MICROWIRE/PLUS ar-

rangement with the internal clock source is called the Master

mode of operation. Similarly, operating the MICROWIRE/

PLUS arrangement with an external shift clock is called the

Slave mode of operation.

Detection of Illegal Conditions

The device can detect various illegal conditions resulting

from coding errors, transient noise, power supply voltage

drops, runaway programs, etc.

The CNTRL register is used to configure and control the

MICROWIRE/PLUS mode. To use the MICROWIRE/PLUS,

the MSEL bit in the CNTRL register is set to one. In the mas-

ter mode, the SK clock rate is selected by the two bits, SL0

and SL1, in the CNTRL register. details the different clock

rates that may be selected.

Reading of undefined ROM gets zeros. The opcode for soft-

ware interrupt is zero. If the program fetches instructions

from undefined ROM, this will force a software interrupt, thus

signaling that an illegal condition has occurred.

27

www.national.com

MICROWIRE/PLUS (Continued)

TABLE 7. WATCHDOG Service Actions

Key

Window

Clock

Monitor

Match

Action

Data

Match

Valid Service: Restart Service Window

Error: Generate WATCHDOG Output

Don’t Care

Mismatch

Don’t Care

Mismatch

Don’t Care

Mismatch

onto the G Port. The SK pin must be selected as an input

and the SO pin is selected as an output pin by setting and re-

setting the appropriate bits in the Port G configuration regis-

ter. Table 9 summarizes the settings required to enter the

Slave mode of operation.

TABLE 8. MICROWIRE/PLUS

Master Mode Clock Select

SL1

0

SL0

SK

2 x t_c

0

1

x

The user must set the BUSY flag immediately upon entering

the Slave mode. This will ensure that all data bits sent by the

Master will be shifted properly. After eight clock pulses the

BUSY flag will be cleared and the sequence may be re-

peated.

0

4 x t_c

8 x t_c

1

Where t is the

c

instruction cycle clock

MICROWIRE/PLUS OPERATION

TABLE 9. MICROWIRE/PLUS Mode Settings

This table assumes that the control flag MSEL is set.

Setting the BUSY bit in the PSW register causes the

MICROWIRE/PLUS to start shifting the data. It gets reset

when eight data bits have been shifted. The user may reset

the BUSY bit by software to allow less than 8 bits to shift. If

enabled, an interrupt is generated when eight data bits have

been shifted. The device may enter the MICROWIRE/PLUS

mode either as a Master or as a Slave. Figure 17 shows how

two microcontroller devices and several peripherals may be

interconnected using the MICROWIRE/PLUS arrangements.

G4 (SO)

G5 (SK)

G4

Fun.

SO

G5

Fun.

Int.

Operation

Config. Bit Config. Bit

1

0

1

0

1

0

MICROWIRE/PLUS

Master

SK

TRI-

STATE

SO

Int.

MICROWIRE/PLUS

Master

SK

Ext.

SK

MICROWIRE/PLUS

Slave

Warning:

The SIO register should only be loaded when the SK clock is

low. Loading the SIO register while the SK clock is high will

result in undefined data in the SIO register. SK clock is nor-

mally low when not shifting.

TRI-

Ext.

SK

MICROWIRE/PLUS

Slave

STATE

Alternate SK Phase Operation

Setting the BUSY flag when the input SK clock is high in the

MICROWIRE/PLUS slave mode may cause the current SK

clock for the SIO shift register to be narrow. For safety, the

BUSY flag should only be set when the input SK clock is low.

The device allows either the normal SK clock or an alternate

phase SK clock to shift data in and out of the SIO register. In

both the modes the SK is normally low. In the normal mode

data is shifted in on the rising edge of the SK clock and the

data is shifted out on the falling edge of the SK clock. The

SIO register is shifted on each falling edge of the SK clock.

In the alternate SK phase operation, data is shifted in on the

falling edge of the SK clock and shifted out on the rising edge

of the SK clock.

MICROWIRE/PLUS Master Mode Operation

In the MICROWIRE/PLUS Master mode of operation the

shift clock (SK) is generated internally by the device. The MI-

CROWIRE Master always initiates all data exchanges. The

MSEL bit in the CNTRL register must be set to enable the

SO and SK functions onto the G Port. The SO and SK pins

must also be selected as outputs by setting appropriate bits

in the Port G configuration register. Table 9 summarizes the

bit settings required for Master mode of operation.

A control flag, SKSEL, allows either the normal SK clock or

the alternate SK clock to be selected. Resetting SKSEL

causes the MICROWIRE/PLUS logic to be clocked from the

normal SK signal. Setting the SKSEL flag selects the alter-

nate SK clock. The SKSEL is mapped into the G6 configura-

tion bit. The SKSEL flag will power up in the reset condition,

selecting the normal SK signal.

MICROWIRE/PLUS Slave Mode Operation

In the MICROWIRE/PLUS Slave mode of operation the SK

clock is generated by an external source. Setting the MSEL

bit in the CNTRL register enables the SO and SK functions

www.national.com

28

MICROWIRE/PLUS (Continued)

DS101133-17

FIGURE 17. MICROWIRE/PLUS Application

29

www.national.com

Memory Map

Address

S/ADD REG

xxD0

Contents

All RAM, ports and registers (except A and PC) are

mapped into data memory address space.

Port L Data Register

Address

Contents

xxD1

Port L Configuration Register

Port L Input Pins (Read Only)

Reserved for Port L

S/ADD REG

0000 to 006F

0070 to 007F

xxD2

On-Chip RAM bytes (112 bytes)

xxD3

Unused RAM Address Space (Reads

As All Ones)

xxD4

Port G Data Register

xxD5

Port G Configuration Register

Port G Input Pins (Read Only)

Port I Input Pins (Read Only)

Port C Data Register

xx80 to xxAF

Unused RAM Address Space (Reads

Undefined Data)

xxD6

xxD7

xxB0

xxB1

xxB2

Timer T3 Lower Byte

Timer T3 Upper Byte

xxD8

xxD9

Port C Configuration Register

Port C Input Pins (Read Only)

Reserved for Port C

Timer T3 Autoload Register T3RA

Lower Byte

xxDA

xxB3

xxB4

xxB5

Timer T3 Autoload Register T3RA

Upper Byte

xxDB

xxDC

Port D

Timer T3 Autoload Register T3RB

Lower Byte

xxDD to xxDF Reserved

xxE0 to xxE5

xxE6

Reserved

Timer T3 Autoload Register T3RB

Upper Byte

Timer T1 Autoload Register T1RB

Lower Byte

xxB6

Timer T3 Control Register

Comparator Select Register (CMPSL)

Reserved

xxE7

Timer T1 Autoload Register T1RB

Upper Byte

xxB7

xxB8 to xxBF

xxC0

xxE8

xxE9

xxEA

xxEB

xxEC

ICNTRL Register

Timer T2 Lower Byte

Timer T2 Upper Byte

MICROWIRE/PLUS Shift Register

Timer T1 Lower Byte

xxC1

xxC2

Timer T2 Autoload Register T2RA

Lower Byte

Timer T1 Upper Byte

Timer T1 Autoload Register T1RA

Lower Byte

xxC3

xxC4

xxC5

Timer T2 Autoload Register T2RA

Upper Byte

xxED

Timer T1 Autoload Register T1RA

Upper Byte

Timer T2 Autoload Register T2RB

Lower Byte

xxEE

CNTRL Control Register

PSW Register

Timer T2 Autoload Register T2RB

Upper Byte

xxEF

xxF0 to xxFB

xxFC

On-Chip RAM Mapped as Registers

X Register

xxC6

xxC7

Timer T2 Control Register

WATCHDOG Service Register

(Reg:WDSVR)

xxFD

SP Register

xxFE

B Register

xxC8

MIWU Edge Select Register

(Reg:WKEDG)

xxFF

S Register

0100 to 017F

On-Chip 128 RAM Bytes

xxC9

xxCA

xxCB

xxCC

MIWU Enable Register (Reg:WKEN)

MIWU Pending Register (Reg:WKPND)

Reserved

Reading memory locations 0070H–007FH (Segment 0) will return all ones.

Reading unused memory locations 0080H–00AFH (Segment 0) will return

undefined data. Reading memory locations from other unused Segments

(i.e., Segment 2, Segment 3, … etc.) will return undefined data.

Reserved

xxCD to xxCF Reserved

www.national.com

30

Addressing Modes

There are ten addressing modes, six for operand addressing

Indirect

and four for transfer of control.

This mode is used with the JID instruction. The contents of

the accumulator are used as a partial address (lower 8 bits of

PC) for accessing a location in the program memory. The

contents of this program memory location serve as a partial

address (lower 8 bits of PC) for the jump to the next instruc-

tion.

OPERAND ADDRESSING MODES

Register Indirect

This is the “normal” addressing mode. The operand is the

data memory addressed by the B pointer or X pointer.

Note: The VIS is a special case of the Indirect Transfer of Control addressing

mode, where the double byte vector associated with the interrupt is

transferred from adjacent addresses in the program memory into the

program counter (PC) in order to jump to the associated interrupt ser-

vice routine.

Register Indirect (with auto post increment or

decrement of pointer)

This addressing mode is used with the LD and X instruc-

tions. The operand is the data memory addressed by the B

pointer or X pointer. This is a register indirect mode that au-

tomatically post increments or decrements the B or X regis-

ter after executing the instruction.

Instruction Set

Register and Symbol Definition

Direct

The instruction contains an 8-bit address field that directly

points to the data memory for the operand.

Registers

A

8-Bit Accumulator Register

8-Bit Address Register

Immediate

B

The instruction contains an 8-bit immediate field as the oper-

and.

X

8-Bit Address Register

S

8-Bit Segment Register

Short Immediate

SP

PC

PU

PL

C

8-Bit Stack Pointer Register

15-Bit Program Counter Register

Upper 7 Bits of PC

This addressing mode is used with the Load B Immediate in-

struction. The instruction contains a 4-bit immediate field as

the operand.

Indirect

Lower 8 Bits of PC

This addressing mode is used with the LAID instruction. The

contents of the accumulator are used as a partial address

(lower 8 bits of PC) for accessing a data operand from the

program memory.

1 Bit of PSW Register for Carry

1 Bit of PSW Register for Half Carry

HC

GIE

1 Bit of PSW Register for Global Interrupt

Enable

TRANSFER OF CONTROL ADDRESSING MODES

VU

VL

Interrupt Vector Upper Byte

Interrupt Vector Lower Byte

Relative

This mode is used for the JP instruction, with the instruction

field being added to the program counter to get the new pro-

gram location. JP has a range from −31 to +32 to allow a

1-byte relative jump (JP + 1 is implemented by a NOP in-

struction). There are no “pages” when using JP, since all 15

bits of PC are used.

Symbols

[B]

Memory Indirectly Addressed by B Register

Memory Indirectly Addressed by X Register

Direct Addressed Memory

[X]

MD

Mem

Meml

Direct Addressed Memory or [B]

Direct Addressed Memory or [B] or

Immediate Data

Absolute

This mode is used with the JMP and JSR instructions, with

the instruction field of 12 bits replacing the lower 12 bits of

the program counter (PC). This allows jumping to any loca-

tion in the current 4k program memory segment.

Imm

Reg

8-Bit Immediate Data

Register Memory: Addresses F0 to FF

(Includes B, X and SP)

Bit

←

↔

Bit Number (0 to 7)

Loaded with

Absolute Long

This mode is used with the JMPL and JSRL instructions, with

the instruction field of 15 bits replacing the entire 15 bits of

the program counter (PC). This allows jumping to any loca-

tion in the current 4k program memory space.

Exchanged with

31

www.national.com

Instruction Set (Continued)

INSTRUCTION SET

←

ADD

ADC

A,Meml

ADD

A

A + Meml

A + Meml + C, C Carry

←

ADD with Carry

←

HC Half Carry

← ←

A − MemI + C, C Carry

SUBC

A,Meml

Subtract with Carry

A

←

HC Half Carry

←

AND

ANDSZ

OR

A,Meml

A,Imm

A,Meml

MD,Imm

A,Meml

#

Logical AND

A

A and Meml

Logical AND Immed., Skip if Zero

Logical OR

Skip next if (A and Imm) = 0

←

A

A or Meml

XOR

IFEQ

IFNE

IFGT

IFBNE

DRSZ

SBIT

RBIT

IFBIT

RPND

X

Logical EXclusive OR

IF EQual

A xor Meml

Compare MD and Imm, Do next if MD = Imm

Compare A and Meml, Do next if A = Meml

IF EQual

≠

Compare A and Meml, Do next if A Meml

IF Not Equal

>

IF Greater Than

Compare A and Meml, Do next if A Meml

≠

If B Not Equal

Do next if lower 4 bits of B Imm

←

Reg

Decrement Reg., Skip if Zero

Set BIT

Reg Reg − 1, Skip if Reg = 0

#

,Mem

1 to bit, Mem (bit = 0 to 7 immediate)

0 to bit, Mem

Reset BIT

IF BIT

If bit in A or Mem is true do next instruction

Reset Software Interrupt Pending Flag

Reset PeNDing Flag

EXchange A with Memory

EXchange A with Memory [X]

LoaD A with Memory

LoaD A with Memory [X]

LoaD B with Immed.

LoaD Memory Immed

LoaD Register Memory Immed.

EXchange A with Memory [B]

EXchange A with Memory [X]

LoaD A with Memory [B]

LoaD A with Memory [X]

LoaD Memory [B] Immed.

CLeaR A

↔

←

A,Mem

A,[X]

A

B

Mem

[X]

X

LD

A,Meml

A,[X]

Meml

[X]

LD

B,Imm

Imm

←

Mem Imm

LD

Mem,Imm

Reg,Imm

←

Reg Imm

LD

↔

←

±

X

A, [B

A, [X

]

A

[B], (B

[X], (X

B

±

1)

←

X

1)

←

±

LD

A, [B ]

[B], (B

B

1)

←

±

LD

A, [X ]

[X], (X X 1)

←

±

LD

[B ],Imm

[B] Imm, (B B 1)

←

→

CLR

INC

A

C

0

INCrement A

A + 1

DEC

LAID

DCOR

RRC

RLC

SWAP

SC

DECrement A

A − 1

Load A InDirect from ROM

Decimal CORrect A

Rotate A Right thru C

Rotate A Left thru C

SWAP nibbles of A

Set C

ROM (PU,A)

A

BCD correction of A (follows ADC, SUBC)

→

←

→

←

→

←

A7

…

A0

C

←

↔

A7…A4 A3…A0

←

C

1, HC

0, HC

1

0

RC

Reset C

IFC

IF C

IF C is true, do next instruction

IFNC

POP

PUSH

VIS

IF Not C

If C is not true, do next instruction

← ←

SP SP + 1, A [SP]

A

POP the stack into A

PUSH A onto the stack

Vector to Interrupt Service Routine

Jump absolute Long

Jump absolute

←

[SP] A, SP SP − 1

←

PU [VU], PL [VL]

←

PC ii (ii = 15 bits, 0 to 32k)

JMPL

JMP

JP

Addr.

Disp.

←

PC9…0 i (i = 12 bits)

←

PC PC + r (r is −31 to +32, except 1)

Jump relative short

www.national.com

32

Instruction Set (Continued)

← ← ←

[SP] PL, [SP−1] PU,SP−2, PC ii

JSRL

JSR

Addr.

Addr

Jump SubRoutine Long

Jump SubRoutine

Jump InDirect

←

[SP] PL, [SP−1] PU,SP−2, PC9…0

i

←

PL ROM (PU,A)

JID

← ←

SP + 2, PL [SP], PU [SP−1]

RET

RETurn from subroutine

RETurn and SKip

RETurn from Interrupt

Generate an Interrupt

No OPeration

← ←

SP + 2, PL [SP],PU [SP−1]

RETSK

RETI

INTR

NOP

←

SP + 2, PL [SP],PU [SP−1],GIE

1

←

[SP] PL, [SP−1] PU, SP−2, PC 0FF

←

PC PC + 1

33

www.national.com

Instructions Using A & C

Instruction Set (Continued)

CLRA

INCA

DECA

LAID

1/1

1/3

1/1

1/3

2/2

Instruction Execution Time

Most instructions are single byte (with immediate addressing

mode instructions taking two bytes).

Most single byte instructions take one cycle time to execute.

•

Skipped instructions require x number of cycles to be

skipped, where x equals the number of bytes in the

skipped instruction opcode.

DCOR

RRCA

RLCA

SWAPA

SC

See the BYTES and CYCLES per INSTRUCTION table for

details.

Bytes and Cycles per Instruction

RC

The following table shows the number of bytes and cycles for

each instruction in the format of byte/cycle.

IFC

IFNC

Arithmetic and Logic Instructions

PUSHA

POPA

ANDSZ

[B]

1/1

Direct

3/4

Immed.

2/2

ADD

ADC

SUBC

AND

OR

3/4

2/2

3/4

2/2

Transfer of Control Instructions

3/4

2/2

JMPL

JMP

JP

3/4

2/3

1/3

3/5

2/5

1/3

1/5

1/7

1/1

3/4

2/2

XOR

IFEQ

IFNE

IFGT

IFBNE

DRSZ

SBIT

RBIT

IFBIT

3/4

2/2

3/4

2/2

JSRL

JSR

3/4

2/2

3/4

2/2

JID

VIS

1/3

3/4

RET

RETSK

RETI

INTR

NOP

1/1

RPND

1/1

Memory Transfer Instructions

Register

Indirect

Direct

Immed.

Register Indirect

Auto Incr. & Decr.

[B]

[X]

1/3

[B+, B−]

1/2

[X+, X−]

1/3

X A, (Note 13)

LD A, (Note 13)

LD B, Imm

1/1

2/3

2/2

1/1

2/2

1/2

1/3

<

(IF B 16)

>

(IF B 15)

LD B, Imm

LD Mem, Imm

LD Reg, Imm

IFEQ MD, Imm

2/2

3/3

2/3

3/3

2/2

Note 13: Memory location addressed by B or X or directly.

www.national.com

34

0 – 3

B i t s

35

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designs.

EWCOP8-M: Full featured ANSI C-Compiler and Embed-

ded Workbench for Windows from IAR (no code limit). A

fully integrated Win32 IDE, ANSI C-Compiler, macro as-

sembler, editor, linker, librarian, C-Spy high-level

simulator/debugger, PLUS MetaLink debugger/hardware

interface (CWCOP8-M).

Manuals, Applications Notes, Literature: Available free

from our web site at: www.national.com/cop8.

COP8 Integrated Software/Hardware Design Develop-

ment Kits

COP8 Productivity Enhancement Tools

•

WCOP8 IDE: Very Low cost IDE (Integrated Develop-

ment Environment) from KKD. Supports COP8C, COP8-

NSASM, COP8-MLSIM, DriveWay COP8, and MetaLink

debugger under a common Windows Project Manage-

ment environment. Code development, debug, and emu-

lation tools can be launched from the project window

framework.

•

COP8-EPU: Very Low cost Evaluation & Programming

Unit. Windows based development and hardware-

simulation tool for COPSx/xG families, with COP8 device

programmer and samples. Includes COP8-NSDEV,

Driveway COP8 Demo, MetaLink Debugger, cables and

power supply.

•

COP8-DM: Moderate cost Debug Module from MetaLink.

A Windows based, real-time in-circuit emulation tool with

COP8 device programmer. Includes COP8-NSDEV,

DriveWay COP8 Demo, MetaLink Debugger, power sup-

ply, emulation cables and adapters.

•

DriveWay-COP8: Low cost COP8 Peripherals Code

Generation tool from Aisys Corporation. Automatically

generates tested and documented C or Assembly source

code modules containing I/O drivers and interrupt han-

dlers for each on-chip peripheral. Application specific

code can be inserted for customization using the inte-

grated editor. (Compatible with COP8-NSASM, COP8C,

and WCOP8 IDE.)

COP8 Development Languages and Environments

•

COP8-NSASM: Free COP8 Assembler v5 for Win32.

Macro assembler, linker, and librarian for COP8 software

development. Supports all COP8 devices. (DOS/Win16

v4.10.2 available with limited support). (Compatible with

WCOP8 IDE, COP8C, and DriveWay COP8).

•

COP8-UTILS: Free set of COP8 assembly code ex-

amples, device drivers, and utilities to speed up code de-

velopment.

www.national.com

36

COP8-NSDEV, Driveway COP8 Demo, MetaLink Win-

dows Debugger, and power supply. Package-specific

probes and surface mount adaptors are ordered sepa-

rately.

Development Support (Continued)

•

COP8-MLSIM: Free Instruction Level Simulator tool for

Windows. For testing and debugging software instruc-

tions only (No I/O or interrupt support).

COP8 Device Programmer Support

COP8 Real-Time Emulation Tools

•

MetaLink’s EPU and Debug Module include development

device programming capability for COP8 devices.

•

COP8-DM: MetaLink Debug Module. A moderately

priced real-time in-circuit emulation tool, with COP8 de-

vice programmer. Includes COP8-NSDEV, DriveWay

COP8 Demo, MetaLink Debugger, power supply, emula-

tion cables and adapters.

IM-COP8: MetaLink iceMASTER^®. A full featured, real-

time in-circuit emulator for COP8 devices. Includes

•

Third-party programmers and automatic handling equip-

ment cover needs from engineering prototype and pilot

production, to full production environments.

•

Factory programming available for high-volume require-

ments.

•

TOOLS ORDERING NUMBERS FOR THE COP87L88EK/RK FAMILY DEVICES

Vendor

Tools

Order Number

COP8-NSEVAL

Cost

Notes

National COP8-NSEVAL

COP8-NSASM

COP8-MLSIM

COP8-NSDEV

COP8-EPU

Free Web site download

COP8-NSASM

Free Included in EPU and DM. Web site download

COP8-MLSIM

COP8-NSDEV

VL

Included in EPU and DM. Order CD from website

Not available for this device

Contact MetaLink

COP8-DM

Development

Devices

COP87L84EK

COP87L88EK

VL

16k OTP devices.

IM-COP8

MetaLink COP8-EPU

COP8-DM

Contact MetaLink

Not available for this device

DM4-COP8-888EK (10

MHz), plus PS-10, plus

DM-COP8/xxx (ie. 28D)

M

Included p/s (PS-10), target cable of choice (DIP or

PLCC; i.e. DM-COP8/28D), 16/20/28/40 DIP/SO and

44 PLCC programming sockets. Add target adapter (if

needed)

DM Target

Adapters

MHW-CNV39

L

DM target converters for 28SO

IM-COP8

IM-COP8-AD-464 (-220)

(10 MHz maximum)

H

Base unit 10 MHz; -220 = 220V; add probe card

(required) and target adapter (if needed); included

software and manuals

IM Probe Card

PC-884EK28DW-AD-10

PC-888EK40DW-AD-10

PC-888EK44PW-AD-10

MHW-SOIC28

M

L

10 MHz 28 DIP probe card; 2.5V to 6.0V

10 MHz 40 DIP probe card; 2.5V to 6.0V

10 MHz 44 PLCC probe card; 2.5V to 6.0V

28 pin SOIC adapter for probe card

IM Probe Target

Adapter

ICU

KKD

IAR

COP8-EVAL

WCOP8-IDE

EWCOP8-xx

COP8C

Not available for this device

WCOP8-IDE

VL

Included in EPU and DM

See summary above

COP8C

L - H Included all software and manuals

Byte

Craft

M

Included all software and manuals

Aisys

DriveWay COP8

Contact vendors

L

Included all software and manuals

L - H For approved programmer listings and vendor

information, go to our OTP support page at:

www.national.com/cop8

OTP Programmers

<

Cost: Free; VL = $100; L = $100 - $300; M = $300 - $1k; H = $1k - $3k; VH = $3k - $5k

37

www.national.com

Development Support (Continued)

WHERE TO GET TOOLS

Tools are ordered directly from the following vendors. Please go to the vendor’s web site for current listings of distributors.

Vendor

Home Office

U.S.A.: Santa Clara, CA

1-408-327-8820

Electronic Sites

www.aisysinc.com

Other Main Offices

Distributors

Aisys

@

info aisysinc.com

fax: 1-408-327-8830

U.S.A.

Byte Craft

www.bytecraft.com

Distributors

@

1-519-888-6911

info bytecraft.com

fax: 1-519-746-6751

U.S.A.: Milford, PA

Hilton

IAR

www.erols.com/sjg1/hilton.htm

@

jhilton warwick.net

Sweden: Uppsala

+46 18 16 78 00

www.iar.se

U.S.A.: San Francisco

1-415-765-5500

@

info iar.se

@

fax: +46 18 16 78 38

info iar.com

fax: 1-415-765-5503

U.K.: London

@

info iarsys.co.uk

@

info iar.de

+44 171 924 33 34

fax: +44 171 924 53 41

Germany: Munich

+49 89 470 6022

fax: +49 89 470 956

Switzeland: Hoehe

+41 34 497 28 21

ICU

Sweden: Polygonvaegen

+46 8 630 11 20

www.icu.se

@

support icu.se

@

fax: +46 8 630 11 70

Denmark:

support icu.ch

KKD

www.kkd.dk

MetaLink

U.S.A.: Chandler, AZ

1-800-638-2423

www.metaice.com

Germany: Kirchseeon

80-91-5696-0

@

sales metaice.com

@

fax: 1-602-926-1198

support metaice.com

fax: 80-91-2386

@

bbs: 1-602-962-0013

www.metalink.de

islanger metalink.de

Distributors Worldwide

National

U.S.A.: Santa Clara, CA

1-800-272-9959

www.national.com/cop8

Europe: +49 (0) 180 530 8585

fax: +49 (0) 180 530 8586

Distributors Worldwide

@

support nsc.com

@

fax: 1-800-737-7018

europe.support nsc.com

The following companies have approved COP8 program-

mers in a variety of configurations. Contact your local office

or distributor. You can link to their web sites and get the lat-

est listing of approved programmers from National’s COP8

OTP Support page at: www.national.com/cop8.

Customer Support

Complete product information and technical support is avail-

able from National’s customer responses centers, and from

our on-line COP8 customer support sites.

Advantech; Advin; BP Microsystems; Data I/O; Hi-Lo Sys-

tems; ICE Technology; Lloyd Research; Logical Devices;

MQP; Needhams; Phyton; SMS; Stag Programmers; Sys-

tem General; Tribal Microsystems; Xeltek.

www.national.com

38

Physical Dimensions inches (millimeters) unless otherwise noted

Molded SO Wide Body Package (WM)

Order Number COP684EK-XXX/WM, COP884EK-XXX/WM,

COP984EK-XXX/WM or COP984EKH-XXX/WM

NS Package Number M28B

Molded Dual-In-Line Package (N)

Order Number COP684EK-XXX/N, COP884EK-XXX/N,

COP984EK-XXX/N or COP984EKH-XXX/N

NS Package Number N28B

39

www.national.com

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

Molded Dual-In-Line Package (N)

Order Number COP688EK-XXX/N, COP888EK-XXX/N,

COP988EK-XXX/N or COP988EKH-XXX/N

NS Package Number N40A

Plastic Leaded Chip Carrier (V)

Order Number COP688EK-XXX/V, COP888EK-XXX/V,

COP988EK-XXX/V or COP988EKH-XXX/V

NS Package Number V44A

www.national.com

40

Notes

LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL

COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or

systems which, (a) are intended for surgical implant

into the body, or (b) support or sustain life, and

whose failure to perform when properly used in

accordance with instructions for use provided in the

labeling, can be reasonably expected to result in a

significant injury to the user.

2. A critical component is any component of a life

support device or system whose failure to perform

can be reasonably expected to cause the failure of

the life support device or system, or to affect its

safety or effectiveness.

National Semiconductor

Corporation

Americas

Tel: 1-800-272-9959

Fax: 1-800-737-7018

Email: support@nsc.com

National Semiconductor

Europe

National Semiconductor

Asia Pacific Customer

Response Group

Tel: 65-2544466

Fax: 65-2504466

National Semiconductor

Japan Ltd.

Tel: 81-3-5639-7560

Fax: 81-3-5639-7507

Fax: +49 (0) 180-530 85 86

Email: europe.support@nsc.com

Deutsch Tel: +49 (0) 69 9508 6208

English Tel: +44 (0) 870 24 0 2171

Français Tel: +33 (0) 1 41 91 8790

Email: ap.support@nsc.com

www.national.com

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.


型号：	COP87L88RKV-XE
厂家：	ETC
描述：	8-Bit Microcontroller 8位微控制器\n 微控制器外围集成电路可编程只读存储器时钟
文件：	总41页 (文件大小：509K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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