COPC912 [ETC]
;
| 型号： | COPC912 |
| 厂家： | 
ETC |
| 描述： |
|
| 文件： | 总20页 (文件大小：278K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
August 2000
COP912C
8-Bit Microcontroller
Family features include an 8-bit memory mapped architec-
ture, 10MHz CKI with 2.5us(912C) or 2us(912CH) instruction
cycle, one multi-function 16-bit timer/counter with PWM,
MICROWIRE/PLUS(tm) serial I/O, power saving HALT
mode, three clock modes, high current outputs, software se-
lectable I/O options, multi-volt operation and 20 pin pack-
ages.
General Description
Note: COP8SA devices are instruction set and pinout com-
patible supersets of the COP912C devices, and are replace-
ments for these in new designs when possible.
The COP912C ROM based microcontrollers are integrated
COP8(tm) Base core devices with smaller memory (768
bytes), and fewer on-board features. These single-chip
CMOS devices are suited for lower-functionality applications
where system cost is of prime consideration. Pin and soft-
ware compatible (different Vcc range) 4k/32k OTP versions
are available (COP87LxxCJ/RJ Family). Erasable windowed
versions are available for use with a range of COP8(tm) soft-
ware and hardware development tools.
Devices included in this datasheet are:
RAM
Device
Memory (bytes)
I/O Pins
Packages
Temperature
Comments
(bytes)
64
COP912C
768 ROM
768ROM
16
16
20 DIP/SOIC
20 DIP/SOIC
0 to +70˚C
0 to +70˚C
2.3v - 4.0v
4.0v - 5.5v
COP912CH
64
n Versatile and easy to use instruction set
n 8-bit Stack Pointer (SP)—stack in RAM
n Two 8-bit Register Indirect Memory Pointers (B, X)
Key Features
n Lowest cost COP8 microcontroller
n 16-bit multi-function timer supporting
— PWM mode
Fully Static CMOS
— External event counter mode
— Input capture mode
<
n Low current drain (typically 1 µA)
n 768 bytes of ROM
n Single supply operation: 2.3V to 4.0V or 4.0V to 5.5V
n 64 bytes of RAM
n Temperature range: 0˚C to +70˚C
I/O Features
n Memory mapped I/O
Development Support
n Emulation and OTP devices
n Software selectable I/O options (TRI-STATE® Output,
Push-Pull Output, Weak Pull-Up Input, High Impedance
Input)
n Real time emulation and full program debug offered by
MetaLink Development System
n Schmitt trigger inputs on Port G
Applications
n Electronic keys and switches
n Remote Control
™
n MICROWIRE/PLUS Serial I/O
n Packages: 20 DIP/SO with 16 I/O pins
n Timers
n Alarms
CPU/Instruction Set Features
n Instruction cycle time of 2 µs for COP912CH and
2.5 µs for COP912C
n Small industrial control units
n Low cost slave controllers
n Temperature meters
n Small domestic appliances
n Toys and games
n Three multi-sourced interrupts servicing
— External Interrupt with selectable edge
— Timer interrupt
— Software interrupt
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
™
™
™
™
COP8 , MICROWIRE/PLUS , WATCHDOG and MICROWIRE are trademarks of National Semiconductor Corporation.
PC® is a registered trademark of International Business Machines Corp.
™
iceMaster is a trademark of MetaLink Corporation.
© 2000 National Semiconductor Corporation
DS012060
www.national.com
Block Diagram
DS012060-1
www.national.com
2
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Total Current into VCC Pin (Source)
Total Current out of GND Pin (Sink)
Storage Temperature Range
Note 1: Absolute maximum ratings indicate limits beyond which damage to
the device may occur. DC and AC electrical specifications are not ensured
when operating the device at absolute maximum ratings.
80 mA
80 mA
−65˚C to +150˚C
Supply Voltage (VCC
Voltage at Any Pin
)
6.0V
−0.3V to VCC +0.3V
DC Electrical Characteristics
COP912C/COP912CH; 0˚C ≤ TA ≤ +70˚C unless other specified
Parameter Conditions
Operating Voltage
Min
Typ
Max
Units
912C
2.3
4.0
4.0
5.5
V
V
V
912CH
Power Supply Ripple 1 (Note 2)
Supply Current (Note 3)
CKI = 4 MHz
Peak to Peak
0.1 VCC
VCC = 5.5V, tc = 2.5 µs
VCC = 4.0V, tc = 2.5 µs
VCC = 5.5V, CKI = 0 MHz
6.0
2.5
8
mA
mA
µA
CKI = 4 MHz
<
HALT Current
1
INPUT LEVELS (VIH, VIL)
Reset, CKI:
Logic High
0.9 VCC
V
V
Logic Low
0.1 VCC
All Other Inputs
Logic High
0.7 VCC
−2
V
V
Logic Low
0.2 VCC
+2
Hi-Z Input Leakage/TRI-STATE Leakage
Input Pullup Current
G-Port Hysteresis
Output Current Levels
Source (Push-Pull Mode)
VCC = 5.5V
VCC = 5.5V
µA
µA
V
250
0.05 VCC
0.35 VCC
VCC = 4.0V, VOH = 3.8V
VCC = 2.3V, VOH = 1.8V
VCC = 4.0V, VOL = 1.0V
VCC = 2.3V, VOL = 0.4V
0.4
0.2
4.0
0.7
mA
mA
mA
mA
mA
pF
Sink (Push-Pull Mode)
Allowable Sink/Source Current Per Pin
Input Capacitance (Note 4)
3
7
Load Capacitance on D2 (Note 4)
1000
pF
Note 2: Rate of voltage change must be less then 0.5 V/ms.
Note 3: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at rails and outputs open.
Note 4: Characterized, not tested.
DS012060-2
FIGURE 1. MICROWIRE/PLUS Timing
3
www.national.com
Typical Performance Characteristics
Halt—IDD
Dynamic—IDD (Crystal Clock Option)
Port L/G Push-Pull Source Current
Port D Source Current
DS012060-16
DS012060-17
Port L/G Weak Pull-Up Source Current
DS012060-18
DS012060-19
Port L/G Push-Pull Sink Current
DS012060-20
DS012060-21
www.national.com
4
Typical Performance Characteristics (Continued)
Port D Sink Current
DS012060-22
AC Electrical Characteristics
COP912C/COP912CH; 0˚C ≤ TA ≤ +70˚C unless otherwise specified
Parameter
INSTRUCTION CYCLE TIME (tc)
Crystal/Resonator
Conditions
Min
Typ
Max
Units
4.0V ≤ VCC ≤ 5.5V
2
DC
DC
DC
DC
µs
µs
µs
µs
<
2.3V ≤ VCC 4.0V
2.5
3
R/C Oscillator
4.0V ≤ VCC ≤ 5.5V
<
2.3V ≤ VCC 4.0V
7.5
Inputs
tSetup
4.0V ≤ VCC ≤ 5.5V
200
500
60
ns
ns
ns
ns
<
2.3V ≤ VCC 4.0V
tHold
4.0V ≤ VCC ≤ 5.5V
<
2.3V ≤ VCC 4.0V
150
Output Propagation Delay
RL = 2.2 kΩ, CL = 100 pF
tPD1, tPD0
SO, SK
4.0V ≤ VCC ≤ 5.5V
0.7
1.75
1
µs
µs
µs
µs
<
2.3V ≤ VCC 4.0V
All Others
4.0V ≤ VCC ≤ 5.5V
<
2.3V ≤ VCC 4.0V
5
Input Pulse Width
Interrupt Input High Time
Interrupt Input Low Time
Timer Input High Time
Timer Input Low Time
MICROWIRE Setup Time (tµWS
1 tc
1 tc
1 tc
1 tc
20
)
ns
ns
ns
MICROWIRE Hold Time (tµWH
MICROWIRE Output
)
56
220
Propagation Delay (tµPD
Reset Pulse Width
)
1.0
µs
5
www.national.com
COP912C/COP912CH Pinout
20 DIP
20 SO Wide
DS012060-3
DS012060-4
Top View
Order Number COP912C-XXX/N,
COP912CH-XXX/N
Top View
Order Number COP912C-XXX/WM,
COP912CH-XXX/WM
FIGURE 2. COP912C/COP912CH Pinout
G7 are Hi-Z input only pins, any attempt by the user to con-
figure them as outputs by writing a one to the configuration
register will be disregarded. Reading the G6 and G7 configu-
ration bits will return zeroes. Note that the chip will be placed
in the Halt mode by writing a “1” to the G7 data bit.
Pin Description
VCC and GND are the power supply pins.
CKI is the clock input. This can come from an external
source, a R/C generated oscillator or a crystal (in conjunc-
tion with CKO). See Oscillator description.
Six pins of Port G have alternate features:
G0 INTR (an external interrupt)
RESET is the master reset input. See Reset description.
PORT L is an 8-bit I/O port.
G3 TIO (timer/counter input/output)
G4 SO (MICROWIRE serial data output)
G5 SK (MICROWIRE clock I/O)
There are two registers associated to configure the L port: a
data register and a configuration register. Therefore, each L
I/O bit can be individually configured under software control
as shown below:
G6 SI (MICROWIRE serial data input)
G7 CKO crystal oscillator output (selected by mask option)
or HALT restart input/general purpose input (if clock op-
tion is R/C- or external clock)
Port L
Port L
PORT L
Setup
Config.
Data
0
0
1
1
0
1
0
1
Hi-Z Input (TRI-STATE)
Input with Weak Pull-Up
Push-Pull Zero Output
Push-Pull One Output
Pins G1 and G2 currently do not have any alternate func-
tions.
The selection of alternate Port G functions are done through
registers PSW [00EF] to enable external interrupt and
CNTRL [00EE] to select TIO and MICROWIRE operations.
Three data memory address locations are allocated for this
port, one each for data register [00D0], configuration register
[00D1] and the input pins [00D2].
Functional Description
The internal architecture is shown in the block diagram. Data
paths are illustrated in simplified form to depict how the vari-
ous logic elements communicate with each other in imple-
menting the instruction set of the device.
PORT G is an 8-bit port with 6 I/O pins (G0–G5) and 2 input
pins (G6, G7).
All eight G-pins have Schmitt Triggers on the inputs.
There are two registers associated to configure the G port: a
data register and a configuration register. Therefore each G
port bit can be individually configured under software control
as shown below:
ALU AND CPU REGISTERS
The ALU can do an 8-bit addition, subtraction, logical or shift
operations in one cycle time. There are five CPU registers:
A
is the 8-bit Accumulator register
Port G
Port G
PORT G
Setup
PC is the 15-bit Program Counter register
Config.
Data
PU is the upper 7 bits of the program counter (PC)
PL is the lower 8 bits of the program counter (PC)
0
0
1
1
0
1
0
1
Hi-Z Input (TRI-STATE)
Input with Weak Pull-Up
Push-Pull Zero Output
Push-Pull One Output
B
X
is the 8-bit address register and can be auto incre-
mented or decremented
is the 8-bit alternate address register and can be auto
incremented or decremented.
Three data memory address locations are allocated for this
port, one for data register [00D4], one for configuration reg-
ister [00D5] and one for the input pins [00D6]. Since G6 and
www.national.com
6
R/C OSCILLATOR
Functional Description (Continued)
By selecting CKI as a single pin oscillator, CKI can make an
R/C oscillator. CKO is available as a general purpose input
and/or HALT control. Table 2 shows variation in the oscillator
frequencies as functions of the component (R and C) value.
SP is the 8-bit stack pointer which points to the subroutine
stack (in RAM).
B, X and SP registers are mapped into the on chip RAM. The
B and X registers are used to address the on chip RAM. The
SP register is used to address the stack in RAM during sub-
routine calls and returns. The SP must be preset by software
upon initialization.
MEMORY
The memory is separated into two memory spaces: program
and data.
PROGRAM MEMORY
Program memory consists of 768 x 8 ROM. These bytes of
ROM may be instructions or constant data. The memory is
addressed by the 15-bit program counter (PC). There are no
“pages” of ROM, the PC counts all 15 bits. ROM can be in-
directly read by the LAlD instruction for table lookup.
DS012060-6
FIGURE 4. Clock Oscillator Configurations
TABLE 1. Crystal Oscillator Configuration
CKI
DATA MEMORY
R1
R2
C1
C2
The data memory address space includes on chip RAM, I/O
and registers. Data memory is addressed directly by the in-
struction or indirectly through B, X and SP registers. The de-
vice has 64 bytes of RAM. Sixteen bytes of RAM are
mapped as “registers”, these can be loaded immediately,
decremented and tested. Three specific registers: X, B, and
SP are mapped into this space, the other registers are avail-
able for general usage.
Freq.
(MHz)
5
(kΩ)
(mΩ)
(pF)
(pF)
0
0
1
1
1
30
30
30–36
30–36
4
5.6
200
100–150
0.455
TABLE 2. RC Oscillator Configuration
(Part-to-Part Variation, TA = 25˚C)
Any bit of data memory can be directly set, reset or tested.
I/O and registers (except A and PC) are memory mapped;
therefore, I/O bits and register bits can be directly and indi-
vidually set, reset and tested.
Intr.
R
C
CKI Freq.
(MHz)
Cycle
(µs)
(kΩ)
(pF)
RESET
3.3
5.6
6.8
82
2.2 to 2.7
1.1 to 1.3
0.9 to 1.1
3.7 to 4.6
7.4 to 9
8.8 to 10.8
The RESET input pin when pulled low initializes the micro-
controller. Upon initialization, the ports L and G are placed in
the TRl-STATE mode. The PC, PSW and CNTRL registers
are cleared. The data and configuration registers for ports L
and G are cleared. The external RC network shown in
Figure 3 should be used to ensure that the RESET pin is
held low until the power supply to the chip stabilizes.
100
100
Note 5: 3k ≤ R ≤ 200 kΩ, 50 pF ≤ C ≤ 200 pF.
HALT MODE
The device is a fully static device. The device enters the
HALT mode by writing a one to the G7 bit of the G data reg-
ister. Once in the HALT mode, the internal circuitry does not
receive any clock signal and is therefore frozen in the exact
state it was in when halted. In this mode the chip will only
draw leakage current.
The device supports two different ways of exiting the HALT
mode. The first method is with a low to high transition on the
CKO (G7) pin. This method precludes the use of the crystal
clock configuration (since CKO is a dedicated output), and
so may be used either with an RC clock configuration (or an
external clock configuration). The second method of exiting
the HALT mode is to pull the RESET low.
DS012060-5
>
RC 5 x POWER SUPPLY RISE TIME
FIGURE 3. Recommended Reset Circuit
Note: To allow clock resynchronization, it is necessary to program two NOP’s
immediately after the device comes out of the HALT mode. The user
must program two NOP’s following the “enter HALT mode” (set G7
data bit) instruction.
OSCILLATOR CIRCUITS
The device can be driven by a clock input which can be be-
tween DC and 5 MHz.
MICROWIRE/PLUS
CRYSTAL OSCILLATOR
MICROWIRE/PLUS is a serial synchronous communications
interface. The MICROWIRE/PLUS capability enables the de-
vice to interface with any of National Semiconductor’s
MICROWIRE peripherals (i.e., A/D converters, display driv-
By selecting CKO as a clock output, CKI and CKO can be
connected to create a crystal controlled oscillator. Table 1
shows the component values required for various standard
crystal values.
7
www.national.com
SK Divide Clock Rates
Functional Description (Continued)
SL1
0
SL0
SK
ers, EEPROMS etc.) and with other microcontrollers which
support the MICROWIRE interface. It consists of an 8-bit se-
rial shift register (SIO) with serial data input (SI), serial data
output (SO) and serial shift clock (SK). Figure 5 shows a
block diagram of the MICROWIRE logic.
0
1
x
2 x tc
4 x tc
8 x tc
0
1
Where tc is the instruction cycle clock.
The shift clock can be derived from either the internal source
or from an external source. Operating the MICROWIRE ar-
rangement with the internal clock source is called the Master
mode of operation. Similarly, operating the MICROWIRE ar-
rangement with an external shift clock is called the Slave
mode of operation.
MICROWIRE/PLUS OPERATION
Setting the BUSY bit in the PSW register causes the
MICROWIRE/PLUS to start shifting the data. It gets reset
when eight data bits have been shifted. The user may reset
the BUSY bit by software to allow less than 8 bits to shift.
The device may enter the MICROWIRE/PLUS mode either
as a Master or as a Slave. Figure 5 shows how two micro-
controllers and several peripherals may be interconnected
using the MICROWIRE/PLUS arrangement.
The CNTRL register is used to configure and control the
MICROWIRE mode. To use the MICROWIRE, the MSEL bit
in the CNTRL register is set to one. The SK clock rate is se-
lected by the two bits, SL0 and SL1, in the CNTRL register.
The following table details the different clock rates that may
be selected.
DS012060-7
FIGURE 5. MICROWIRE/PLUS Application
WARNING: The SIO register should only be loaded when
the SK clock is low. Loading the SIO register while the SK
clock is high will result in undefined data in the SIO register.
G4
(SO)
Config.
Bit
G5
(SK)
G4
G5
G6
Operation
Config.
Bit
Pin
Pin
Pin
Setting the BUSY flag when the input SK clock is high in the
MICROWIRE/PLUS slave mode may cause the current SK
clock for the SIO shift register to be narrow. For safety, the
BUSY flag should only be set when the input SK clock is low.
1
0
SO
Ext. SK
Ext. SK
SI MICROWIRE
Slave
0
0
TRI-STATE
SI MICROWIRE
Slave
Table 3 summarizes the settings required to enter the
Master/Slave modes of operations.
MICROWIRE/PLUS MASTER MODE OPERATION
The table assumes that the control flag MSEL is set.
In MICROWIRE/PLUS Master mode operation, the SK shift
clock is generated internally. The MSEL bit in the CNTRL
register must be set to allow the SK and SO functions onto
the G5 and G4 pins. The G5 and G4 pins must also be se-
lected as outputs by setting the appropriate bits in the Port G
configuration register. The MICROWIRE Master mode al-
ways initiates all data exchanges. The MSEL bit in the
CNTRL register is set to enable MICROWIRE/PLUS. G4 and
G5 are selected as output.
TABLE 3. MICROWIRE/PLUS G Port Configuration
G4
(SO)
Config.
Bit
G5
(SK)
G4
G5
G6
Operation
Config.
Bit
Pin
Pin
Pin
1
1
SO
Int. SK
Int. SK
SI MICROWIRE
Master
0
1
TRI-STATE
SI MICROWIRE
Master
www.national.com
8
Functional Description (Continued)
DS012060-10
FIGURE 7. Timer in PWM Mode
EXTERNAL EVENT COUNTER MODE
DS012060-8
In this mode, the timer becomes a 16-bit external event
counter, clocked from an input signal applied to the G3 input.
The maximum frequency for this G3 input clock is 250 kHz
(half of the 0.5 MHz instruction cycle clock). When the exter-
nal event counter underflows, the value in the autoreload
register is copied into the timer. This timer underflow may
also be used to generate an interrupt. Bit 5 of the CNTRL
register is used to select whether the external event counter
clocks on positive or negative edges from the G3 input. Con-
sequently, half cycles of an external input signal could be
counted. The External Event counter mode is shown in Fig-
ure 8.
FIGURE 6. MICROWIRE/PLUS Block Diagram
MICROWIRE/PLUS SLAVE MODE
In MICROWIRE/PLUS Slave mode operation, the SK shift
clock is generated by an external source. Setting the MSEL
bit in the CNTRL register enables the SO and SK functions
onto the G port. The SK pin must be selected as an input and
the SO pin as an output by resetting and setting their respec-
tive bits in the G port configuration register.
The user must set the BUSY flag immediately upon entering
the slave mode. This will ensure that all data bits sent by the
master will be shifted in properly. After eight clock pulses, the
BUSY flag will be cleared and the sequence may be re-
peated.
Note: In the Slave mode the SIO register does not stop shifting even after the
busy flag goes low. Since SK is an external output, the SIO register
stops shifting only when SK is turned off by the master.
Note: Setting the BUSY flag when the input SK clock is high in the
MICROWIRE/PLUS slave mode may cause the current SK clock for
the SIO register to be narrow. When the BUSY flag is set, the MI-
CROWIRE logic becomes active with the internal SIO shift clock en-
abled. If SK is high in slave mode, this will cause the internal shift clock
to go from low in standby mode to high in active mode. This generates
a rising edge, and causes one bit to be shifted into the SIO register
from the SI input. For safety, the BUSY flag should only be set when
the input SK clock is low.
Note: The SIO register must be loaded only when the SK shift clock is low.
Loading the SIO register while the SK clock is high will result in unde-
fined data in the SIO register.
DS012060-11
FIGURE 8. Timer in External Event Mode
Timer/Counter
INPUT CAPTURE MODE
The device has an on board 16-bit timer/counter (organized
as two 8-bit registers) with an associated 16-bit autoreload/
capture register (also organized as two 8-bit registers). Both
are read/write registers.
In this mode, the timer counts down at the instruction clock
rate. When an external edge occurs on pin G3, the value in
the timer is copied into the capture register. Consequently,
the time of an external edge on the G3 pin is “captured”. Bit
5 of the CNTRL register is used to select the polarity of the
external edge. This external edge capture can also be pro-
grammed to generate an interrupt. The duration of an input
signal can be computed by capturing the time of the leading
edge, saving this captured value, changing the capture
edge, capturing the time of the trailing edge, and then sub-
tracting this trailing edge time from the earlier leading edge
time. The Input Capture mode is shown in Figure 9.
The timer has three modes of operation:
PWM (PULSE WIDTH MODULATION) MODE
The timer counts down at the instruction cycle rate (2 µs
max). When the timer count underflows, the value in the au-
toreload register is copied into the timer. Consequently, the
timer is programmable to divide by any value from 1 to
65536. Bit 5 of the timer CNTRL register selects the timer
underflow to toggle the G3 output. This allows the user to
generate a square wave output or a pulse-width-modulated
output. The timer underflow can also be enabled to interrupt
the processor. The timer PWM mode is shown in Figure 7.
9
www.national.com
Table 4 below details the TIMER modes of operation and
their associated interrupts. Bit 4 of CNTRL is used to start
and stop the timer/counter. Bits 5, 6 and 7 of the CNTRL reg-
ister select the timer modes. The ENTI (Enable Timer Inter-
rupt) and TPND (Timer Interrupt Pending) bits in the PSW
register are used to control the timer interrupts.
Timer/Counter (Continued)
Care must be taken when reading from and writing to the
timer and its associated autoreload/capture register. The
timer and autoreload/capture register are both 16-bit, but
they are read from and written to one byte at a time. It is rec-
ommended that the timer be stopped before writing a new
value into it. The timer may be read “on the fly” without stop-
ping it if suitable precautions are taken. One method of read-
ing the timer “on the fly” is to read the upper byte of the timer
first, and then read the lower byte. If the most significant bit
of the lower byte is then tested and found to be high, then the
upper byte of the timer should be read again and this new
value used.
DS012060-12
FIGURE 9. Timer in Input Capture Mode
TABLE 4. Timer Modes and Control Bits
CNTRL Bits
Timer
Timer
Operation Mode
Interrupt
Counts On
7
0
0
0
0
1
1
1
1
6
0
0
1
1
0
0
1
1
5
0
1
0
1
0
1
0
1
External Event Counter with Autoreload Register
External Event Counter with Autoreload Register
Not Allowed
Timer Underflow
Timer Underflow
Not Allowed
TIO Positive Edge
TIO Negative Edge
Not Allowed
Not Allowed
Not Allowed
Not Allowed
Timer with Autoreload Register
Timer with Autoreload Register and Toggle TIO Out
Timer with Capture Register
Timer Underflow
Timer Underflow
TIO Positive Edge
TIO Negative Edge
tc
tc
tc
tc
Timer with Capture Register
TIMER APPLICATION EXAMPLE
The timer has an autoreload register that allows any fre-
quency to be programmed in the timer PWM mode. The
timer underflow can be programmed to toggle output bit G3,
and may also be programmed to generate a timer interrupt.
Consequently, a fully programmable PWM output may be
easily generated.
The timer counts down and when it underflows, the value
from the autoreload register is copied into the timer. The
CNTRL register is programmed to both toggle the G3 output
and generate a timer interrupt when the timer underflows.
Following each timer interrupt, the user’s program alternately
loads the values of the “on” time and the “off” time into the
DS012060-13
timer
autoreload
register.
Consequently,
a
FIGURE 10. Timer Based PWM Application
pulse-width-modulated (PWM) output waveform is gener-
ated to a resolution of one instruction cycle time. This PWM
application example is shown in Figure 10.
Interrupts
There are three interrupt sources:
1. A maskable interrupt on external G0 input positive or
negative edge sensitive under software control
2. A maskable interrupt on timer underflow or timer capture
3. A non-maskable software/error interrupt on opcode zero.
The GIE (global interrupt enable) bit enables the inter-
rupt function. This is used in conjunction with ENI and
ENTI to select one or both of the interrupt sources. This
bit is reset when interrupt is acknowledged.
ENI and ENTI bits select external and timer interrupt respec-
tively. Thus the user can select either or both sources to in-
terrupt the microcontroller when GIE is enabled. IEDG se-
www.national.com
10
(maskable) interrupt subroutine. The user should use the
RETSK instruction when returning from a software interrupt
subroutine to avoid an infinite loop situation.
Interrupts (Continued)
lects the external interrupt edge (1 = rising edge, 0 = falling
edge). The user can get an interrupt on both rising and falling
edges by toggling the state of IEDG bit after each interrupt.
The software interrupt is a special kind of non-maskable in-
terrupt which occurs when the INTR instruction (opcode 00
used to acknowledge interrupts) is fetched from ROM and
placed inside the instruction register. This may happen when
the PC is pointing beyond the available ROM address space
or when the stack is over-popped. When the software inter-
rupt occurs, the user can re-initialize the stack pointer and do
a recovery procedure (similar to reset, but not necessarily
containing all of the same initialization procedures) before
restarting.
IPND and TPND bits signal which interrupt is pending. After
interrupt is acknowledged, the user can check these two bits
to determine which interrupt is pending. The user can priori-
tize the interrupt and clear the pending bit that corresponds
to the interrupt being serviced. The user can also enable GIE
at this point for nesting interrupts. Two things have to be kept
in mind when using the software interrupt. The first is that ex-
ecuting a simple RET instruction will take the program con-
trol back to the software interrupt instruction itself. In other
words, the program will be stuck in an infinite loop. To avoid
the infinite loop, the software interrupt service routine should
end with a RETSK instruction or with a JMP instruction. The
second thing to keep in mind is that unlike the other interrupt
sources, the software interrupt does not reset the GIE bit.
This means that the device can be interrupted by other inter-
rupt sources while servicing the software interrupt.
Hardware and Software interrupts are treated differently. The
software interrupt is not gated by the GIE bit. However, it has
the lowest arbitration ranking. Also the fact that all interrupts
vector to the same address 00FF Hex means that a software
interrupt happening at the same time as a hardware interrupt
will be missed.
Note: There is always the possibility of an interrupt occurring during an in-
struction which is attempting to reset the GIE bit or any other interrupt
enable bit. If this occurs when a single cycle instruction is being used
to reset the interrupt enable bit, the interrupt enable bit will be reset but
an interrupt may still occur. This is because interrupt processing is
started at the same time as the interrupt bit is being reset. To avoid this
scenario, the user should always use a two, three, or four cycle instruc-
tion to reset interrupt enable bits.
Interrupts push the PC to the stack, reset the GIE bit to dis-
able further interrupts and branch to address 00FF. The
RETI instruction will pop the stack to PC and set the GIE bit
to enable further interrupts. The user should use the RETI or
the RET instruction when returning from
a hardware
DS012060-14
FIGURE 11. Interrupt Block Diagram
DETECTION OF ILLEGAL CONDITIONS
if the SP = 30, 31 it implies that the stack was over “POP”ed
(with the SP=2F hex initially). If the SP contains a legal value
(less than or equal to the initialized SP value), then the value
in the PC gives a clue as to where in the user program an at-
tempt to access an illegal (an address over 300 Hex) was
made. The opcode returned in this case is 00 which is a soft-
ware interrupt.
Reading of undefined ROM gets zeroes. The opcode for
software interrupt is zero. If the program fetches instructions
from undefined ROM, this will force a software interrupt, thus
signalling that an illegal condition has occurred.
Note: A software interrupt is acted upon only when a timer or external inter-
rupt is not pending as hardware interrupts have priority over software
interrupt. In addition, the Global Interrupt bit is not set when a software
interrupt is being serviced thereby opening the door for the hardware
interrupts to occur. The subroutine stack grows down for each call and
grows up for each return. If the stack pointer is initialized to 2F Hex,
then if there are more returns than calls, the stack pointer will point to
addresses 30 and 31 (which are undefined RAM). Undefined RAM is
read as all 1’s, thus, the program will return to address FFFF. This is a
undefined ROM location and the instruction fetched will generate a
software interrupt signalling an illegal condition. The device can detect
the following illegal conditions:
The detection of illegal conditions is illustrated with an ex-
ample:
0043 CLRA
0044 RC
0045 JMP 04FF
0046 NOP
When the device is executing this program, it seemingly
“locks-up” having executed a software interrupt. To debug
this condition, the user takes a look at the SP and the con-
tents of the stack. The SP has a legal value and the contents
of the stack are 04FF. The perceptive user immediately real-
izes that an illegal ROM location (04FF) was accessed and
the opcode returned (00) was a software interrupt. Another
way to decode this is to run a trace and follow the sequence
of steps that ended in a software interrupt. The damaging
jump statement is changed.
1. Executing from undefined ROM
2. Over “POP”ing the stack by having more returns than calls.
Illegal conditions may occur from coding errors, “brown out”
voltage drops, static, supply noise, etc. When the software
interrupt occurs, the user can re-initialize the stack pointer
and do a recovery procedure before restarting (this recovery
program is probably similar to RESET but might not clear the
RAM). Examination of the stack can help in identifying the
source of the error. For example, upon a software interrupt,
11
www.national.com
Control Registers
Address
Contents
30 to 7F
Unused RAM Address Space (Reads as all
ones)
CNTRL REGISTER (ADDRESS X’00EE)
The Timer and MICROWIRE control register contains the fol-
lowing bits:
80 to BF
Expansion Space for On-Chip EERAM
(Reads Undefined Data)
SL1 and SL0 Select the MICROWIRE clock divide-by
(00 = 2, 01 = 4, 1x = 8)
C0 to CF
D0
Expansion Space for I/O and Registers
Port L Data Register
IEDG
External interrupt edge polarity select
D1
Port L Configuration Register
Port L Input Pins (read only)
Reserved for Port L
MSEL
Selects G5 and G4 as MICROWIRE signals
SK and SO respectively
D2
D3
TRUN
Used to start and stop the timer/counter
(1 = run, 0 = stop)
D4
Port G Data Register
D5
Port G Configuration Register
Port G Input Pins (read only)
Reserved
TC1
TC2
TC3
Timer Mode Control Bit
Timer Mode Control Bit
D6
Timer Mode Control Bit
D7
D8 to DB
DC to DF
E0 to EF
E0 to E7
E8
Reserved
7
0
Reserved
TC1
TC2
TC3
TRUN MSEL
IEDG
SL1
SL0
On-Chip Functions and Registers
Reserved for Future Parts
Reserved
PSW REGISTER (ADDRESS X’00EF)
The PSW register contains the following select bits:
GIE
ENI
Global interrupt enable (enables interrupts)
External interrupt enable
E9
MICROWIRE Shift Register
Timer Lower Byte
EA
BUSY MICROWIRE busy shifting flag
IPND External interrupt pending
ENTI Timer interrupt enable
EB
Timer Upper Byte
EC
Timer Autoreload Register Lower Byte
Timer Autoreload Register Upper Byte
CNTRL Control Register
PSW Register
ED
TPND Timer interrupt pending
(timer underflow or capture edge)
EE
EF
C
Carry Flip/flop
F0 to FF
On-Chip RAM Mapped as Registers
(16 Bytes)
HC
Half carry Flip/flop
7
0
FC
FD
FE
X Register
SP Register
B Register
HC
C
TPND
ENTI
IPND
BUSY
ENI
GIE
The Half-Carry bit is also effected by all the instructions that
effect the Carry flag. The flag values depend upon the in-
struction. For example, after executing the ADC instruction
the values of the Carry and the Half-Carry flag depend upon
the operands involved. However, instructions like SET C and
RESET C will set and clear both the carry flags. Table 5 lists
out the instructions that effect the HC and the C flags.
Reading other unused memory locations will return unde-
fined data.
Addressing Modes
The device has ten addressing modes, six for operand ad-
dressing and four for transfer of control.
TABLE 5. Instructions Effecting HC and C Flags
OPERAND ADDRESSING MODES
Register Indirect
Instr.
ADC
HC Flag
Depends on Operands
Depends on Operands
Set
C Flag
Depends on Operands
Depends on Operands
Set
This is the “normal” addressing mode for the chip. The oper-
and is the data memory addressed by the B or X pointer.
SUBC
SETC
Register Indirect With Auto Post Increment Or Decre-
ment
RESET
C
Set
Set
RRC
Depends on Operands
Depends on Operands
This addressing mode is used with the LD and X instruc-
tions. The operand is the data memory addressed by the B
or X pointer. This is a register indirect mode that automati-
cally post increments or post decrements the B or X pointer
after executing the instruction.
MEMORY MAP
All RAM, ports and registers (except A and PC) are mapped
into data memory address space.
Direct
The instruction contains an 8-bit address field that directly
points to the data memory for the operand.
TABLE 6. Memory Map
Address
Contents
Immediate
00 to 2F
On-chip RAM Bytes (48 Bytes)
The instruction contains an 8-bit immediate field as the oper-
and.
Short Immediate
www.national.com
12
Addressing Modes (Continued)
Instruction Set
#
This addressing mode issued with the LD B, instruction,
REGISTER AND SYMBOL DEFINITIONS
Registers
#
where the immediate is less than 16. The instruction con-
tains a 4-bit immediate field as the operand.
Indirect
A
8-Bit Accumulator Register
8-Bit Address Register
This addressing mode is used with the LAID instruction. The
contents of the accumulator are used as a partial address
(lower 8 bits of PC) for accessing a data operand from the
program memory.
B
X
8-Bit Address Register
SP
S
8-Bit Stack Pointer Register
8-Bit Data Segment Address Register
15-Bit Program Counter Register
Upper 7 Bits of PC
TRANSFER OF CONTROL ADDRESSING MODES
Relative
PC
PU
PL
C
This mode is used for the JP instruction with the instruction
field being added to the program counter to produce the next
instruction address. JP has a range from −31 to +32 to allow
a one byte relative jump (JP + 1 is implemented by a NOP in-
struction). There are no “blocks” or “pages” when using JP
since all 15 bits of the PC are used.
Lower 8 Bits of PC
1-Bit of PSW Register for Carry
1-Bit of PSW Register for Half Carry
HC
GIE 1-Bit of PSW Register for Global Interrupt Enable
Symbols
Absolute
[B]
Memory Indirectly Addressed by B Register
Memory Indirectly Addressed by X Register
Direct Addressed Memory
This mode is used with the JMP and JSR instructions with
the instruction field of 12 bits replacing the lower 12 bits of
the program counter (PC). This allows jumping to any loca-
tion in the current 4k program memory segment.
[X]
MD
Mem
MemI
Imm
Reg
Direct Addressed Memory, or B
Direct Addressed Memory, B, or Immediate Data
8-Bit Immediate Data
Absolute Long
This mode is used with the JMPL and JSRL instructions with
the instruction field of 15 bits replacing the entire 15 bits of
the program counter (PC). This allows jumping to any loca-
tion in the entire 32k program memory space.
Register Memory: Addresses F0 to FF
(Includes B, X, and SP)
Indirect
Bit
←
↔
Bit Number (0 to 7)
This mode is used with the JID instruction. The contents of
the accumulator are used as a partial address (lower 8 bits of
PC) for accessing a location in the program memory. The
contents of this program memory location serves as a partial
address (lower 8 bits of PC) for the jump to the next instruc-
tion.
Loaded with
Exchanged with
TABLE 7. Instruction Set
Function
Instr
A, MemI
Register Operation
←
←
←
←
←
←
ADD
ADC
SUBC
AND
OR
Add
A
A
A
A
A
A
A + MemI
A + MemI + C, C Carry
←
A, MemI
A, MemI
A, MemI
A, MemI
A, MemI
A, MemI
A, MemI
#
Add with Carry
←
Subtract with Carry
Logical AND
A − MemI + C, C Carry
A and MemI
A or MemI
A xor MemI
Logical OR
XOR
IFEQ
IFGT
IFBNE
DRSZ
SBIT
RBIT
IFBIT
X
Logical Exclusive-OR
IF Equal
Compare A and MemI, Do Next if A = MemI
>
IF Greater than
Compare A and MemI, Do Next if A MemI
IF B not Equal
Do Next If Lower 4 Bits of B not = Imm
←
Reg
Decrement Reg, Skip if Zero
Set Bit
Reg Reg - 1, Skip if Reg Goes to Zero
#
#
#
, Mem
, Mem
, Mem
1 to Mem.Bit (Bit = 0 to 7 Immediate)
0 to Mem.Bit (Bit = 0 to 7 Immediate)
If Mem.Bit is True, Do Next Instruction
Reset Bit
If Bit
↔
←
A, Mem
Exchange A with Memory
Load A with Memory
Load Direct Memory Immed.
Load Register Memory Immed.
Exchange A with Memory [B]
Exchange A with Memory [X]
A
A
Mem
LD
A, MemI
Mem, Imm
Reg, Imm
MemI
←
Mem Imm
LD
←
Reg Imm
LD
↔
↔
←
±
±
X
A, [B ]
A
A
[B] (B B 1)
←
±
[X] (X X 1)
±
X
A, [X ]
13
www.national.com
Instruction Set (Continued)
TABLE 7. Instruction Set (Continued)
Instr
Function
Register Operation
←
←
±
±
LD
A, [B ]
Load A with Memory [B]
Load A with Memory [X]
Load Memory Immediate
Clear A
A
A
[B] (B B 1)
←
←
±
[X] (X X 1)
±
LD
A, [X ]
←
←
±
±
LD
[B ], Imm
[B] Imm (B B 1)
←
A
←
A
←
A
←
A
←
A
→
C
CLRA
INC
0
Increment A
A + 1
DEC
LAID
DCOR
RRC
SWAP
SC
Decrement A
A − 1
A
A
Load A Indirect from ROM
Decimal Correct A
Rotate Right Through Carry
Swap Nibbles of A
Set C
ROM(PU, A)
BCD Correction (follows ADC, SUBC)
→
→
→
A0 C
A7
…
↔
A7…A4 A3…A0
A
A
A
←
←
C
C
1
0
RC
Reset C
IFC
If C
If C is True, do Next Instruction
IFNC
JMPL
JMP
If Not C
If C is not True, do Next Instruction
←
PC ii (ii = 15 Bits, 0k to 32k)
Jump Absolute Long
Jump Absolute
←
PC11…PC0 i (i = 12 Bits)
PC15…PC12 Remain Unchanged
←
PC PC + r (r is −31 to +32, not 1)
JP
Jump Relative Short
Jump Subroutine Long
Jump Subroutine
← ← ←
[SP] PL, [SP−1] PU, SP−2, PC ii
JSRL
JSR
JID
Addr.
Addr.
Disp.
Addr.
Addr.
←
←
←
[SP] PL, [SP−1] PU, SP−2, PC11..PC0 ii
←
PL ROM(PU, A)
Jump Indirect
← ←
SP+2, PL [SP], PU [SP−1]
RET
RETSK
Return from Subroutine
Return and Skip
←
←
SP+2, PL [SP], PU [SP−1],
Skip next Instr.
←
←
←
RETI
INTR
NOP
Return from Interrupt
Generate an Interrupt
No Operation
SP+2, PL [SP], PU [SP−1], GIE 1
←
←
←
[SP] PL, [SP−1] PU, SP−2, PC 0FF
←
PC PC+1
•
•
•
Most instructions are single byte (with immediate ad-
dressing mode instructions requiring two bytes).
Instr
IFGT
[B]
1/1
1/1
1/1
1/1
1/1
1/1
Direct
Immediate
3/4
2/2
2/2
Most single byte instructions take one cycle time to ex-
ecute.
IFBNE
DRSZ
SBIT
1/3
3/4
3/4
3/4
Skipped instructions require x number of cycles to be
skipped, where x equals the number of bytes in the
skipped instruction opcode.
RBIT
The following tables show the number of bytes and cycles for
each instruction in the format byte/cycle.
IFBIT
Instructions Using A and C (Bytes/Cycles)
Instr Bytes/Cycles
Arithmetic and Logic
Instructions (Bytes/Cycles)
CLRA
INCA
DECA
LAID
1/1
1/1
1/1
1/3
1/1
1/1
1/1
1/1
1/1
Instr
ADD
[B]
1/1
1/1
1/1
1/1
1/1
1/1
1/1
1/1
Direct
3/4
Immediate
ADC
SUBC
AND
OR
3/4
2/2
2/2
2/2
2/2
2/2
2/2
2/2
3/4
DCOR
RRCA
SWAPA
SC
3/4
3/4
XOR
IFEQ
IFNE
3/4
3/4
RC
3/4
www.national.com
14
Instruction Set (Continued)
Instructions Using A and C (Bytes/Cycles) (Continued)
Instr
Bytes/Cycles
JP
1/3
3/5
2/5
1/3
1/5
1/5
1/5
1/7
1/1
JSRL
JSR
Instr
Bytes/Cycles
IFC
1/1
1/1
JID
IFNC
RET
RETSK
RETI
INTR
NOP
Transfer of Control Instructions
(Bytes/Cycles)
Instr
JMPL
Bytes/Cycles
3/4
2/3
JMP
Memory Transfer Instructions (Bytes/Cycles)
Register Indirect
Register Indirect
Instr
Direct
Immed.
Auto Incr and Decr
[B]
1/1
1/1
[X]
[B+, B−]
[X+, X−]
X A,a
LD A,
2/3
2/3
1/2
1/2
*
LD B,Imm
1/3
1/3
2/2
1/1b
2/3c
1/3
1/3
LD B,Imm
LD Mem,Imm
LD Reg,Imm
2/2
3/3
2/3
2/2
a. Memory location addressed by B or X directly
<
b. IF B 16
>
c. IF B 15
15
www.national.com
Instruction Set (Continued)
0 – 3
B I T S
N I B B L E L O W E R
www.national.com
16
COP8 Starter Kits and Hardware Target Solutions
Option List
•
COP8-EVAL-xxx: A variety of Multifunction Evaluation,
Design Test, and Target Boards for COP8 Families. Real-
time target design environments with a selection of pe-
ripherals and features including multi I/O, LCD display,
keyboard, A/D, D/A, EEPROM, USART, LEDs, and
bread-board area. Quickly design, test, and implement a
custom target system (some target boards are stand-
alone, and ready for mounting into a standard enclosure),
or just evaluate and test your code. Includes COP8-
NSDEV with IDE and Assembler, software routines, refer-
ence designs, and source code (no p/s).
The mask programmable options are listed out below. The
options are programmed at the same time as the ROM pat-
tern to provide the user with hardware flexibility to use a va-
riety of oscillator configuration.
OPTION 1: CKI INPUT
= 1 Crystal (CKI/10) CKO for crystal configuration
= 2
NA
= 3 R/C
(CKI/10) CKO available as G7 input
OPTION 2: BONDING
= 1 NA
COP8 Software Development Languages and Integrated
Environments
•
COP8-NSDEV: National’s COP8 Software Development
package for Windows on CD. A fully Integrated Develop-
ment Environment for COP8. Includes a fully licensed
WCOP8 IDE, COP8-NSASM. Plus Manuals, Applications
Software, and other COP8 technical information.
= 2 NA
= 3 20 pin DIP package
= 4 20 pin SO package
= 5 NA
The following option information is to be sent to National
along with the EPROM.
•
COP8C: ByteCraft - C Cross-Compiler and Code Devel-
opment System. Includes BCLIDE (Integrated Develop-
ment Environment) for Win32, editor, optimizing C Cross-
Compiler, macro cross assembler, BC-Linker, and
MetaLinktools support. (DOS/SUN versions available;
Compiler is linkable under WCOP8 IDE; Compatible with
DriveWay COP8)
Option Data
Option 1 Value__is: CKI Input
Option 2 Value__is: COP Bonding
•
EWCOP8, EWCOP8-M, EWCOP8-BL: IAR - ANSI
COP8 Tools Overview
C-Compiler and Embedded Workbench. (M version in-
cludes MetaLink debugger support) (BL version: 4k code
limit; no FP). A fully integrated Win32 IDE, ANSI
C-Compiler, macro assembler, editor, linker, librarian,
and C-Spy high-level simulator/debugger.
National is engaged with an international community of inde-
pendent 3rd party vendors who provide hardware and soft-
ware development tool support. Through National’s interac-
tion and guidance, these tools cooperate to form a choice of
tools that fits each developer’s needs.
COP8 Development Productivity Tools
This section provides a summary of the tool and develop-
ment kits currently available. Up-to-date information, selec-
tion guides, free tools, demos, updates, and purchase infor-
mation can be obtained at our web site at:
www.national.com/cop8.
•
DriveWay-COP8: Aisys Corporation - COP8 Peripherals
Code Generation tool. Automatically generates tested
and documented C or Assembly source code modules
containing I/O drivers and interrupt handlers for each on-
chip peripheral. Application specific code can be inserted
for customization using the integrated editor. (Compatible
with COP8-NSASM, COP8C, and WCOP8 IDE.)
SUMMARY OF TOOLS
COP8 Evaluation Software and Reference Designs
•
•
COP8-UTILS: COP8 assembly code examples, device
drivers, and utilities to speed up code development. (In-
cluded with COP8-NSDEV and COP8-NSEVAL.)
•
COP8–NSEVAL: Software Evaluation package for Win-
dows. A fully integrated evaluation environment for
COP8. Includes WCOP8 IDE evaluation version (Inte-
grated Development Environment), COP8-NSASM (Full
COP8 Assembler), COP8-MLSIM (COP8 Instruction
WCOP8 IDE: KKD - COP8 IDE (Integrated Development
Environment). Supports COP8C, COP8-NSASM, COP8-
MLSIM, DriveWay COP8, and MetaLink debugger under
a common Windows Project Management environment.
Code development, debug, and emulation tools can be
launched from a single project window framework. (In-
cluded in COP8-NSDEV and COP8-NSEVAL.)
™
Level Simulator), COP8C Compiler Demo, DriveWay
COP8 Device-Driver-Builder Demo, Manuals, Applica-
tions Software, and other COP8 technical information.
•
COP8–REF-xx: Reference Designs for COP8 Families.
Realtime hardware environment with a variety of func-
tions for demonstrating the various capabilities and fea-
tures of specific COP8 device families. Run Win 95 demo
reference software and exercise specific device capabili-
ties.
COP8 Hardware Debug Tools
•
COP8xx-DM: Metalink COP8 Debug Module for non-
flash COP8 Families. Windows based development and
real-time in-circuit emulation tool, with 100 frame trace,
32k s/w breaks, Enhanced User Interface, MetaLinkDe-
bugger, and COP8 OTP Programmer with sockets. In-
cludes COP8-NSDEV, power supply, DIP and/or SMD
emulation cables and adapters.
Includes PCB with pre-programmed COP8, 9v battery for
stand-alone operation, assembly listing, full applications
source code, BOM, and schematics.
(Add COP8-NSEVAL and an OTP programmer to imple-
ment your own software ideas in Assembly Code.)
17
www.national.com
•
Development: Metalink’s Debug Module includes devel-
opment device programming capability for COP8 de-
vices. Many other third-party programmers are approved
for development and engineering use.
COP8 Tools Overview (Continued)
•
IM-COP8: MetaLink iceMASTER® for non-flash COP8
devices. Windows based, full featured real-time in-circuit
emulator, with 4k trace, 32k s/w breaks, and MetaLink-
Windows Debugger. Includes COP8-NSDEV and power
supply. Package-specific probes and surface mount
adaptors are ordered separately. (Add COP8-PM and
adapters for OTP programming.)
•
•
Production: Third-party programmers and automatic
handling equipment cover needs from engineering proto-
type and pilot production, to full production environments.
Factory Programming: Factory programming available
for high-volume requirements.
COP8 Development and OTP Programming Tools
•
COP8-PM: COP8 Development Programming Module.
Windows programming tool for COP8 OTP Families. In-
cludes 40 DIP programming socket, control software,
RS232 cable, and power supply. (SMD and 87Lxx pro-
gramming adapters are extra.)
WHERE TO GET TOOLS
Tools are ordered directly from the following vendors. Please go to the vendor’s web site for current listings of distributors.
Vendor
Home Office
U.S.A.: Santa Clara, CA
1-408-327-8820
Electronic Sites
Other Main Offices
Distributors
Aisys
www.aisysinc.com
@
info aisysinc.com
fax: 1-408-327-8830
U.S.A.
Byte Craft
IAR
www.bytecraft.com
Distributors
@
1-519-888-6911
info bytecraft.com
fax: 1-519-746-6751
Sweden: Uppsala
+46 18 16 78 00
fax: +46 18 16 78 38
www.iar.se
U.S.A.: San Francisco
1-415-765-5500
@
info iar.se
@
info iar.com
fax: 1-415-765-5503
U.K.: London
@
info iarsys.co.uk
@
info iar.de
+44 171 924 33 34
fax: +44 171 924 53 41
Germany: Munich
+49 89 470 6022
fax: +49 89 470 956
Switzeland: Hoehe
+41 34 497 28 20
fax: +41 34 497 28 21
ICU
Sweden: Polygonvaegen
+46 8 630 11 20
www.icu.se
@
support icu.se
@
fax: +46 8 630 11 70
Denmark:
support icu.ch
KKD
www.kkd.dk
MetaLink
U.S.A.: Chandler, AZ
1-800-638-2423
www.metaice.com
Germany: Kirchseeon
80-91-5696-0
@
sales metaice.com
@
fax: 1-602-926-1198
support metaice.com
fax: 80-91-2386
@
bbs: 1-602-962-0013
www.metalink.de
islanger metalink.de
Distributors Worldwide
National
U.S.A.: Santa Clara, CA
1-800-272-9959
www.national.com/cop8
Europe: +49 (0) 180 530 8585
fax: +49 (0) 180 530 8586
Distributors Worldwide
@
support nsc.com
@
europe.support nsc.com
fax: 1-800-737-7018
The following companies have approved COP8 program-
mers in a variety of configurations. Contact your local office
or distributor. You can link to their web sites and get the lat-
est listing of approved programmers from National’s COP8
OTP Support page at: www.national.com/cop8.
Logical Devices; MQP; Needhams; Phyton; SMS; Stag Pro-
grammers; System General; Tribal Microsystems; Xeltek.
CUSTOMER SUPPORT
Complete product information and technical support is avail-
able from National’s customer response centers, and from
our on-line COP8 customer support sites.
Advantech; Dataman; EE tools; Minato; BP Microsystems;
Data I/O; Hi-Lo Systems; ICE Technology; Lloyd Research;
www.national.com
18
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Molded Small Outline Package (M)
Order Number COP912C-XXX/WM, COP912CH-XXX/WM
NS Package Number M20B
20-Lead Molded Dual-In-Line Package (N)
Order Number COP912C-XXX/N, COP912CH-XXX/N
NS Package Number N20A
19
www.national.com
Notes
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a
significant injury to the user.
2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
National Semiconductor
Corporation
Americas
Tel: 1-800-272-9959
Fax: 1-800-737-7018
Email: support@nsc.com
National Semiconductor
Europe
National Semiconductor
Asia Pacific Customer
Response Group
Tel: 65-2544466
Fax: 65-2504466
National Semiconductor
Japan Ltd.
Tel: 81-3-5639-7560
Fax: 81-3-5639-7507
Fax: +49 (0) 180-530 85 86
Email: europe.support@nsc.com
Deutsch Tel: +49 (0) 69 9508 6208
English Tel: +44 (0) 870 24 0 2171
Français Tel: +33 (0) 1 41 91 8790
Email: ap.support@nsc.com
www.national.com
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
相关型号：
COPC912-XXX/N/NOPB
IC 8-BIT, MROM, 10 MHz, MICROCONTROLLER, PDIP20, PLASTIC, DIP-20, Microcontroller
NSC
©2020 ICPDF网 联系我们和版权申明