CS18LV10245LI [ETC]
HIgh Speed Super Low Power SRAM; 高速超低功率SRAM
| 型号： | CS18LV10245LI |
| 厂家： | 
ETC |
| 描述： | HIgh Speed Super Low Power SRAM |
| 文件： | 总15页 (文件大小：375K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High Speed Super Low Power SRAM
CS18LV10245
128K-Word By 8 Bit
DESCRIPTION
The CS18LV10245 is a high performance, high speed and super low power CMOS Static
Random Access Memory organized as 131,072 words by 8bits and operates from a wide range of
4.5 to 5.5V supply voltage. Advanced CMOS technology and circuit techniques provide both high
speed, super low power features and maximum access time of 55/70ns in 5V operation. Easy
memory expansion is provided by an active LOW chip enable (/CE) and active LOW output enable
(/OE).
The CS18LV10245 has an automatic power down feature, reducing the power consumption
significantly when chip is deselected. The CS18LV10245 is available in JEDEC standard 32-pin
sTSOP - I (8x13.4 mm), TSOP - I (8x20mm), SOP (450 mil) and PDIP (600 mil) packages.
FEATURES
1.
2.
3.
Fully static operation and Tri-state output
TTL compatible inputs and outputs
Ultra low power consumption :
z
2.0V (min) data retention
z
Low operation voltage : 4.5 ~ 5.5V ; 5mA＠1MHz (Max.) operating current (Vcc = 5.0V)
4.
5.
Standby Typ. = 0.50uA, (Typical value @ Vcc = 5.0V, TA = 25 0C)
Standard pin configuration
z
z
z
z
32 - SOP 450mil
32 - sTSOP-I - 8X13.4mm
32 - TSOP-I 8X20mm
32 - PDIP 600mil
Product Family
Part No.
Operating Temp Vcc. Range Speed (ns) Standby (Typ.)
Package Type
32 SOP
CS18LV10245CC
CS18LV10245DC
CS18LV10245EC
CS18LV10245LC
CS18LV10245CI
CS18LV10245DI
CS18LV10245EI
CS18LV10245LI
0.50uA
32 STSOP
32 TSOP (I)
32 PDIP
0~70oC
4.5 ~ 5.5
55/70
32 SOP
0.80uA
32 STSOP
32 TSOP (I)
32 PDIP
-40~85oC
Note: Green package part no, sees order information.
Rev. 1.2
P 1
Copyright 2004 March Chiplus Semiconductor Corp. All rights reserved. .
High Speed Super Low Power SRAM
CS18LV10245
128K-Word By 8 Bit
PIN CONFIGURATIONS
32 STSOP 8x13.4mm
32 TSOP(I) 8x20mm
32 SOP 450 mil
32 PDIP 600 mil
BLOCK DIAGRAM
Rev. 1.2
P 2
Copyright 2004 March Chiplus Semiconductor Corp. All rights reserved. .
High Speed Super Low Power SRAM
CS18LV10245
128K-Word By 8 Bit
PIN DESCRIPTIONS
Name
Function
These 17 address inputs select one of the 131,072 x 8-bit words in the RAM.
A0-A16
Address Input
/CE
Chip Enable Input
CE2
Chip Enable 2 Input
/CE is active LOW and CE2 is active HIGH. Both chip enables must be active
when data read from or write to the device. If either chip enable is not active,
the device is deselected and is in a standby power mode. The DQ pins will be
in the high impedance state when the device is deselected.
The write enable input is active LOW and controls read and write operations.
With the chip selected, when /WE is HIGH and /OE is LOW, output data will
be present on the DQ pins; when /WE is LOW, the data present on the DQ
pins will be written into the selected memory location.
/WE
Write Enable Input
The output enable input is active LOW. If the output enable is active while the
chip is selected and the write enable is inactive, data will be present on the
DQ pins and they will be enabled. The DQ pins will be in the high impedance
state when /OE is inactive.
/OE
Output Enable Input
These 8 bi-directional ports are used to read data from or write data into the
RAM.
DQ0-DQ7
Data Input/Output
Ports
Power Supply
Ground
Vcc
Gnd
TRUTH TABLE
MODE
/WE
X
/CE
H
CE2
X
/OE
X
DQ0~7
Vcc Current
Not
High Z
ICCSB, ICCSB1
Selected
X
X
L
X
Output
Disabled
H
L
H
H
High Z
ICC
H
L
L
L
H
H
L
X
DOUT
DIN
ICC
ICC
Read
Write
Rev. 1.2
P 3
Copyright 2004 March Chiplus Semiconductor Corp. All rights reserved. .
High Speed Super Low Power SRAM
128K-Word By 8 Bit
CS18LV10245
(1)
ABSOLUTE MAXIMUM RATINGS
Symbol
VTERM
TBIAS
TSTG
Parameter
Rating
-0.5 to Vcc+0.5
-40 to +125
-60 to +150
1.0
Unit
V
OC
OC
W
Terminal Voltage with Respect to GND
Temperature Under Bias
Storage Temperature
Power Dissipation
PT
DC Output Current
20
mA
IOUT
Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
OPERATING RANGE
Range
Ambient Temperature
0~70oC
Vcc
4.5V ~5.5V
Commercial
Industrial
-40~85oC
4.5V ~ 5.5V
CAPACITANCE (1) (TA = 25oC, f =1.0 MHz)
Symbol
CIN
Parameter
Conditions
VIN=0V
MAX.
Unit
pF
Input Capacitance
6
Input/Output Capacitance
VI/O=0V
8
pF
CDQ
1. This parameter is guaranteed and not tested.
Rev. 1.2
P 4
Copyright 2004 March Chiplus Semiconductor Corp. All rights reserved. .
High Speed Super Low Power SRAM
128K-Word By 8 Bit
CS18LV10245
DC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC )
Parameter
Parameter
Test Conduction
MIN TYP(1) MAX Unit
Name
Guaranteed Input Low
Voltage (2)
-0.5
0.8
V
VIL
Guaranteed Input High
Voltage (2)
2.0
Vcc+0.2
V
VIH
Input Leakage Current VCC=MAX, VIN=0 to VCC
1
1
uA
uA
IIL
IOL
Output Leakage
Current
VCC=MAX, /CE=VIN, or
/OE=VIN , VIO=0V to VCC
VCC=MAX, IOL = 2mA
Output Low Voltage
0.4
35
V
VOL
Output High Voltage
Operating Power
Supply Current
VCC=MIN, IOH = -1mA
2.4
V
VOH
ICC
(3)
/CE=VIL, IDQ=0mA, F=FMAX
mA
Standby Supply - TTL /CE=VIH, IDQ=0mA,
2
mA
uA
ICCSB
ICCSB1
/CE≧VCC-0.2V, VIN≧
VCC-0.2V or VIN≦0.2V
Standby Current
-CMOS
0.3
10
1. Typical characteristics are at TA = 25oC.
2. These are absolute values with respect to device ground and all overshoots due to system or tester
notice are included.
3. Fmax = 1/tRC.
DATA RETENTION CHARACTERISTICS ( TA = 0 to +70oC )
Parameter
Parameter
Test Conduction
MIN TYP(1) MAX Unit
Name
/CE≧VCC-0.2V,
VCC for Data Retention
1.5
V
VRD
VIN≧VCC-0.2V or VIN≦0.2V
/CE≧VCC-0.2V,
Data Retention Current
0.2
2.0
uA
ICCDR
VIN≧VCC-0.2V or VIN≦0.2V
Chip Deselect to Data
Retention Time
0
ns
ns
TCDR
tR
See Retention Waveform
(2)
tRC
Operation Recovery Time
1. Vcc = 3.0V, T = + 25oC. 2. t = Read Cycle Time.
A
RC
Rev. 1.2
P 5
Copyright 2004 March Chiplus Semiconductor Corp. All rights reserved. .
High Speed Super Low Power SRAM
128K-Word By 8 Bit
CS18LV10245
LOW Vcc DATA RETENTION WAVEFORM(1) ( /CE Controlled )
LOW Vcc DATA RETENTION WAVEFORM(2) ( CE2 Controlled )
KEY TO SWITCHING WAVEFORMS
WAFEFORM
INPUTS
OUTPUTS
Must be standby
Must be standby
May change for H to L
May change for L to H
Don’t care any change permitted
Does not apply
Will be change from H to L
May change for L to H
Change state unknown
Center line is high impedance “OFF” state
AC TEST CONDITIONS
Input Pulse Levels
Vcc/0V
5ns
Input Rise and Fall Times
Input and Output
Timing Reference Level
0.5Vcc
Rev. 1.2
P 6
Copyright 2004 March Chiplus Semiconductor Corp. All rights reserved. .
High Speed Super Low Power SRAM
128K-Word By 8 Bit
CS18LV10245
AC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC , Vcc = 5.0V )
< READ CYCLE >
JEDEC Parameter
Parameter Name
Name
Description
-55
-70
Unit
MIN MAX MIN MAX
Read Cycle Time
55
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAVAX
tAVQV
tELQV
tELQV
tGLQV
tE1LQX
tE2LOX
tGLQX
tEHQZ
tEHQZ
tGHQZ
tAXOX
tRC
Address Access Time
55
55
55
20
70
70
70
30
tAA
Chip Select Access Time (/CE)
Chip Select Access Time (CE2)
Output Enable to Output Valid
tACS1
tACS2
tOE
Chip Select to Output Low Z (/CE)
Chip Select to Output Low Z (CE2)
Output Enable to Output in Low Z
Chip Deselect to Output in High Z (/CE)
Chip Deselect to Output in High Z (CE2)
Output Disable to Output in High Z
Out Disable to Address Change
10
10
5
10
10
5
tCLZ1
tCLZ2
tOLZ
tCHZ1
tCHZ2
tOHZ
tOH
0
25
25
25
0
30
30
30
0
0
0
0
10
10
Rev. 1.2
P 7
Copyright 2004 March Chiplus Semiconductor Corp. All rights reserved. .
High Speed Super Low Power SRAM
CS18LV10245
128K-Word By 8 Bit
NOTES:
1. /WE is high in read Cycle.
2. Device is continuously selected when /CE = VIL.
3. Address valid prior to or coincident with CE transition low.
4. /OE = VIL.
5. Transition is measured ±500mV from steady state with CL = 5pF as shown in Figure 1B. The parameter is
guaranteed but not 100% tested.
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE (1,2,4)
READ CYCLE (1,3,4)
READ CYCLE (1,4)
Rev. 1.2
P 8
Copyright 2004 March Chiplus Semiconductor Corp. All rights reserved. .
High Speed Super Low Power SRAM
128K-Word By 8 Bit
CS18LV10245
AC ELECTRICAL CHARACTERISTICS ( TA = 0~70oC , Vcc = 5.0V )
< WRITE CYCLE >
JEDEC Parameter
Description
-55
-70
Unit
Parameter
Name
tAVAX
tE1LWH
tAVWL
Name
MIN MAX MIN MAX
Write Cycle Time
55
55
0
70
70
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tWC
tCW
tAS
tAW
tWP
tWR
tWR2
tWHZ
tDW
tDH
Chip Select to End of Write
Address Setup Time
Address Valid to End of Write
Write Pulse Width
55
55
0
70
70
0
tAVWH
tWLWH
tWHAX
tE2LAX
tWLQZ
tDVWH
tWHDX
tWHOX
Write Recovery Time (/CE, /WE)
Write Recovery Time (CE2, )
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
End of Write to Output Active
0
0
0
20
0
25
25
0
25
0
5
5
tOW
Rev. 1.2
P 9
Copyright 2004 March Chiplus Semiconductor Corp. All rights reserved. .
High Speed Super Low Power SRAM
128K-Word By 8 Bit
CS18LV10245
SWITCHING WAVEFORMS (WRITE CYCLE)
Rev. 1.2
P 10
Copyright 2004 March Chiplus Semiconductor Corp. All rights reserved. .
High Speed Super Low Power SRAM
CS18LV10245
128K-Word By 8 Bit
NOTES:
1. TAS is measured from the address valid to the beginning of write.
2. The internal write time of the memory is defined by the overlap of /CE and /WE low. All
signals must be active to initiate a write and any one signal can terminate a write by
going inactive. The data input setup and hold timing should be referenced to the second
transition edge of the signal that terminates the write.
3. TWR is measured from the earlier of /CE or /WE going high or CE2 going low at the end
of write cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite
phase to the outputs must not be applied.
5. If the /CE low transition occurs simultaneously with the /WE low transitions or after the
/WE transition, output remain in a high impedance state.
Rev. 1.2
Copyright 2004 March Chiplus Semiconductor Corp. All rights reserved. .
P 11
High Speed Super Low Power SRAM
128K-Word By 8 Bit
CS18LV10245
6. /OE is continuously low (/OE = VIL ).
7. DOUT is the same phase of write data of this write cycle.
8. DOUT is the read data of next address.
9. If /CE is low during this period, DQ pins are in the output state. Then the data input
signals of opposite phase to the outputs must not be applied to them.
10.Transition is measured ±500mV from steady state with CL = 5pF as shown in Figure 1B.
The parameter is guaranteed but not 100% tested.
11.TCW is measured from the later of /CE going low to the end of write.
Rev. 1.2
Copyright 2004 March Chiplus Semiconductor Corp. All rights reserved. .
P 12
High Speed Super Low Power SRAM
CS18LV10245
128K-Word By 8 Bit
ORDER INFORMATION
1. NON-GREEN PACKAGE:
CS18LV10245XX -XX
Speed:
55: 55NS
70: 70ns
Package:
C: 32SOP (450mil)
Grade:
C: 0~70°C
I: -40~85°C
D: 32STSOP I (8x13.4mm)
E: 32TSOP I (8x20mm)
L: 32PDIP (600mil)
2. GREEN PACKAGE:
CS18LV10245 X X X XX
Package:
Grade:
C: 0~70°C
I: -40~85°C
C: 32SOP (450mil)
D: 32STSOP I (8x13.4mm)
E: 32TSOP I (8x20mm)
Speed:
55: 55ns
70: 70ns
Green Code
A: Pb Free + Halogen Free (SOP / TSOP Types)
Rev. 1.2
P 13
Copyright 2004 March Chiplus Semiconductor Corp. All rights reserved. .
High Speed Super Low Power SRAM
CS18LV10245
128K-Word By 8 Bit
PACKAGE DIMENSIONS
-
32 pin SOP (450 mil) :
b
WITH PLATING
c1
BASE METAL
c
b1
SECTION A-A
SYMBOL
y
c
e
A
A1
A2
b
b1
c1
D
E
E1
L
L1
UNIT
_
_
Min. 2.645 0.102 2.540 0.35 0.35 0.15 0.15 20.320 11.176 13.792 1.118 0.584 1.194
0°
_
_
_
_
_
mm
Nom. 2.821 0.229 2.680
Max. 2.997 0.356 2.820 0.50 0.46 0.32
Min. 0.104 0.004 0.1000 0.014 0.014 0.006 0.006 0.800 0.440 0.543 0.044 0.023 0.047
20.447 11.303 14.097 1.270 0.834 1.397
0.28 20.574 11.430 14.402 1.422 1.084 1.600
0.1
_
_
10°
0°
_
_
_
_
_
inch Nom. 0.111 0.009 0.1055
0.805 0.445 0.555 0.050 0.033 0.055
Max. 0.118 0.014 0.1110 0.020 0.018 0.012 0.011 0.810 0.450 0.567 0.056 0.043 0.063 0.004 10°
-
32 pin STSOP I ( 8x13.4 mm) :
12°(2x)
12°(2x)
HD
c
L
1
32
Seating Plane
12°(2X)
y
16
17
"A"
D
GAUGE PLANE
A
0
16
17
A
L
SEATING PLANE
12°(2X)
L1
"A" DATAIL VIEW
b
WITH PLATING
c
c1
1
32
c
BASE METAL
b1
SECTION A-A
SYMBOL
UNIT
y
e
A
A1
A2
b
b1
c1
D
E
HD
L
L1
_
_
Min. 1.00
Nom. 1.10
Max. 1.20
0.05 0.95 0.17 0.17 0.10 0.10 11.70 7.90 0.40 13.20 0.40
0.70
0.80
0.90
0°
_
_
_
mm
0.10 1.00
0.15 1.05
0.22 0.20
0.27 0.23
11.80 8.00
0.21 0.16 11.90 8.10
0.50 13.40 0.50
0.60 13.60 0.70
0.1
_
_
8°
0°
_
Min. 0.0393 0.002 0.037 0.007 0.007 0.004 0.004 0.461 0.311 0.016 0.520 0.0157 0.0275
_
_
inch Nom. 0.0433 0.004 0.039 0.009 0.008
0.465 0.315 0.020 0.528 0.0197 0.0315
Max. 0.0473 0.006 0.041 0.011 0.009 0.008 0.006 0.469 0.319 0.024 0.536 0.0277 0.0355 0.004
8°
-
Rev. 1.2
P 14
Copyright 2004 March Chiplus Semiconductor Corp. All rights reserved. .
High Speed Super Low Power SRAM
CS18LV10245
128K-Word By 8 Bit
-
32 pin TSOP(I) ( 8x20mm)
HD
C
L
1
32
Seating Plane
12°(2x)
y
16
17
"A"
D
GAUGE PLANE
A
A
SEATING PLANE
12°(2x)
L
L1
"A" DETAIL VIEW
16
17
b
WITH PLATING
c
c1
BASE METAL
b1
1
32
SECTION A-A
SYMBOL
UNIT
y
c
e
A
A1
A2
b
b1
c1
D
E
HD
L
L1
_
_
Min. 1.00
Nom. 1.10
Max. 1.20
0.05
0.10 1.00
0.15 1.05
0.95 0.17
0.17 0.10
_
0.10 18.30 7.90
0.40 19.80 0.40 0.70
0.50 20.00 0.50 0.80
0.60 20.20 0.70 0.90
0°
_
_
mm
0.22 0.20
0.27
18.40 8.00
0.23
0.21 0.16 18.50 8.10
0.1
_
_
8°
0°
_
Min. 0.0393 0.002 0.037 0.007 0.007 0.004 0.004 0.720 0.311 0.016 0.779 0.0157 0.0275
inch Nom. 0.0433 0.004 0.039 0.009 0.008
_
_
0.724 0.315 0.020 0.787 0.0197 0.0315
Max. 0.0473 0.006 0.041 0.011 0.009 0.008 0.006 0.728 0.319 0.024 0.795 0.0277 0.0355 0.004
8°
-
32 pin PDIP ( 600 mil)
SYMBOL
c
e
Q1
A1
A2
B
B1
D
E
E1
eB
L
S
UNIT
Min. 0.254 3.785 0.330 1.143 0.152 41.783 14.986 13.716
_
16.002 3.048 1.651 1.651
16.510 3.302 1.905 1.778
17.018 3.556 2.159 1.905
0.630 0.120 0.065 0.065
0.650 0.130 0.075 0.070
0.670 0.140 0.085 0.075
2.540
mm
Nom.
Max.
3.912 0.457 1.270 0.254 41.910 15.240 13.818
4.039 0.584 1.397 0.356 42.037 15.494 13.920
(TYP)
_
Min. 0.010 0.149 0.013 0.045 0.006 1.645 0.590 0.540
_
0.100
inch Nom.
Max.
0.154 0.018 0.050 0.010 1.650 0.600 0.544
0.159 0.023 0.055 0.014 1.655 0.610 0.548
(TYP)
_
Rev. 1.2
P 15
Copyright 2004 March Chiplus Semiconductor Corp. All rights reserved. .
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