CS18LV20483AZI-70 [ETC]
High Speec Super Low Power SRAM; 高Speec超低功率SRAM
| 型号： | CS18LV20483AZI-70 |
| 厂家： | 
ETC |
| 描述： | High Speec Super Low Power SRAM |
| 文件： | 总16页 (文件大小：757K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High Speed Super Low Power SRAM
CS18LV20483
256K-Word By 8 Bit
Revision History
Rev. No.
History
Initial issue
Issue Date
Jan.26,2005
Remark
1.0
1
Rev. 1.0
Chiplus reserves the right to change product or specification without notice.
High Speed Super Low Power SRAM
CS18LV20483
256K-Word By 8 Bit
ꢀGENERAL DESCRIPTION
The CS18LV20483 is a high performance, high speed, and super low power CMOS Static
Random Access Memory organized as 262,144 words by 8 bits and operates from a wide range of
2.7 to 3.6V supply voltage. Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of 0.50uA and maximum
access time of 55/70ns in 3.0V operation. Easy memory expansion is provided by an active LOW
chip enable inputs (/CE1,CE2) and active LOW output enable (/OE) and three-state output drivers.
The CS18LV20483 has an automatic power down feature, reducing the power consumption
significantly when chip is deselected. The CS18LV20483 is available in JEDEC standard 32-pin
sTSOP (8x13.4 mm), TSOP (8x20mm), TSOP (II) (400mil) and SOP (450 mil) packages.
.
ꢀFEATURES
ꢁ
Low operation voltage : 2.7 ~ 3.6V
Ultra low power consumption : 2mA＠1MHz (Max.) operating current
0.50 uA (Typ.) CMOS standby current
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
High speed access time : 55/70ns (Max.) at Vcc = 3.0V.
Automatic power down when chip is deselected.
Three state outputs and TTL compatible
Data retention supply voltage as low as 1.5V.
Easy expansion with /CE and /OE options.
ꢀProduct Family
Operating
Product Family
Vcc. Range Speed (ns) Standby (Typ.) Package Type
Temp
32 SOP
32 STSOP
0.50 uA
0~70oC
2.7~3.6
2.7~3.6
55/70
55/70
32 TSOP
32 TSOP (II)
Dice
(Vcc = 3.0V)
CS18LV20483
32 SOP
32 STSOP
32 TSOP
32 TSOP (II)
Dice
0.8 uA
-40~85oC
(Vcc= 3.0V)
2
Rev. 1.0
Chiplus reserves the right to change product or specification without notice.
High Speed Super Low Power SRAM
256K-Word By 8 Bit
CS18LV20483
ꢀ PIN CONFIGURATIONS
ꢀ FUNCTIONAL BLOCK DIAGRAM
3
Rev. 1.0
Chiplus reserves the right to change product or specification without notice.
High Speed Super Low Power SRAM
CS18LV20483
256K-Word By 8 Bit
ꢀPIN DESCRIPTIONS
Type
Function
Name
Input
Address inputs for selecting one of the 262,144 x 8 bit words in the RAM
/CE1 is active LOW and CE2 is active HIGH. Both chip enables must be
active when data read from or write to the device. If either chip enable is
not active, the device is deselected and in a standby power down mode.
The DQ pins will be in high impedance state when the device is
deselected.
A0 – A17
Input
/CE1, CE2
The Write enable input is active LOW. It controls read and write
operations. With the chip selected, when /WE is HIGH and /OE is LOW,
output data will be present on the DQ pins, when /WE is LOW, the data
present on the DQ pins will be written into the selected memory location.
The output enable input is active LOW. If the output enable is active
while the chip is selected and the write enable is inactive, data will be
present on the DQ pins and they will be enabled. The DQ pins will be in
the high impedance state when /OE is inactive.
Input
/WE
Input
I/O
/OE
These 8 bi-directional ports are used to read data from or write data into
the RAM.
DQ0~DQ7
Power Power Supply
Power Ground
No connection
Vcc
Gnd
NC
ꢀTRUTH TABLE
MODE
/CE1 CE2
/WE
/OE
DQ0~7
Vcc Current
X
H
X
L
X
High Z
ICCSB, ICCSB1
Standby
X
H
X
L
H
Output
Disabled
Read
L
H
High Z
ICC
L
L
H
H
H
L
L
X
DOUT
DIN
ICC
ICC
Write
4
Rev. 1.0
Chiplus reserves the right to change product or specification without notice.
High Speed Super Low Power SRAM
CS18LV20483
256K-Word By 8 Bit
(1)
ꢀABSOLUTE MAXIMUM RATINGS
Symbol
VTERM
TBIAS
TSTG
Parameter
Rating
Unit
V
OC
OC
W
Terminal Voltage with Respect to GND
Temperature Under Bias
Storage Temperature
-0.5 to Vcc+0.5
-40 to +125
-60 to +150
1.0
Power Dissipation
PT
DC Output Current
25
mA
IOUT
1.Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect reliability.
ꢀ OPERATING RANGE
Range
Ambient Temperature
0~70oC
Vcc
2.7V ~ 3.6V
2.7V ~ 3.6V
Commercial
Industrial
-40~85oC
1. Overshoot : Vcc +2.0V in case of pulse width ≦20ns.
2. Undershoot : - 2.0V in case of pulse width ≦20ns.
3. Overshoot and undershoot are sampled, not 100% tested.
ꢀ CAPACITANCE (1) (TA = 25oC, f =1.0 MHz)
Symbol
CIN
Parameter
Conditions
VIN=0V
MAX.
Unit
pF
Input Capacitance
6
Input/Output Capacitance
VI/O=0V
8
pF
CDQ
1. This parameter is guaranteed and not tested.
5
Rev. 1.0
Chiplus reserves the right to change product or specification without notice.
High Speed Super Low Power SRAM
CS18LV20483
256K-Word By 8 Bit
ꢀ DC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC , Vcc = 3.0V )
Parameter
Name
VIL
Parameter
Test Conduction
MIN TYP(1)
MAX Unit
Guaranteed Input Low
Voltage (2)
-0.5
0.8
V
Guaranteed Input High
Voltage (2)
2.0
Vcc+0.2
V
VIH
Input Leakage Current VCC=MAX, VIN=0 to VCC
-1
-1
1
1
uA
uA
IIL
IOL
Output Leakage
Current
VCC=MAX, /CE=VIN, or
/OE=VIN , VIO=0V to VCC
VCC=MAX, IOL = 2mA
Output Low Voltage
0.4
25
V
VOL
Output High Voltage
Operating Power
Supply Current
VCC=MIN, IOH = -1mA
2.4
V
VOH
ICC
(3)
/CE=VIL, IDQ=0mA, F=FMAX
mA
Standby Supply - TTL /CE=VIH, IDQ=0mA,
1
4
mA
uA
ICCSB
ICCSB1
/CE≧VCC-0.2V, VIN≧
VCC-0.2V or VIN≦0.2V
Standby Current
-CMOS
0.5
1. Typical characteristics are at TA = 25oC.
2. These are absolute values with respect to device ground and all overshoots due to system or
tester notice are included.
3. Fmax = 1/tRC.
ꢀ DATA RETENTION CHARACTERISTICS ( TA = 0 to + 70oC)
Parameter Name
Parameter
VCC for Data Retention
Test Conduction
MIN TYP MAX Unit
/CE≧VCC-0.2V,
1.5
V
VDR
VIN≧VCC-0.2V or VIN≦0.2V
/CE≧VCC-0.2V, VCC=1.5V
VIN≧VCC-0.2V or VIN≦0.2V
Data Retention Current
0.3
2
uA
ns
ns
ICCDR
TCDR
Chip Deselect to Data
Retention Time
Operation Recovery
Time
0
See Retention Waveform
tRC (1)
tR
1. Read Cycle Time.
6
Rev. 1.0
Chiplus reserves the right to change product or specification without notice.
High Speed Super Low Power SRAM
256K-Word By 8 Bit
CS18LV20483
ꢀ
LOW Vcc DATA RETENTION WAVEFORM 1 ( /CE1 Controlled )
ꢀ
LOW Vcc DATA RETENTION WAVEFORM 2 ( CE2
Controlled )
ꢀ AC TEST CONDITIONS
ꢀ KEY TO SWITCHING WAVEFORMS
WAVEFORMS
INPUTS
OUTPUTS
Input Pulse Levels
Vcc/0V
MUST BE STEADY MUST BE STEADY
Input Rise and Fall Times
5ns
Input and Output Timing
Reference Level
0.5Vcc
MAY CHANGE
FROM H TO L
WILL BE CHANGE FROM H
TO L
See FIGURE 1A
and 1B
Output Load
MAY CHANGE
FROM L TO H
WILL BE CHANGE FROM L
TO H
DON’T CARE ANY
CHANGE
CHANGE STATE
UNKNOWN
PERMITTED
CENTER LINE IS HIGH
IMPEDANCE OFF STATE
DOES NOT APPLY
7
Rev. 1.0
Chiplus reserves the right to change product or specification without notice.
High Speed Super Low Power SRAM
CS18LV20483
256K-Word By 8 Bit
ꢀ AC TEST LOADS AND WAVEFORMS
TERMINAL EQUIVALENT
667Ω
OUTPUT
1.73V
ALL INPUT PULSES
VCC
90% 90%
10%
10%
GND
FIGURE 2
5ns
5ns
FIGURE 1A
FIGURE 1B
ꢀ AC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC , Vcc = 3.3V )
< READ CYCLE >
JEDEC Parameter
Parameter Name
Name
Description
-55
-70
Unit
MIN MAX MIN MAX
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Enable to Output Valid
Chip Select to Output Low Z
Output Enable to Output in Low Z
Chip Deselect to Output in High Z
Output Disable to Output in High Z
Out Disable to Address Change
55
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAVAX
tAVQV
tELQV
tGLQV
tELQX
tGLQX
tEHQZ
tGHQZ
tAXOX
tRC
tAA
tCO
tOE
tLZ
tOLZ
tCHZ
tOHZ
tOH
55
55
25
70
70
35
10
5
0
0
10
10
5
0
0
10
20
20
25
25
8
Rev. 1.0
Chiplus reserves the right to change product or specification without notice.
High Speed Super Low Power SRAM
CS18LV20483
256K-Word By 8 Bit
ꢀ SWITCHING WAVEFORMS (READ CYCLE)
NOTES:
1. tHZ and tOHZ are defined as the outputs achieve the open circuit conditions and are not
referenced to output voltage levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both
for a given device and from device to device interconnection.
9
Rev. 1.0
Chiplus reserves the right to change product or specification without notice.
High Speed Super Low Power SRAM
256K-Word By 8 Bit
CS18LV20483
ꢀ AC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC , Vcc = 3.3V )
< WRITE CYCLE >
JEDEC Parameter
Description
-55
-70
Unit
Parameter
Name
tAVAX
Name
tWC
tCW
tAS
MIN MAX MIN MAX
Write Cycle Time
55
45
0
70
60
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Select to End of Write
Address Setup Time
tE1LWH
tAVWL
tAVWH
tWLWH
tWHAX
tWLQZ
tDVWH
tWHDX
tWHOX
Address Valid to End of Write
Write Pulse Width
45
40
0
60
50
0
tAW
tWP
Write Recovery Time
tWR
tWHZ
tDW
tDH
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
End of Write to Output Active
20
20
25
0
30
0
5
5
tOW
10
Rev. 1.0
Chiplus reserves the right to change product or specification without notice.
High Speed Super Low Power SRAM
256K-Word By 8 Bit
CS18LV20483
ꢀ SWITCHING WAVEFORMS (WRITE CYCLE)
11
Rev. 1.0
Chiplus reserves the right to change product or specification without notice.
High Speed Super Low Power SRAM
CS18LV20483
256K-Word By 8 Bit
NOTES:
1. A write occurs during the overlap(tWP) of low /CE1, a high CE2 and low /WE. A write
begins when /CE1 goes low, CE2 going high and /WE goes low. A write ends at the
earliest transition when /CE1 goes high , CE2 goes high an /WE goes high. The tWP is
measured from the beginning of the write to the end of write.
2. tCW is measured from the /CE1 going low or CE2 going low to end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end or write to the address change. TWR applied in case a
write ends as /CE1 or /WE going high or CE2 going low.
ꢀ ORDER INFORMATION
12
Rev. 1.0
Chiplus reserves the right to change product or specification without notice.
相关型号：
©2020 ICPDF网 联系我们和版权申明