CS3712中文资料_数据手册_规格书

PRELIMINARY DRAFT

CL-CS3712

Integrated AVI/ATAPI DVD

Drive Manager Datasheet

Features

Overview

• Integrates all required components for a complete AVI

or ATAPI interface DVD drive (front-end) electronics

solution:

The CL-CS3712 is Cirrus Logic’s high-integration, high-

performance ATAPI DVD drive manager. It integrates all

required components for a DVD loader for DVD players,

game consoles, and DVD-ROM drives. The CL-CS3712

includes an RF amp, servo control processor, data

channel, DVD ECC, CSS authorization, CD-ROM

decoder, and ATAPI interface.

- RF amp

- Data channel

- Servo control processor

- DVD ECC (error correction code)

- CSS (content scramble system)

- ATAPI decoder

The CL-CS3712 can be configured with an audio DAC

(digital-to-analog converter), external buffer memory (8- or

16-bit DRAM), a local micro-controller with its RAM and

ROM, and power drivers to create a complete DVD-ROM

electronics solution.

• Reads DVD+RW, DVD-ROM, DVD-RW, CDDA, CD-

ROM, CD-R, CD-RW, VCD, and DVCD discs

• Direct Audio/Video interface for DVD player

applications

• ATAPI interface for game console and DVD loader

solutions

• High-performance controller supports DVD disc speeds

up to 8x and CD-ROM disc speeds up to 40x

• Partial Response Maximum Likelihood (PRML) data

channel

• Servo Control Processor (SCP) on-chip

• DVD navigation support

• 208-pin LQFP/EPAD packages

The CL-CS3712 supports DVD disc speeds up to 8x and

Ultra DMA host speeds up to 33.3 Mbytes/sec.

The RF signal is over-sampled by a high-speed ADC

(analog-to-digital converter). The timing loop is closed in

the digital domain with variable decimation and

interpolation used to provide the output samples to the

data recovery logic. A channel-quality logic circuit is

provided to allow parametric calibration.

The CL-CS3712 data channel supports partial response

maximum likelihood (PRML) data acquisition, providing

state-of-the-art data recognition in a noisy environment,

coming from the pick-up head.

Block

Diagram

FROM

SENSORS

SPINDLE

CONTROL

TO POWER

DRIVERS

DACS

MICRO

INTERFACE

SAMPLE

RATE GEN

LOCAL

RAM

MICROCONTROLLER

CSS

FROM

IV AMP

AUTHENTIFICATION

VGA

ADCS

SCP

CSS

DESCRAMBLE

CHANNEL

QUALITY

BAC

CAPTURE

ATAPI OR

HOST

INTERFACE

SUM &

VGA

LOW PASS

FILTER

RF

ADC

DPLL &

DATA CHNL

MPEG

NAVIGATION

LAYERED ECC

& DVD ECC

SYNTHESIZER

BUFFER

MANAGER

8/16

DEMOD

BUFFER

MEMORY

HEADER

SEARCH &

CHECKS

C1/C2 ECC &

DE-INTERLEAVE

EFM

DEMOD

SUBCODE

DE-INTERLEAVE

SUB-Q READ

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Features (Cont.)

RF Amp

Host Interface

• Provides laser power control

• True real-time hardware/software ATAPI compatibility

• Gain control in digital domain

• Supports Ultra DMA: capable of synchronous DMA

data rates up to 33.3 Mbytes/sec.

• Supports ATA PIO modes 3 and 4 transfers without

IOCHRDY

• Generates focus error and tracking signal

• Provides RF signal for the data channel

• Bypass for external RF amp applications

Host Interface (cont.)

Data Channel

• Supports DMA modes 1 and 2

• Hardware implementation of:

- ATAPI packet command

• Digital PLL provides flexible control of center

frequency to support improved access times

• Channel quality provided for parametric calibration

• Channel data rates up to 210 Mbits/sec.

- ATAPI reset command

• Flexible and error-tolerant channel sync mark

High-Performance

windowing

• PIO/DMA ATAPI bus transfer rate:

SCP (Servo Control Processor)

- PIO modes 3 and 4, multiword DMA modes 1

and 2, and singleword DMA modes 1 and 2

• Data transfer rate:

• Includes a servo control processor for focus, tracking,

sled, and spindle servo loops

• Significantly faster capture for focus and tracking

• Effective in a wide range of parameter variations

• Superior response to defects, shock, and vibration

• Supports both CLV (constant linear velocity) and CAV

(constant angular velocity) modes

- CD-ROM CLV –maximum 32 × data rate with

25% overspeed capture

- CD-ROM CAV – maximum 40× OD data rate

- DVD-ROM CLV – maximum 6× data rate with

33% overspeed capture

- DVD-ROM CAV – maximum 8× OD data rate

- DVD+R CLV – max. 4x read

ECC

• Real-time DVD ECC error correction

• Buffer bandwidth:

• Real-time CD-ROM layered ECC error correction with

programmable number of sets of P-word and Q-word

corrections per sector (up to 64 total)

- 55 Mbytes per second with 16-bit DRAM

Buffer Manager

• C1/C2 ECC and de-interleaving

• Real-time subcode error correction in CD-DA

(compact disc digital audio) mode

• Dual-port circular buffer control with access-priority

resolver

• Supports streaming operation

• Direct addressing of up to 4 Mbytes of DRAM

• Supports variable buffer segmentation

• Programmable timing control for SDRAM

• Host overrun control

Decoder

• Supports hardware streaming operation

• DVD navigation support

• Supports ADB (audio data buffering)

• Automatic target sector header search

• Hardware sector header validity check

• Supports 16-bit SDRAM

• Supports high-speed Intel - and Motorola -type

microcontrollers

• Supports nonmultiplexed and multiplexed address

and data buses

Overview (Cont.)

The CL-CS3712 servo control processor implements the

focus, tracking, sled, and spindle servo loops. An ADC is

provided to convert the focus and tracking error signal.

The outputs to the power drivers are linear DACs.

The buffer manager controls the flow of data from the data

channel, through the ECC, and to either the host interface

or the serial audio channel. Data is stored and retrieved in

the external buffer memory using interleaved access

cycles. The buffer memory is implemented with SDRAM

devices. Up to 4 Mbytes of SDRAM can be directly

addressed by the CL-CS3712.

The CL-CS3712 supports real-time DVD ECC, CD-ROM

C1/C2, and layered ECC correction, which is

programmable for up to 64 P- and Q-word corrections per

sector. It also supports subcode R/W correction in CD-

DA (compact disc digital audio) mode.

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Features (Cont.)

Microcontroller Interface

• Supports high-speed Intel - and Motorola -type

microcontrollers

• Supports nonmultiplexed and multiplexed address

and data busses

• Interrupt or polled microcontroller interface

• Microcontroller access to six external switch settings

on the buffer bus

- Three-level power-down capability when idle,

automatic power-up when command is

received

Overview (Cont.)

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Table of Contents

System Block Diagrams .........................................................................................................................1

DVD-ROM ...................................................................................................................1

DVD PLAYER ..............................................................................................................1

Functional Decriptions............................................................................................................................2

Decoder.....................................................................................................................................2

DVD Mode....................................................................................................................2

CD Form.......................................................................................................................3

Data Channel ............................................................................................................................4

Servo Channel...........................................................................................................................6

Pickup/Sensor Interface ...............................................................................................6

Servo Control Processor ..............................................................................................6

Servo DACs..................................................................................................................6

Register Map ..........................................................................................................................................8

Pinout Information ...............................................................................................................................13

Pinout Diagram .......................................................................................................................13

Pin Decriptions ........................................................................................................................14

Package And Order Information...........................................................................................................19

Package Information ...............................................................................................................19

LQFP Ordering Information .....................................................................................................21

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System Block Diagrams

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System Block Diagrams

DVD-ROM

BUFFER

MEMORY

CL-CS3712

DATA

CHANNEL

DECODER

HOST

INTERFACE

ATAPI

RF AMP

SPINDLE

SERVO

DVD/CD-ROM

ECC

CSS

CONTROL

PROCESSOR

3

SLED/TRACK/FOCUS

POWER

DRIVERS

ROM

MC

DVD PLAYER

BUFFER

MEMORY

USER

CONTROL

LED

DISPLAY

IR

ROM

MC

SENSOR

CL-CS3712

DATA

CHANNEL

DECODER

AC-3

6

6 CHANNEL

AUDIO

DECODER

AUDIO

RF AMP

MPEG2

NTSC/PAL

ENCODER

VIDEO

DECODER

SPINDLE

SERVO

CONTROL

PROCESSOR

DVD/CD-ROM

ECC

CSS

3

SLED/TRACK/FOCUS

BUFFER MEMORY

(2 MBYTES)

POWER

DRIVERS

ROM

MC

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Functional Decriptions

This section overviews the main functional blocks of the CL-CS3712 Integrated AVI/

ATAPI DVD Drive Manager, and is divided into the following sub-sections:

• "Decoder" on page 2

• "Data Channel" on page 4

• "Servo Channel" on page 6

Decoder

The CL-CS3712 contains a highly automated DVD/CD decoder that takes EFM data from

the Analog Front and Digital PRML read channel and transform this data through a series

of operations into user data and sends it to the Host controller.

The sequence of operation is as follows:

The high level firmware sets up the decoder through the UP control interface. The

decoder is controlled through a register set. The high level FW sets up the mode of

operation (CD or DVD), the buffer manager and the host interface. The external SDRAM

buffer is controlled through a set of address pointers programmed by the FW. This

address pointers controls the data flow from the DISC, to and fro to the ECC Block and

the HOST.

DVD Mode

The actual data that is written on the DVD DISC is a transformed version of the user data

and follows the DVD Physical Specification.

To understand the decoder flow the transformation process needs to be understood,

which is beyond the scope of this document. In summary the user data is organized in

sectors (2048 bytes). The transformation process involves adding ID (Sector #) and other

information such as copy protection etc. to the data, Scrambling the data, ECC encoding,

splitting the data into recording frames , EFM modulation and creation of EFMP frames

with unique sync patterns inserted for EFMP frame identification.

The function of the decoder is to take this transformed data and convert back into the

user format.

Once the FW sets the start transfer control bit(s) in the decoder, the Decoder starts

processing the data from the Read Channel. The data is in the EFMP format (Eight to

Fourteen Modulation Plus) as defined in the DVD Physical Specification. The first step is

to synchronize and align the data on the EFMP frame boundaries by detecting unique

sync patterns that are embedded in the EFMP data stream. Once the data is aligned on

the EFMP frame boundary it is de-serialized into 16-bit symbols, and than demodulated

into 8 bits of data according to the EFMP modulation standard.

The next step is to determine the right starting point to start the transfer of data into the

buffer. The FW will program the Target Header or ID information. Once the incoming data

ID matches the programmed ID, data transfer to the Buffer starts. The data transfer

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Functional Decriptions

PRELIMINARY DRAFT

always start on an ECC boundary. The HW monitors the subsequent ID to detect any

interruption in the DVD data stream.

After sufficient data is stored (at least 1 ECC Block = 16 sectors) in the Buffer, the Error

Correction (ECC) system can start the Error Detection and Correction. The Error

Correction algorithm is programmable to allow for multi-pass correction, depending

upon the application e.g. in the DVD-ROM case, one would program it with more passes

than for DVD-Movie case.

Once ECC system has corrected one ECC block, this data can be transferred to the

host. However before transferring this data need to be de-scrambled. The de-

scrambling process is done during Host transfer to save Buffer BW.

All the Disc Transfer, ECC correction, Descrambling and Host Transfers are done in

parallel without any intervention from the micro-controller. The hardware keeps track of

how many sectors are transferred from the disc to the buffer, how many sectors have

been corrected and how many transferred to the host. This is a fully automated

operation also known as "full streaming".

CD Form

The actual data that is written on the CD DISC is a transformed version of the user data

and follows the CD Physical Specification. The Physical format of a CD disc is defined

by the CD-Digital Audio Physical Specification. All CD whether CD-ROM or CD-Audio

follows this standard. The recordable formats also follow this format, except for the

linking area for multi-session recordings.

Again it is beyond the scope of this document to describe the CD formats as unlike the

DVD format, there are host of different formats that the decoder needs to process.

These are CD-DA, CD-ROM Mode 0, CD-ROM Mode 2/Form1 CD-ROM Mode 2/ Form

2 plus CD-Recordable data. In addition for the CD-DA mode the decoder needs to

process the Sub Channel Data. The Sub-Channel contains additional information that is

embedded in the EFM data stream, which contains sector identifications and other

information unique to the data.

Basically there are two types of data, CD-Audio and CD-ROM (with different modes and

form). For CD-Audio both the main channel and the Sub Channel Data needs to be

processed, for the CD-ROM case only the main channel data is processed.

The data arriving from the Read Channel is in the EFM format, first it is synchronized

and aligned on the EFM frame boundaries. After synchronization the data is

demodulated using the EFM demodulation table.

CD data is protected through 2 levels of correction C1 and C2 for the CD-DA and 3

levels C1, C2 and C3 for CD-ROM formats.

C1 and C2 correction is done on the fly, i.e. before the data is transferred to the Buffer.

After EFM demodulation, the data is sent to CIRC block (Cross Interleaved Reed

Solomon Code) which performs C1 and C2 correction on the incoming data. It also

marks data it cannot correct, these markers called C2 Pointers are used by the Audio

Interpolator block to perform audio interpolation and in the case of CD-ROM data, help

the C3 correction engine in identifying the errors quickly.

After the EFM demodulation, the Target Header Search looks for the target sector ID in

the data stream. In the case of CD-DA this ID is in the sub channel data stream,

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Functional Decriptions

whereas in the case of CD-ROM data it is embedded in the main channel data. Once the

Target Header is found the data transfer to the Buffer starts and the de-scrambling is

done while storing the data in the buffer from the disc. This data is than transferred to the

Host (ATAPI or Audio DAC interface)

In the case of CD-ROM data, depending on the format additional C3 correction needs to

be performed. This flow is similar to the DVD case, i.e. when sufficient sectors are

available in the buffer, the ECC engine starts correcting the data and the Host transfer

starts as soon as sufficient sectors are available after C3 correction.

Data Channel

The CL-CS3712 contains a partial response maximum likelihood (PRML) read channel.

The channel takes the analog signals from the optical pickup's (OPU) photo detector

outputs, detects the EFM or EFM+ data, and sends the data to the decoder. Figure 1

illustrates the Data Channel architecture.

OFFSET

CONTROL

PD A

PD B

PD C

PD D

ATTENUATOR

DIGITAL

AND

VGA

DAC

+

LPF

RF ADC

EQUALIZER

SUMMATION

DAC

OFFSET

CONTROL

OFFSET

ENVELOPE

CONTROL

DETECT

GAIN

CONTROL

DEFECT

DETECT

RF TRACK

CROSSING

CHANNEL

QUALITY

SEQUENCE

DETECTOR

ITR

TO DECODER

Figure 1. Data Channel Diagram

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The CL-CS3712 data channel architecture minimizes analog signal processing and

migrates all feasible functionality to real-time digital signal processing blocks. The

analog blocks are:

• Summation Amplifier

• Digitally Controlled Variable Gain Amplifier (VGA)

• Analog Low Pass Filter (LPF)

• Analog-to-Digital Converter (RF ADC)

The main data path digital blocks are:

• Digital Equalizer

• Interpolate Timing Recovery (ITR)

• Sequence Detector

The data path blocks are supported by the loop control blocks: the digital automatic gain

control (DAGC), offset control, and digital asymmetry control. The digital defect detect

block allows the loops and the servo processor to coast through defects. u-Controller

accessible channel quality metrics support servo error signal gain and offset calibration.

The Attenuator and Summation block interfaces the OPU's A, B, C, and D photodetector

outputs or the RF signal to the data channel. The attenuator and offset loop keeps the

signals within the linear range of the circuitry. The channel can use either internally or

externally summed RF.

The variable gain amplifier (VGA) is part of the automatic gain control (AGC) loop. This

amplifier's gain is exponentially proportional to its gain control. The analog low pass filter

is designed to limit noise and serve as an anti-aliasing filter.

The CL-CS3712 contains a high speed analog to digtial convertor that allows the

majority of the signal processing to be performed in the digital domain. The sampling

frequency is fixed and can be Fsynth/2 or Fsynth/4. This allows for a wide range of

allowable input data rates.

The digital equalizer is a 5 tap finite impulse response filter. It's coefficients change

automatically as the data rate changes. The envelope detector is used to generate error

signals for the offset and AGC loops. The defect detection is also performed here. The

digital offset loop keeps the read signal's baseline at the ADC's range center. The AGC

also keeps the signal's amplitude within the ADC's range. These loops are digital with

the exception of the digital to analog convertors (DACs), ADC, an adder, and a VGA.

The CL-CS3712 data channel performs data separation via the ITR. This all digital

implementation of a phase locked-loop (PLL) makes for consistent chip to chip

performance. It also allows for wide capture ranges. This decreases the speed of seeks

in constant linear velocity (CLV) mode. It has been designed handle the rate changes

inherent in constant angular velocity (CAV) mode automatically. Asymmetry

compensation is performed at the ITR input.

The CL-CS3712 contains a maximum likelihood sequence detector especially designed

for low resolution DVD signals. This sequence detector achieves substantial signal

processing gain over a slicer detector.

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Functional Decriptions

The channel is controlled by a state machine that automatically starts timing recovery and

deals with defects. This ensures quick recovery from defects and fast data acquisition

after seeks.

The CL-CS3712 contains a versatile digital block that can be used to monitor the ongoing

‘health’ or ‘quality’ of the channel, and that enables accurate equalization calibration to

compensate for wide variations in disc resolution.

Servo Channel

The CL-CS3712 contains an integrated servo system that can control either a CDROM or

a DVD mechanism, with the following features:

• Servo Control Processor (SCP), implementing algorithms designed specifically

for optical disc drives

• Supports dual pick up for CD and DVD applications

• Integrated RF amplifier with Laser Diode Automatic Power Control (LD APC)

• Track counter with velocity estimation

• Multi-function register banks

• External microcontroller interface circuitry

• Programmable Sample Rate Subsystem

Figure 2 shows the CL-CS3712 in a complete servo system. Four control loops can be

processed by this chip: focus, track, sled, spindle. Since the CL-CS3712 contains a

processor, control algorithms and interface circuitry, little external hardware and little

microcontroller intervention is required to implement the servo system.

Pickup/Sensor Interface

The Pickup Interface is the input to the servo control processor (SCP). This circuitry

provides the analog and digital processing needed before the SCP can process the

control signals from the sensors. Since laser diode automatic power control and

reference voltage generation are also provided, the CL-CS3712 can be connected

directly to the pick up electronics without the need for an external RF amplifier.

Servo Control Processor

The SCP does all the processing necessary to control all four servo loops with little

loading of the external microcontroller. The microcontroller sends setup information and

commands to the control system through the microcontroller interface. It can also monitor

key metrics and change control variables to optimize system performance.

All parameter variables and SCP instructions are stored in internal RAM. Since the CL-

CS3712 is a RAM based device, the microcontroller must first initialize these RAMs

before servo operations can begin.

Servo DACs

Control outputs for the sled, focus, and track loops are converted to analog through an

array of three 11-bit DACs. The spindle loop has a pulse width modulated (PWM) output.

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Functional Decriptions

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SERVO SYSTEM

PD OUTPUTS

10

DAC

VREF1

OUTPUTS

SERVO

CONTROL

PROCESSOR

(SCP)

LD-MON1

LD-PC1

PICK UP

INTERFACE

PICK UP

ELECTRONICS

4

SERVO

DACS

VREF2

LD-MON2

LD-PC2

PWM-SP

MICROCONTROLLER

INTERFACE

MICROCONTROLLER

POWER AMPS

SPIN

TRANSDUCER

SPINDLE

MOTOR

SLED

MOTOR

FOCUS

ACTUATOR

MOTION

TRACKING

ACTUATOR

Figure 2. Servo System Diagram

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Register Map

Table 1: CL-CS3712 Registers

Address (Hex)

Register Name

R/W

00H

01H

ATAPI Error (ATERR)

R/W

R

ATAPI Features (ATFEA)

02H

ATAPI Interrupt Reason (ATINT)

ATA Sector Number (ATSECN)

ATAPI Byte Count Low (ATBCL)

ATAPI Byte Count High (ATBCH)

ATAPI Drive Select (ATDSEL)

03H

04H

05H

06H

07H

ATAPI Command (ATCMD)

08H

ATAPI Packet (ATPKT)

R

09H

Alternate ATAPI Error (ALTERR)

ATA Drive Control/Status (ATDRV)

Host Drive Address (HDA)

R/W

W

0AH

0BH

0CH

0DH

0EH

10H

AT Control 1 (ATCTRL1)

AT Control 2 (ATCTRL2)

AT Control 3 (ATCTRL3)

Host Interrupt Status 1 (HIST1)

Host Interrupt Enable 1 (HIEN1)

Host Interrupt Status 2 (HIST2)

Host Interrupt Enable 2 (HIEN2)

PC Mode Control 1 (PCMODE1)

Host Transfer/Packet FIFO Control (HXFR)

ATAPI Phase Lock Release (ATULOCK)

Synchronous DMA Control (SDMA)

PC Mode Control 2 (PCMODE2)

MPEG Interface Configuration 1 (MPEGCFG1)

MPEG Interface Configuration 2 (MPEGCFG2)

MPEG Interface Configuration 3 (MPEGCFG3)

MPEG/BCA Interface Interrupt Status (MPEGIST)

MPEG/BCA Interface Interrupt Enable (MPEGIEN)

C2P Threshold Control (C2PTC)

C2P Threshold Counter

11H

12H

13H

15H

16H

17H

18H

R/W

19H

1BH

1CH

1DH

1EH

1FH

2CH

2DH

2EH

2FH

30H-31H

34H-35H

Servo Coefficient Control

DAC Interface Status/Control (DACS)

Audio Address Pointer (AAP)

Host Address Pointer (HAP)

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Register Map

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Table 1: CL-CS3712 Registers

Address (Hex)

Register Name

R/W

38H-39H

3CH-3DH

40H-41H

44H-45H

46H

Host Buffer Start Address (HBSA)

R/W

R

Local Address Base Pointer (LABP)

Host Buffer End Address (HBEA)

Host Transfer Count (HTC)

Scheduled Buffer Data Access (SBDA)

Buffer Transfer Control (BTC)

47H

48H-49H

4AH

Adjust Difference Block Count (ADBC)

Host Transfer Sector Type (HTST)

Host Transfer Format 1 (HTF1)

Host Transfer Format 2 (HTF2)

Buffer Timing Control (BTIM)

4BH

4CH

4DH

4EH

Buffer Mode Control (BMC)

4FH

DRAM Refresh Period (RFSH)

50H-51H

54H-55H

58H-5BH

5CH-5DH

60H-61H

64H-65H

66H-67H

68H-6BH

70H-71H

72H-73H

74H-77H

78H-79H

7AH-7BH

7CH

Disc Address Pointer (DAP)

Disc Buffer Start Address (DBSA)

Disc Transfer Count (DTC)

Disc Buffer End Address (DBEA)

Corrector Address Pointer (CAP)

Sector to be Corrected (STC)

Current Host Transfer Count (CHTC)

Corrector Transfer Count (CTC)

Buffer Sector Size (BSS)

R/W

R

Difference Block Count (DBC)

Local Address Offset Pointer (LAOP)

Navigation Pack Address Pointer (NAP)

Navigation Pack Detected (NAVPKDET)

Navigation Play Control (NAVCTL)

Threshold Transfer Count (TTC)

Decoder Operation Mode (DOPMD)

Disc Configuration (DCFG)

R

R/W

R

7FH

80H

81H

82H

Disc Transfer Control/Status (DCTRL)

ECC Control/Status 1 (ECC1)

83H

84H

DVD ECC Error Information (ECC2)

Data Channel Interface Configuration 2 (DCCFG2)

Target Header (TRGHD)

85H

86H

87H

Target Header Search Time-Out (HSTO)

RAW Header/Subheader Read-Out (RHDRD)

RAW Header Mismatch Threshold (RHDMTH)

Expected Header Read-Out (EXPHD)

88H

89H

R/W

R

8BH

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Register Map

Table 1: CL-CS3712 Registers

Address (Hex)

Register Name

R/W

8CH

8DH

8EH

90H

RAW Header/SubHeader Flag (HDFLG)

Header Read-Out Control (RDCTRL)

Data Channel Interface Configuration 3 (DCCFG3)

Disc Interrupt Status 1 (DIST1)

Disc Interrupt Enable 1 (DIEN1)

Disc Interrupt Status 2 (DIST2)

Disc Interrupt Enable 2 (DIEN2)

Disc Transfer Control 1 (DCTRL1)

Sector Per Track Count (SPTC)

BCA Control 1

R

R/W

R

91H

92H

93H

94H

95H

98H

99H

BCA Status 1

9AH

9BH

9CH

9DH

9EH-9FH

A0H

A1H

A2H

A3H

A4H

A5H

A6H

A7H

B5H

B6H

B7H

B8H

B9H

BAH

BBH

BDH

BEH

BFH

C0H

C1H

C2H

C3H

C4H

BCA Control 2

BCA Control 3

BCA Control 4

BCA Channel Clock

Spindle Speed

Defect Address FIFO1/FIFO2(DMF)

C1/C2 Control (C12CNTL)

R/W

R

EFM Sync Control (EFMSYCTL)

EFM Plus Sync Control (EFMPSYCTL)

Subcode Read-Out (SBRD)

Subcode Control/Status (SBCTL)

EFM Plus Sync Status (EFMPSYNSTS)

Corrected ID Read-Out (CIDR)

SRAM Diagnostics Status 1 (SRAMST1)

SRAM Diagnostics Status 2 (SRAMST2)

SRAM Diagnostics Status 3 (SRAMST3)

SRAM Diagnostics Control 1 (SRAMDIACTL1)

SRAM Diagnostics Control 2 (SRAMDIACTL2)

SRAM uC Access Data (SRAMUPDATA)

SRAM uC Access Address (SRAMUPADDR)

Test1 (TEST)

R/W

R

R/W

R

R/W

R

Product and Revision Number (PRVN)

Miscellaneous Control (MISC)

Power Control

R/W

Clock Selection

RF ADC Diagnostic Control 1

RF ADC Diagnostic Control 2

Analog Diagnostic

DS588PP1 - rev 0.4 April 11, 2002

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Register Map

PRELIMINARY DRAFT

Table 1: CL-CS3712 Registers

Address (Hex)

Register Name

R/W

C5H-C7H

C8H

C9H

CAH

CBH

CCH

CDH

CEH

CFH

D0H

D1H

D2H

D3H

D4H

D5H

D7H

D8H

D9H

DAH

DBH

DCH

DDH

DEH

DFH

E0H

RF ADC Diagnostic Accumulator

R

Laser Diode 1 Control

R/W

R

Laser Diode 2 Control

Reference Voltage/Diode/RF Amp Configuration

Pickup Interface

Analog Static Data Channel VGA

Analog Static Data Channel LPF

RF ADC Calibration Control

Bandgap Reference Calibration Control

Moving-Average Filter/Digital Filtering 1

Digital Filtering 2

Zone Control

Offset Loop Control

Automatic Gain Control

Gain Loop Accumulator Layer 0 and Layer 1

Offset Loop Accumulator Layer 0 and Layer 1

RF Envelope Detector Read

LF Envelope Detector

Topstate Monitor

Asymmetry Accumulator Layer 0 and Layer 1

Asymmetry Control

Channel Top Level State Control 1

Channel Top Level State Control 2

Channel Top Level State Control 3

DPLL Control 1

E1H

DPLL Control 2

E2H

DPLL Control 3

E3H

Sequence Detector

E4H-E5H

E6H-E7H

E8H

DPLL Center Period Accumulator

Channel Quality Accumulator

Channel Quality Mode Select

Defect Control 1

R/W

E9H

EAH

EBH

ECH

EDH

EFH

F0H

Defect Control 2

Defect Control 3

RF BCA Slicer

RF BCA Parser

Digital Diagnostic

Track Crossing Control

F1H

Servo Control

CONFIDEN TIAL

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PRELIMINARY DRAFT

Register Map

Table 1: CL-CS3712 Registers

Address (Hex)

Register Name

R/W

F2H

FBH

SCP Program Command (SPC)

R/W

SCP State Generator M Divider

SCP State Generator N/P Dividers

Memory Data

FCH

FDH

FEH-FFH

SCP Memory Control/Address

DS588PP1 - rev 0.4 April 11, 2002

CONFIDENTIAL

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Pinout Information

PRELIMINARY DRAFT

Pinout Information

Pinout Diagram

DIAG4

DIAG3

1

156 NC

2

155 NC

DIAG2

3

154 NC

DIAG1

4

153 NC

RF_ENV

CH QUAL MON

AGND

5

152 NC

6

151 AVDD

150 XTALO

149 MCLK2/XTALI

148 AGND

147 BGND

146 MCLK1

145 CLK_OUT

144 uC_CLK

143 CGND

142 DMA33CLK

141 RST*

7

AVDD

8

BGND

9

SDCLK

CKE

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

DQMU

DQML

BGND

WE*

BVDD

CS0*

140

INT1

CS1*

139 INT2

138 BGND

137 CS*

136 WR*/R/W*

135 RD*/DS

134 A7/ALE

133 A6

CAS*

RAS*

BD15

BD14

BD13

BD12

BVDD

132 A5

CL-CS3712

CVDD

131 A4

BD11

130 BVDD

129 A3

208-Pin LQFP

CGND

BD10

128 CGND

127 A2

BD9/PLL_CLK_BP_SL

BD8/CS_POLARITY

BD7/MOT-I*

BD6/M-NM*

BD5/DEC_CLK_BP_SL

BD4/DTSL

BD3/XTSL

BGND

126 A1

125 A0

124 CVDD

123 AD7

122 BGND

121 AD6

120 AD5

119 AD4

118 AD3

BD2/UCSL2

BVDD

BD1/UCSL1

BD0/UCSL0

BA11

117

AD2

116 AD1

115 AD0

114 EF2

113 BVDD

112 EF1

BA10

BA9

BA8

BA7

BGND

111

BA6

110 N/C

BA5

109

108

N/C

BGND

EXTCR

BA4

107 N/C

BVDD

106 TEST

BA3

105 TEST_ENBL*

CONFIDEN TIAL

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PRELIMINARY DRAFT

Pinout Information

Pin Decriptions

Table 2: Pin Map Legend

Description

Abbreviation or Convention

I

A pin that functions as an input only.

A pin that functions as an output only.

A pin that operates as an input or an output.

An open-drain output.

O

I/O

OD

TS

Z

A test pin.

A tristate output or input/output.

Following a signal name designates an active-low signal.

(*)

An italicized function name for a multifunction pin indicates that the function is

only valid on the low-to-high transition of RST*.

Pin name in italics

Table 3: CL-CS3712 Pin Map

Type

Name

Pin(s)

I/O

Function

DD15

DD14

DD13

DD12

DD11

DD10

DD9

DD8

DD7

DD6

DD5

DD4

DD3

DD2

DD1

DD0

79

77

74

71

69

67

63

60

58

62

65

68

70

72

76

78

I/O-TS

Host Data Bus

Host

Interface

Signals

DA2

DA1

DA0

94

89

92

I

Host Address Lines

CS1FX*

CS3FX*

DIOR*

95

96

82

81

57

88

87

83

I

Host Chip Select 0*

Host Chip Select 1*

Host I/O Read Strobe*

Host I/O Write Strobe*

Host Reset*

I

DIOW*

I

HRESET*

IOCS16*

INTRQ

I

OD

16-bit Data Transfer*

Host Interrupt Request

I/O Channel Ready

O -TS

IORDY

DS588PP1 - rev 0.4 April 11, 2002

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Pinout Information

PRELIMINARY DRAFT

Table 3: CL-CS3712 Pin Map (Continued)

Type

Name

Pin(s)

I/O

Function

DMARQ

DMACK*

PDIAG*

DASP*

SDCLK

CKE

80

85

90

98

10

11

12

13

15

17

18

19

20

O -TS

I

DMA Request

DMA Acknowledge*

Passed Diagnostics*

Slave Present

Host

Interface

I/O

O

Signals (cont.)

SDRAM CLK

O

Clock Enable

DQMU

DQML

WE*

O

Upper Data Mask Enable

Lower Data Mask Enable

Write Enable

O

CS0*

O

Chip Select 0

CS1*

O

Chip Select 1

CAS*

O

Column Address Strobe Low

Row Address Strobe

RAS*

O

BA11

BA10

BA9

BA8

BA7

BA6

BA5

BA4

BA3

BA2

BA1

BA0

42

43

44

45

46

47

48

50

52

53

54

55

O

Buffer Address [11:0]

Buffer

Interface

Signals

BD15

BD14

BD13

BD12

BD11

BD10

21

22

23

24

27

29

I/O

Buffer Data Bus

BD9/

PLL_CLK_BP_SL

30

I/O

Buffer Data Bus Bit 9 / PLL Clock Bypass

BD8/CS_POLARITY

BD7/MOT-I*

31

32

33

I/O

Buffer Data Bus Bit 8 / uComputer Clock Select

Buffer Data Bus Bit 7 / Motorola-Intel

BD6/M-NM*

Buffer Data Bus Bit 6 / Multiplexed - Nonmultiplexed

BD5/

DEC_CLK_BP_SL

34

I/O

Buffer Data Bus Bit 5 / Decoder Clock

BD4/DTSL

BD3/XTSL

35

36

I/O

Buffer Data Bus Bit 4 / Drive Test Select

Buffer Data Bus Bit3 / XTAL Select

BD2/UCSL2

BD1/UCSL1

BD0/UCSL0

38

40

41

I/O

Buffer Data Bus Bit 2-0 / uComputer Clock Select

CONFIDEN TIAL

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PRELIMINARY DRAFT

Pinout Information

Table 3: CL-CS3712 Pin Map (Continued)

Type

Name

Pin(s)

I/O

Function

AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0

123

121

120

119

118

117

116

115

I/O

Local Microcontroller Address And Data Bus

Local Microcontroller Address Bus Bit 5 /

Address Latch Enable

A7/ALE

134

I

A6

A5

A4

A3

A2

A1

A0

133

132

131

129

127

126

125

I

Microcontroller

Interface

Signals

Local Microcontroller Address Bus

CS*

137

135

136

140

139

141

I

Chip Select*

Read Strobe*/data Strobe

Write Strobe/ Read/write*

Interrupt1

RD*/DS

I

WR*/ R/W*

INT1

I

O-OD

I

INT2

Interrupt2

RST*

Reset*

SPIN_P

SPIN_N

158

157

I

Spin Transducer

DAC-TL

DAC-SL

DAC-F

164

165

171

170

169

159

108

102

167

146

149

150

142

145

144

O

I

Tilt DAC

Sled DAC

Servo

Analog

Interface

Signals

Focus DAC

Tracking DAC

Auxiliary ADC

Spin PWM

DAC-T

ADC-AUX

PWM-SP

EXTCR

O

I

External Track Counter Real And External Track Counter

Quadrature

EXTCQ

I

VREF2

O

I

Voltage Reference 2

Master Clock 1

MCLK1

MCLK2/XTALI

XTALO

I

Master Clock 2 / Crystal Input

Crystal Output

Clock

Interface

Signals

O

I

DMA33CLK

CLK_OUT

uC_CLK

DMA33 Clock

O

Clock Output

Microcontroller Clock

DS588PP1 - rev 0.4 April 11, 2002

CONFIDENTIAL

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Pinout Information

PRELIMINARY DRAFT

Table 3: CL-CS3712 Pin Map (Continued)

Type

Name

Pin(s)

I/O

Function

PD-DE1

PD-DE2

PD-DF1

PD-DF2

175

176

177

178

I

Servo Differential Push Pull Amp Inputs

PD-DA

PD-DC

PD-DD

PD-DB

182

183

184

185

I

Photo Detector-DVD

RF External Summation Inputs

Photo Detector-CDROM

RF_P

RF_N

194

195

I

PD-CA

PD-CB

PD-CC

PD-CD

192

193

190

189

I

RF

Amplifier

Interface

Signals

PD-CE

PD-CF

191

197

I

Photo Detector E & F-CDROM

Photo Detector-T

PD-T

187

I

LD-PC1

LD-PC2

179

201

O

Laser Diode Power Control

LD-MON1

LD-MON2

180

202

I

Laser Diode Monitor

VREF1

REXT

200

205

I/O

Voltage Reference 1

External Resistor

HP_FILT1

HP_FILT2

HP_FILT3

181

196

186

I

High Pass Filter

DIAG1

DIAG2

DIAG3

DIAG4

4

3

2

1

I/O

Diagnostic 1-4

RF_ENV

5

6

O

RF Envelope

Diagnostic

Signals

CH QUAL MON

Channel Quality Monitor

EF2

EF1

114

112

O

Error Flag (2:1)

TEST_ENBL*

TEST

105

106

I

Test Enable

Test

CONFIDEN TIAL

DS588PP1 - rev 0.4 April 11, 2002

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PRELIMINARY DRAFT

Pinout Information

Table 3: CL-CS3712 Pin Map (Continued)

Type

Name

Pin(s)

I/O

Function

8 , 151, 162,

168, 173, 198,

204

AVDD

–

Analog Power Supply

7, 148, 160,

174, 199, 206,

208

AGND

BVDD

–

Analog Ground

16, 25, 39, 51,

66, 73, 86, 91,

113, 130

Buffer Power Supply

Power

and

Ground

Pins

9, 14, 37, 49,

56, 64, 75, 84,

93, 104, 111,

122, 138, 147

BGND

–

Buffer Ground

CVDD

CGND

26 , 61 , 99, 124

–

Core Power Supply

Core Ground

Apc Ground

28, 59, 97, 128,

143

APC_GND

NC_GND

172

161, 163, 166,

188, 203, 207

Nc Ground

DS588PP1 - rev 0.4 April 11, 2002

CONFIDENTIAL

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Package And Order Information

PRELIMINARY DRAFT

Package And Order Information

Package Information

For complete dimensional and thermal information, see the latest version of the Cirrus

Logic Package Information Guide. The package and PCB design affects the amount of

power that can be dissipated by the package and could limit the maximum transfer rate.

29.60 (1.165)

30.40 (1.197)

27.80 (1.094)

28.20 (1.110)

0.17 (0.007)

0.27 (0.011)

27.80 (1.094)

28.20 (1.110)

29.60 (1.165)

30.40 (1.197)

CL-CS3712

208-Pin LQFP

0.50

(0.0197)

BSC

Pin 1 Indicator

Pin 208

Pin 1

1.35 (0.053)

1.45 (0.057)

1.00 (0.039) BSC

0.45 (0.018)

0.75 (0.030)

0.09 (0.004)

0.20 (0.008)

0° MIN

7° MAX

0.05 (0.002)

0.15 (0.006)

1.40 (0.055)

1.60 (0.063)

Note: Dimensions are in millimeters (inches), and controlling dimension is millimeter.

Drawing above does not reflect exact package pin count.

Before beginning any new design with this device, please contact Cirrus Logic for

the latest package information.

CONFIDEN TIAL

DS588PP1 - rev 0.4 April 11, 2002

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PRELIMINARY DRAFT

Package And Order Information

CL-CS3712

208-Pin EPAD

DS588PP1 - rev 0.4 April 11, 2002

CONFIDENTIAL

20

www.cirrus.com

Package And Order Information

PRELIMINARY DRAFT

LQFP Ordering Information

– 33 QC – A

CL-CS3712

Revision

Cirrus Logic, Inc.

Temperature Range:

C = Commercial

Mass Storage

Part Number

Package Type: LQFP = Q

Data Rate:

Mb/s

Preliminary product information describes products that are in production, but for which full characterization data is not yet available. Cirrus Logic Inc

has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change

without notice. No responsibility is assumed by Cirrus Logic Inc. for the use of this information, nor for infringements of patents or other rights of third

parties. This document is the property of Cirrus Logic Inc. and implies no license under patents, copyrights, or trade secrets. Cirrus Logic and Logo

are trademarks of Cirrus Logic, Inc. Other trademarks in this document belong to their respective companies. Cirrus Logic Inc. products are covered

by the following U.S. patents: 4,293,783; Re. 31,287; 4,763,332; 4,777,635; 4,839,896; 4,931,946; 4,975,828; 4,979,173; 5,032,981; 5,122,783

5,131,015; 5,140,595; 5,157,618; 5,179,292; 5,185,602; 5,220,295; 5,280,488; 5,287,241; 5,291,499; 5,293,159; 5,293,474; 5,297,184; 5,298,915

5,300,835; 5,311,460; 5,313,224; 5,327,128; 5,329,554; 5,351,231; 5,359,631. Additional patents pending.

CONFIDEN TIAL

DS588PP1 - rev 0.4 April 11, 2002

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