CXG1150ER [ETC]
Triple Low Noise Amplifier/Dual Mixer ; 三重低噪声放大器/双通道混频器\n
| 型号： | CXG1150ER |
| 厂家： | 
ETC |
| 描述： | Triple Low Noise Amplifier/Dual Mixer
|
| 文件： | 总11页 (文件大小：146K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CXG1150ER
Triple Low Noise Amplifier/Dual Mixer
Description
24 pin VQFN (Plastic)
The CXG1150ER is a triple low noise amplifier/dual
mixer MMIC, which has made through the Sony's
GaAs J-FET process.
Features
• 3V single power supply operation
• 3-pin control by the on-chip logic circuit
• High gain:
Gp = 16.5dB (LNA typ.)
Gc = 10dB (MIX typ.)
Absolute Maximum Ratings (Ta = 25°C)
• Low noise figure: NF = 1.1 to 1.9dB (LNA typ.)
NF = 4.5dB (MIX typ.)
• Supply voltage
• Input power
VDD
PIN
IDD
4.5
+13
15
V
dBm
mA
• Low LO input power operation: PLO = –15dBm
• 24-pin VQFN small package
• Current consumption
• Operating temperature Topr
• Storage temperature Tstg
–35 to +85 °C
–65 to +150 °C
Applications
800MHz/1.5GHz Japan digital cellular phones (PDC)
Recommended Operating Conditions
• Supply voltage
• Control voltage
VDD
2.7 to 3.3
VCTL (H) 2.4 to 3.3
VCTL (L) 0 to 0.5
V
V
V
Structure
GaAs J-FET MMIC
GaAs MMICs are ESD sensitive devices. Special handling precautions are required.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1 –
E03114-PS
CXG1150ER
Block Diagram and Pin Configuration
12 11 10
9
8
7
13
14
15
16
17
18
6
5
4
3
2
1
CTL1
CTL2
GND
RFout2
RFout1
CTL3
NC
V
DD_LO1
GND
GND
V
DD_LO2
MIXin1
19 20 21 22 23 24
Recommended Evaluation Circuit
LNAin_810MHz LNAin_885MHz
LNAin_1490MHz
5.6nH
27nH
22nH
100pF 1nF
22pF
6.8nH
7
12 11 10
9
8
100pF
3.9nH
LNAout_1500MHz
CTL1
CTL2
13
14
15
16
17
18
6
5
6.8nH
V
DD_LNA
4
NC
1nF
10nH
15nH
V
DD_LO680/755MHz
3
LNAout_800MHz
CLT3
33nH
1nF
DD_LO1360MHz
1nF
100pF
2
V
1
MIXin_810/885MHz
6.8nH
22nH
6.8nH
19 20 21 22 23 24
8.2nH
39nH
MIXin_1490MHz
LOin_680/755MHz
6pF
2.7nH
2.7nH
LOin_1360MHz
120nH
IFout_130MHz
6.8nH
100pF
82nH
1nF
V
DD_MIX
– 2 –
CXG1150ER
Information for the evaluation circuit and components
The IF block is the evaluation circuit matching with 50Ω.
If the inductors with high Q value are not used in the IF block, gain might be dropped about 1dB.
In a recommended evaluation circuit board, the LK1608 series inductors made by "TAIYO YUDEN" are adopted,
and in this board, the components of 1005 size are used except for the inductors in the above IF block.
When the matching of the IF block is changed to high impedance, operation might be unstable when the value
of the capacitance (6pF) nearest from Pin 22 is drastically changed.
Operating Logic
VCTL1 VCTL2 VCTL3 LNA1 (800MHz_D) LNA2 (800MHz_T) LNA3 (1.5GHz)
MIX1 (800MHz)
MIX2 (1.5GHz)
L
L
L
L
H
L
ON
ON
ON
ON
ON
ON
H
—
L
—
—
H
ON
ON
(Blank is OFF)
– 3 –
CXG1150ER
Electrical Characteristics
The normalized values are those when the Sony's recommended evaluation board and components are used.
800MHz_TDMA Band Low Noise Amplifier (Pin 9 Input →Pin 4 Output)
Conditions: Unless otherwise specified, VDD = 2.8V, VCTL (H) = 2.8V, VCTL (L) = 0V, fRF1 = 810MHz, fRF2 = 885MHz
(Ta = 25°C)
Measurement
condition
Item
Symbol
IDD
Path
—
Frequency VCTL1 VCTL2 VCTL3 Min. Typ. Max. Unit
—
—
—
—
—
L
—
L
L
H
L
L
L
L
H
L
H
L
L
L
L
L
L
L
L
L
L
L
—
L
—
—
—
—
—
2.9 4.0
Current
consumption
mA
0
0
0.1
5
When no
signal
Control
current
ICTL
—
H
H
L
L
43 69 µA
86 138
H
L
15.2 17 18.8
–22 –18
14.5 16 17.8
fRF1
—
L
—
L
—
Power gain
Gp
RFIN2 →RFOUT1
RFIN2 →RFOUT1
dB
When a
small signal
fRF2
—
L
—
L
—
—
—
–21 –18
1.6 2.0
1.5 1.9
fRF1
fRF2
Noise figure NF
dB
dBm
dB
L
L
fRF1
L
L
–7 –4
–7 –3
25 30
23 28
—
—
—
—
1
Input IP3
Isolation
IIP3 RFIN2 →RFOUT1
fRF2
L
L
680MHz
755MHz
fRF1
L
L
When a
small signal
ISO
RFOUT1 →RFIN2
RFIN2
L
L
L
L
—
—
—
—
2.4 3.2
1.8 2.2
1.7 2.2
1.8 2.2
fRF2
L
L
Input
reflection
2
VSWR
—
fRF1
L
L
RFOUT1
fRF2
L
L
Besides the above logical condition, when VCTL1 = H, VCTL2 = L, VCTL3 = L/H, the Path "RFIN2 →RFOUT1" turns
on and the electrical characteristics at this time are same as the "ON" condition in the above table.
1
Conversion from the IM3 suppression ratio for two-wave input: fRFoffset = 100kHz, PRF = –30dBm.
2
Input reflection is the value on the edge of IC and at the measurement power –30dBm.
– 4 –
CXG1150ER
800MHz_D Band Low Noise Amplifier (Pin 12 Input →Pin 4 Output)
Conditions: Unless otherwise specified, VDD = 2.8V, VCTL (H) = 2.8V, VCTL (L) = 0V, fRF1 = 810MHz,
fRF4 = 828MHz
(Ta = 25°C)
Measurement
condition
Item
Symbol
Path
—
Frequency VCTL1 VCTL2 VCTL3 Min. Typ. Max. Unit
—
—
L
L
H
—
—
2
0
2.8
0.1
Current
consumption
IDD
mA
—
H
—
When no
signal
Control
current
ICTL
—
L
L
H
—
43 69 µA
—
L
—
L
L
H
L
H
L
L
L
L
L
L
H
—
H
—
H
H
H
H
H
H
15.2 17 18.8
–24 –20
14.5 16.3 18.1
fRF1
—
Gp
dB
Power gain
RFIN1 →RFOUT1
When a
small signal
fRF4
—
L
—
—
—
–23 –20
1.6 2.0
1.5 1.9
fRF1
fRF4
NF
dB
dBm
dB
Noise figure
Input IP3
Isolation
RFIN1 →RFOUT1
RFIN1 →RFOUT1
RFOUT1 →RFIN1
L
fRF1
L
–10 –7
–10 –7
26 30
25 29
—
—
—
—
1
IIP3
ISO
fRF4
L
680MHz
698MHz
L
When a
small signal
L
Gain
difference
from TDMA
band
Same
frequency
∆Gp
—
—
—
—
–0.7
0
+0.7 dB
—
fRF1
fRF4
fRF1
fRF4
L
L
L
L
L
L
L
L
H
H
H
H
—
—
—
—
2.4 3.2
2.1 2.6
2.0 2.4
1.9 2.3
RFIN1
Input
reflection
2
VSWR
—
RFOUT1
1
Conversion from the IM3 suppression ratio for two-wave input: fRFoffset = 100kHz, PRF = –30dBm.
Input reflection is the value on the edge of IC and at the measurement power –30dBm.
2
– 5 –
CXG1150ER
1.5GHz Band Low Noise Amplifier
Conditions: Unless otherwise specified, VDD = 2.8V, VCTL (H) = 2.8V, VCTL (L) = 0V, fRF3 = 1490MHz
(Ta = 25°C)
Measurement
condition
Item
Symbol
IDD
Path
—
Frequency VCTL1 VCTL2 VCTL3 Min. Typ. Max. Unit
Current
consumption
—
—
—
L
H
H
—
L
—
—
2.9
43
mA
µA
4.0
69
When no
signal
Control
current
ICTL
—
Power gain
Gp
RFIN3 →RFOUT2
RFIN3 →RFOUT2
fRF3
fRF3
fRF3
—
—
—
H
H
H
—
—
—
14.5 16
dB
dB
17.8
1.9
—
When a
small signal
Noise figure NF
—
1.5
–4
1
Input IP3
Isolation
IIP3 RFIN3 →RFOUT2
–7
dBm
When a
small signal
ISO
RFOUT2 →RFIN3 1371MHz
—
H
—
17.5 20.5
dB
—
—
RFIN2
fRF3
—
—
H
H
—
—
—
—
2.0
1.8
2.5
2.3
Input
reflection
2
VSWR
RFOUT1
fRF3
1
Conversion from the IM3 suppression ratio for two-wave input: fRFoffset = 100kHz, PRF = –30dBm.
Input reflection is the value on the edge of IC and at the measurement power –30dBm.
2
– 6 –
CXG1150ER
800MHz Band Mixer
Conditions: Unless otherwise specified, VDD = 2.8V, VCTL (H) = 2.8V, VCTL (L) = 0V,
fRF1 = 810MHz, fRF2 = 885MHz, fLO = fRF – 130MHz, PLO = –15dBm
(Ta = 25°C)
RF
frequency
Measurement
condition
Item
Current
Symbol
VCTL1 VCTL2 VCTL3 Min.
Typ. Max. Unit
IDD_LO
—
—
—
—
—
—
—
—
—
—
—
—
—
—
L
L
L
L
L
L
L
L
L
L
L
L
L
L
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1.1
5.0
10
1.4
6.6
11.2
11.0
5.5
6.5
—
—
mA When no signal
consumption
IDD_MIX
fRF1
fRF2
8.8
8.6
—
Gc
dB
Conversion gain
9.8
4
When a small
signal
dB
fRF1
NF
IIP3
Plk
Noise figure
Input IP3
fRF2
—
5
fRF1
1.0
1.0
—
+4.3
+4.3
–26
–22
2.4
2.7
2.0
1.9
3
dBm
fRF2
—
fRF1
–20
–17
3.2
3.6
2.5
2.4
fLO = 680MHz
dBm
LO →RF leak
fRF2
—
fLO = 755MHz
fRF1
—
RF input
reflection
fRF2
—
2
VSWR
—
680MHz
755MHz
—
LO input
reflection
—
1.5GHz Band Mixer
Conditions: Unless otherwise specified, VDD = 2.8V, VCTL (H) = 2.8V, VCTL (L) = 0V,
fRF3 = 1490MHz, LO = 1360MHz/–15dBm
(Ta = 25°C)
RF
frequency
Measurement
condition
Item
Current
Symbol
VCTL1 VCTL2 VCTL3 Min.
Typ. Max. Unit
IDD_LO
IDD_MIX
ICTL
—
—
L
H
H
H
H
H
H
H
—
—
L
—
—
1.1
5.3
43
1.5
7.0
69
—
mA
consumption
When no signal
Control current
Conversion gain
Noise figure
fRF3
fRF3
fRF3
fRF3
fRF3
—
µA
dB
Gc
—
—
—
—
—
—
—
—
9.8
—
11
12.2
5.5
—
When a small
signal
NF
3.9
dB
3
2
IIP3
Plk
–1.0 +1.8
dBm
Input IP3
LO →RF leak
—
—
–21
1.6
–17 dBm
RF input
reflection
fRF3
—
—
H
H
—
—
2.1
—
VSWR
LO input
reflection
1360MHz
—
2.9
3.9
3
Conversion from the IM3 suppression ratio for two-wave input: fRFoffset = 100kHz, PRF = –25dBm
– 7 –
CXG1150ER
Example of Representative Characteristics
1. Frequency characteristics of main items in LNA block
Conditions: VDD = 2.8V, 800MHz_D (Pin 12 input →Pin 4 output): VCTL1 = 0V, VCTL2 = 0V, VCTL3 = 2.8V etc.
800MHz_TDMA (Pin 9 input →Pin 4 output): VCTL2 = 0V, VCTL3 = 0V,
1500MHz (Pin 7 input →Pin 5 output): VCTL2 = 2.8V, VCTL3 = 0V
Gp and NF are those when a small signal is input. The input IP3 is converted from the IM3
suppression ratio for two-wave input: fRFoffset = 100kHz, PRF = –30dBm.
Power gain Gp
Power gain Gp
19
18
17
16
15
14
19
18
17
16
15
14
800MHz_TDMA
1500MHz
800MHz_D
780 800 820 840 860 880 900 920
1440
1460
1460
1460
1480
1500
1520
1520
1520
1540
1540
1540
f [MHz]
f [MHz]
Noise figure NF
Noise figure NF
2.5
2.5
2.0
1.5
1.0
0.5
0
2.0
1.5
1.0
0.5
0
800MHz_D
1500MHz
800MHz_TDMA
780 800 820 840 860 880 900 920
1440
1480
f [MHz]
Input IP3
1500
f [MHz]
Input IP3
–2
–4
–2
800MHz_TDMA
–4
–6
1500MHz
–6
800MHz_D
–8
–8
–10
–10
–12
1440
–12
1480
1500
780 800 820 840 860 880 900 920
f [MHz]
f [MHz]
– 8 –
CXG1150ER
2. Frequency characteristics of main items in MIX block
Conditions: VDD = 2.8V, fLO = fRF – 130MHz, PLO = –15dBm, 800MHz: VCTL2 = 0V, 1500MHz: VCTL2 = 2.8V
Gc and NF are those when a small signal is input. The input IP3 is concerted from the IM3
suppression ratio for two-wave input: fRFoffset = 100kHz, PRF = –25dBm.
Conversion gain Gc
Conversion gain Gc
12
11
10
9
12
11
10
9
1500MHz
800MHz
8
8
7
7
780 800 820 840 860 880 900 920
1440
1460
1460
1460
1480
1500
1520
1520
1520
1540
1540
1540
f [MHz]
f [MHz]
Noise figure NF
Noise figure NF
10
10
8
8
6
4
2
0
6
800MHz
1500MHz
4
2
0
1440
780 800 820 840 860 880 900 920
1480
1500
f [MHz]
f [MHz]
Input IP3
Input IP3
5
4
3
2
1
6
5
4
3
2
1
800MHz
1500MHz
0
1440
1480
1500
780 800 820 840 860 880 900 920
f [MHz]
f [MHz]
– 9 –
CXG1150ER
Recommended Evaluation Board
LNA_800MHz (L) in LNA_800MHz (U) in LNA_1500MHz in
LNA_1500MHz out
LNA_800MHz out
LO_800MHz in
LO_1500MHz in
MIX_800MHz in
MIX_1500MHz in
IFout
SONY
Enlarged Diagram of External Circuit Block
L8
C4
L3
C3
L1 = 2.7nH
C1 = 6pF
C2
L2
C3
C4
L2 = 3.9nH
L3 = 5.6nH
L4 = 6.8nH
L5 = 8.2nH
L6 = 10nH
L7 = 15nH
L8 = 22nH
L9 = 27nH
L10 = 33nH
L11 = 39nH
L12 = 82nH
L13 = 120nH
C2 = 22pF
C3 = 100pF
C4 = 1nF
L9
L4
L4
C4
L7
C4
L6
C3
L10
C4
L4
L11
L8
L5
L1
C1
L4
L1
L4
L13
L12
C3
C4
– 10 –
CXG1150ER
Package Outline
Unit: mm
24PIN VQFN(PLASTIC)
0.9 ± 0.1
0.6 ± 0.1
4.0
3.6
0.05 S
0.7
C
18
13
19
A
12
7
B
4.78
(0.39)
PIN 1 INDEX
24
45˚
1
6
C 0.6
S
x 4
0.4
1.0
S A-B
S A-B
0.2
0.2
C
(0.15)
x 4
C
M S A-B C
0.05
Solder Plating
0.13 ± 0.025
+ 0.09
– 0.03
0.14
TERMINAL SECTION
PACKAGE STRUCTURE
EPOXY RESIN
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
SOLDER PLATING
SONY CODE
VQFN-24P-03
EIAJ CODE
COPPER ALLOY
0.04g
JEDEC CODE
PACKAGE MASS
LEAD SPECIFICATIONS
ITEM
LEAD MATERIAL
SOLDER PLATING
SPEC.
COPPER ALLOY
Sn-Bi Bi:1-4wt%
LEAD TREATMENT THICKNESS 5-18µm
Sony Corporation
– 11 –
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