CXP84220S [ETC]
8-Bit Microcontroller ; 8位微控制器\n
| 型号： | CXP84220S |
| 厂家： | 
ETC |
| 描述： | 8-Bit Microcontroller
|
| 文件： | 总19页 (文件大小：212K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CXP84220/84224
CMOS 8-bit Single Chip Microcomputer
Description
64 pin SDIP (Plastic)
The CXP84220/84224 is a CMOS 8-bit single chip
microcomputer integrating on a single chip an A/D
converter, serial interface, timer/counter, time base
timer, capture timer counter, remote control reception
circuit besides the basic configurations of 8-bit CPU,
ROM, RAM, and l/O port.
The CXP84220/84224 also provides a power-on
reset function and a sleep/stop function that enables
lower power consumption.
Features
• Wide-range instruction system (213 instructions) to cover various types of data
—16-bit arithmetic/multiplication and division/Boolean bit operation instructions
• Minimum instruction cycle
400ns at 10MHz operation
• Incorporated ROM capacity 20K bytes (CXP84220)
24K bytes (CXP84224)
• Incorporated RAM capacity 624 bytes
• Peripheral functions
—A/D converter
8-bit, 8-channel, successive approximation method
(Conversion time of 32µs/10MHz)
—Serial interface
SIO with 8-bit, 8-stage FIFO incorporated for data use
(Auto transfer for 1 to 8 bytes), 1 channel
8-bit standard SIO, 1 channel
—Timer
8-bit timer, 8-bit timer/counter, 19-bit time base timer,
16-bit capture timer/counter
—Remote control reception circuit Incorporated noise elimination circuit
Incorporated 8-bit, 6-stage FIFO for measurement data
14 bits, 1 channel
—PWM output circuit
• Interruption
13 factors, 14 vectors, multi-interruption possible
Sleep/stop
• Standby mode
• Package
64-pin plastic SDIP
• Piggyback/evaluation chip
CXP84200 64-pin ceramic SDIP
Structure
Silicon gate CMOS IC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1 –
E93236B15-PS
CXP84220/84224
P O R T F P O R T G
P O R T A P O R T B P O R T C P O R T D P O R T E
P O R T I
V s s
D D V
R S T
X T A L
E X T A L
P E 3 / N M I
P I 3 / I N T 3
P I 2 / I N T 2
P I 1 / I N T 1
P I 0 / I N T 0
I N T E R R U P T C O N T R O L L E R
R E F A V
A V s s
– 2 –
CXP84220/84224
Pin Assignment (Top View)
1
2
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
NC
PG0
PG1
PG2
PF0
PF1
PF2
PF3
PF4
PF5
PF6
PF7
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
VDD
PI6
3
PI5
4
PI4
5
PI3/INT3
PI2/INT2
PI1/INT1
PI0/INT0
PE5/TO
PE4/PWM
PE3/NMI
PE2/RMC
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PE1/EC1
PE0/EC0
PB7/SO1
PB6/SI1
PB5/SCK1
PB4/SO0
PB3/SI0
PB2/SCK0
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
RST
PB1/CS0
PB0/CINT
PA7/AN7
PA6/AN6
PA5/AN5
PA4/AN4
PA3/AN3
PA2/AN2
PA1/AN1
PA0/AN0
AVREF
XTAL
EXTAL
Vss
AVss
Note) NC (Pin 1) is always connected to VDD.
– 3 –
CXP84220/84224
Pin Description
Pin code
I/O
Description
(Port A)
8-bit l/O port. l/O can be
set in a unit of single bit.
Incorporation of the pull- Analog inputs to A/D converter.
up resistance can be set (8 pins)
through the software in a
unit of 4 bits.
PA0/AN0
to
PA7/AN7
I/O/Analog input
(8 pins)
External capture input to 16-bit timer/counter.
Chip select input for serial interface (CH0).
Serial clock l/O (CH0).
PB0/CINT
PB1/CS0
PB2/SCK0
PB3/SI0
I/O/Input
I/O/Input
I/O/I/O
(Port B)
7-bit l/O port in which
l/O can be set in a unit
of single bit. Also, an
uppermost bit (PB7)
exclusively for output.
Incorporation of pull-up
resistor can be set
through the software in
a unit of 4 bits.
Serial data input (CH0).
I/O/Input
I/O/Output
I/O/I/O
Serial data output (CH0).
PB4/SO0
PB5/SCK1
PB6/SI1
Serial clock l/O (CH1).
Serial data input (CH1).
I/O/Input
Output/Output
(8 pins)
Serial data output (CH1).
PB7/SO1
(Port C)
8-bit l/O port. l/O can be set in a unit of single bit. Capable of driving
12mA sink current. Incorporation of pull-up resistor can be set through
the software in a unit of 4 bits.
PC0 to PC7
PD0 to PD7
I/O
I/O
(8 pins)
(Port D)
8-bit l/O port. l/O can be set in a unit of single bits. Incorporation of pull-
up resistor can be set through the software in a unit of 4 bits.
(8 pins)
Input/Input
Input/Input
Input/Input
Input/Input
Output/Output
PE0/EC0
PE1/EC1
PE2/RMC
PE3/NMI
PE4/PWM
External event inputs for timer/counter.
(2 pins)
(Port E)
Remote control reception circuit input.
6-bit port. Lower 4 bits
are for inputs; upper 2
bits are for outputs. (6
Non-maskable interruption request input.
14-bit PWM output.
pins)
Rectangular wave output for 16-bit
timer/counter.
Output/Output
PE5/TO
(Port F)
8-bit output port. I/O can be set in a unit of single bit. Incorporation of
pull-up resistor can be set through the software in a unit of 4 bits.
(8 pins)
PF0 to PF7
I/O
(Port G)
8-bit I/O port. I/O can be set in a unit of single bit. Incorporation of pull-up
resistor can be set through the software in a unit of 4 bits.
(3 pins)
PG0 to PG2
I/O
– 4 –
CXP84220/84224
Pin code
PI0/INT0
I/O
Description
(Port l)
External
interruption
request inputs.
7-bit output ports. I/O can be set in a unit of single bit.
Incorporation of pull-up resistor can be set through
the software in a unit of 4 bits.
I/O/Input
to
PI3/INT3
I/O
(7 pins)
PI4 to PI6
EXTAL
XTAL
Crystal connectors for system clock oscillation. When the clock is
supplied externally, input to EXTAL; opposite phase clock should be
input to XTAL.
Input
Output
I/O
Low-level active, system reset.
NC. Under normal operating conditions, connect to VDD.
Reference voltage input for A/D converter.
A/D converter GND.
RST
NC
Input
AVREF
AVss
VDD
Positive power supply.
GND
Vss
– 5 –
CXP84220/84224
Input/Output Circuit Formats for Pins
Pin
Circuit format
When reset
Port A
Pull-up resistance
"0" when reset
Port A data
PA0/AN0
to
PA7/AN7
Port A direction
"0" when reset
Input protection
circuit
IP
Hi-Z
Data bus
RD (Port A)
Port A input
selection
Input multiplexer
"0" when reset
A/D converter
Pull-up transistors
approx. 10kΩ
8 pins
Port B
Pull-up resistance
"0" when reset
Port B data
PB0/CINT
PB1/CS0
PB3/SI0
PB6/SI1
Hi-Z
Port B direction
"0" when reset
IP
Schmitt input
Data bus
RD (Port B)
CINT
CS0
SI0
Pull-up transistors
approx. 10kΩ
SI1
4 pins
Port B
Pull-up resistance
"0" when reset
SCK OUT
Output enable
Port B output
selection
PB2/SCK0
PB5/SCK1
"0" when reset
IP
Port B data
Hi-Z
Port B direction
"0" when reset
Schmitt input
Data bus
RD (Port B)
Pull-up transistors
approx. 10kΩ
2 pins
SCK in
– 6 –
CXP84220/84224
Pin
Circuit format
When reset
Port B
Pull-up resistance
SO
Output enable
Port B output
selection
"0" when reset
Port B data
PB4/SO0
IP
Hi-Z
Port B direction
"0" when reset
Data bus
RD (Port B)
Pull-up transistors
approx. 10kΩ
1 pin
Port B
Internal reset signal
SO
Output enable
Port B output
selection
PB7/SO1
High level
"1" when reset
Port B data
Data bus
Pull-up transistors
approx. 200kΩ
1 pin
RD (Port B)
Port C
2
Pull-up resistance
"0" when reset
Port C data
PC0 to PC7
Hi-Z
1
Port C direction
"0" when reset
IP
Data bus
RD (Port C)
1 Large current drive of 2 Pull-up transistors
12mA possible approx. 10kΩ
8 pins
– 7 –
CXP84220/84224
Pin
Circuit format
When reset
Port E
PE0/EC0
PE1/EC1
PE2/RMC
PE3/NMI
Schmitt input
EC0
EC1
RMC/NMI
IP
Hi-Z
Data bus
4 pins
RD (Port E)
Port E
PWM
Port E output
selection
PE4/PWM
1 pin
High level
"0" when reset
Port E data
"1" when reset
RD (Port E)
Data bus
Port E
Output enable
TO
Port E output
selection
Port E output
selection
PE5/TO
High level
"00" when reset
Port E output
selection
"0" when reset
Port E data
"1" when reset
Data bus
1 pin
RD (Pot E)
Port D
Pull-up resistance
Port F
Port G
Port I
"0" when reset
Port data
PD0 to PD7
PF0 to PF7
PG0 to PG2
PI4 to PI6
Hi-Z
Port direction
"0" when reset
IP
Data bus
RD
22 pins
Pull-up transistors
approx. 10kΩ
– 8 –
CXP84220/84224
Pin
Circuit format
When reset
Port I
Pull-up resistance
"0" when reset
Port data
PI0 to PI3
Port direction
"0" when reset
IP
Hi-Z
Data bus
RD
INT0
INT1
INT2
INT3
Pull-up transistors
approx. 10kΩ
4 pins
• Diagram shows
circuit composition
during oscillation
EXTAL
XTAL
EXTAL
IP
IP
Oscillation
• Feedback resistor is
removed during stop.
2 pins
XTAL
Pull-up resistor
Mask option
OP
RST
1 pin
Low level
IP
Schmitt input
Power-on reset function
(Mask option)
– 9 –
CXP84220/84224
Absolute Maximum Ratings
(VSS = 0V reference)
Item
Symbol
VDD
Rating
–0.3 to +7.0
–0.3 to +0.3
–0.3 to +7.0
–0.3 to +7.0
–5
Unit
V
Remarks
Supply voltage
V
AVSS
VIN
1
1
V
Input voltage
V
Output voltage
VOUT
IOH
mA
mA
mA
mA
mA
°C
°C
mW
High level output current
Output per pin
Total for all output pins
–50
High level total output current ∑IOH
15
IOL
Value per pin, excluding large current outputs
Value per pin 2 for large current outputs
Total for all output pins
Low level output current
20
IOLC
100
Low level total output current ∑IOL
–20 to +75
–55 to +150
1000
Operating temperature
Storage temperature
Topr
Tstg
Allowable power dissipation PD
1
VIN and VOUT must not exceed VDD + 0.3V.
2
The large current drive transistor is the N-ch transistor of Port C (PC).
Note) Usage exceeding absolute maximum ratings may permanently impair the LSl. Normal operation should
be conducted under the recommended operating conditions. Exceeding these conditions may adversely
affect the reliability of the LSI.
Recommended Operating Conditions
(VSS = 0V reference)
Remarks
Item
Symbol
Min.
4.5
Max.
5.5
Unit
V
High-speed mode
guaranteed operation range
1
Supply voltage
VDD
Low-speed mode
guaranteed operation range
3.5
5.5
1
2.5
5.5
VDD
VDD
Guaranteed data hold range during stop
2
VIH
0.7VDD
0.8VDD
V
V
3
High level input voltage
VIHS
VIHEX
VIL
Hysteresis input
4
VDD – 0.4 VDD + 0.3
EXTAL
V
2
0
0
0.3VDD
0.2VDD
0.4
V
3
Low level input voltage
Operating temperature
VILS
VILEX
Topr
Hysteresis input
V
4
–0.3
–20
EXTAL
V
+75
°C
1
High-speed mode is 1/2 frequency demultiplication clock selection; Iow-speed mode is 1/16 frequency
demultiplication clock selection.
2
3
4
Value for each pin of normal input ports (PA, PB3, PB4, PB6, PC, PD, PF, PG, PI4 to PI6).
Value of the following pins: RST, CINT, CS0, SCK0, SCK1, EC0, EC1, RMC, NMI, INT0, INT1, INT2, INT3.
Specifies only during external clock input.
– 10 –
CXP84220/84224
Electrical Characteristics
DC Characteristics
(Ta = –20 to +75°C, Vss = 0V reference)
Item
Symbol
Pins
Conditions
VDD = 4.5V, IOH = –0.5mA
VDD = 4.5V, IOH = –1.2mA
VDD = 4.5V, IOL = 1.8mA
VDD = 4.5V, IOL = 3.6mA
VDD = 4.5V, IOL = 12.0mA
VDD = 5.5V, VIH = 5.5V
VDD = 5.5V, VIL = 0.4V
Min.
4.0
Typ. Max. Unit
V
V
High level
output voltage
VOH
PA to PD,
PE4, PE5,
PF, PG, PI
3.5
0.4
0.6
V
V
Low level
output voltage
VOL
1.5
PC
V
IIHE
IILE
IILR
0.5
40
µA
µA
µA
mA
µA
EXTAL
–0.5
–1.5
–40
–400
–2.0
1
Input current
RST
VDD = 5.5V
VIL = 0.4V
2
PA to PD ,
PF, PG, PI
IIL
2
–10
VDD = 4.5V, VIL = 4.0V
I/O leakage
current
PE0 to PE3,
RST
VDD = 5.5V
VI = 0, 5.5V
±10
40
IIZ
µA
1
High-speed mode operation
(1/2 frequency demultiplier clock)
mA
18
IDD1
VDD = 5.5V, 10MHz crystal oscillation
(C1 = C2 = 15pF)
Sleep mode
Supply
current
8
mA
µA
1.1
IDDS1
IDDS3
VDD
3
VDD = 5.5V, 10MHz crystal oscillation
(C1 = C2 = 15pF)
Stop mode
10
VDD = 5.5V, termination of 10MHz
crystal oscillation
Pins other
than PB7,
PE4, PE5,
AVREF,
Clock 1MHz
0V for all pins excluding measured pins
Input
capacity
CIN
20
pF
10
AVss,
VDD, VSS
1
RST specifies the input current when pull-up resistance has been selected; Ieakage current wnen no
resistance has been selected.
2
3
Pins PA to PD, and PF, PG, Pl specify the input current when pull-up resistance has been selected;
leakage current when no resistance has been selected. (Excludes output PB7)
When all pins are open.
– 11 –
CXP84220/84224
AC Characteristics
(1) Clook timing
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Item
Symbol
Pins
Conditions
Min.
1
Typ.
Max. Unit
XTAL
EXTAL
Fig. 1, Fig. 2
System clock frequency
fC
MHz
ns
10
200
20
Fig. 1, Fig. 2
External clock drive
t
t
XL
System clock input pulse width
EXTAL
EXTAL
37.5
XH
Fig. 1, Fig. 2
External clock drive
System clock input rise time,
fall time
t
t
CR
CF
ns
Event count input clock pulse
width
t
t
EH
EL
EC0
EC1
1
Fig. 3
Fig. 3
ns
tsys + 50
Event count input clock rise time,
fall time
t
t
ER
EF
EC0
EC1
ms
1
tsys indicates the three values below according to the upper two bits (CPU clock selection) of the clock
control register (address: 00FEH).
tsys [ns] = 2000/fc (upper two bits = “00”), 4000/fc (upper two bits = “01”), 16000/fc (upper two bits = “11”)
1/fc
VDD – 0.4V
EXTAL
0.4V
tXH
tCF
tXL
tCR
Fig. 1. Clock timing
Crystal oscillation
Ceramic oscillation
External clock
EXTAL
XTAL
EXTAL
XTAL
C1
C2
74HC04
Fig. 2. Clock applied condition
0.8VDD
0.2VDD
EC0
EC1
tEH
tEF
tEL
tER
Fig. 3. Event count clock timing
– 12 –
CXP84220/84224
(2) Serial transfer (CH0)
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Item
Symbol
Pin
Condition
Min.
Max.
Unit
ns
Chip select transfer mode
(SCK0 = output mode)
CS0 ↓ → SCK0
tDCSK
tDCSKF
t
DCSO
tsys + 200
SCK0
delay time
Chip select transfer mode
(SCK0 = output mode)
CS0 ↑ → SCK0
float delay time
ns
ns
ns
tsys + 200
tsys + 200
tsys + 200
SCK0
SO0
CS0 ↓ → SO0
Chip select transfer mode
Chip select transfer mode
delay time
CS0 ↑ → SO0
float delay time
t
DCSOF
WHCS
SO0
CS0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
tsys + 200
2tsys + 200
16000/fc
tsys + 100
8000/fc – 50
100
Chip select transfer mode
Input mode
CS0 High level width
tKCY
SCK0 cycle time
SCK0
SCK0
SI0
Output mode
Input mode
t
KH
KL
SCK0 High, Low level width
t
Output mode
SCK0 input mode
SCK0 output mode
SCK0 input mode
SCK0 output mode
SCK0 input mode
SCK0 output mode
SI0 input setup time
(for SCK0 ↑ )
t
t
t
SIK
200
tsys + 200
100
SI0 input hold time
(for SCK0 ↑ )
KSI
SI0
tsys + 200
100
SCK0 ↓ → SO0
KSO
SO0
delay time
Note 1) tsys indicates the three values below according to the upper two bits (CPU clock selection) of the
clock control register (address: 00FEH).
tsys [ns] = 2000/fc (upper two bits = “00”), 4000/fc (upper two bits = “01”), 16000/fc (upper two bits =
“11”)
Note 2) The load condition for the SCK0 output mode, SO0 output delay time is 50pF + 1TTL.
– 13 –
CXP84220/84224
tWHCS
CS0
0.8VDD
0.2VDD
tKCY
tDCSKF
tDCSK
tKL
tKH
0.8VDD
0.8VDD
0.2VDD
SCK0
tKSI
tSIK
0.8VDD
SI0
Input data
0.2VDD
tDCSO
tKSO
tDCSOF
0.8VDD
0.2VDD
SO0
Output data
Fig. 4. Serial transfer CH0 timing
– 14 –
CXP84220/84224
Serial transfer (CH1)
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Item
Symbol Pin
Condition
Input mode
Min.
1000
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCK1 cycle time
t
KCY
SCK1
SCK1
SI1
16000/fc
400
Output mode
Input mode
t
t
KH
KL
SCK1 High, Low level width
8000/fc – 50
100
Output mode
SCK1 input mode
SCK1 output mode
SCK1 input mode
SCK1 output mode
SCK1 input mode
SCK1 output mode
SI1 input setup time
(for SCK1 ↑)
t
t
t
SIK
200
200
SI1 input hold time
(for SCK1 ↑)
KSI
SI1
100
200
100
SCK1 ↓ → SO1 delay time
KSO
SO1
Note) The load condition for the SCK1 output mode, SO1 output delay time is 50pF + 1TTL.
tKCY
tKL
tKH
SCK1
0.8VDD
0.2VDD
tSIK
tKSI
0.8VDD
0.2VDD
Input data
SI1
tKSO
0.8VDD
SO1
Output data
0.2VDD
Fig. 5. Serial transfer CH1 timing
– 15 –
CXP84220/84224
(3) A/D converter characteristics
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, AVREF = 4.0 to AVDD, Vss = AVSS = 0V reference)
Min.
Pin
Condition
Typ.
Max.
8
Item
Resolution
Symbol
Unit
Bits
LSB
±3
Linearity error
Ta = 25°C
VDD = 5.0V
VSS = AVSS = 0V
Zero transition
voltage
1
VZT
–10
70
150
mV
mV
Full-scale transition
voltage
2
VFT
4930
5050
5120
3
Conversion time
Sampling time
t
CONV
SAMP
160/fADC
12/fADC
µs
µs
3
t
Reference input
voltage
VREF
AVREF
VDD – 0.5
VDD
V
Analog input voltage VIAN
AN0 to AN7
AVREF
0
AVREF
V
IREF
0.6
1.0
mA
Operation mode
AVREF current
Sleep mode
Stop mode
IREFS
10
µA
FFH
FEH
1
VZT: Value at which the digital conversion value changes
from 00H to 01H and vice versa.
2
3
VFT: Value at which the digital conversion value changes
from FEH to FFH and vice versa.
fADC indicates the below values due to ADC operation
clock selection.
Linearity error
During PS2 selection, fADC = fc/2
01H
00H
During PS1 selection, fADC = fc
VZT
VFT
Analog input
Fig. 6. Definition of A/D converter terms
– 16 –
CXP84220/84224
(4) Interruption, reset input
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Item
Symbol
Pin
INT0
Condition Min.
Max. Unit
INT1
INT2
INT3
NMI
External interruption
High, Low level width
t
t
IH
IL
1
µs
µs
8/fc
Reset input Low level width
t
RSL
RST
tIH
tIL
0.8VDD
INT0
0.2VDD
INT1
tIL
tIH
INT2
INT3
NMI
(NMI specifies only for
the falling edge)
Fig. 7. Interruption input timing
tRSL
RST
0.2VDD
Fig. 8. RST input timing
(5) Power-on reset
Power-on reset
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, VSS = 0V reference)
Item
Symbol Pin
Condition
Min.
0.05
1
Max. Unit
ms
50
Power-on reset
tR
Power supply rising time
Power supply cut-off time
VDD
ms
Repetitive power-on reset
tOFF
Specifies only when power-on reset function is selected.
4.5V
VDD
0.2V
0.2V
tR
tOFF
The power supply should be rise smoothly.
Fig. 9. Power-on reset
– 17 –
CXP84220/84224
Appendix
(i) Main clock
EXTAL
(ii) Main clock
EXTAL
XTAL
Rd
XTAL
Rd
C1
C2
C1 C2
Fig. 10. SPC700 Series recommended oscillation circuit
Manufacturer
Model
fc (MHz)
4.19
C1 (pF)
Rd (Ω)
Circuit example
C2 (pF)
CSA4.19MG
CSA8.00MTZ
CSA10.0MTZ
CST4.19MGW
CST8.00MTW
CST10.0MTW
8.00
(i)
10.00
MURATA MFG
CO., LTD.
30
0
30
4.19
8.00
(ii)
10.00
4.19
RIVER
ELETEC
CORPORATIO
N
8.00
12
0
0
HC-49/U03
12
10.00
4.19
(i)
27
20
27
20
8.00
HC-49/U (-S)
KINSEKI LTD.
10.00
Those marked with an asterisk ( ) signify types with built-in ground capacitance (C1, C2).
Mask option table
Item
Content
Non-existent
Non-existent
Reset pin pull-up resistance
Power-on reset circuit
Existent
Existent
– 18 –
CXP84220/84224
Package Outline
Unit: mm
64PIN SDIP (PLASTIC)
+ 0.4
57.6 – 0.1
33
64
0˚ to 15˚
1
32
1.778
0.5 ± 0.1
0.9 ± 0.15
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE MASS
EPOXY RESIN
SONY CODE
EIAJ CODE
SOLDER PLATING
SDIP-64P-01
P-SDIP64-17.1x57.6-1.778
42/COPPER ALLOY
8.6g
JEDEC CODE
64PIN SDIP (PLASTIC)
+ 0.4
57.6 – 0.1
33
64
0˚ to 15˚
1
32
1.778
0.5 ± 0.1
0.9 ± 0.15
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE MASS
EPOXY RESIN
SONY CODE
EIAJ CODE
SOLDER PLATING
SDIP-64P-01
P-SDIP64-17.1x57.6-1.778
42/COPPER ALLOY
8.6g
JEDEC CODE
LEAD SPECIFICATIONS
ITEM
LEAD MATERIAL
LEAD TREATMENT
SPEC.
ALLOY 42
Sn-Bi 2.5%
LEAD TREATMENT THICKNESS 5-18µm
Sony Corporation
– 19 –
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