CY24712 [ETC]
Clocks and Buffers ; 时钟和缓冲器\n
| 型号： | CY24712 |
| 厂家： | 
ETC |
| 描述： | Clocks and Buffers
|
| 文件： | 总5页 (文件大小：91K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY24712
MediaClock™
Set-top Box Clock Generator with VCXO
Features
• Integrated phase-locked loop (PLL)
• Low-jitter, high-accuracy outputs
• VCXO with analog adjust
• 3.3V Operation
Benefits
High-performance PLL tailored for Set Top Box applications
Meets critical timing requirements in complex system designs
Large ±150-ppm range, better linearity
Meet industry standard voltage platforms
• 8-pin SOIC
Industry standard packaging saves on board space
Part Number Outputs
Input Frequency Range
Output Frequencies
CY24712
3
27-MHz pullable crystal input
per Cypress specification
11.0592 MHz, 13.5 MHz, 27 MHz
Logic Block Diagram
CLK_C 27 MHz
27 XIN
XOUT
OUTPUT
OSC
Q
Φ
CLK_A 11.0592 MHz
DIVIDERS
VCO
P
VCXO
PLL
/2
CLK_B 13.5 MHz
VSS
VDD
Pin Configuration
CY24712
8-pin SOIC
1
2
3
4
XOUT
XIN
8
7
6
5
CLK_C
CLK_A
VDD
VCXO
VSS
CLK_B
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-07319 Rev. *B
Revised December 14, 2002
CY24712
Summary
Pin Name
XIN
Pin Number
Pin Description
1
Reference Crystal Input
3.3V Voltage Supply
Input Analog Control for VCXO
Ground
VDD
2
3
4
5
6
7
8
VCXO
VSS
CLK_B
CLK_A
CLK_C
XOUT[1]
13.5-MHz Clock Output
11.0592-MHz Clock Output
27-MHz Clock Output
Reference Crystal Output
Pullable Crystal Specifications
Parameter
Description
Min.
Typ.
Max.
Unit
CRYSTALLoad
C0/C1
ESR
Load Capacitance
14
pF
240
35
Ω
To
Operating Temperature
Initial Accuracy
0
70
°C
Accinit
±30
±80
ppm
ppm
Stability
Temperature plus Aging Stability
Absolute Maximum Conditions
Parameter Description
VDD
Min.
Max.
Unit
V
Supply Voltage
–0.5
–65
7.0
125
TS
TJ
Storage Temperature[2]
Junction Temperature
Digital Inputs
°C
°C
V
125
VSS – 0.3
VSS – 0.3
VDD + 0.3
VDD + 0.3
2000
Digital Outputs referred to VDD
Electrostatic Discharge
Analog Input
V
V
–0.5
7.0
V
Recommended Operating Conditions
Parameter Description
VDD
Min.
3.135
0
Typ.
Max.
Unit
V
Operating Voltage
3.3
3.465
70
TA
Ambient Temperature
Max. Load Capacitance
Reference Frequency
°C
CLOAD
fREF
15
pF
27
MHz
Power-up time for all VDD's to
reach minimum specified voltage
(power ramps must be monotonic)
tPU
0.05
500
ms
DC Electrical Characteristics
Parameter
IOH
Description
Conditions
Min.
12
Typ.
24
Max.
Unit
mA
mA
pF
Output High Current
Output Low Current
Input Capacitance
Input Leakage Current
VCXO pullability range[3]
VCXO input range
Supply Current
VOH = VDD – 0.5, VDD = 3.3V
IOL
VOL = 0.5, VDD = 3.3V
12
24
CIN
7
IIZ
5
µA
f∆XO
±150
0
ppm
V
VVCXO
IVDD
VDD
36
mA
Document #: 38-07319 Rev. *B
Page 2 of 5
CY24712
DC Electrical Characteristics
Parameter
Description
Conditions
Min.
Typ.
Max.
Unit
Notes:
1. Float XOUT if XIN is externally driven.
2. Rated for 10 years.
3. Must meet pullable crystal specifications.
AC Electrical Characteristics (VDD = 3.3V)
Parameter[4]
Description
Output Duty Cycle
Rising Edge Rate
Conditions
Min.
Typ.
50
Max.
Unit
%
DC
Duty Cycle is defined in Figure 1 50% of VDD
45
55
ER0
Output Clock Edge Rate, Measured from 20%
0.8
1.4
V/ns
to 80% of VDD, CLOAD = 15 pF Figure 2.
EF1
Falling Edge Rate
Output Clock Edge Rate, Measured from 80%
to 20% of VDD, CLOAD = 15 pF Figure 2.
0.8
1.4
V/ns
t9
Clock Jitter
Peak-Peak period jitter
300
350
3
ps
t10
PLL Lock Time
ms
Note:
4. Not 100% tested.
Test Circuit
V
DD
CLK out
LOAD
0.1 µF
C
OUTPUTS
GND
t3
t4
t1
t2
80%
50%
50%
CLK
CLK
20%
igure 2. Rise and Fall Time Definitions: ER = 0.6 x VDD/t3,
EF = 0.6 x VDD/t4
Figure 1. Duty Cycle Definition; DC = t2/t1
Ordering Information
Ordering Code
Package Name
Package Type
Operating Range
Operating Voltage
CY24712SC
S8
8-pin SOIC
Commercial
3.3V
Document #: 38-07319 Rev. *B
Page 3 of 5
CY24712
Package Diagram
8-pin (150-mil) SOIC S8
51-85066-A
All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-07319 Rev. *B
Page 4 of 5
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY24712
Document Title: CY24712 MediaClock™ Set-top Box Clock Generator with VCXO
Document Number: 38-07319
Issue
Date
Orig. of
Change
REV.
**
ECN No.
111555
113937
121887
Description of Change
02/29/02
05/02/02
12/14/02
CKN
CKN
RBI
New Data Sheet
*A
Removed Kony from the Pullable Crystal Specification table, p. 2
Power up requirements added to Operating Conditions Information
*B
Document #: 38-07319 Rev. *B
Page 5 of 5
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