CY26210 [ETC]
Clocks and Buffers ; 时钟和缓冲器\n
| 型号： | CY26210 |
| 厂家： | 
ETC |
| 描述： | Clocks and Buffers
|
| 文件： | 总5页 (文件大小：108K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY26210
PRELIMINARY
PacketClock™
T1/E1 to 19.44 MHz Clock Translator
Features
• Integrated phase-locked loop
• Low jitter, high accuracy outputs
• 3.3V Operation
Benefits
High performance PLL tailored for T1/E1 clock generation
Meets critical timing requirements in complex system designs
Enables application compatibility
Part Number Outputs
Input Frequency Range
1.544 or 2.048 MHz
Output Frequencies
CY26210
1
19.44 MHz
Logic Block Diagram
Q
Φ
Fref
VCO
OUTPUT
DIVIDERS
CLK1
P
PLL
FS
AVSS
AVDD
VSS
VDD
Pin Configuration
CY26210
8-pin SOIC
Table 1. CY26210 Frequency Select Option
Frequency Select
Input
1.544
2.048
CLK1
19.44
19.44
Unit
MHz
MHz
NC
1
2
3
4
8
7
6
5
Fref
0
1
VSS
AVDD
FS
CLK1
AVSS
VDD
Cypress Semiconductor Corporation
Document #: 38-07446 Rev. *A
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Revised December 14, 2002
CY26210
Pin Description
Name
Pin Number Description
Fref
1
2
3
4
5
6
7
8
1.544 MHz/2.048 MHz Reference Input
AVDD
FS
Analog Voltage Supply
Frequency Select – See Table 1
Analog Ground
AVSS
VDD
CLK1
VSS
NC
Voltage Supply
19.44 MHz Clock Output
Ground
Leave floating No Connect
Absolute Maximum Conditions
Parameter
VDD
Description
Min.
–0.5
–65
Max.
7.0
Unit
V
Supply Voltage
TS
TJ
Storage Temperature[1]
Junction Temperature
Digital Inputs
125
°C
°C
V
125
VSS – 0.3
VSS – 0.3
2000
VDD + 0.3
VDD + 0.3
Digital Outputs referred to VDD
Electro-Static Discharge
V
V
Recommended Operating Conditions
Parameter
VDD/AVDD
Description
Operating Voltage
Min.
3.135
0
Typ.
Max.
Unit
V
3.3
3.465
70
TA
Ambient Temperature (Commercial)
Max. Load Capacitance
°C
CLOAD
fREF
15
pF
Reference Frequency
1.544
0.05
2.048
MHz
Power-up time for all VDD's to reach
minimum specified voltage (power
ramps must be monotonic)
tPU
500
ms
DC Electrical Specifications (Commercial)
Parameter
Name
Output High Current
Output Low Current
Input Capacitance
Input Current
Description
Min.
Typ.
Max.
Unit
mA
mA
pF
µA
mA
V
IOH
IOL
CIN
IIZ
VOH = VDD – 0.5, VDD = 3.3V
12
12
24
24
VOL = 0.5, VDD = 3.3V
7
20
5
IDD
VIH
VIL
Supply Current
Sum of Core and Output Current
CMOS levels, 70% of VDD
CMOS levels, 30% of VDD
Input High Voltage
Input Low Voltage
0.7VDD
0.3VDD
V
AC Electrical Specifications (V = 3.3V)
DD
Parameter[2]
Name
Description
Min
45
Typ
50
Max
Unit
%
DC
Output Duty Cycle
Rising Edge Rate
Duty Cycle is defined in Figure 1, 50% of VDD
55
ERO
Output Clock Edge Rate, Measured from 20%
0.8
1.4
V/ns
to 80% of VDD, CLOAD = 15pF See Figure 2.
EFO
Falling Edge Rate
Output Clock Edge Rate, Measured from 80%
to 20% of VDD, CLOAD = 15pF See Figure 2.
0.8
1.4
V/ns
t9
Clock Jitter
Peak to Peak Period Jitter
200
ps
ms
t10
PLL Lock Time
3
Document #: 38-07446 Rev. *A
Page 2 of 5
CY26210
AC Electrical Specifications (V = 3.3V)
DD
Parameter[2]
Name
Description
Min
Typ
Max
Unit
Note:
1. Rated for 10 years
2. Not 100% tested
Test and Measurement Set-up
VDD
CLK out
CLOAD
0.1 µF
OUTPUTS
GND
Voltage and Timing Definitions
t1
t2
50%
50%
CLK
Figure 1. Duty Cycle Definition; DC = t2/t1
t3
t4
80%
20%
CLK
Figure 2. Rise and Fall Time Definitions: ER = 0.6 x VDD / t3, EF = 0.6 x VDD / t4
Ordering Information
Ordering Code
CY26210SC
Package Name
Package Type
Operating Range
Commercial
Operating Voltage
S8
S8
8-Pin SOIC
3.3V
3.3V
CY26210SCT
8-Pin SOIC - Tape and Reel
Commercial
Document #: 38-07446 Rev. *A
Page 3 of 5
PRELIMINARY
CY26210
Package Drawing and Dimensions
8-Lead (150-Mil) SOIC S8
51-85066-A
Document #: 38-07446 Rev. *A
Page 4 of 5
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY26210
Document History Page
Document Title: CY26210 PacketClock™ T1/E1 to 19.44 MHz Clock Translator
Document Number: 38-07446
Issue
Date
Orig. of
REV.
**
ECN NO.
116739
Change Description of Change
09/12/02
12/14/02
CKN
RBI
New data sheet
Power up requirements added to Operating Conditions Information
*A
121904
Document #: 38-07446 Rev. *A
Page 5 of 5
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