CY2LL8422 [ETC]
Clocks and Buffers ; 时钟和缓冲器\n
| 型号： | CY2LL8422 |
| 厂家： | 
ETC |
| 描述： | Clocks and Buffers
|
| 文件： | 总12页 (文件大小：198K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
8422
COMLINK™ SERIES
CY2LL8422
High Drive Dual 2-Channel LVDS Repeater/Mux
Features
Description
• ANSI TIA/EIA-644-1995 Compliant
• Designed for Data rates to 650 MBps = (325 MHz)
• Dual 2x2
The Cypress CY2LL8422 are differential line drivers and re-
ceivers that utilize Low Voltage Signaling or LVDS, to achieve
signaling rates of 650 MBps. The receiver outputs can be
switched to either or both drivers through the multiplexer con-
trol signals S2/S3. This provides flexibility in application for
either a splitter or router configuration with a single device.
— Low Voltage Differential Signaling with output volt-
ages of ±350 mV into 100-ohm load version (Std)
• Single 3.3V supply
• Accepts ±35 mV differential inputs
The Cypress CY2LL8422 are configured as dual 2-channel
repeaters/Muxes.
• Output drivers are high impedance when disabled or
The LVDS standard provides a minimum differential output
voltage of 247 mV into a 100-ohm load and receipt of as little
as 100 mV signals with up to 1V of DC offset between trans-
mitter and receiver.
when VDD <1.5V
• 28-pin SSOP/TSSOP packages
• Industrial version available
A doubly terminated Bus LVDS line enables multipoint con-
figurations.
Designed for both point-to-point based-band multipoint data
transmission over controlled impedance lines.
Block Diagram
Pin Configuration
1DE
4
2
1
27
26
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDD
1Y
1B
1A
1A
1B
1
2
3
4
5
6
7
8
1Y
1Z
1Z
2DE
2Z
S0
6
7
2A
2B
23
24
2Y
2Z
1DE
S1
2Y
25
2A
2B
GND
VDD
2DE
3
5
3A
S0S1
3Y
9
3B
3DE
3Z
4DE
4Y
10
11
12
13
14
S2
3DE
S3
11
8
9
20
19
3A
3Y
3Z
4Z
3B
4A
GND
4B
13
14
17
16
4A
4B
4Y
4Z
28pin TSSOP/SSOP
18
4DE
10 12
S2S3
Cypress Semiconductor Corporation
Document #: 38-07411 Rev. **
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Revised July 3, 2002
CY2LL8422
Pin Description
Pin Number
Pin Name
GND
1A, 1B
S0
Description
15, 22
2, 1
3
Ground
Differential Input Channel 1
Function Select Channel 1&2
Data Enable Channel 1
4
1DE
5
S1
Function Select Channel 1& 2
Differential Input Channel 2
Power Supply
6, 7
21, 28
8, 9
10
2A, 2B
VDD
3A, 3B
S2
Differential Input Channel 3
Function Select Channel 3 & 4
Data Enable Channel 3
11
3DE
12
S3
Function Select Channel 3 & 4
Differential Input Channel 4
Differential Output Channel 4
Data Enable Channel 4
13, 14
17, 16
18
4A, 4B
4Y, 4Z
4DE
20, 19
23, 24
25
3Y, 3Z
2Y, 2Z
2DE
Differential Output Channel 3
Differential Output Channel 2
Data Enable Channel 2
27, 26
1Y, 1Z
Differential Output Channel 1
Table 1. Mux Function Table
Input
Output
Function
S0
0
S1
1Y/1Z
2Y/2Z
1A/1B
2A/2B
2A/2B
1A/1B
0
0
1
1
1A/1B
2A/2B
1A/1B
2A/2B
Splitter A
Splitter B
1
0
Pass Thru Router
Cross Point Router
1
S2
0
S3
0
3Y/3Z
3A/3B
4A/4B
3A/3B
4A/4B
4Y/4Z
3A/3B
4A/4B
4A/4B
3A/3B
Splitter A
Splitter B
1
0
0
1
Pass Thru Router
Cross Point Router
1
1
Document #: 38-07411 Rev. **
Page 2 of 12
CY2LL8422
Table 2. Absolute Maximum Rating Over Operating Free-Air Temperature[1]
Supply Voltage Range, VDD(1)
Voltage Range (DE,S0,S1)
Input Voltage Range, VIN (A or B)
ESD (All pins)
–0.5V to 4V
–0.5V to 6.0V
–0.5V to VDD + 0.5V
Class 3, A: 2KV, B:500V
–65°C to 150°C
Storage Temperature Range
Table 3. Recommended Operating Conditions
Parameter
VDD
Description
Min.
Typ.
Max.
Unit
Supply Voltage
3
3.3
3.6
V
VIH
High Level Input Voltage
(S0,S1,1DE,2DE)
(S2,S3,3DE,4DE)
2
VIL
Low Level Input Voltage
(S0,S1,1DE,2DE)
(S2,S3,3DE,4DE)
0.8
VID
VIC
TA
Magnitude of Differential Input Voltage
Common Mode Input Voltage
0.1
VID/2
–40
0
0.6
2.4 – (VID/2)
Operating Free Air Temperature
Industrial
85
70
°C
Commercial
Table 4. Receiver Electrical Characteristics Over Recommended Operating Conditions
Parameter
VITH+
VITH-
II
Description
Condition
VCM = 1.2V
Min.
Typ. Max.
Unit
mV
mV
µA
Positive-going Differential Input Voltage Threshold
Negative-going Differential Input Voltage Threshold
Input Current (A Inputs) [Fail Safe]
100
VCM = 1.2V
VI = 0V
–100
–0.5
–10
–10
10
VI = 2.4V
VI = 0.8V
VI = 2.4V
VDD = 0V
µA
II
Input Current (B Inputs) [Fail Safe]
Power Off Current (A or B Inputs)
0.5
µA
10
µA
II (Off)
0.1
10
µA
Note:
1. Stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. This is intended to be a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect reliability.
Document #: 38-07411 Rev. **
Page 3 of 12
CY2LL8422
Table 5. Receiver Electrical Characteristics Over Recommended Operating Conditions
Parameter
VOD
Description
Condition
Min. Typ. Max.
Unit
mV
mV
Differential Output Voltage Swing
RL = 100 ohm See Figure 6
247
340
454
50
~VOD
Change in differential Output Voltage
Swing between Logic States
–50
VOC(SS)
Steady State Common-mode output
voltage
See Figure 6
1.125
1.375
50
V
~VOC(SS)
Change in Steady State Com-
mon-mode output between Logic
States
–50
3
mV
VOC(PP)
Peak to Peak Common-mode output
voltage
150
mV
ICC
Supply Current
No load
20
28
50
24
mA
mA
mA
µA
RL = 100 ohm @3.3V, FIN = 75 MHz
Both Channels Disabled
16
15
IIH
High-Level Input Current
Low-Level Input Current
s0,s1,S2, S3,
1de,2de,3DE,
4DE
VIH = 5V
IIL
s0,s1,S2, S3, VIL = 0.8V
1de,2de,3DE,
4DE
5
µA
IOS
IOZ
Short Circuit Current
VOY or V0Z = 0V
20
20
1
mA
VOD = 0V
High Impedance Output Current
VOD = 600 mV
VO= 0V or VDD
VDD = 0V, VO = 3.6V
0.1
0.1
0.1
3
µA
1
IO(off)
Cin
Power-Off Output Current
Input Capacitance
10
µA
1A, 1B, 2A, 2B, 3A, 3B,
4A, 4B
pF
Control Input Capacitance
s0,s1,S2, S3,
6
pF
1de,2de,3DE, 4DE
Document #: 38-07411 Rev. **
Page 4 of 12
CY2LL8422
Table 6. Differential Receiver to Driver Switching Characteristics Over Recommended Operating Conditions[2]
Parameter
TPLH
Description
Condition
Min. Typ.[3]
Max. Unit
Differential Propagation delay, low to high
Differential Propagation delay, high to low
CL = 10 pF
4
4
6
6
ns
ns
ns
ps
ps
ns
ns
ns
ns
ps
TPHL
Tsk(p)
Tr
(see Figure 8)
Pulse Skew (TPHL-TPLH
Transition Low to High
Transition High to Low
)
0.2
800
800
4
1500
1500
10
Tf
TPHZ
TPLZ
Propagation delay, high level to high impedance output
Propagation delay, low level to high impedance output
Propagation delay, high impedance to high level output
Propagation delay, high impedance to low level output
(see Figure 8)
4.3
3
10
TPZH
TPZL
10
2
10
TPHL_skR1_Dx
Channel to Channel skew-receiver 1 to Any mux related
drivers
95
TPLH_skR1_Dx
Channel to Channel skew-receiver 1 to Any mux related
drivers
95
95
95
95
95
95
95
ps
ps
ps
ps
ps
ps
ps
TPPHL_skR2_Dx Channel to Channel skew-receiver 2 to Any mux related
drivers
TPLH_skR2_Dx
TPHL_skR3_Dx
TPLH_skR3_Dx
TPHL_skR4_Dx
Channel to Channel skew-receiver 2 to Any mux related
drivers
Channel to Channel skew-receiver 3 to Any mux related
drivers
Channel to Channel skew-receiver 3 to Any mux related
drivers
Channel to Channel skew-receiver 4 to Any mux related
drivers
TPLH_skR4_Dx
Channel to Channel skew-receiver 4 to Any mux related
drivers
Note:
2. These parameters are measured over supply voltage and temperature ranges recommended for the device.
3. All typical values are measured at 25°C with a 3.3V supply.
Document #: 38-07411 Rev. **
Page 5 of 12
CY2LL8422
Router Options
Splitter Options
Router Options
Splitter Options
S0/S1
S2/S3
S0/S1
S2/S3
1Y/1Z
Cross Point
Router
3Y/3Z
Cross Point
Router
1A/1B
3A/3B
1Y/1Z
3Y/3Z
1A/1B
3A/3B
Splitter A
2Y/2Z
Splitter A
4Y/4Z
4A/4B
3A/3B
4A/4B
2A/2B
1A/1B
2Y/2Z
4Y42Z
2A/2B
1A/1B
4A/4B
3A/3B
1Y/1Z
3Y/3Z
1Y/1Z
3Y/3Z
Pass Thru
Router
2Y/2Z
Pass Thru
Router
4Y/4Z
Splitter B
2Y/2Z
Splitter B
4Y/4Z
2A/2B
2A/2B
4A/4B
S0/S1
S0/S1
S2/S3
S2/S3
Figure 1. 2-Channel Cross Point Switch/Mux
Dynamic Idd
Dynamic Idd
VID=0.4V, VIC=1.2V, S0, S1=00
VID=0.4V, VIC=1.2V, S0,S1=01
25°C CY2LL8422
25°C CY2LL8422
40.00
50.00
45.00
40.00
35.00
30.00
25.00
20.00
38.00
36.00
34.00
32.00
30.00
28.00
26.00
24.00
22.00
20.00
3.0V
3.3V
3.6V
3.0V
3.3V
3.6V
Fin (Mhz)
Fin (MHz)
Dynamic Idd
VID=0.4V, VIC=1.2V, S0,S1=00;S2,S3=00
Dynamic Idd
VID=0.4V, VIC=1.2V, S0,S1=01;S2,S3=01
25°C CY2LL8422
25°C CY2LL8422
70.00
60.00
50.00
40.00
30.00
20.00
70.00
60.00
50.00
40.00
30.00
20.00
3.0V
3.3V
3.6V
3.0V
3.3V
3.6V
50 75 100 125 150 175 200 225 250 275 300 325 350
50 75 100 125 150 175 200 225 250 275 300 325 350
Fin (MHz)
Fin (Mhz)
Figure 2. Dynamic IDD Diagrams
Document #: 38-07411 Rev. **
Page 6 of 12
CY2LL8422
7.500
7.000
6.500
6.000
5.500
5.000
4.500
4.000
0.100
0.200
0.300
0.400
0.500
0.600
0
0.5
1
1.5
2
2.5
VIC
Figure 3. TPHL vs. VIC
6.500
6.000
5.500
5.000
4.500
4.000
0.100
0.200
0.300
0.400
0.500
0.600
0
0.5
1
1.5
2
2.5
VIC
Figure 4. TPLH vs. VIC
400
200
0.100
0.200
0.300
0.400
0.500
0.600
0
0
0.5
1
1.5
2
2.5
-200
-400
-600
-800
-1000
-1200
VIC
Figure 5. TPLH- TPHL vs. VIC
Document #: 38-07411 Rev. **
Page 7 of 12
CY2LL8422
A
B
Y
Z
Pulse
Generator
A
B
R
D
Y
Z
RL & RC
Pulse
R
D
RL
Generator
DE
10 pF
10 pF
DE
CL = 10pF
VIA
1.4 V
0 V Diffe re n tia l
1.0 V
10 pF
1 .2
V C M
VIB
100%
80%
1.4 V
0 V Diffe re n tia l
V0Y
1.2
V
C M
1.4V
1.0V
VI(A)
VI(B)
V0Z
1.0 V
T P HL
T P LH
0.0V
20%
0%
8 0 %
0 V Diffe re n tia l
2 0 %
V0Y - V0 Z
tR
tF
tF
tR
Figure 8. Differential Receiver to Driver Propagation
Delay and Driver Transition Time[4,8,9]
Figure 6. Test Circuit & Voltage Definitions for the
Differential Output Signal[4,5,6]
A
Y
A
Pulse
Y
1.0 V or 1.2V
B
R
RL
D
Generator
Z
B
R
D
Z
1.2V
1.2V
DE
DE
CL = 10pF
10 pF
CL =10 pF
2.0V
1.4V
1.4V
1.0V
VI(A)
VI(B)
DE
0.8V
1.4V
TPZH
1.25V
TPHZ
TPLZ
V0Y or V0Z
V0Y or V0Z
1.2V
1.2V
TPZL
Voc (pp)
1.15V
1.0V
VDD
Voc (ss)
Figure 9. Test Circuit & Voltage Definitions for the Driver
Common-Mode Output Voltage[4,8]
Figure 7. Test Circuit & Voltage Definitions for the Driver
Common-Mode Output Voltage[4,5,6,7]
Notes:
4. All input pulses are supplied by a frequency generator with the following characteristics: tR & tF ≤ 1nS; Pulse rep rate = 50 Mpps; Pulse width = 10±0.2 ns.
5. RL = 100 Ohm.
6. CL includes instrumentation and fixture capacitance within 6 mm of the DUT.
7. VOC measurement requires equipment with a 3-dB bandwidth of at least 300 MHz.
8. RL = 100 Ohm ±1%.
9. Point to Point: RL = 100 Ohm ±1% CL 3 pF.
Document #: 38-07411 Rev. **
Page 8 of 12
CY2LL8422
Application Engineering
CY2LL8422
ZO=50
ZO=50
RL=100 ohm
Pulse
Generator
4
3
2
Vol - Io
1
CL = 10pF
2 locations
0
-1
Figure 10. Termination Scheme for 100-Ohm External
Termination
0
1
2
3
4
Voltage
Figure 13. VOL vs. IOL
ZO =50
Receiver chip
Table 7. Technical Notes on STD Drive (LL842, A & D) vs.
High Drive (LL843, B & C)[10]
with
100
100 Ohm on chip
termination
ohm
ZO =50
A
B
C
D
1.2
Unit
V
CL
CL
VOX
1.2
1.2
1.0
0.5
0.9
1.4
1.4
1.2
DC Offset
VOD Min
VOD Max
T/Rise
1.0
1.0
1.0
V
0.25
0.45
1.4
0.25
0.45
0.6
0.125
0.225
0.6
V
Figure 11. Termination Scheme for 100-Ohm
Self Termination Interface Chip
V
ns
ns
T/Fall
1.4
0.6
0.6
TypicalCharacteristics(@VDD=3.3V/TA=25°C)
Note:
10. See Figure 14.
CY2LL8422
Hi Drive
Current drive of 2i
Standard Drive
Current drive of 1i
5
0
100
ohm
+/-
B
2i
A
+/-
i
100
ohm
-5
-10
-15
Voh - Ioh
0
1
2
3
4
25 ohm
50
ohm
50
ohm
+/-
i
+/-
2i
D
Voltage
C
25 ohm
Figure 12. VOH vs. IOH
Figure 14.
Document #: 38-07411 Rev. **
Page 9 of 12
CY2LL8422
Ordering Information
Part Number
CY2LL8422ZI
Package Type
28-pin TSSOP
Product Flow
Industrial, –40° to 85°C
CY2LL8422ZIT
CY2LL8422ZC
28-pin TSSOP -Tape and Reel
28-pin TSSOP
Industrial, –40° to 85°C
Commercial, 0°C to 70°C
Commercial, 0°C to 70°C
Industrial, –40°to 85°C
Industrial, –40°Cto 85°C
Commercial, 0°C to 70°C
Commercial, 0°C to 70°C
CY2LL8422ZCT
CY2LL8422OI
28-pin TSSOP -Tape and Reel
28-pin SSOP
CY2LL8422OIT
CY2LL8422OC
CY2LL8422OCT
28-pin SSOP -Tape and Reel
28-pin SSOP
28-pin SSOP -Tape and Reel
Package Diagrams
28-Lead (5.3 mm) Shrunk Small Outline Package O28
51-85079-*C
Document #: 38-07411 Rev. **
Page 10 of 12
CY2LL8422
Package Diagrams (continued)
28-Lead Thin Small Outline Package Type 1 (8x13.4 mm) Z28
51-85071-*G
ComLink is a trademark of Cypress Semiconductor Corp. All product and company names mentioned in this document may be
the trademarks of their respective holders.
Document #: 38-07411 Rev. **
Page 11 of 12
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges..
CY2LL8422
Document Title: CY2LL8422 High Drive Dual 2-Channel LVDS Repeater/Mux
Document #: 38-07411
REV.
ECN NO.
Issue Date
Orig. of Change
Description of Change
New Data Sheet
**
116743
07/05/02
HWT
Document #: 38-07411 Rev. **
Page 12 of 12
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