CY7C1319V18 [ETC]
Memory ; 内存\n
| 型号： | CY7C1319V18 |
| 厂家： | 
ETC |
| 描述： | Memory
|
| 文件： | 总23页 (文件大小：593K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1317V18
CY7C1319V18
CY7C1321V18
PRELIMINARY
18-Mb DDR-II SRAM
Four-word Burst Architecture
Features
Functional Description
• 18-Mb density (2M x 8, 1M x 18, 512K x 36)
— Supports concurrent transactions
The CY7C1317V18/CY7C1319V18/CY7C1321V18 are 1.8V
Synchronous Pipelined SRAM equipped with DDR-II (Double
Data Rate) architecture. The DDR-II consists of an SRAM core
with advanced synchronous peripheral circuitry and a two-bit
burst counter. Addresses for Read and Write are latched on
alternate rising edges of the input (K) clock. Write data is regis-
tered on the rising edges of both K and K. Read data is driven
on the rising edges of C and C if provided, or on the rising edge
of K and K if C/C are not provided. Each address location is
associated with four 8-bit words in the case of CY7C1317V18
that burst sequentially into or out of the device. The burst
counter always starts with “00” internally in the case of
CY7C1317V18. On CY7C1319V18 and CY7C1321V18, the
burst counter takes in the last two significant bits of the
external address and bursts four 18-bit words in the case of
CY7C1319V18, and four 36-bit words in the case of
CY7C1321V18, sequentially into or out of the device.
• 250-MHz clock for high bandwidth
• Four-word burst for reducing address bus frequency
• Double Data Rate (DDR) interfaces (data transferred at
500 MHz) @ 250 MHz
• Two input clocks (K and K) for precise DDR timing
— SRAM uses rising edges only
• Two output clocks (C and C) accounts for clock skew
and flight time mismatches
• Echo clocks (CQ and CQ) simplify data capture in high
speed systems
• Synchronous internally self-timed writes
• 1.8V core power supply with HSTL inputs and outputs
• Variable drive HSTL output buffers
Asynchronous inputs include impedance match (ZQ).
Synchronous data outputs (Q, sharing the same physical pins
as the data inputs, D) are tightly matched to the two output
echo clocks CQ/CQ, eliminating the need for separately
capturing data from each individual DDR SRAM in the system
design. Output data clocks (C/C) enable maximum system
clocking and data synchronization flexibility.
• Expanded HSTL output voltage (1.4V–VDD
• 13 x 15 mm 1.0-mm pitch fBGA package, 165-ball
(11 x 15 matrix)
• JTAG interface
• On-chip Delay Lock Loop (DLL)
)
Configurations
All synchronous inputs pass through input registers controlled
by the K or K input clocks. All data outputs pass through output
registers controlled by the C or C input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
CY7C1317V18 – 2M x 8
CY7C1319V18 – 1M x 18
CY7C1321V18 – 512K x 36
Logic Block Diagram (CY7C1317V18)
Burst
Logic
Write Write Write Write
Reg
A
Reg
Reg
Reg
(18:0)
Address
Register
19
LD
8
K
K
Output
Logic
Control
CLK
Gen.
R/W
C
C
Read Data Reg.
32
CQ
CQ
16
V
REF
Reg.
Reg.
Reg.
R/W
Control
Logic
16
BWS
[1:0]
8
DQ
[7:0]
8
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-05178 Rev. *A
Revised July 31, 2002
CY7C1317V18
CY7C1319V18
CY7C1321V18
PRELIMINARY
Logic Block Diagram (CY7C1319V18)
Burst
A
Logic
(1:0)
2
18
Write Write Write Write
Reg
20
Reg Reg Reg
A
Address
Register
(19:0)
A
(19:2)
18
LD
K
K
Output
Logic
Control
CLK
Gen.
R/W
C
Read Data Reg.
72
CQ
CQ
C
36
V
REF
Reg.
Reg.
Reg.
18
R/W
Control
Logic
36
BWS
[1:0]
DQ
[17:0]
18
Logic Block Diagram (CY7C1321V18)
Burst
A
Logic
(1:0)
2
17
Write Write Write Write
Reg
19
Reg Reg Reg
A
Address
Register
(18:0)
A
(18:2)
36
LD
K
K
Output
Logic
Control
R/W
CLK
Gen.
C
C
Read Data Reg.
144
CQ
CQ
72
V
REF
Reg.
Reg.
Reg.
36
R/W
Control
Logic
72
BWS
[3:0]
DQ
[35:0]
36
Selection Guide[1]
300 MHz
300
250 MHz
200 MHz
200
167 MHz
167
Unit
MHz
mA
Maximum Operating Frequency
Maximum Operating Current
250
TBD
TBD
TBD
TBD
Note:
1. Shaded cells indicate advanced information.
Document #: 38-05178 Rev. *A
Page 2 of 23
CY7C1317V18
CY7C1319V18
CY7C1321V18
PRELIMINARY
Pin Configurations
1
CY7C1317V18 (2M x 8) - 11 x 15 FBGA
2
3
A
4
R/W
5
6
K
7
NC
8
LD
9
A
10
VSS/36M
11
CQ
DQ3
NC
CQ
NC
NC
NC
VSS/72M
BWS1
A
B
C
D
NC
NC
NC
NC
NC
NC
A
NC
A
K
BWS0
A
A
NC
NC
NC
NC
NC
NC
VSS
VSS
NC
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
NC
NC
DQ4
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
NC
NC
NC
DQ2
NC
E
F
NC
NC
DQ5
VDDQ
NC
NC
NC
NC
G
H
J
DOFF
NC
VREF
NC
VDDQ
NC
VREF
DQ1
NC
ZQ
NC
NC
NC
NC
NC
NC
K
L
NC
DQ6
NC
NC
NC
DQ0
NC
NC
NC
NC
NC
NC
NC
NC
VSS
VSS
VSS
A
VSS
A
VSS
A
VSS
VSS
NC
NC
NC
NC
NC
NC
NC
NC
NC
M
N
P
DQ7
A
C
A
A
A
A
A
A
A
TDO
TCK
A
C
A
TMS
TDI
R
CY7C1319V18 (1M x 18) - 11 x 15 FBGA
1
2
3
A
4
R/W
5
6
K
7
NC
8
LD
9
A
10
VSS/36M
11
CQ
DQ8
NC
CQ
NC
NC
NC
VSS/72M
BWS1
A
B
C
D
DQ9
NC
NC
NC
A
NC
A
K
BWS0
A1
A
NC
NC
NC
NC
DQ7
NC
VSS
VSS
A0
VSS
VSS
NC
DQ10
VSS
VSS
VSS
NC
NC
NC
DQ11
NC
VDDQ
VSS
VDD
VDD
VDD
VDD
VSS
VSS
VDDQ
NC
NC
NC
DQ6
E
F
NC
NC
DQ12
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
NC
DQ5
NC
DQ13
VDDQ
NC
NC
G
H
J
DOFF
NC
VREF
NC
VDDQ
NC
VREF
DQ4
NC
ZQ
NC
NC
NC
DQ14
NC
VDD
VSS
VSS
A
NC
NC
NC
NC
NC
DQ3
DQ2
K
L
NC
DQ15
NC
NC
NC
NC
NC
NC
NC
NC
VSS
VSS
VSS
A
VSS
A
VSS
VSS
DQ1
NC
NC
NC
M
N
P
DQ16
DQ17
A
C
A
NC
DQ0
A
A
A
A
A
A
TDO
TCK
A
C
A
TMS
TDI
R
Document #: 38-05178 Rev. *A
Page 3 of 23
CY7C1317V18
CY7C1319V18
CY7C1321V18
PRELIMINARY
Pin Configurations (continued)
CY7C1321V18 (512K x 36) - 11 x 15 FBGA
1
2
3
4
R/W
5
6
K
7
8
LD
9
A
10
VSS/72M
11
CQ
CQ
NC
NC
NC
VSS/144M NC/36M
BWS2
BWS1
BWS0
A1
A
B
C
D
DQ27
NC
DQ18
DQ28
DQ19
A
BWS3
A
K
A
NC
NC
NC
NC
DQ17
NC
DQ8
DQ7
DQ16
VSS
VSS
A0
VSS
VSS
DQ29
VSS
VSS
VSS
NC
NC
DQ30
DQ31
VREF
NC
DQ20
DQ21
DQ22
VDDQ
DQ32
DQ23
DQ24
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
NC
DQ15
NC
DQ6
E
F
NC
NC
VDD
VDD
VDD
VDD
VDD
VSS
DQ5
DQ14
ZQ
NC
NC
G
H
J
DOFF
NC
VDDQ
NC
VREF
DQ13
DQ12
NC
DQ4
DQ3
DQ2
NC
NC
NC
K
L
NC
DQ33
NC
NC
NC
NC
NC
DQ35
NC
DQ34
DQ25
DQ26
VSS
VSS
VSS
A
VSS
A
VSS
A
VSS
VSS
NC
NC
NC
DQ11
NC
DQ1
DQ10
DQ0
M
N
P
A
C
A
DQ9
A
A
A
A
A
A
TDO
TCK
A
C
A
TMS
TDI
R
Pin Definitions
Pin Name
I/O
Pin Description
DQ[x:0]
Input/Output- Data input/Output signals. Inputs are sampled on the rising edge of K and K clocks during valid
Synchronous write operations. These pins drive out the requested data during a Read operation. Valid data is
driven out on the rising edge of both the C and C clocks during Read operations or K and K when
in single clock mode. When the Read port is deselected, Q[x:0] are automatically three-stated.
CY7C1317V18 - DQ[7:0]
CY7C1319V18 - DQ[17:0]
CY7C1321V18 − DQ[35:0]
LD
Input-
Synchronous Load. This input is brought LOW when a bus cycle sequence is to be defined.
Synchronous This definition includes address and read/write direction. All transactions operate on a burst of
4 data (two clock periods of bus activity).
BWS0,BWS1,
Input-
Byte Write Select 0, 1, 2, and 3 − active LOW. Sampled on the rising edge of the K and K clocks
BWS2, BWS3 Synchronous during write operations. Used to select which byte is written into the device during the current
portion of the write operations. Bytes not written remain unaltered.
CY7C1311V18 − BWS0 controls D[3:0] and BWS1 controls D[7:4]
.
CY7C1313V18 − BWS0 controls D[8:0] and BWS1 controls D[17:9].
CY7C1315V18 − BWS0 controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18] and BWS3
controls D[35:27]
.
All the byte writes are sampled on the same edge as the data. Deselecting a Byte Write Select
will cause the corresponding byte of data to be ignored and not written into the device.
A, A0, A1
Input-
Address inputs. These address inputs are multiplexed for both Read and Write operations.
Synchronous Internally, the device is organized as 2M x 8 (4 arrays each of 512K x 8) for CY7C1317V18, 1M
x 18 (4 arrays each of 256K x 18) for CY7C1319V18 and 256K x 36 (four arrays each of 128K x
36) for CY7C1321V18. CY7C1317V18 – Since the least two significant bits of the address inter-
nally are “00,” only 19 address inputs are needed to access the entire memory array.
CY7C1319V18 – A0 and A1 are the inputs to the burst counter. These are incremented in a linear
fashion internally. 20 address inputs are needed to access the entire memory array.
CY7C1321V18 – A0 and A1 are the inputs to the burst counter. These are incremented in a linear
fashion internally. 19 address inputs are needed to access the entire memory array. All the
address inputs are ignored when the appropriate port is deselected.
Document #: 38-05178 Rev. *A
Page 4 of 23
CY7C1317V18
CY7C1319V18
CY7C1321V18
PRELIMINARY
Pin Definitions (continued)
Pin Name
R/W
I/O
Pin Description
Synchronous Read/Write Input. When LD is LOW, this input designates the access type (Read
Input-
Synchronous when R/W is HIGH, Write when R/W is LOW) for loaded address. R/W must meet the set-up and
hold times around edge of K.
C
C
K
Input-
Clock
Positive Output Clock Input. C is used in conjunction with C to clock out the Read data from
the device. C and C can be used together to deskew the flight times of various devices on the
board back to the controller. See application example for further details.
Input-
Clock
Negative Output Clock Input. C is used in conjunction with C to clock out the Read data from
the device. C and C can be used together to deskew the flight times of various devices on the
board back to the controller. See application example for further details.
Input-
Clock
Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the
device and to drive out data through Q[x:0] when in single clock mode. All accesses are initiated
on the rising edge of K.
K
Input-
Clock
Negative Input Clock Input. K is used to capture synchronous inputs being presented to the
device and to drive out data through Q[x:0] when in single clock mode.
CQ
Echo Clock CQ is referenced with respect to C. This is a free running clock and is synchronized to the
output clock of the QDRTM-II. In the single clock mode, CQ is generated with respect to K. The
timings for the echo clocks are shown in the AC timing table.
CQ
ZQ
Echo Clock CQ is referenced with respect to C. This is a free running clock and is synchronized to the
output clock of the QDRTM-II. In the single clock mode, CQ is generated with respect to K. The
timings for the echo clocks are shown in the AC timing table.
Input
Output Impedance Matching Input. This input is used to tune the device outputs to the system
data bus impedance. Q[x:0] output impedance are set to 0.2 x RQ, where RQ is a resistor
connected between ZQ and ground. Alternately, this pin can be connected directly to VDD, which
enables the minimum impedance mode. This pin cannot be connected directly to GND or left
unconnected.
DOFF
Input
DLL Turn Off. Connecting this pin to ground will turn off the DLL inside the device. The timings
in the DLL turned off operation will be different from those listed in this data sheet. More details
on this operation can be found in the application note, “DLL Operation in the QDRTM-II.”
TDO
Output
Input
Input
Input
Input
Input
Input
TDO for JTAG.
TCK
TCK pin for JTAG.
TDI
TDI pin for JTAG.
TMS
TMS pin for JTAG.
NC
No connects. Can be tied to any voltage level.
Address expansion for 36M. This is not connected to the die.
NC/36M
NC/72M
Address expansion for 72M. This is not connected to the die and so can be tied to any voltage
level.
VSS/72M
VSS/144M
VSS/288M
VREF
Input
Input
Input
Input-
Address expansion for 72M. This must be tied LOW on the 18M SRAM.
Address expansion for 144M. This must be tied LOW on the 18M SRAM.
Address expansion for 288M. This must be tied LOW on the 18M SRAM.
Reference Voltage Input. Static input used to set the reference level for HSTL inputs and
Reference Outputs as well as AC measurement points.
VDD
Power Supply Power supply inputs to the core of the device. Should be connected to 1.8V power supply.
VSS
Ground
Ground for the device. Should be connected to ground of the system.
VDDQ
Power Supply Power supply inputs for the outputs of the device. Should be connected to 1.5V power supply.
Document #: 38-05178 Rev. *A
Page 5 of 23
CY7C1317V18
CY7C1319V18
CY7C1321V18
PRELIMINARY
address presented to Address inputs are stored in the Write
address register and the least two significant bits of the
address are presented to the burst counter. The burst counter
increments the address in a linear fashion. On the following K
clock rise the data presented to D[17:0] is latched and stored
into the 18-bit Write Data register provided BWS[1:0] are both
asserted active. On the subsequent rising edge of the
Negative Input Clock (K) the information presented to D[17:0]
is also stored into the Write Data Register provided BWS[1:0]
are both asserted active. This process continues for one more
cycle until four 18-bit words (a total of 72 bits) of data are
stored in the SRAM. The 72 bits of data are then written into
the memory array at the specified location. Therefore, Write
accesses to the device can not be initiated on two consecutive
K clock rises. The internal logic of the device will ignore the
second Write request. Write accesses can be initiated on
every other rising edge of the Positive Input Clock (K). Doing
so will pipeline the data flow such that 18 bits of data can be
transferred into the device on every rising edge of the input
clocks (K and K).
Introduction
Functional Overview
The
CY7C1317V18/CY7C1319V18/CY7C1321V18
are
synchronous pipelined Burst SRAMs equipped with a DDR
interface.
Accesses are initiated on the Positive Input Clock (K). All
synchronous input timing is referenced from the rising edge of
the input clocks (K and K) and all output timing is referenced
to the output clocks (C/C or K/K when in single-clock mode).
All synchronous data inputs (D[x:0]) pass through input
registers controlled by the input clocks (K and K). All
synchronous data outputs (Q[x:0]) pass through output
registers controlled by the rising edge of the output clocks (C/C
or K/K when in single clock mode).
All synchronous control (R/W, LD, BWS[0:X]) inputs pass
through input registers controlled by the rising edge of the
input clock (K).
The following descriptions take CY7C1319V18 as an
example. However, the same is true for the other DDR-II
SRAMs, CY7C1317V18 and CY7C1321V18.
When deselected, the write port will ignore all inputs after the
pending Write operations have been completed.
These chips utilize a Delay Lock Loop (DLL) that is designed
to function between 80 MHz and the specified maximum clock
frequency. The DLL may be disabled by applying ground to the
DOFF pin.
Byte Write Operations
Byte Write operations are supported by the CY7C1319V18. A
Write operation is initiated as described in the Write Operation
section above. The bytes that are written are determined by
BWS0 and BWS1, which are sampled with each set of 18-bit
data words. Asserting the appropriate Byte Write Select input
during the data portion of a write will allow the data being
presented to be latched and written into the device.
Deasserting the Byte Write Select input during the data portion
of a write will allow the data stored in the device for that byte
to remain unaltered. This feature can be used to simplify
Read/Modify/Write operations to a Byte Write operation.
Read Operations
The CY7C1319V18 is organized internally as a 256K x 72
SRAM. Accesses are completed in a burst of four sequential
18-bit data words. Read operations are initiated by asserting
R/WHIGH and LD LOW at the rising edge of the Positive Input
Clock (K). The address presented to the Address inputs is
stored in the Read address register and the least two signif-
icant bits of the address are presented to the burst counter.
The burst counter increments the address in a linear fashion.
Following the next K clock rise the corresponding 18-bit word
of data from this address location is driven onto the Q[17:0]
using C as the output timing reference. On the subsequent
rising edge of C the next 18-bit data word from the address
location generated by the burst counter is driven onto the
Q[17:0]. This process continues until all four 18-bit data words
have been driven out onto Q[17:0]. The requested data will be
valid 0.35 ns from the rising edge of the output clock (C or C,
250-MHz device). In order to maintain the internal logic, each
read access must be allowed to complete. Each Read access
consists of four 18-bit data words and takes two clock cycles
to complete. Therefore, Read accesses to the device can not
be initiated on two consecutive K clock rises. The internal logic
of the device will ignore the second Read request. Read
accesses can be initiated on every other K clock rise. Doing
so will pipeline the data flow such that data is transferred out
of the device on every rising edge of the output clocks (C/C or
K/K when in single-clock mode).
Single Clock Mode
The CY7C1319V18 can be used with a single clock that
controls both the input and output registers. In this mode the
device will recognize only a single pair of input clocks (K and
K) that control both the input and output registers. This
operation is identical to the operation if the device had zero
skew between the K/K and C/C clocks. All timing parameters
remain the same in this mode. To use this mode of operation,
the user must tie C and C HIGH at power-on. This function is
a strap option and not alterable during device operation.
DDR Operation
The CY7C1319V18 enables high-performance operation
through high clock frequencies (achieved through pipelining)
and double data rate mode of operation. The CY7C1319V18
requires a No Operation (NOP) cycle when transitioning from
a Read to a Write cycle. At higher frequencies, some applica-
tions may require a second NOP cycle to prevent contention.
When the read port is deselected, the CY7C1319V18 will first
complete the pending read transactions. Synchronous internal
circuitry will automatically three-state the outputs following the
next rising edge of the Positive Output Clock (C). This will
allow for a seamless transition between devices without the
insertion of wait states in a depth expanded memory.
If a Read occurs after a Write cycle, address and data for the
Write are stored in registers. The write information must be
stored because the SRAM can not perform the last word Write
to the array without conflicting with the Read. The data stays
in this register until the next Write cycle occurs. On the first
Write cycle after the Read(s), the stored data from the earlier
Write will be written into the SRAM array. This is called a
Posted Write.
Write Operations
Write operations are initiated by asserting R/W LOW and LD
LOW at the rising edge of the Positive Input Clock (K). The
Document #: 38-05178 Rev. *A
Page 6 of 23
CY7C1317V18
CY7C1319V18
CY7C1321V18
PRELIMINARY
Depth Expansion
VDDQ = 1.5V. The output impedance is adjusted every 1024
cycles to adjust for drifts in supply voltage and temperature.
Depth expansion requires replicating the LD control signal for
each bank. All other control signals can be common between
banks as appropriate.
Echo Clocks
Echo clocks are provided on the DDR-II to simplify data
capture on high-speed systems. Two echo clocks are
generated by the DDR-II. CQ is referenced with respect to C
and CQ is referenced with respect to C. These are free running
clocks and are synchronized to the output clock of the DDR-II.
In the single clock mode, CQ is generated with respect to K
and CQ is generated with respect to K. The timings for the
echo clocks are shown in the AC Timing table.
Programmable Impedance
An external resistor, RQ must be connected between the ZQ
pin on the SRAM and VSS to allow the SRAM to adjust its
output driver impedance. The value of RQ must be 5X the
value of the intended line impedance driven by the SRAM, The
allowable range of RQ to guarantee impedance matching with
a tolerance of ± 10% is between 175Ω and 350Ω, with
Application Example[2]
VTERM= VREF
SRAM #1
SRAM #4
DQ
DQ
18
18
R = 50Ω
Memory
Controller
72
DQ
20
20
LD
Add.
R/W
2
2
CLK/CLK (input)
CLK/CLK (output)
R = 50Ω
VT = VREF
Truth Table[3, 4, 5, 6, 7, 8]
Operation
K
LD
R/W
DQ
DQ
DQ
DQ
Write Cycle:
L-H
L
L
D(A1)atK(t + 1) D(A2) at
D(A3) at
D(A4) at
Load address; input write
data on 2 consecutive K and
K rising edges.
↑
K(t + 1) ↑
K(t + 2) ↑
K(t + 2) ↑
Read Cycle:
L-H
L-H
L
H
Q(A1) at
C(t + 1)↑
Q(A2) at
C(t + 2) ↑
Q(A3) at
C(t + 2)↑
Q(A4) at
C(t + 3) ↑
Load address; wait one
cycle; read data on 2
consecutive C and C rising
edges.
NOP: No Operation
H
X
X
High-Z
High-Z
High-Z
High-Z
Standby: Clock Stopped
Stopped
X
Previous State Previous State Previous
State
Previous State
Notes:
2. The above application shows 4 CY7C1319V18 being used. This holds true for CY7C1317V18 and CY7C1321V18 as well.
3. X = “Don't Care,” H = Logic HIGH, L = Logic LOW, ↑ represents rising edge.
4. Device will power-up deselected and the outputs in a three-state condition.
5. On CY7C1319V18 and CY7C1321V18, “A1” represents address location latched by the devices when transaction was initiated and A2, A3, A4 represents the
addresses sequence in the burst. On CY7C1317V18, “A1” represents A + ‘00’, A2 represents A + ‘01’, “A3” represents A + ‘10’ and A4 represents A + ‘11’.
6. t” represents the cycle at which a read/write operation is started. t+1, t + 2 and t +3 are the first, second and third clock cycles succeeding the “t” clock cycle.
7. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
8. It is recommended that K = K and C = C = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line
charging symmetrically.
Document #: 38-05178 Rev. *A
Page 7 of 23
CY7C1317V18
CY7C1319V18
CY7C1321V18
PRELIMINARY
Linear Burst Address Table (CY7C1319V18 and CY7C1321V18)
First Address (External)
Second Address (Internal)
Third Address (Internal)
Fourth Address (Internal)
X..X00
X..X01
X..X10
X..X11
X..X01
X..X10
X..X11
X..X00
X..X10
X..X11
X..X00
X..X01
X..X11
X..X00
X..X01
X..X10
Write Cycle Descriptions[3, 9](CY7C1317V18 and CY7C1319V18)
BWS0
BWS1
K
K
Comments
During the Data portion of a Write sequence :
L
L
L-H
-
CY7C1317V18 − both nibbles (D[7:0]) are written into the device,
CY7C1319V18 − both bytes (D[17:0]) are written into the device.
L
L
L
-
L-H
-
During the Data portion of a Write sequence :
CY7C1317V18 − both nibbles (D[7:0]) are written into the device,
CY7C1319V18 − both bytes (D[17:0]) are written into the device.
H
L-H
During the Data portion of a Write sequence :
CY7C1317V18 − only the lower nibble (D[3:0]) is written into the device. D[7:4] will remain
unaltered,
CY7C1319V18 − only the lower byte (D[8:0]) is written into the device. D[17:9] will remain
unaltered.
L
H
L
L
-
L-H
-
L-H
During the Data portion of a Write sequence :
CY7C1317V18 − only the lower nibble (D[3:0]) is written into the device. D[7:4] will remain
unaltered,
CY7C1319V18 − only the lower byte (D[8:0]) is written into the device. D[17:9] will remain
unaltered.
H
H
H
-
During the Data portion of a Write sequence :
CY7C1317V18 − only the upper nibble (D[7:4]) is written into the device. D[3:0] will remain
unaltered,
CY7C1319V18 − only the upper byte (D[17:9]) is written into the device. D[8:0] will remain
unaltered.
L-H
During the Data portion of a Write sequence :
CY7C1317V18 − only the upper nibble (D[7:4]) is written into the device. D[3:0] will remain
unaltered,
CY7C1319V18 − only the upper byte (D[17:9]) is written into the device. D[8:0] will remain
unaltered.
H
H
L-H
-
-
No data is written into the devices during this portion of a write operation.
No data is written into the devices during this portion of a write operation.
H
L-H
Note:
9. Assumes a Write cycle was initiated per the Write Port Cycle Description Truth Table. BWS0, BWS1 in the case of CY7C1317V18 and CY7C1319V18 and
also BWS2, BWS3 in the case of CY7C1321V18 can be altered on different portions of a write cycle, as long as the set-up and hold requirements are achieved.
Write Cycle Descriptions[3, 9] (CY7C1321V18)
BWS0 BWS1 BWS2 BWS3
K
K
Comments
L
L
L
L
L
L
L-H
-
During the Data portion of a Write sequence, all four bytes (D[35:0]) are written
into the device.
L
L
L
-
L-H
-
During the Data portion of a Write sequence, all four bytes (D[35:0]) are written
into the device.
H
H
H
L-H
During the Data portion of a Write sequence, only the lower byte (D[8:0]) is written
into the device. D[35:9] will remain unaltered.
Document #: 38-05178 Rev. *A
Page 8 of 23
CY7C1317V18
CY7C1319V18
CY7C1321V18
PRELIMINARY
Write Cycle Descriptions[3, 9] (CY7C1321V18) (continued)
L
H
H
H
H
L
H
H
H
H
H
L
-
L-H
During the Data portion of a Write sequence, only the lower byte (D[8:0]) is written
into the device. D[35:9] will remain unaltered.
H
H
H
H
H
H
L
L-H
-
During the Data portion of a Write sequence, only the byte (D[17:9]) is written into
the device. D[8:0] and D[35:18] will remain unaltered.
L
-
L-H
-
During the Data portion of a Write sequence, only the byte (D[17:9]) is written into
the device. D[8:0] and D[35:18] will remain unaltered.
H
H
H
H
L-H
During the Data portion of a Write sequence, only the byte (D[26:18]) is written
into the device. D[17:0] and D[35:27] will remain unaltered.
L
-
L-H
During the Data portion of a Write sequence, only the byte (D[26:18]) is written
into the device. D[17:0] and D[35:27] will remain unaltered.
H
H
L-H
-
During the Data portion of a Write sequence, only the byte (D[35:27]) is written
into the device. D[26:0] will remain unaltered.
L
L-H
During the Data portion of a Write sequence, only the byte (D[35:27]) is written
into the device. D[26:0] will remain unaltered.
H
H
H
H
H
H
H
H
L-H
-
-
No data is written into the device during this portion of a write operation.
No data is written into the device during this portion of a write operation.
L-H
Document #: 38-05178 Rev. *A
Page 9 of 23
CY7C1317V18
CY7C1319V18
CY7C1321V18
PRELIMINARY
Current into Outputs (LOW)......................................... 20 mA
Maximum Ratings
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-up Current.................................................... > 200 mA
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Operating Range
Ambient
Supply Voltage on VDD Relative to GND........ –0.5V to +2.9V
Range Temperature[10]
VDD
VDDQ
DC Voltage Applied to Outputs
in High-Z State[12] ............................... –0.5V to VDDQ + 0.5V
Com’l
0°C to +70°C
1.8 ± 100 mV 1.4V to VDD
DC Input Voltage[12] ............................ –0.5V to VDDQ + 0.5V
Electrical Characteristics Over the Operating Range[1, 11]
Parameter
VDD
Description
Test Conditions
Min.
1.7
Typ.
1.8
Max.
1.9
Unit
V
Power Supply Voltage
I/O Supply Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage[12]
Input LOW Voltage[12]
Input Load Current
VDDQ
VOH
VOL
1.4
1.5
VDD
VDDQ
0.2
V
IOH = −2.0 mA, Nominal Impedance
VDDQ – 0.2 VDDQ – 0.2
V
IOL = 2.0 mA, Nominal Impedance
VSS
VREF + 0.1
–0.3
VSS
V
VIH
VREF + 0.1 VDDQ + 0.3
V
VIL
VREF – 0.1 VREF – 0.1
V
IX
GND ≤ VI ≤ VDDQ
–5
–5
–5
5
5
µA
µA
V
IOZ
Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled
–5
VREF
Input Reference
Voltage[13]
Typical Value = 0.75V
0.68
0.75
0.95
IDD
IDD
ISB1
VDD Operating Supply VDD = Max., IOUT = 0 mA, 167 MHz
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
x8, x18
f = fMAX = 1/tCYC
200 MHz
250 MHz
300 MHz
VDD Operating Supply VDD = Max., IOUT = 0 mA, 167 MHz
x36
f = fMAX = 1/tCYC
200 MHz
250 MHz
300 MHz
167 MHz
200 MHz
250 MHz
300 MHz
167 MHz
200 MHz
250 MHz
300 MHz
Automatic
Power-down
Current, x8, x18
Max. VDD, both ports
Deselected, VIN ≥ VIH or
VIN ≤ VIL f = fMAX = 1/tCYC
,
,
Inputs Static
ISB1
Automatic
Power-down
Current, x36
Max. VDD, both ports
Deselected, VIN ≥ VIH or
VIN ≤ VIL f = fMAX = 1/tCYC
Inputs Static
Notes:
10. Ambient temperature = TA. This is the case temperature.
11. All voltage referenced to ground.
12. Overshoot: VIH(AC) < VDD + 0.5V for t < tTCYC/2; undershoot VIL(AC) < – 0.5V for t < tTCYC/2; power-up: VIH < 1.8V and VDD < 1.8V and VDDQ < 1.4V for
t < 200 ms.
13. VREF Min. = 0.68V or 0.46VDDQ, whichever is larger, VREF Max, = 0.95V or 0.54VDDQ, whichever is smaller.
Document #: 38-05178 Rev. *A
Page 10 of 23
CY7C1317V18
CY7C1319V18
CY7C1321V18
PRELIMINARY
Switching Characteristics Over the Operating Range[1, 14]
300
250
200
167
Parameter
tCYC
Description
K Clock and C Clock Cycle Time
Input Clock (K/K and C/C) HIGH
Input Clock (K/K and C/C) LOW
Min. Max. Min. Max. Min. Max. Min. Max. Unit
3.3
4.0
–
4.0
1.6
1.6
1.8
5.0
–
5.0
2.0
2.0
2.2
6.0
–
6.0
2.4
2.4
2.7
7.5
–
ns
ns
ns
ns
tKH
1.32
1.32
tKL
–
–
–
–
tKHKH
K/K Clock Rise to K/K Clock Rise and C/C to
C/C Rise (rising edge to rising edge)
1.49 1.82
–
–
–
tKHCH
K/K Clock Rise to C/C Clock Rise (rising edge 0.0
to rising edge)
1.45
0.0
1.8
0.0
2.3
0.0
2.8
ns
Set-up Times
tSA Address Set-up to K Clock Rise
tSC
0.4
0.4
–
–
0.5
0.5
–
–
0.6
0.6
–
–
0.7
0.7
–
–
ns
ns
Control Set-up to Clock (K) Rise (R/W, LD,
BWS0, BWS1, BWS2, BWS3)
tSD
D[17:0] Set-up to Clock (K and K) Rise
0.3
–
0.4
–
0.5
–
0.6
–
ns
Hold Times
tHA
tHC
Address Hold after Clock (K) Rise
0.4
0.4
–
–
0.5
0.5
–
–
0.6
0.6
–
–
0.7
0.7
–
–
ns
ns
Control Hold after Clock (K) Rise (R/W, LD,
BWS0, BWS1, BWS2, BWS3)
tHD
D[17:0] Hold after Clock (K and K) Rise
0.3
–
0.4
–
0.5
–
0.6
–
ns
Output Times
tCO
C/C Clock Rise (or K/K in single clock mode) to
Data Valid[14]
–
0.29
–
0.35
–
0.38
–
0.40
ns
ns
tDOH
Data Output Hold after Output C/C Clock Rise –0.29
–
–0.35
–
–0.38
–
–0.40
–
(Active to Active)
tCCQO
tCQOH
tCQD
tCLZ
C/C Clock Rise to Echo Clock Valid
Echo Clock Hold after C/C Clock Rise
Echo Clock High to Data Change
Clock (C and C) Rise to Low-Z[15, 16]
–
0.27
-
0.33
-
0.36
-
0.38
ns
ns
ns
ns
ns
–0.27
–
–0.27
–
–0.36
–
–0.38
–
–0.27 0.29 –0.33 0.35 –0.36 0.38 −0.38 0.40
–0.29
–
–0.35
–
–0.38
–
−0.4
–
tCHZ
Clock (C and C) Rise to High-Z (Active to
High-Z)[15, 16]
–
0.29
–
0.35
–
0.38
–
0.4
DLL Timing
tKC
Clock Phase Jitter
–
0.08
–
0.10
–
0.13
0.15
ns
tKC lock
DLL Lock Time (K, C)
1024
–
1024
–
1024
–
1024
–
cycles
Capacitance[17]
Parameter
CIN
Description
Input Capacitance
Test Conditions
Max.
Unit
TA = 25°C, f = 1 MHz,
VDD = 1.8V
VDDQ = 1.5V
TBD
TBD
TBD
pF
pF
pF
CCLK
Clock Input Capacitance
Output Capacitance
CO
Notes:
14. Unless otherwise noted, test conditions assume signal transition time of 2V/ns, timing reference levels of 0.75V, Vref=0.75V, RQ=250Ω, VDDQ=1.5V, input
pulse levels of 0.25V to 1.25V, and output loading of the specified IOL/IOH and load capacitance shown in (a) of AC test loads.
15. tCHZ, tCLZ, are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 100 mV from steady-state voltage.
16. At any given voltage and temperature tCHZ is less than tCLZ and tCHZ less than tCO
.
Document #: 38-05178 Rev. *A
Page 11 of 23
CY7C1317V18
CY7C1319V18
CY7C1321V18
PRELIMINARY
AC Test Loads and Waveforms
V
= 0.75V
REF
0.75V
V
REF
V
0.75V
REF
R = 50Ω
OUTPUT
[14]
ALL INPUT PULSES
1.25V
Z = 50Ω
0
OUTPUT
Device
Device
Under
Test
R = 50Ω
L
0.75V
0.25V
5 pF
Under
V
= 0.75V
Slew Rate = 2V / ns
REF
ZQ
ZQ
Test
RQ =
250Ω
RQ =
250Ω
(a)
INCLUDING
JIG AND
SCOPE
(b)
Switching Waveforms
[18]
Read/Deselect Sequence
Ignored
Deselect
tCYC
Deselect
Deselect
Read
Read
Ignored
tKHKH
tKL
tKHKH
K
K
tKH
tKL
tKH
LD
tSA
tHA
A(16:0)
A
B
R/W
DQ
Q(A+1)
Q(A)
Q(A+3)
Q(B+1)
Q(B+2) Q(B+3)
Q(A+2)
Q(B)
tKHCH
tCHZ
tDOH
tCQD
C
C
tCLZ
tKH
tKL
tKHKH
tCO
tKH
tCQD
CQ
CQ
tCCQO
tCQOH
= UNDEFINED
= DON’T CARE
Notes:
17. Tested initially and after any design or process change that may affect these parameters.
18. Device originally deselected.
Document #: 38-05178 Rev. *A
Page 12 of 23
CY7C1317V18
CY7C1319V18
CY7C1321V18
PRELIMINARY
Switching Waveforms
Write/Deselect Sequence[19, 20]
Ignored
Ignored
tCYC
Write
Deselect
Deselect
Write
tKL
K
tKH
tKL
K
tSA
tHA
A
A
B
tHC
tSC
LD
tSC
tHC
R/W
tHC
tSC
BWSx
D(A+3)
D(B)
D(B+1)
D(B+2)
D(B+3)
D(A)
D(A+2)
D(A+1)
Data In
tHD
tSD
= UNDEFINED
= DON’T CARE
Notes:
19. C and C reference to Data Outputs and do not affect Write operations.
20. BWSx LOW=Valid, Byte writes allowed, see Byte write table for details.
Document #: 38-05178 Rev. *A
Page 13 of 23
CY7C1317V18
CY7C1319V18
CY7C1321V18
PRELIMINARY
Switching Waveforms
Read/Write/Deselect Sequence[21, 22]
Write
Ignored
Read
Ignored
NOP/Deselect
Write
1
2
3
4
5
6
K
K
A
A
B
C
LD
R/W
DQ(A+1)
D(A+3)
DQ[17:0]
D(A)
D(A+2)
Q(B)
Q(Q(B+1)
Q(B+2)
Q(B+3)
C
C
CQ
CQ
= UNDEFINED
= DON’T CARE
Notes:
21. Read Port previously deselected.
22. BWSx assumed active.
Document #: 38-05178 Rev. *A
Page 14 of 23
CY7C1317V18
CY7C1319V18
CY7C1321V18
PRELIMINARY
on the rising edge of TCK. Data is output on the TDO pin on
the falling edge of TCK.
IEEE 1149.1 Serial Boundary Scan (JTAG)
The DDR-II incorporates a serial boundary scan test access
port (TAP) in the FBGA package. This port operates in accor-
dance with IEEE Standard 1149.1-1900, but does not have the
set of functions required for full 1149.1 compliance. These
functions from the IEEE specification are excluded because
their inclusion places an added delay in the critical speed path
of the SRAM. Note that the TAP controller functions in a
manner that does not conflict with the operation of other
devices using 1149.1 fully compliant TAPs. The TAP operates
using JEDEC standard 1.8V I/O logic levels.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
TDI and TDO pins as shown in TAP Controller Block Diagram.
Upon power-up, the instruction register is loaded with the
IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.
When the TAP controller is in the Capture IR state, the two
least significant bits are loaded with a binary “01” pattern to
allow for fault isolation of the board level serial test path.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are inter-
nally pulled up and may be unconnected. They may alternately
be connected to VDD through a pull-up resistor. TDO should
be left unconnected. Upon power-up, the device will come up
in a reset state which will not interfere with the operation of the
device.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(VSS) when the BYPASS instruction is executed.
Test Access Port –Test Clock
Boundary Scan Register
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
The boundary scan register is connected to all the input and
output pins on the SRAM. Several no connect (NC) pins are
also included in the scan register to reserve pins for higher
density devices.
Test Mode Select
The boundary scan register is loaded with the contents of the
RAM Input and Output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and
TDO pins when the controller is moved to the Shift-DR state.
The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instruc-
tions can be used to capture the contents of the Input and
Output ring.
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this pin unconnected if the TAP is not used. The pin is
pulled up internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI pin is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. For
information on loading the instruction register, see the TAP
Controller State Diagram. TDI is internally pulled up and can
be unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) on any register.
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI, and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register
Definitions table.
Test Data Out (TDO)
The TDO output pin is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine (see Instruction codes). The
output changes on the falling edge of TCK. TDO is connected
to the least significant bit (LSB) of any register.
TAP Instruction Set
Performing a TAP Reset
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in the
Instruction Code table. Three of these instructions are listed
as RESERVED and should not be used. The other five instruc-
tions are described in detail below.
A Reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of
the SRAM and may be performed while the SRAM is
operating. At power-up, the TAP is reset internally to ensure
that TDO comes up in a high-Z state.
The TAP controller used in this SRAM is not fully compliant
with the 1149.1 convention because some of the mandatory
1149.1 instructions are not fully implemented. The TAP
controller cannot be used to load address, data, or control
signals into the SRAM and cannot preload the Input or Output
buffers. The SRAM does not implement the 1149.1 commands
EXTEST or INTEST or the PRELOAD portion of SAMPLE/
TAP Registers
Registers are connected between the TDI and TDO pins and
allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through
the instruction registers. Data is serially loaded into the TDI pin
Document #: 38-05178 Rev. *A
Page 15 of 23
CY7C1317V18
CY7C1319V18
CY7C1321V18
PRELIMINARY
PRELOAD; rather it performs a capture of the Input and
Output ring when these instructions are executed.
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO pins.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 10 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is
possible that, during the Capture-DR state, an input or output
will undergo a transition. The TAP may then try to capture a
signal while in transition (metastable state). This will not harm
the device, but there is no guarantee as to the value that will
be captured. Repeatable results may not be possible.
EXTEST
EXTEST is a mandatory 1149.1 instruction which is to be
executed whenever the instruction register is loaded with all
0s. EXTEST is not implemented in the TAP controller, and
therefore this device is not compliant with the 1149.1 standard.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture set-up plus
hold times (tCS and tCH). The SRAM clock inputs might not be
captured correctly if there is no way in a design to stop (or
slow) the clock during a SAMPLE/PRELOAD instruction. If this
is an issue, it is still possible to capture all other signals and
simply ignore the value of the K, K, C, and C captured in the
boundary scan register.
The TAP controller does recognize an all-0 instruction. When
an EXTEST instruction is loaded into the instruction register,
the SRAM responds as if a SAMPLE/PRELOAD instruction
has been loaded.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO pins and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state. The IDCODE instruction
is loaded into the instruction register upon power-up or
whenever the TAP controller is given a test logic reset state.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO pins.
Note that since the PRELOAD part of the command is not
implemented, putting the TAP into the Update to the
Update-DR state while performing a SAMPLE/PRELOAD
instruction will have the same effect as the Pause-DR
command.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR state.
Bypass
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO pins. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The
PRELOAD portion of this instruction is not implemented, so
the TAP controller is not fully 1149.1-compliant.
Reserved
When the SAMPLE/PRELOAD instruction is loaded into the
instruction register and the TAP controller is in the Capture-DR
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Document #: 38-05178 Rev. *A
Page 16 of 23
CY7C1317V18
CY7C1319V18
CY7C1321V18
PRELIMINARY
TAP Controller State Diagram[23]
TEST-LOGIC
1
RESET
0
1
1
1
TEST-LOGIC/
IDLE
SELECT
DR-SCAN
SELECT
IR-SCAN
0
0
0
1
1
CAPTURE-DR
CAPTURE-IR
0
0
SHIFT-DR
0
SHIFT-IR
0
1
1
EXIT1-DR
0
1
EXIT1-IR
0
1
0
0
PAUSE-DR
1
PAUSE-IR
1
0
0
EXIT2-DR
1
EXIT2-IR
1
UPDATE-DR
UPDATE-IR
1
1
0
0
Note:
23. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
Document #: 38-05178 Rev. *A
Page 17 of 23
CY7C1317V18
CY7C1319V18
CY7C1321V18
PRELIMINARY
TAP Controller Block Diagram
0
Bypass Register
Selection
Circuitry
Selection
Circuitry
2
1
1
0
TDO
TDI
Instruction Register
29
31 30
.
.
2
0
0
Identification Register
.
.
.
.
2
1
106
Boundary Scan Register
TCK
TMS
TAP Controller
TAP Electrical Characteristics Over the Operating Range[11, 12, 24]
Parameter
VOH1
VOH2
VOL1
VOL2
VIH
Description
Output HIGH Voltage
Test Conditions
IOH = −2.0 mA
IOH = −100 µA
IOL = 2.0 mA
Min.
Max.
Unit
V
VDD – 0.45
VDD – 0.2
Output HIGH Voltage
Output LOW Voltage
Output LOW Voltage
Input HIGH Voltage
V
0.45
0.2
V
IOL = 100 µA
V
0.65VDD
–0.3
VDD + 0.3
0.35VDD
5
V
VIL
Input LOW Voltage
V
IX
Input and OutputLoad Current
GND ≤ VI ≤ VDD
–5
µA
[25, 26]
TAP AC Switching Characteristics Over the Operating Range
Parameter
tTCYC
Description
Min.
Max.
Unit
ns
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH
100
tTF
10
MHz
ns
tTH
40
40
tTL
TCK Clock LOW
ns
Set-up Times
tTMSS
TMS Set-up to TCK Clock Rise
TDI Set-up to TCK Clock Rise
Capture Set-up to TCK Rise
10
10
10
ns
ns
ns
tTDIS
tCS
Notes:
24. These characteristic pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics Table.
25. CS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.
t
26. Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns.
Document #: 38-05178 Rev. *A
Page 18 of 23
CY7C1317V18
CY7C1319V18
CY7C1321V18
PRELIMINARY
TAP AC Switching Characteristics Over the Operating Range (continued)[25, 26]
Parameter
Hold Times
tTMSH
Description
Min.
Max.
Unit
TMS Hold after TCK Clock Rise
TDI Hold after Clock Rise
10
10
10
ns
ns
ns
tTDIH
tCH
Capture Hold after Clock Rise
Output Times
tTDOV
TCK Clock LOW to TDO Valid
TCK Clock LOW to TDO Invalid
20
ns
ns
tTDOX
0
TAP Timing and Test Conditions[26]
0.9V
50Ω
ALL INPUT PULSES
0.9V
TDO
1.8V
Z = 50Ω
0
C = 20 pF
L
0V
tTL
(a)
tTH
GND
Test Clock
TCK
tTCYC
tTMSS
tTMSH
Test Mode Select
TMS
tTDIS
tTDIH
Test Data-In
TDI
Test Data-Out
TDO
tTDOV
tTDOX
Document #: 38-05178 Rev. *A
Page 19 of 23
CY7C1317V18
CY7C1319V18
CY7C1321V18
PRELIMINARY
Identification Register Definitions
Value
CY7C1319V18
000
Instruction Field
CY7C1317V18
CY7C1321V18
Description
Revision Number (31:29)
000
000
Version number.
Cypress Device ID (28:12) 11010100011000101 11010100011010101 11010100011100101 Defines the type of SRAM.
Cypress JEDEC ID (11:1)
00000110100
00000110100
00000110100
Allows unique identification of
SRAM vendor.
ID Register Presence (0)
1
1
1
Indicate the presence of an ID
register.
Scan Register Sizes
Register Name
Instruction
Bit Size
3
1
Bypass
ID
32
107
Boundary Scan
Instruction Codes
Instruction
EXTEST
Code
Description
000
Captures the Input/Output ring contents. Places the boundary scan register between the TDI
and TDO. This instruction is not 1149.1-compliant. The EXTEST command implemented by
these devices will NOT place the output buffers into a high-Z condition. If the output
buffers need to be in high-Z condition, this can be accomplished by deselecting the
Read port.
IDCODE
001
010
Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operation.
SAMPLE Z
Captures the Input/Output contents. Places the boundary scan register between TDI and TDO.
The SAMPLE Z command implemented by these devices will place the output buffers
into a high-Z condition.
RESERVED
011
100
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
Captures the Input/Output ring contents. Places the boundary scan register between TDI and
TDO. Does not affect the SRAM operation. This instruction does not implement 1149.1 preload
function and is therefore not 1149.1-compliant.
RESERVED
RESERVED
BYPASS
101
110
111
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operation.
Boundary Scan Order
Boundary Scan Order
Bit #
Bump ID
6R
Bit #
10
11
Bump ID
10P
10N
9P
0
1
2
3
4
5
6
7
8
9
6P
6N
12
13
14
15
16
17
18
19
7P
10M
11N
9M
7N
7R
8R
9N
8P
11L
9R
11M
9L
11P
Document #: 38-05178 Rev. *A
Page 20 of 23
CY7C1317V18
CY7C1319V18
CY7C1321V18
PRELIMINARY
Boundary Scan Order
Boundary Scan Order
Bit #
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
Bump ID
10L
11K
10K
9J
Bit #
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
Bump ID
1A
2B
3B
1C
1B
3D
3C
1D
2C
3E
2D
2E
1E
2F
9K
10J
11J
11H
10G
9G
11F
11G
9F
10F
11E
10E
10D
9E
3F
1G
1F
3G
2G
1J
10C
11D
9C
2J
9D
3K
3J
11B
11C
9B
2K
1K
2L
10B
11A
10A
9A
3L
1M
1L
8B
3N
3M
1N
2M
3P
2N
2P
1P
3R
4R
4P
5P
5N
5R
7C
6C
8A
7A
7B
6B
6A
5B
5A
4A
5C
4B
3A
2A
Document #: 38-05178 Rev. *A
Page 21 of 23
CY7C1317V18
CY7C1319V18
CY7C1321V18
PRELIMINARY
Ordering Information[1]
Speed
Package
Operating
Range
(MHz)
Ordering Code
Name
Package Type
13 x 15 mm FBGA
300
CY7C1317V18-300BZC
CY7C1319V18-300BZC
CY7C1321V18-300BZC
CY7C1317V18-250BZC
CY7C1319V18-250BZC
CY7C1321V18-250BZC
CY7C1317V18-200BZC
CY7C1319V18-200BZC
CY7C1321V18-200BZC
CY7C1317V18-167BZC
CY7C1319V18-167BZC
CY7C1321V18-167BZC
BB165A
Commercial
Commercial
Commercial
Commercial
250
200
167
BB165A
BB165A
BB165A
13 x 15 mm FBGA
13 x 15 mm FBGA
13 x 15 mm FBGA
Package Diagram
165-Ball FBGA (13 x 15 x 1.2 mm) BB165A
51-85122-*B
QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, Hitachi, IDT, Micron, NEC and
Samsung technology. All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05178 Rev. *A
Page 22 of 23
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C1317V18
CY7C1319V18
CY7C1321V18
PRELIMINARY
Document Title: CY7C1317V18/CY7C1319V18/CY7C1321V18 18-Mb DDR-II SRAM Four-word Burst Architecture
Document Number: 38-05178
ISSUE
DATE
ORIG. OF
REV.
**
ECN NO.
110857
115920
CHANGE DESCRIPTION OF CHANGE
11/09/01
08/01/02
SKX
RCS
New Data Sheet
*A
Changed Status to Preliminary. Shaded 300-MHz Bin.
Updated JTAG Scan Order.
Document #: 38-05178 Rev. *A
Page 23 of 23
相关型号：
CY7C1319V18-167BZC
DDR SRAM, 1MX18, 0.4ns, CMOS, PBGA165, 13 X 15 MM, 1.20 MM HEIGHT, FBGA-165
CYPRESS
CY7C1319V18-300BZC
DDR SRAM, 1MX18, 0.29ns, CMOS, PBGA165, 13 X 15 MM, 1.20 MM HEIGHT, FBGA-165
CYPRESS
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