CY7C341B-25JI [ETC]
;
| 型号： | CY7C341B-25JI |
| 厂家： | 
ETC |
| 描述： | 可编程逻辑 输入元件 时钟 |
| 文件： | 总11页 (文件大小：208K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
341B
CY7C341B
192-Macrocell MAX® EPLD
may be individually configured for input, output, or bidirectional data
flow.
Features
• 192 macrocells in 12 logic array blocks (LABs)
• Eight dedicated inputs, 64 bidirectional I/O pins
400
• Advanced 0.65-micron CMOS technology to increase
performance
• Programmable interconnect array
• 384 expander product terms
300
V
= 5.0V
CC
• Available in 84-pin HLCC, PLCC, and PGA packages
Room Temp.
Functional Description
200
100
0
The CY7C341B is an Erasable Programmable Logic Device
(EPLD) in which CMOS EPROM cells are used to configure
logic functions within the device. The MAX® architecture is
100% user-configurable, allowing the devices to accom-
modate a variety of independent logic functions.
The 192 macrocells in the CY7C341B are divided into 12 Logic
Array Blocks (LABs), 16 per LAB. There are 384 expander
product terms, 32 per LAB, to be used and shared by the
macrocells within each LAB. Each LAB is interconnected with
a programmable interconnect array, allowing all signals to be
routed throughout the chip.
100 Hz 1 kHz 10 kHz 100 kHz 1 MHz 10 MHz 50 MHz
MAXIMUM FREQUENCY
Typical I vs. f
CC
MAX
The speed and density of the CY7C341B allows it to be used in a
wide range of applications, from replacement of large amounts of
7400-series TTL logic, to complex controllers and multifunction
chips. With greater than 37 times the functionality of 20-pin PLDs,
the CY7C341B allows the replacement of over 75 TTL devices. By
replacing large amounts of logic, the CY7C341B reduces board
space, part count, and increases system reliability.
Programmable Interconnect Array
The Programmable Interconnect Array (PIA) solves inter-
connect limitations by routing only the signals needed by each
logic array block. The inputs to the PIA are the outputs of every
macrocell within the device and the I/O pin feedback of every
pin on the device.
Unlike masked or programmable gate arrays, which induce
variable delay dependent on routing, the PIA has a fixed delay.
This eliminates undesired skews among logic signals, which
may cause glitches in internal or external logic. The fixed delay,
regardless of programmable interconnect array configuration,
simplifies design by assuring that internal signal skews or
races are avoided. The result is ease of design implemen-
tation, often in a single pass, without the multiple internal logic
placement and routing iterations required for a programmable
gate array to achieve design timing objectives.
Each LAB contains 16 macrocells. In LABs A, F, G, and L, 8
macrocells are connected to I/O pins and eight are buried,
while for LABs B, C, D, E, H, I, J, and K, four macrocells are
connected to I/O pins and 12 are buried. Moreover, in addition
to the I/O and buried macrocells, there are 32 single product
term logic expanders in each LAB. Their use greatly enhances
the capability of the macrocells without increasing the number
of product terms in each macrocell.
Logic Array Blocks
There are 12 logic array blocks in the CY7C341B. Each LAB consists
of a macrocell array containing 16 macrocells, an expander product
term array containing 32 expanders, and an I/O block. The LAB is
fedbythe programmableinterconnect arrayandthededicated input
bus. Allmacrocellfeedbacksgotothemacrocellarray, theexpander
array, and the programmable interconnect array. Expanders feed
themselves and the macrocell array. All I/O feedbacks go to the
programmable interconnect array so that they may be accessed by
macrocells in other LABs as well as the macrocells in the LAB in
which they are situated.
Design Recommendations
For proper operation, input and output pins must be
constrained to the range GND < (VIN or VOUT) < VCC. Unused
inputs must always be tied to an appropriate logic level (either VCC
or GND). Each set of VCC and GND pins must be connected
together directly at the device. Power supply decoupling capacitors
of at least 0.2 µF must be connected between VCC and GND. For
the most effective decoupling, each VCC pin should be separately
decoupled to GND, directly at the device. Decoupling capacitors
should have good frequency response, such as monolithic ceramic
types.
Externally, the CY7C341B provides eight dedicated inputs, one of
which may be used as a system clock. There are 64 I/O pins that
Selection Guide
7C341B-25
7C341B-35
Unit
Maximum Access Time
25
35
ns
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-03016 Rev. *A
Revised February 21, 2002
CY7C341B
Design Security
The CY7C341B contains a programmable design security
feature that controls the access to the data programmed into
the device. If this programmable feature is used, a proprietary
design implemented in the device cannot be copied or
retrieved. This enables a high level of design control to be
obtained since programmed data within EPROM cells is
invisible. The bit that controls this function, along with all other
program data, may be reset simply by erasing the device.
250
200
150
I
OL
V
= 5.0V
CC
Room Temp.
100
50
The CY7C341B is fully functionally tested and guaranteed through
complete testing of each programmable EPROM bit and all internal
logic elements thus ensuring 100% programming yield.
I
OH
The erasable nature of these devices allows test programs to
be used and erased during early stages of the production flow.
The devices also contain on-board logic test circuitry to allow
verification of function and AC specification once encapsu-
lated in non-windowed packages.
0
1
2
3
4
5
V
O
OUTPUTVOLTAGE (V)
Output Drive Current
1 (A6)
2 (A5)
41 (K6)
42 (J6)
INPUT/CLK
INPUT
INPUT
INPUT
INPUT
(C6) 84
(C7) 83
(L7) 44
(J7) 43
INPUT
Logic Block Diagram
INPUT
INPUT
SYSTEMCLOCK
LAB A
MACROCELL1
LAB G
4
5
6
7
8
9
(C5)
(A4)
(B4)
(A3)
(A2)
(B3)
MACROCELL97
MACROCELL98
MACROCELL99
MACROCELL100
MACROCELL101
MACROCELL102
MACROCELL103
MACROCELL104
46 (L6)
MACROCELL2
MACROCELL3
MACROCELL4
MACROCELL5
MACROCELL6
MACROCELL7
MACROCELL8
47 (L8)
48 (K8)
49 (L9)
50 (L10)
51 (K9)
52 (L11)
53 (K10)
10 (A1)
11 (B2)
MACROCELL 9–16
MACROCELL 105–112
LAB B
LAB H
12 (C2)
13 (B1)
14 (C1)
15 (D2)
MACROCELL17
MACROCELL18
MACROCELL19
MACROCELL20
MACROCELL113
MACROCELL114
MACROCELL115
MACROCELL116
54 (J10)
55 (K11)
56 (J11)
57 (H10)
MACROCELL 21–32
MACROCELL 117–128
LAB C
LAB I
16 (D1)
17 (E3)
20 (F2)
21 (F3)
MACROCELL33
MACROCELL34
MACROCELL35
MACROCELL36
MACROCELL129
MACROCELL130
MACROCELL131
MACROCELL132
58 (H11)
59 (F10)
62 (G9)
63 (F9)
P
I
A
MACROCELL 37–48
MACROCELL 133–144
LAB D
LAB J
22 (G3)
23 (G1)
25 (F1)
26 (H1)
MACROCELL49
MACROCELL50
MACROCELL51
MACROCELL52
MACROCELL145
MACROCELL146
MACROCELL147
MACROCELL148
64 (F11)
65 (E11)
67 (E9)
68 (D11)
MACROCELL 53–64
MACROCELL 149–160
LAB E
LAB K
27 (H2)
28 (J1)
29 (K1)
30 (J2)
MACROCELL65
MACROCELL66
MACROCELL67
MACROCELL68
MACROCELL161
MACROCELL162
MACROCELL163
MACROCELL164
69 (D10)
70 (C11)
71 (B11)
72 (C10)
MACROCELL 69–80
MACROCELL 165–176
LAB F
LAB L
MACROCELL81
MACROCELL82
MACROCELL83
MACROCELL84
MACROCELL85
MACROCELL86
MACROCELL87
MACROCELL88
MACROCELL177
MACROCELL178
MACROCELL179
MACROCELL180
MACROCELL181
MACROCELL182
MACROCELL183
MACROCELL184
31 (L1)
32 (K2)
33 (K3)
34 (L2)
35 (L3)
36 (K4)
37 (L4)
38 (J5)
73 (A11)
74 (B10)
75 (B9)
76 (A10)
77 (A9)
78 (B8)
79 (A8)
80 (B6)
MACROCELL 89–96
MACROCELL 185–192
() – PERTAIN TO 84-PIN PGA PACKAGE
3, 24, 45, 66 (B5, G2, K7, E10)
18, 19, 39, 40, 60, 61, 81, 82 (E1, E2, K5, L5, G10, G11, A7, B7)
V
CC
GND
Document #: 38-03016 Rev. *A
Page 2 of 11
CY7C341B
Pin Configurations
PGA
Bottom View
PLCC/HLCC
Top View
L
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O INPUT I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND INPUT
V
CC
I/O
K
J
11 10
2 1
9
8
7
6
5
4
3
84 83 82 81 80 79 78 77 76 75
74
I/O
I/O
I/O
I/O
12
13
14
15
16
17
I/O
INPUT INPUT
I/O
I/O
73
I/O
I/O
I/O
72
71
70
69
68
67
I/O
I/O
I/O
H
I/O
I/O
I/O
I/O
I/O
V
I/O
GND
V
CC
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
GND
I/O
G
F
18
19
20
21
22
23
24
GND
I/O
I/O
66
65
64
63
62
61
60
59
58
CC
7C341B
I/O
I/O
I/O
I/O
I/O
GND
GND
7C341B
I/O
I/O
GND GND
V
CC
I/O
E
V
CC
I/O
25
26
27
28
29
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
D
C
I/O
I/O
I/O
57
56
55
54
I/O
INPUT INPUT
I/O
I/O
I/O
I/O
I/O
I/O
I/O
30
31
32
I/O
I/O
V
I/O
GND
I/O
I/O
I/O
I/O
11
B
A
CC
INPUT
5
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
INPUT/
CLK
I/O
1
I/O
2
I/O
3
I/O
4
GND
7
I/O
8
I/O
9
I/O
10
6
EXPANDER
DELAY
t
EXP
REGISTER
LOGIC ARRAY
OUTPUT
DELAY
t
CONTROLDELAY
INPUT/
OUTPUT
CLR
INPUT
t
INPUT
DELAY
LAC
t
PRE
t
OD
XZ
ZX
t
IN
t
LOGIC ARRAY
DELAY
t
t
RD
t
RSU
t
t
COMB
LATCH
t
RH
t
LAD
SYSTEM CLOCK DELAY t
ICS
CLOCK
DELAY
PIA
DELAY
t
t
IC
PIA
LOGIC ARRAY
DELAY
t
FD
I/O DELAY
t
IO
Figure 1. CY7C341B Internal Timing Model
Document #: 38-03016 Rev. *A
Page 3 of 11
CY7C341B
DC Output Current, per Pin[1]..................... −25 mA to +25 mA
DC Input Voltage[1]................................................−2.0V to+7.0V
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Operating Range
Storage Temperature .......................................−65°C to +135°C
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
VCC
Ambient Temperature with
Power Applied.............................................. –65°C to +135°C
5V ± 5%
5V ± 10%
–40°C to +85°C
Maximum Junction Temperature
(Under Bias)................................................................. 150°C
Supply Voltage to Ground Potential[1]..............−2.0V to +7.0V
Electrical Characteristics Over the Operating Range
Parameter
Description
Output HIGH Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Level
Input LOW Level
Test Conditions
Min.
Max.
Unit
V
VCC
VOH
VOL
VIH
VIL
Maximum VCC risetimeis 10ms 4.75(4.5)
VCC = Min., IOH = –4.0 mA[2]
VCC = Min., IOL = 8 mA[2]
5.25(5.5)
2.4
V
0.45
VCC+ 0.3
0.8
V
2.0
−0.3
−10
−40
V
V
IIX
Input Current
GND ≤ VIN ≤ VCC
+10
µA
µA
ns
ns
IOZ
Output Leakage Current
Input Rise Time
VO = VCC or GND
+40
tR (Recommended)
tF (Recommended)
100
Input Fall Time
100
Capacitance
Parameter
Description
Input Capacitance
Output Capacitance
Test Conditions
VIN = 0V, f = 1.0 MHz
VOUT = 0V, f = 1.0 MHz
Max.
Unit
pF
CIN
10
20
COUT
pF
AC Test Loads and Waveforms
R1 464Ω
R1 464Ω
5V
5V
OUTPUT
ALL INPUT PULSES
OUTPUT
3.0V
GND
90%
10%
90%
10%
R2
250 Ω
R2
250 Ω
50 pF
5 pF
< 6 ns
<
6 ns
INCLUDING
JIG AND
SCOPE
t
R
t
F
C341B-7
C341B-8
(a)
(b)
Equivalent to:
THÉVENIN EQUIVALENT (commercial/military)
163Ω
OUTPUT
1.75V
Notes:
1. Minimum DC input is –0.3V. During transactions, input may undershoot to –2.0V or overshoot to 7.0V for input currents less then 100 mA and periods shorter
than 20 ns.
2. The IOH parameter refers to high-level TTL output current; the IOL parameter refers to low-level TTL output current.
Document #: 38-03016 Rev. *A
Page 4 of 11
CY7C341B
External Switching Characteristics Over the Operating Range
7C341B-25
7C341B-35
Parameter
Description
Min.
Max
Min.
Max
Unit
tPD1
Dedicated Input to Combinatorial Output
Delay[3]
Commercial
25
35
ns
tPD2
tSU
tCO1
tH
I/O Input to Combinatorial Output Delay[3]
Commercial
Commercial
40
55
ns
ns
ns
ns
Global Clock Set-up Time
Synchronous Clock Input to Output Delay[3] Commercial
15
0
25
0
14
25
20
35
Input Hold Time from Synchronous Clock
Input
Commercial
tWH
Synchronous Clock Input High Time
Synchronous Clock Input Low Time
Maximum Register Toggle Frequency[4]
Commercial
Commercial
Commercial
Commercial
8
8
12.5
12.5
40.0
ns
ns
tWL
fMAX
tACO1
62.5
MHz
ns
Dedicated Asynchronous Clock Input to
Output Delay[3]
tAS1
tAH
Dedicated Input or Feedback Set-up Time to Commercial
Asynchronous Clock Input
5
6
10
10
ns
ns
Input Hold Time from Asynchronous Clock Commercial
Input
tAWH
tAWL
tCNT
Asynchronous Clock Input HIGH Time[5]
Asynchronous Clock Input LOW Time[5]
Minimum Global Clock Period
Commercial
Commercial
Commercial
Commercial
11
9
16
14
ns
ns
20
20
30
30
ns
tODH
fCNT
tACNT
fACNT
Output Data Hold Time After Clock
2
2
ns
Maximum Internal Global Clock Frequency[6] Commercial
Minimum Internal Array Clock Frequency Commercial
Maximum Internal Array Clock Frequency[6] Commercial
50
33.3
MHz
ns
50
33.3
MHz
Notes:
3. C1 = 35 pF.
4. The fMAX values represent the highest frequency for pipeline data.
5. This parameter is measured with a positive-edge-triggered clock at the register. For negative-edge clocking, the tACH and tACL parameter must be swapped.
6. This parameter is measured with a 16-bit counter programmed into each LAB.
Document #: 38-03016 Rev. *A
Page 5 of 11
CY7C341B
Internal Switching Characteristics Over the Operating Range
7C341B-25
Min. Max
7C341B-35
Min. Max
Parameter
tIN
Description
Dedicated Input Pad and Buffer Delay
I/O Input Pad and Buffer Delay
Expander Array Delay
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
5
11
11
20
14
13
6
tIO
6
tEXP
tLAD
tLAC
tOD
tZX
12
12
10
5
Logic Array Data Delay
Logic Array Control Delay
Output Buffer and Pad Delay[3]
Output Buffer Enable Delay[3]
Output Buffer Disable Delay[7]
10
10
13
13
tXZ
tRSU
Register Set-Up Time Relative to Clock Commercial
Signal at Register
6
4
12
8
tRH
Register Hold Time Relative to Clock
Signal at Register
Commercial
ns
tLATCH
tRD
tCOMB
tIC
Flow-Through Latch Delay
Register Delay
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
3
1
4
2
ns
ns
ns
ns
ns
ns
ns
ns
ns
Transparent Mode Delay
Asynchronous Clock Logic Delay
Synchronous Clock Delay
Feedback Delay
3
4
14
3
16
1
tICS
tFD
1
2
tPRE
tCLR
tPIA
Asynchronous Register Preset Time
Asynchronous Register Clear Time
5
7
5
7
Programmable Interconnect Array Delay Commercial
14
20
Note:
7. C1 = 5 pF.
Document #: 38-03016 Rev. *A
Page 6 of 11
CY7C341B
Switching Waveforms
External Combinatorial
DEDICATED INPUT/
I/O INPUT
t
/t
PD1 PD2
COMBINATORIAL
OUTPUT
External Synchronous
tWH
tWL
SYNCHRONOUS
CLOCK PIN
SYNCHRONOUS
CLOCK AT REGISTER
tSU
tH
DATA FROM
LOGIC ARRAY
tCO1
REGISTERED
OUTPUTS
External Asynchronous
DEDICATED INPUTS OR
REGISTERED FEEDBACK
t
t
t
AWL
t
AH
AWH
AS1
ASYNCHRONOUS
CLOCK INPUT
Internal Combinatorial
t
IN
INPUT PIN
t
IO
I/O PIN
t
EXP
EXPANDER
ARRAY DELAY
t
, t
LAC LAD
LOGIC ARRAY
INPUT
LOGIC ARRAY
OUTPUT
tCOMB
tOD
OUTPUT
PIN
Document #: 38-03016 Rev. *A
Page 7 of 11
CY7C341B
Switching Waveforms (continued)
Internal Asynchronous
t
t
AWL
AWH
t
R
t
F
CLOCK PIN
t
IN
CLOCK INTO
LOGIC ARRAY
t
IC
CLOCK FROM
LOGIC ARRAY
t
t
RH
RSU
DATA FROM
LOGIC ARRAY
t
,t
t
FD
t
,t
t
FD
RD LATCH
CLR PRE
REGISTER OUTPUT
TO LOCAL LAB
LOGIC ARRAY
t
PIA
REGISTER OUTPUT
TO ANOTHER LAB
Internal Synchronous
SYSTEM CLOCK PIN
t
IN
t
ICS
SYSTEM CLOCK
AT REGISTER
t
t
RH
RSU
DATA FROM
LOGIC ARRAY
Internal Synchronous
CLOCK FROM
LOGIC ARRAY
t
OD
t
RD
DATA FROM
LOGIC ARRAY
t
XZ
t
ZX
HIGH IMPEDANCE
STATE
OUTPUT PIN
Ordering Information
Speed (ns)
Ordering Code
CY7C341B-25HC/HI
CY7C341B-25JC/JI
CY7C341B-25RC/RI
CY7C341B-35HC/HI
CY7C341B-35JC/JI
CY7C341B-35RC/RI
Package Name
Package Type
Operating Range
25
H84
J83
R84
H84
J83
R84
84-lead Windowed Leaded Chip Carrier Commercial/Industrial
84-lead Plastic Leaded Chip Carrier
84-lead Windowed Pin Grid Array
35
84-lead Windowed Leaded Chip Carrier Commercial/Industrial
84-lead Plastic Leaded Chip Carrier
84-lead Windowed Pin Grid Array
Document #: 38-03016 Rev. *A
Page 8 of 11
CY7C341B
Package Diagrams
84-Leaded Windowed Leaded Chip Carrier H84
51-80081
Document #: 38-03016 Rev. *A
Page 9 of 11
CY7C341B
Package Diagrams (continued)
84-Lead Plastic Leaded Chip Carrier J83
51-85006-A
84-Lead Windowed Pin Grid Array R84
51-80026-*B
MAX is a registered trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this
document are the trademarks of their respective holders.
Document #: 38-03016 Rev. *A
Page 10 of 11
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C341B
Document Title: CY7C341B 192-Macrocell MAX® EPLD
Document Number: 38-03016
Issue
Date
Orig. of
Change
REV.
**
ECN NO.
106316
113613
Description of Change
Change from ecn #: 38-00137 to 38-03016
PGA package diagram dimensions were updated
05/17/01
04/11/02
SZV
*A
OOR
Document #: 38-03016 Rev. *A
Page 11 of 11
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