CY7C462-15JC [ETC]
IC-SM 16KX9 CMOS FIFO ; IC- SM 16KX9 CMOS FIFO\n
| 型号： | CY7C462-15JC |
| 厂家： | 
ETC |
| 描述： | IC-SM 16KX9 CMOS FIFO
|
| 文件： | 总14页 (文件大小：239K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C460A/CY7C462A
CY7C464A/CY7C466A
Asynchronous, Cascadable 8K/16K/32K/64K x9 FIFOs
Features
Functional Description
• High-speed, low-power, first-in first-out (FIFO)
memories
• 8K x 9 FIFO (CY7C460A)
• 16K x 9 FIFO (CY7C462A)
• 32K x 9 FIFO (CY7C464A)
• 64K x 9 FIFO (CY7C466A)
• 10-ns access times, 20-ns read/write cycle times
• High-speed 50-MHz read/write independent of
depth/width
• Low operating power
The CY7C460A, CY7C462A, CY7C464A, and CY7C466A are
respectively, 8K, 16K, 32K, and 64K words by 9-bit wide first-in
first-out (FIFO) memories. Each FIFO memory is organized
such that the data is read in the same sequential order that it
was written. Full and Empty flags are provided to prevent over-
run and underrun. Three additional pins are also provided to
facilitate unlimited expansion in width, depth, or both. The
depth expansion technique steers the control signals from one
device to another by passing tokens.
The read and write operations may be asynchronous; each
can occur at a rate of up to 50 MHz. The write operation occurs
when the Write (W) signal is LOW. Read occurs when Read
(R) goes LOW. The nine data outputs go to the high-imped-
ance state when R is HIGH.
— I = 60 mA
CC
— I =8 mA
SB
• Asynchronous read/write
• Empty and Full flags
• Half Full flag (in standalone mode)
• Retransmit (in standalone mode)
• TTL-compatible
A Half Full (HF) output flag is provided that is valid in the stan-
dalone (single device) and width expansion configurations. In
the depth expansion configuration, this pin provides the expan-
sion out (XO) information that is used to tell the next FIFO that
it will be activated.
• Width and Depth Expansion Capability
In the standalone and width expansion configurations, a LOW
on the Retransmit (RT) input causes the FIFOs to retransmit
the data. Read Enable (R) and Write Enable (W) must both be
HIGH during a retransmit cycle, and then R is used to access
the data.
5V 10% supply
•
±
• PLCC, LCC, 300-mil and 600-mil DIP packaging
• Three-state outputs
• Pin compatible density upgrade to CY7C42X/46X family
• Pin compatible and functionally equivalent to IDT7205,
IDT7206, IDT7207, IDT7208
The CY7C460A, CY7C462A, CY7C464A, and CY7C466A are
fabricated using Cypress’s advanced 0.5µ RAM3 CMOS tech-
nology. Input ESD protection is greater than 2000V and
latch-up is prevented by careful layout and the use of guard
rings.
Pin Configurations
Logic BlockDiagram
DATAINPUTS
DIP
Top View
(D −D
)
PLCC/LCC
Top View
0
8
1
28
V
CC
W
2
3
4
27
26
D
D
4
WRITE
CONTROL
8
4
3
2
1
32 31 30
29
W
D
2
D
D
5
6
7
6
D
D
5
3
DUAL PORT
RAM ARRAY
8K x 9
16K x 9
32K x 9
64K x 9
D
D
28
27
7
1
D
25
24
23
22
21
D
6
2
WRITE
POINTER
READ
POINTER
NC
0
5
D
D
1
7
7C460A
7C462A
7C464A
7C466A
7C460A
7C462A
7C464A
7C466A
XI
FL/RT
MR
8
9
26
25
24
23
D
0
XI
FF
6
FL/RT
MR
EF
FF
7
Q
0
EF
10
11
8
Q
1
XO/HF
Q
9
20
19
18
17
16
15
0
XO/HF
THREE–
NC
Q
7
6
12
13
22
21
Q
1
10
11
12
13
Q
STATE
7
Q
2
Q
BUFFERS
Q
6
Q
2
14 15 16 17 18 19 20
Q
3
Q
8
Q
5
DATAOUTPUTS
Q
4
(Q -Q
0
)
8
14
R
GND
MR
FL/RT
RESET
LOGIC
C46XA–2
READ
CONTROL
R
C46XA–3
FLAG
LOGIC
EF
FF
EXPANSION
LOGIC
XI
XO/HF
C46XA–1
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
October 4, 1999
CY7C460A/CY7C462A
CY7C464A/CY7C466A
Selection Guide
7C460A-10
7C462A-10
7C464A-10
7C466A-10
7C460A-15
7C460A-25
7C462A-25
7C464A-25
7C466A-25
7C462A-15
7C464A-15
7C466A-15
Frequency (MHz)
50
10
40
15
28.5
25
Maximum Access Time (ns)
Output Current, into Outputs (LOW)............................ 20 mA
Maximum Ratings
Static Discharge Voltage ........................................... >2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-Up Current..................................................... >200 mA
Storage Temperature ..................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Operating Range
Ambient
Supply Voltage to Ground Potential ............... –0.5V to +7.0V
Range
Commercial
Industrial
Temperature
V
CC
DC Voltage Applied to Outputs
in High Z State ............................................... –0.5V to +7.0V
0°C to + 70°C
5V ± 10%
5V ± 10%
5V ± 10%
–40°C to +85°C
–55°C to +125°C
DC Input Voltage............................................ –0.5V to +7.0V
[1]
Power Dissipation ..........................................................1.0W
Military
[2]
Electrical Characteristics Over the Operating Range
7C460A/462A/464A/466A
(-10,-15,-25)
Parameter
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage Current
Output Leakage Current
Operating Current
Test Conditions
= Min., I = −2.0 mA
Min.
Max.
Unit
V
V
V
2.4
V
V
OH
CC
OH
V
= Min., I = 8.0 mA
0.4
OL
CC
OL
V
2.2
−0.5
–10
–10
V
V
IH
IL
CC
V
0.8
+10
+10
60
V
I
I
I
GND < V < V
CC
µA
µA
mA
IX
I
R > V , GND < V < V
OZ
CC
IH
O
CC
V
= Max.,
CC
I
= 0 mA, Freq. = 20 MHz
OUT
I
Standby Current
All Inputs = V min.
8
mA
SB
IH
Capacitance[4]
Parameter
Description
Test Conditions
Max.
10
Unit
pF
C
C
Input Capacitance
Output Capacitance
T = 25°C, f = 1 MHz,
IN
A
V
= 4.5V
CC
12
pF
OUT
Notes:
1. A is the “instant on” case temperature.
2. See the last page of this specification for Group A subgroup testing information.
T
3. For test purposes, not more than one output at a time should be shorted. Short circuit test duration should not exceed 1 second.
4. Tested initially and after any design or process changes that may affect these parameters.
2
CY7C460A/CY7C462A
CY7C464A/CY7C466A
AC Test Loads and Waveforms
R1 500
R1 500
Ω
Ω
ALL INPUT PULSES
5V
5V
3.0V
GND
OUTPUT
OUTPUT
90%
90%
10%
10%
R2
333
R2
333
30 pF
5 pF
Ω
Ω
5 ns
≤
5 ns
≤
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
C460A–6
C460A–4
C460A–5
(a)
(b)
Equivalent to:
THÉVENIN EQUIVALENT
200
Ω
OUTPUT
2V
[2, 5]
Switching Characteristics Over the Operating Range
7C460A-10
7C462A-10
7C464A-10
7C466A-10
7C460A-15
7C462A-15
7C464A-15
7C466A-15
7C460A-25
7C462A-25
7C464A-25
7C466A-25
Parameter
Description
Read Cycle Time
Min.
Max.
Min.
Max.
Min.
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRC
20
25
35
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Access Time
10
15
25
A
Read Recovery Time
Read Pulse Width
10
10
3
10
15
3
10
25
3
RR
PR
Read LOW to Low Z
Data Valid After Read HIGH
Read HIGH to High Z
Write Cycle Time
LZR
DVR
HZR
WC
[6]
[6]
3
3
3
15
15
18
20
10
5
25
15
5
35
25
5
Write Pulse Width
PW
Write HIGH to Low Z
Write Recovery Time
Data Set-Up Time
HWZ
WR
10
9
10
9
10
9
SD
Data Hold Time
0
0
0
HD
MR Cycle Time
20
10
10
10
10
20
10
10
25
15
10
15
15
25
15
10
35
25
10
25
25
35
25
10
MRSC
PMR
RMR
RPW
WPW
RTC
PRT
RTR
EFL
MR Pulse Width
MR Recovery Time
Read HIGH to MR HIGH
Write HIGH to MR HIGH
Retransmit Cycle Time
Retransmit Pulse Width
Retransmit Recovery Time
MR to EF LOW
20
20
20
10
10
25
25
25
15
15
35
35
35
25
25
MR to HF HIGH
HFH
FFH
REF
RFF
MR to FF HIGH
Read LOW to EF LOW
Read HIGH to FF HIGH
Notes:
5. Test conditions assume signal transmission time of 5 ns or less, timing reference levels of 1.5V and output loading of the specified IOL/IOH and 30-pF load
capacitance, as in part (a) of AC Test Loads, unless otherwise specified.
6. tHZR and tDVR use capacitance loading as in part (b) of AC Test Loads.
3
CY7C460A/CY7C462A
CY7C464A/CY7C466A
[2, 5]
Switching Characteristics Over the Operating Range
(continued)
7C460A-10
7C462A-10
7C464A-10
7C466A-10
7C460A-15
7C462A-15
7C464A-15
7C466A-15
7C460A-25
7C462A-25
7C464A-25
7C466A-25
Parameter
Description
Write HIGH to EF HIGH
Write LOW to FF LOW
Write LOW to HF LOW
Read HIGH to HF HIGH
Min.
Max.
Min.
Max.
Min.
Max.
25
Unit
ns
t
t
t
t
t
10
10
10
10
10
15
15
15
15
15
WEF
25
ns
WFF
WHF
RHF
RAE
35
ns
35
ns
Effective Read from Write
HIGH
25
ns
t
t
t
t
t
Effective Read Pulse Width
After EF HIGH
10
10
15
15
25
25
ns
ns
ns
ns
ns
RPE
WAF
WPF
XOL
XOH
Effective Write from Read
HIGH
10
15
25
Effective Write Pulse
Width After FF HIGH
Expansion Out LOW
Delay from Clock
10
10
15
15
25
25
Expansion Out HIGH
Delay from Clock
4
CY7C460A/CY7C462A
CY7C464A/CY7C466A
Switching Waveforms[7]
Asynchronous Read and Write
t
t
PR
RC
t
A
t
t
A
RR
R
t
t
t
HZR
LZR
DVR
DATA VALID
DATA VALID
Q
Q
−
8
0
t
WC
t
t
t
PW
PW
WR
W
t
t
t
t
HD
SD
HD
SD
DATA VALID
DATA VALID
D D
−
0 8
C460A–7
Master Reset
[9]
t
MRSC
t
PMR
MR
[8]
R, W
t
RPW
t
EFL
t
WPW
EF
t
RMR
t
HFH
HF
FF
t
FFH
C460A–8
Half FullFlag
HALF FULL
HALF FULL+1
HALF FULL
RHF
W
R
t
t
WHF
HF
C460A–9
Notes:
7. A HIGH-to-LOW transition of either the write or read strobe causes a HIGH-to-LOW transition of the responding flag. Correspondingly, a LOW-to-HIGH strobe
transition causes a LOW-to-HIGH flag transition.
8. W and R = VIH around the rising edge of MR.
9.
tMSRC = t PMR + t RMR
5
CY7C460A/CY7C462A
CY7C464A/CY7C466A
Switching Waveforms[7] (continued)
Last Write to First ReadFullFlag
ADDITIONAL
READS
LAST WRITE
R
FIRST READ
FIRST WRITE
W
t
t
RFF
WFF
FF
C460A–10
Last READ to First WRITE Empty Flag
ADDITIONAL
WRITES
LAST READ
W
FIRST WRITE
FIRST READ
R
t
t
WEF
REF
EF
t
A
VALID
VALID
DATA OUT
C460A–11
Retransmit[10,11]
t
RTC
t
PRT
FL/RT
R,W
t
RTR
t
t
RTR
RTC
C460A–12
Notes:
10.
tRTC = tPRT + tRTR.
11. EF, HF, andFF maychange state during retransmit as a result of the offset of the read and write pointers, but flags willbe valid at tRTC, except for the CY7C46x-20
(Military), whose flags will be valid after tRTC + 10 ns.
6
CY7C460A/CY7C462A
CY7C464A/CY7C466A
Switching Waveforms[7] (continued)
Full Flag and Write Data Flow-Through Mode
R
t
t
t
WAF
WPF
W
t
WFF
RFF
FF
t
HD
DATA IN
DATA VALID
t
A
t
SD
DATA OUT
DATA VALID
C460A–1
Empty Flag and Read Data Flow-Through Mode
DATA IN
W
t
RAE
R
t
RPE
t
REF
EF
t
WEF
t
A
t
HWZ
DATA OUT
DATA VALID
C460A–14
7
CY7C460A/CY7C462A
CY7C464A/CY7C466A
Switching Waveforms[7] (continued)
Expansion TimingDiagrams
W
t
WR
t
t
XOL
XOH
[12]
XO (XI )
1
2
t
t
HD
HD
t
t
SD
SD
DATA VALID
DATA VALID
D
−
0
D
8
C460A–15
R
t
RR
t
XOH
t
XOL
[12]
XO (XI )
1
2
t
HZR
t
DVR
t
t
DVR
LZR
DATA
VALID
DATA
VALID
Q
Q
−
8
0
t
A
t
A
C460A–16
Note:
12. Expansion out of device 1 (XO1) is connected to expansion in of device 2 (XI2).
is available in standalone and width expansion modes. FF
goes LOW t after the falling edge of W, during the cycle in
Architecture
WFF
Resetting the FIFO
which the last available location is filled. Internal logic prevents
overrunning a full FIFO. Writes to a full FIFO are ignored and
Upon power-up, the FIFO must be reset with a master reset
(MR) cycle. This causes the FIFO to enter the empty condition
signified by the Empty flag (EF) being LOW, and both the Half
Full (HF), and Full flags (FF) being HIGH. Read (R) and Write
the write pointer is not incremented. FF goes HIGH t
a read from a full FIFO.
after
RFF
Reading Data from the FIFO
(W) must be HIGH t
/t
before and t
after the rising
RPW WPW
RMR
The falling edge of R initiates a read cycle if the EF is not LOW.
Data outputs (Q −Q ) are in a high-impedance condition be-
edge of MR for a valid reset cycle. If reading from the FIFO
after a reset cycle is attempted, the outputs will all be in the
high-impedance state.
0
8
tween read operations (R HIGH), when the FIFO is empty, or
when the FIFO is not the active device in the depth expansion
mode.
Writing Data to the FIFO
The availability of at least one empty location is indicated by a
HIGH FF. The falling edge of W initiates a write cycle. Data
When one word is in the FIFO, the falling edge of R initiates a
HIGH-to-LOW transition of EF. When the FIFO is empty, the
outputs are in a high-impedance state. Reads to an empty
FIFO are ignored and do not increment the read pointer. From
appearing at the inputs (D −D ) t before and t after the
0
8
SD
HD
rising edge of W will be stored sequentially in the FIFO.
the empty condition, the FIFO can be read t
write.
after a valid
WEF
The EF LOW-to-HIGH transition occurs t after the first
WEF
LOW-to-HIGH transition of W for an empty FIFO. HF goes
LOW t after the falling edge of W following the FIFO actu-
WHF
Retransmit
ally being half full. Therefore, the HF is active once the FIFO
is filled to half its capacity plus one word. HF will remain LOW
while less than one half of total memory is available for writing.
The retransmit feature is beneficial when transferring packets
of data. It enables the receipt of data to be acknowledged by
the receiver and retransmitted if necessary. The retransmit
(RT) input is active in the standalone and width expansion
modes. The retransmit feature is intended for use when a num-
The LOW-to-HIGH transition of HF occurs t
after the rising
RHF
edge of R when the FIFO goes from half full +1 to half full. HF
8
CY7C460A/CY7C462A
CY7C464A/CY7C466A
ber of writes equal-to-or-less-than the depth of the FIFO have
occurred since the last MR cycle. A LOW pulse on RT resets
the internal read pointer to the first physical location of the
Depth Expansion Mode (see Figure 1)
Depth expansion mode is entered when, during a MR cycle,
expansion out (XO) of one device is connected to expansion
in (XI) of the next device, with XO of the last device connected
to XI of the first device. In the depth expansion mode, the first
load (FL) input, when grounded, indicates that this is the first
part to be loaded. All other devices must have this pin HIGH.
To enable the correct FIFO, XO is pulsed LOW when the last
physical location of the previous FIFO is written to and is
pulsed LOW again when the last physical location is read. Only
one FIFO is enabled for Read and one is enabled for Write at
any given time. All other devices are in standby.
FIFO. R and W must both be HIGH while and t
after re-
RTR
transmit is LOW. With every read cycle after retransmit, previ-
ously accessed data is read and the read pointer incremented
until equal to the write pointer. Full, Half Full, and Empty flags
are governed by the relative locations of the read and write
pointers and are updated during a retransmit cycle. Data writ-
ten to the FIFO after activation of RT are transmitted also.
The full depth of the FIFO can be repeatedly retransmitted.
Standalone/Width Expansion Modes
FIFOs can also be expanded simultaneously in depth and
width. Consequently, any depth or width FIFO can be created
with word widths in increments of nine. When expanding in
depth, a composite FF is created by ORing the FFs together.
Likewise, a composite EF is created by ORing EFs together.
HF and RT functions are not available in depth expansion
mode.
Standalone and width expansion modes are set by grounding
expansion in (XI) and tying first load (FL) to V prior to a MR
CC
cycle. FIFOs can be expanded in width to provide word widths
greater than nine in increments of nine. During width expan-
sion mode, all control line inputs are common to all devices,
and flag outputs from any device can be monitored.
XO
R
W
EF
FL
FF
D
Q
0-8
0-8
9
9
9
CY7C460A
CY7C462A
CY7C464A
CY7C466A
V
CC
XI
XO
FULL
EF
FL
FF
EMPTY
9
CY7C460A
CY7C462A
CY7C464A
CY7C466A
XI
XO
*
EF
FL
FF
CY7C460A
CY7C462A
CY7C464A
CY7C466A
9
RS
XI
* FIRSTDEVICE
C460A–17
Figure 1. Depth Expansion
9
CY7C460A/CY7C462A
CY7C464A/CY7C466A
Ordering Information
8K x 9 Asynchronous FIFO
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
Package Type
10
CY7C460A-10JC
CY7C460A-10PC
CY7C460A-10PTC
CY7C460A-10JI
CY7C460A-15JC
CY7C460A-15PC
CY7C460A-15PTC
CY7C460A-25JC
CY7C460A-25PC
CY7C460A-25PTC
J65
P15
P21
J65
J65
P15
P21
J65
P15
P21
32-Lead Plastic Leaded Chip Carrier
28-Lead (600-Mil) Molded DIP
28-Lead (300-Mil) Molded DIP
32-Lead Plastic Leaded Chip Carrier
32-Lead Plastic Leaded Chip Carrier
28-Lead (600-Mil) Molded DIP
28-Lead (300-Mil) Molded DIP
32-Lead Plastic Leaded Chip Carrier
28-Lead (600-Mil) Molded DIP
28-Lead (300-Mil) Molded DIP
Commercial
Industrial
15
25
Commercial
Commercial
16K x 9 Asynchronous FIFO
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
Package Type
32-Lead Plastic Leaded Chip Carrier
28-Lead (600-Mil) Molded DIP
28-Lead (300-Mil) Molded DIP
32-Lead Plastic Leaded Chip Carrier
32-Lead Plastic Leaded Chip Carrier
28-Lead (600-Mil) Molded DIP
28-Lead (300-Mil) Molded DIP
32-Lead Plastic Leaded Chip Carrier
28-Lead (600-Mil) Molded DIP
28-Lead (300-Mil) Molded DIP
10
CY7C462A-10JC
J65
P15
P21
J65
J65
P15
P21
J65
P15
P21
Commercial
CY7C462A-10PC
CY7C462A-10PTC
CY7C462A-10JI
CY7C462A-15JC
CY7C462A-15PC
CY7C462A-15PTC
CY7C462A-25JC
CY7C462A-25PC
CY7C462A-25PTC
Industrial
15
25
Commercial
Commercial
32K x 9 Asynchronous FIFO
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
Package Type
32-Lead Plastic Leaded Chip Carrier
28-Lead (600-Mil) Molded DIP
10
CY7C464A-10JC
J65
P15
P21
J65
J65
P15
P21
L55
J65
P15
P21
Commercial
CY7C464A-10PC
CY7C464A-10PTC
CY7C464A-10JI
28-Lead (300-Mil) Molded DIP
32-Lead Plastic Leaded Chip Carrier
32-Lead Plastic Leaded Chip Carrier
28-Lead (600-Mil) Molded DIP
Industrial
15
25
CY7C464A-15JC
CY7C464A-15PC
CY7C464A-15PTC
CY7C464A-15LMB
CY7C464A-25JC
CY7C464A-25PC
CY7C464A-25PTC
Commercial
28-Lead (300-Mil) Molded DIP
32-Pin Rectangular Leadless Chip Carrier
32-Lead Plastic Leaded Chip Carrier
28-Lead (600-Mil) Molded DIP
Military
Commercial
28-Lead (300-Mil) Molded DIP
10
CY7C460A/CY7C462A
CY7C464A/CY7C466A
Ordering Information (continued)
64K x 9 Asynchronous FIFO
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
Package Type
10
CY7C466A-10JC
J65
P15
P21
J65
J65
P15
P21
L55
J65
P15
P21
32-Lead Plastic Leaded Chip Carrier
28-Lead (600-Mil) Molded DIP
Commercial
CY7C466A-10PC
CY7C466A-10PTC
CY7C466A-10JI
28-Lead (300-Mil) Molded DIP
32-Lead Plastic Leaded Chip Carrier
32-Lead Plastic Leaded Chip Carrier
28-Lead (600-Mil) Molded DIP
Industrial
15
25
CY7C466A-15JC
CY7C466A-15PC
CY7C466A-15PTC
CY7C466A-15LMB
CY7C466A-25JC
CY7C466A-25PC
CY7C466A-25PTC
Commercial
28-Lead (300-Mil) Molded DIP
32-Pin Rectangular Leadless Chip Carrier
32-Lead Plastic Leaded Chip Carrier
28-Lead (600-Mil) Molded DIP
Military
Commercial
28-Lead (300-Mil) Molded DIP
11
CY7C460A/CY7C462A
CY7C464A/CY7C466A
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Switching Characteristics
Parameter
Subgroups
1, 2, 3
Parameter
Subgroups
9, 10, 11
V
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
OH
RC
A
V
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
OL
V
IH
RR
PR
V Max.
IL
I
I
I
I
I
I
IX
LZR
DVR
HZR
WC
CC
SB1
SB2
OS
OZ
PW
HWZ
WR
SD
HD
MRSC
PMR
RMR
RPW
WPW
RTC
PRT
RTR
EFL
HFH
FFH
REF
RFF
WEF
WFF
WHF
RHF
RAE
RPE
WAF
WPF
XOL
XOH
Document #: 38-00627-A
12
CY7C460A/CY7C462A
CY7C464A/CY7C466A
Package Diagrams
32-Lead Plastic Leaded Chip Carrier J65
51-85002-B
32-Pin Rectangular Leadless Chip Carrier L55
MIL-STD-1835 C-12
51-80068
13
CY7C460A/CY7C462A
CY7C464A/CY7C466A
Package Diagrams (continued)
28-Lead (600-Mil) Molded DIP P15
51-85017-A
28-Lead (300-Mil) Molded DIP P21
51-85014-B
© Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
相关型号：
©2020 ICPDF网 联系我们和版权申明