CYBUS3384LMB [ETC]
Bus Switch ; 总线开关\n
| 型号： | CYBUS3384LMB |
| 厂家： | 
ETC |
| 描述： | Bus Switch
|
| 文件： | 总8页 (文件大小：190K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1CYBUS3L384
CYBUS3384
CYBUS3L384
Dual 5-Bit Bus Switch
Features
Functional Description
• Zero propagation delay
The CYBUS3384 and CYBUS3L384 are ten-bit, two-port bidi-
rectional bus switches that allow one bus to be connected di-
rectly to, or isolated from, another without introducing addition-
al propagation delay or ground noise. The input and output
voltage levels allow direct interface with TTL and CMOS de-
• 2Ω switches connect inputs to outputs
• Direct bus connection when switches are ON
• High (>500 Meg Ω) resistance when switch is OFF
• Performs bidirectional translator function between
3.3V and 5.0V power supplies
• CMOS for low power dissipation
• Edge-rate control circuitry for significantly improved
noise characteristics
vices. Two bus enable signals, BE and BE , turn on the upper
1
2
and lower five bits, respectively.
Designed with a low resistance of 2Ω, the CYBUS3384 and
CYBUS3L384 are ideal for use in VME or other high DC drive
applications.
• Inputs and outputs interface with 5.0V CMOS, TTL, or
3.3V CMOS
• ESD > 2000V
The power-off disable feature enables modules and cards to
be either inserted or withdrawn from operating equipment
without shutting down power. Additionally, they facilitate bidi-
rectional interfacing between 3.3V and 5V systems by placing
• Power-off disable
a single diode in series with the 5V V line and a resistor from
pin 24 to ground.
CC
CYBUS3L384
• Low power version
The CYBUS3384 and CYBUS3L384 are also suitable for
small signal analog application where crosstalk and off isola-
tion performance of –66 dB at 50 MHz is required.
The CYBUS3L384 is a low-power version of the CYBUS3384
with a typical I of 0.2 µA.
CC
Logic Block Diagram
Pin Configurations
BE
1
DIP/SOIC/QSOP
Top View
BE
2
1
BE
1
24
V
CC
A
B
B
B
0
0
1
2
2
3
4
5
6
B
B
9
23
22
21
0
A
0
A
9
A
1
A
8
A
1
B
B
1
20
19
18
17
16
A
2
8
B
A
B
2
7
A
3
A
7
B
B
2
7
8
9
3
4
A
3
A
6
A
4
B
3
4
B
6
B
10
11
12
B
A
5
15
14
A
5
B
B
B
5
6
A
4
5
GND
BE
2
13
A
6
BUS3384-2
A
7
7
8
9
A
8
B
B
BUS3384-1
A
9
Function Table[1]
Pin Description
Inputs
Name
Description
BE
H
L
BE
H
H
L
B
B
Function
Non-connect
Connect
A
B
Bus A, Inputs or Outputs
Bus B, Inputs or Outputs
Bus Switch Enable
1
2
0–4
5–9
High-Z
High-Z
A
High-Z
BE , BE
0–4
1
2
H
L
High-Z
A
A
Connect
5–9
L
A
Connect
0–4
5–9
Note:
1. H = HIGH Voltage Level. L = LOW Voltage Level. X = Don’t Care.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
May 1994 – Revised March 1996
•
408-943-2600
CYBUS3384
CYBUS3L384
Maximum Ratings[2, 3]
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Power Dissipation.......................................................... 0.5W
Static Discharge Voltage ........................................... >2001V
(per MIL-STD-883, Method 3015)
Storage Temperature ................................. –65°C to +165°C
Ambient Temperature with
Power Applied............................................. –65°C to +135°C
Operating Range
Supply Voltage to Ground Potential............... –0.5V to +7.0V
DC Input Voltage............................................ –0.5V to +7.0V
DC Output Voltage......................................... –0.5V to +7.0V
DC Output Current (Maximum Sink Current/Pin).......120 mA
Ambient
Range
Commercial
Military
Temperature
–40°C to +85°C
–55°C to +125°C
V
CC
4.0V to 5.5V
4.0V to 5.5V
Electrical Characteristics Over the Operating Range
[4]
Parameter
Description
Input HIGH Voltage
Input LOW Voltage
Test Conditions
Control Inputs Only
Min.
Typ.
Max.
Unit
V
V
V
V
V
2.0
IH
IL
H
Control Inputs Only
Control Inputs Only
0.8
V
[5]
Hysteresis
0.2
–0.7
2
V
Input Clamp Diode Voltage
V
V
V
V
V
V
V
=Min., I =–18 mA
–1.2
4
V
IK
CC
CC
CC
CC
CC
CC
CC
IN
[6]
R
Switch On Resistance
=4.75V, V =0.0V, I =30 mA
W
ON
IN
ON
=4.75V, V =2.4V, I =15 mA
4
8
W
IN
ON
I
I
I
I
Input Leakage Current
Off State Current (High-Z)
Power-Off Disable
=Max., V =V
CC
±1
±1
±1
µA
µA
µA
mA
IN
IN
=Max., V
=0.5V
OUT
0.001
100
OZ
=0V, V
=4.5V, V =V
IN CC
OFF
OS
OUT
[7]
Output Short Circuit Current
=Max., V
=0.0V
OUT
On Resistance vs. V @ 4.75 V
IN
CC
14.00
12.00
10.00
8.00
R Ω
ON
6.00
4.00
2.00
0.00
0.00
0.50
1.00
1.50
2.00
V , Volts
2.50
3.00
3.50
IN
Notes:
2. Unless otherwise noted, these limits are over the operating free-air temperature range.
3. Unused inputs must always be connected to an appropriate logic voltage level, preferably either VCC or ground.
4. Typical values are at VCC=5.0V, TA=+25°C ambient.
5. This parameter is guaranteed but not tested.
6. Measured by voltage drop between A and B pin at indicated current through the switch. On resistance is determined by the lower of the voltages on pin A
or pin B.
7. Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample
and hold techniques are preferable in order to minimize internal chip heating and more accurately reflect operational values. Otherwise prolonged shorting
of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter
tests, IOS tests should be performed last.
2
CYBUS3384
CYBUS3L384
Capacitance[6]
[4]
Parameter
Description
Typ.
3
Max.
Unit
pF
C
C
Input Capacitance
Output Capacitance
4
8
IN
7
pF
OUT
Power Supply Characteristics
[8]
[4]
Parameter
Description
Test Conditions
=Max., V ≤GND or V , f=0
Typ.
Max.
3.0
Unit
I
Quiescent Power Supply Current
V
3384
0.2
0.2
µA
µA
CC
CC
IN
CC
3L384
3.0
∆I
Quiescent Power Supply Current
(Input HIGH)
V
V
=Max., V =3.4V, f=0, Per Control Input
2.0
mA
CC
CCD
C
CC
IN
[9]
[10]
I
I
Dynamic Power Supply Current
=Max., Control Input Toggling,
0.12
mA/
MHz
CC
@ 50% Duty Cycle, A & B Pins Open
[11, 12]
Total Power Supply Current
V
=Max.,
3384
4.4
4.4
mA
mA
CC
Two Control Inputs Toggling, @ 50%
Duty Cycle, f =10 MHz, V =3.4V
3L384
1
IN
[13]
Switching Characteristics Over the Operating Range
Military
Commercial
Parameter
Description
Propagation Delay
A to B
Min.
Max.
Min.
Max.
Unit
t
t
0.25
.25
6.5
5.5
1.5
ns
ns
ns
pC
PLH
PHL
[14, 15]
t
t
Switch Turn On Delay,
1.5
1.5
7.5
6.5
1.5
1.5
1.5
PZH
PZL
[13]
BE , BE to A, B
1
2
t
t
Switch Turn Off Delay,
PHZ
PHZ
[13, 14]
BE , BE to A, B
1
2
[16, 17]
|Q |
Charge Injection, Typical
ci
Notes:
8. For conditions shown as MIN or MAX use the appropriate values specified under DC specifications.
9. Per TTL driven input (VIN=3.4V); A and B pins do not contribute to ICC. All other inputs at VCC or GND.
10. This current applies to the control inputs only and represents the current required to switch internal capacitance at the specified frequency. The A and B inputs
generate no significant AC or DC currents as they transition. This parameter is not tested but is guaranteed by design.
11. IC
IC
=
=
=
=
=
=
=
=
=
=
IQUIESCENT + IINPUTS + IDYNAMIC
ICC+∆ICCDHNT+ICCD(f0/2 + f1N1)
Quiescent Current with CMOS input levels
Power Supply Current for a TTL HIGH input (VIN=3.4V)
Duty Cycle for TTL inputs HIGH
ICC
∆ICC
DH
NT
ICCD
f0
f1
N1
Number of TTL inputs at DH
Dynamic Current caused by an input transition pair (HLH or LHL)
Clock frequency for registered devices, otherwise zero
Input signal frequency
Number of inputs changing at f1
12. Note that activity on A or B inputs do not contribute to IC. The switches merely connect and pass through activity on these pins.
13. See Test Circuit and Waveform. Minimum limits are guaranteed but not tested.
14. This parameter is guaranteed by design but not tested.
15. The bus switch contributes no propagation delay other than the RC delay of the on resistance of the switch and the load capacitance. The time constant for
the switch is much smaller than the rise/fall times of typical driving signals, it adds very little propagation delay to the system. Propagation delay of the bus
switch when used in a system is determined by the driving circuit on the driving side of the switch and its interaction with the load on the driven side.
16. Measured at switch turn off, A to C, load=50 pF in parallel with 10 meg scope probe, VIN at A=0.0V.
17. Tested initially and after any design change which may affect this parameter.
3
CYBUS3384
CYBUS3L384
Ordering Information CYBUS3384
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
CYBUS3384PC
Package Type
24-Lead (300-Mil) Molded DIP
24-Lead (150-Mil) QSOP
0.25
P13/13A
Q13
Commercial
CYBUS3384QC
CYBUS3384SOC
CYBUS3384DMB
CYBUS3384LMB
S13
24-Lead (300-Mil) Molded SOIC
24-Lead (300-Mil) CerDIP
0.25
D14
Military
L64
28-Square Leadless Chip Carrier
Ordering Information CYBUS3L384
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
CYBUS3L384PC
Package Type
24-Lead (300-Mil) Molded DIP
24-Lead (150-Mil) QSOP
0.25
P13/13A
Q13
Commercial
CYBUS3L384QC
CYBUS3L384SOC
S13
24-Lead (300-Mil) Molded SOIC
A
0
B
0
5.0
A
1
B
1
1K ohm
10K ohm
10 meg
A
2
B
2
4.0
3.0
A
3
B
3
B
4
A
4
BE
1
2.0
1.0
0
A
B
5
5
A
6
B
B
B
B
6
7
8
9
A
7
A
8
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
A
9
V , Volts
IN
BE
2
BUS3384-4
BUS3384-3
Figure 1. CYBUS3384
Figure 2. V
vs. Volts
OUT
effective resistance (R ) such that further increases to input
voltage no longer increase the output voltage (see Figure 2).
Application Information
ON
The CYBUS3384 is a ten-channel bidirectional solid state bus
switch with a “near zero” propagation delay.
When either the input or output of the CYBUS3384 is near zero
volts and the gate is at V , the device is fully on, (low resis-
CC
The CYBUS3384 is organized into two groups of five N-Chan-
nel MOSFETs. Each group has an independent control input
for output enable (see Figure 1). Because the N-channel
MOSFET is physically symmetric, the device pin can act as an
input or an output.
tance) and available to pass large currents in either direction.
In this condition, the CYBUS3384 inputs are directly connect-
ed to the outputs.
The CYBUS3384 provides no signal drive itself. As a result the
rise and fall times of the CYBUS3384 outputs are determined
by the device driving the CYBUS3384 inputs rather than the
CYBUS3384 itself.
The two enable input (BE and BE ) sense TTL level signals
1
2
and drive the gates of the N-channel MOSFETs to VCC. With
the gate at V , the output voltage will follow the input voltage
CC
The propagation delay contributed by the CYBUS3384 is es-
up to V
minus the threshold voltage. At this point the
CC
sentially zero when the N-channel gate is at V
.
CC
N-channel MOSFET begins to turn off, rapidly increasing the
When the device is unpowered, the CYBUS3384 draws no
current from the I/O or control inputs, and there is no current
4
CYBUS3384
CYBUS3L384
path from the I/O or control to the power pins. There are no
back power or current drain problems when the device is un-
powered.
5V
STEP-UP REG.
3.3V
5V
The CYBUS3384 provides an ideal interface between 5V and
3.3V components, since the CYBUS3384 provides no signal
V
CC
CYBUS3384
drive, the I
demands are small, limited to AC switching of
CC
BUS3384-6
the N-channel gates, control circuitry, and a minute amount of
I/O leakage. Due to the low current demands of the
CYBUS3384, it is possible to lower the CYBUS3384 VCC from
a standard 5.0V supply with a small, inexpensive diode and a
resistor to provide a low-current full-bidirectional signal com-
patibility between 5V logic family signals and 3.3V logic family
signals.
Figure 4. 3.3V/5V Supply Switch
Low Power Bus Isolation
Modern battery-operated systems rely on internal power man-
agement schemes to disconnect power from subsystems not
in use. Usually the subsystem bus input ESD protection cir-
cuits consist of a pair of clamp diodes to limit input voltage
By adding a small, inexpensive diode and a resistor, the
excursions to a maximum of V +Vt and –Vt (see Figure 5).
CYBUS3384 V
supply voltage can be shifted to 4.3V as
CC
CC
Removing power from these causes the VCC ESD clamp di-
ode to connect the dead circuit inputs to GND, often signifi-
cantly increasing bus loading and power dissipation (see Fig-
ure 6). The CYBUS3384 placed on the input of the load to be
disconnected effectively prevents bus loading and its associ-
ated problems.
shown in Figure 3. 5V signals will then be limited to 3.3V as
they pass through the CYBUS3384. 3.3V signals will pass
back through the CYBUS3384 unaltered and provide compat-
ibility with 5V TTL input requirements. Note that the conversion
is bidirectional and is limited to 3.3V independent of which side
is driven to 5V. The CYBUS3384 could convert 5V signals for
use on a 3.3V bus of convert a 5V bus to signals compatible
with 3.3V components.
V
CC
3.3V/5V Supply Operation
In certain system applications, the CYBUS3384 must operate
from either a 5V or 3.3V power supply, depending on the state
of the system. If this occurs, the circuit shown in Figure 4 can
be added to step the 3.3V supply up to a nominal 5V level. The
low-cost, high-efficiency Step Up regulator shown in the figure
is available for Linear Technology, Maxim, and other suppliers.
The diode arrangement will automatically select the active
supply. Standard silicon diodes can be used because the
V
t
V
t
CYBUS3384 V is specified at 4.0V.
CC
BUS3384-7
+5V
Figure 5. Gate Input (Power ON)
V
CC
5.0V EPROM
3.3V LOGIC
V
t
4.3 V
CC
5.0V BUS
CHIP SET
3.3V CPU
V
t
5.0V I/O
5.0V I/O
BUS3384-5
CYBUS3384
3.3V < – > 5.0V
CONVERTER
3.3V DRAM
BUS3384-8
Figure 6. Gate Input (Power OFF)
Figure 3. System with CYBUS3384
as 5V TTL to 3V Converter
5
CYBUS3384
CYBUS3L384
Processor 1
BUS1
Static RAM
Arbiter
ADDR/Enables
CYBUS3384
BE /BE
1
2
Processor 2
BUS2
CYBUS3384
CYBUS3384
CYBUS3384
CYBUS3384
Enables 1
Address 1
Enables 2
Address 2
BUS3384-9
Figure 7. High Speed Dual Port RAM
High Speed Dual Port RAM
current, a 1 volt “droop” from the initial voltage level would take
50 microseconds. Figure 9 shows the addition of a physical
capacitor if there is insufficient stray capacitance. Figure 10
shows an active bus termination capable of sustaining the pro-
grammed logic for an indefinite period of time in the presence
As shown in Figure 7, a high-speed, dual-port memory is im-
plemented using a combination of commodity SRAM, a simple
arbitration circuit, and the CYBUS3384. Processor 1 is the
system host processor while Processor 2 is dedicated periph-
eral processor (such as a DSP for acquisitioning and manipu-
lating data). Either processor can own the SRAM by first read-
ing the BUSY bit to determine if the SRAM is available. If so,
the requesting processor takes control by writing the OWN bit
(which redirects the bus through the CYBUS3384s and sets
the BUSY bit notifying the other bus the SRAM is not avail-
able). Processor 1 owns the bus and may now access the
SRAM as needed. When finished, Processor 1 resets the
OWN bit releasing the SRAM. The SRAM access sequence is
identical for Processor 2. In this application, the CYBUS3384
saves 10 ns compared to using an F244 address buffer and
an F245 data bus transceiver. This, in turn, allows the use of
a slower, more available SRAM, resulting in lower system cost
and power savings.
of V
.
CC
RAM or Other Logic
Stray Cap. (50pF)
CYBUS3384
BUS3384-10
Figure 8. Latch Variation with Spray Capacitance
RAM or Other Logic
CYBUS3384
Selectable Termination Loads
C1
In some applications, it is desirable to vary the characteristic
termination impedance as the system configuration changes.
This is a common problem in automatic test equipment appli-
cations. Because of their low ON resistance, miniature relays
are often used to switch termination loads. A single
CYBUS3384 can replace as many as 10 such relays resulting
in faster switching operation, lower power, and significant cost
savings.
BUS3384-11
Figure 9. Latch Variation with Physical Capacitor
RAM or Other Logic
CYBUS3384
FCT244T
Fast Latch
Figures 8 and 9 show variations of a latch having a sub 1-ns
propagational delay time using the CYBUS3384 in combina-
tion with other components. This circuit has the advantage of
being four to ten times faster than an equivalent implementa-
tion using a 373 latch—and with no added noise. Figure 8
relies on the stray capacitance of the bus to maintain data
when the CYBUS3384 opens. Assuming 50-pF stray capaci-
tance at room temperature and a 1 microampere input leakage
BUS3384-12
1K
Figure 10. Active Bus Termination
Document #: 38–00355
6
CYBUS3384
CYBUS3L384
Package Diagrams
24-Lead (300-Mil) CerDIP D14
MIL–STD–1835 D–9 Config.A
28-Square Leadless Chip Carrier L64
MIL–STD–1835 C–4
24-Lead (300-Mil) Molded DIP P13/P13A
7
CYBUS3384
CYBUS3L384
Package Diagrams (Continued)
24-Lead Quarter Size Outline Q13
24-Lead (300-Mil) Molded SOIC S13
© Cypress Semiconductor Corporation, 1996. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of anycircuitry other than circuitry embodied in a CypressSemiconductor product. Nor does it conveyor imply any license under patent or other rights. CypressSemiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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