DAC0831LCN [ETC]
IC-8-BIT DAC ; IC- 8位DAC\n
| 型号： | DAC0831LCN |
| 厂家： | 
ETC |
| 描述： | IC-8-BIT DAC
|
| 文件： | 总20页 (文件大小：397K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
February 1995
DAC0830/DAC0831/DAC0832 8-Bit mP
Compatible, Double-Buffered D to A Converters
General Description
The DAC0830 is an advanced CMOS/Si-Cr 8-bit multiplying
Features
Y
Double-buffered, single-buffered or flow-through digital
data inputs
DAC designed to interface directly with the 8080, 8048,
8085, Z80 , and other popular microprocessors. A deposit-
Y
Easy interchange and pin-compatible with 12-bit
DAC1230 series
É
ed silicon-chromium R-2R resistor ladder network divides
the reference current and provides the circuit with excellent
temperature tracking characteristics (0.05% of Full Scale
Range maximum linearity error over temperature). The cir-
cuit uses CMOS current switches and control logic to
achieve low power consumption and low output leakage
current errors. Special circuitry provides TTL logic input volt-
age level compatibility.
Y
Y
Direct interface to all popular microprocessors
Linearity specified with zero and full scale adjust onlyÐ
NOT BEST STRAIGHT LINE FIT.
Y
g
Works with 10V reference-full 4-quadrant
multiplication
Y
Y
Can be used in the voltage switching mode
Logic inputs which meet TTL voltage level specs (1.4V
logic threshold)
Double buffering allows these DACs to output a voltage cor-
responding to one digital word while holding the next digital
word. This permits the simultaneous updating of any num-
ber of DACs.
Y
Y
Operates ‘‘STAND ALONE’’ (without mP) if desired
Available in 20-pin small-outline or molded chip carrier
package
The DAC0830 series are the 8-bit members of a family of
microprocessor-compatible DACs (MICRO-DACTM). For ap-
plications demanding higher resolution, the DAC1000 series
(10-bits) and the DAC1208 and DAC1230 (12-bits) are avail-
able alternatives.
Key Specifications
Y
Current settling time
1 ms
8 bits
Y
Resolution
Y
Linearity
(guaranteed over temp.)
8, 9, or 10 bits
Y
Gain Tempco
0.0002% FS/ C
§
20 mW
Y
Low power dissipation
BI-FETTM and MICRO-DACTM are trademarks of National Semiconductor Corporation.
Y
Single power supply
5 to 15 V
DC
Z80É is a registered trademark of Zilog Corporation.
Typical Application
C1230,
TL/H/5608–1
Connection Diagrams (Top Views)
Dual-In-Line and
Small-Outline Packages
Molded Chip Carrier Package
²
This is necessary for the
12-bit DAC1230 series to
permit interchanging from
an 8-bit to a 12-bit DAC
with No PC board changes
and no software changes,
See applications section.
TL/H/5608–22
TL/H/5608–21
C
1995 National Semiconductor Corporation
TL/H/5608
RRD-B30M115/Printed in U. S. A.
Absolute Maximum Ratings (Notes 1 & 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Lead Temperature (soldering, 10 sec.)
Dual-In-Line Package (plastic)
Dual-In-Line Package (ceramic)
Surface Mount Package
260 C
§
300 C
§
Supply Voltage (V
)
CC
17 V
DC
Vapor Phase (60 sec.)
Infrared (15 sec.)
215 C
§
Voltage at Any Digital Input
Voltage at V Input
V
CC
to GND
220 C
§
g
25V
REF
b
a
65 C to 150 C
Storage Temperature Range
Package Dissipation
§
§
Operating Conditions
Temperature Range
s
s
T
MAX
T
MIN
T
A
e
at T
25 C (Note 3)
500 mW
§
DC Voltage Applied to
A
a
0 C to 70 C
Part numbers with ‘LCN’ suffix
Part numbers with ‘LCWM’ suffix
Part numbers with ‘LCV’ suffix
Part numbers with ‘LCJ’ suffix
Part numbers with ‘LJ’ suffix
Voltage at Any Digital Input
§
§
§
§
§
§
a
0 C to 70 C
b
I
or I (Note 4)
OUT2
100 mV to V
CC
OUT1
a
0 C to 70 C
§
ESD Susceptability (Note 14)
800V
b
a
40 C to 85 C
§
55 C to 125 C
b
a
§
§
to GND
V
CC
e
25 C.
§
Electrical Characteristics V
10.000 V unless otherwise noted. Boldface limits apply over tempera-
DC
REF
e
s
s
T . For all other limits T
MAX
ture, T
MIN
T
A
A
e
g
5%
V
5 V
DC
12 V
CC
e
e
V
4.75 V
DC
CC
e
g
5%
V
5%
CC
to 15 V
DC
V
15.75 V
DC
CC
g
See
Limit
Units
DC
Parameter
Conditions
Note
Tested
Limit
Typ
Design Limit
(Note 6)
(Note 12)
(Note 5)
CONVERTER CHARACTERISTICS
Resolution
8
8
8
bits
Linearity Error Max
Zero and full scale adjusted
s
a
4, 8
s
b
10V
V
10V
REF
DAC0830LJ & LCJ
0.05
0.2
0.05
0.1
0.05
0.2
% FSR
% FSR
% FSR
% FSR
% FSR
DAC0832LJ & LCJ
DAC0830LCN, LCWM & LCV
DAC0831LCN
0.05
0.1
0.2
DAC0832LCN, LCWM & LCV
0.2
Differential Nonlinearity
Max
Zero and full scale adjusted
s
a
4, 8
s
b
10V
V
10V
REF
DAC0830LJ & LCJ
DAC0832LJ & LCJ
DAC0830LCN, LCWM & LCV
DAC0831LCN
0.1
0.4
0.1
0.1
0.4
0.1
0.2
0.4
% FSR
% FSR
% FSR
% FSR
% FSR
0.2
DAC0832LCN, LCWM & LCV
0.4
s
b
Monotonicity
10V
s
V
LJ & LCJ
4
7
8
8
8
bits
bits
REF
a
10V
LCN, LCWM & LCV
8
Gain Error Max
Using Internal R
s
fb
a
g
g
g
1
0.2
1
% FS
%
s
b
10V
V
REF
10V
Gain Error Tempco Max
Power Supply Rejection
Using internal R
fb
0.0002
0.0006
FS/ C
§
All digital inputs latched high
e
V
CC
14.5V to 15.5V
11.5V to 12.5V
4.5V to 5.5V
0.0002
0.0006
0.013
0.0025
%
FSR/V
0.015
20
Reference Input
Max
Min
15
15
20
10
kX
kX
10
e
All data inputs latched low
e
20 Vp-p, f 100 kHz
Output Feedthrough Error
V
REF
3
mVp-p
2
e
§
Electrical Characteristics V
10.000 V unless otherwise noted. Boldface limits apply over tempera-
DC
25 C. (Continued)
REF
s
s
T . For all other limits T
MAX
e
ture, T
MIN
T
A
A
e
g
5%
V
5 V
DC
CC
e
e
V
4.75 V
DC
CC
e
g
5%
V
12 V
5%
CC
to 15 V
DC
V
15.75 V
DC
CC
g
See
Limit
Units
DC
Parameter
Conditions
Note
Tested
Limit
Typ
Design Limit
(Note 6)
(Note 12)
(Note 5)
CONVERTER CHARACTERISTICS (Continued)
Output Leakage
Current Max
I
All data inputs
latched low
LJ & LCJ
10
100
100
100
OUT1
nA
nA
pF
pF
LCN, LCWM & LCV
50
I
All data inputs
latched high
LJ & LCJ
100
100
100
OUT2
LCN, LCWM & LCV
50
Output
I
I
All data inputs
latched low
45
OUT1
Capacitance
115
OUT2
I
I
All data inputs
latched high
130
30
OUT1
OUT2
DIGITAL AND DC CHARACTERISTICS
Digital Input
Voltages
Max
Logic Low
LJ
4.75V
15.75V
4.75V
0.6
0.8
0.7
0.8
0.95
LJ
LCJ
LCJ
V
V
DC
15.75V
LCN, LCWM, LCV
0.8
Min
Logic High
LJ & LCJ
2.0
2.0
2.0
DC
LCN, LCWM, LCV
1.9
k
Digital Input
Currents
Max
Digital inputs 0.8V
LJ & LCJ
LCN, LCWM, LCV
b
b
b
b
b
50
200
200
200
mA
mA
160
l
Digital inputs 2.0V
a
a
a
a
LJ & LCJ
0.1
10
10
10
mA
LCN, LCWM, LCV
8
Supply Current
Drain
Max
LJ & LCJ
1.2
3.5
3.5
2.0
mA
LCN, LCWM, LCV
1.7
3
e
§
Electrical Characteristics V
10.000 V unless otherwise noted. Boldface limits apply over tempera-
DC
25 C. (Continued)
REF
s
s
T
MAX
e
ture, T
T
A
. For all other limits T
A
MIN
e
e
5 V
DC
g
V
12 V
DC
5%
V
CC
CC
to 15 V
e
e
4.75 V
DC
V
15.75 V
DC
V
CC
CC
g
g
5%
5%
DC
See
Note
Limit
Units
Symbol
Parameter
Conditions
Tested
Limit
Design
Limit
Tested
Limit
Design
Limit
Typ
Typ
(Note 12)
(Note 12)
(Note 5)
(Note 6)
(Note 5) (Note 6)
AC CHARACTERISTICS
e
e
e
e
e
e
e
e
e
e
e
e
t
t
t
t
t
t
Current Setting
Time
V
V
V
V
0V, V
0V, V
0V, V
0V, V
0V, V
0V, V
5V
s
IL
IL
IL
IL
IL
IL
IH
IH
IH
IH
IH
IH
1.0
1.0
ms
Write and XFER
Pulse Width Min
5V 11
9
100
250
375
600
W
320
320
320
900
900
900
Data Setup Time
Min
5V
9
100
250
375
600
DS
DH
CS
CH
320
900
Data Hold Time
Min
5V
9
30
50
ns
30
50
Control Setup Time V
Min
5V
9
110
0
250
600
0
900
320
320
10
1100
1100
Control Hold Time
Min
V
5V
9
0
0
0
0
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.
Note 2: All voltages are measured with respect to GND, unless otherwise specified.
Note 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by T
b
T
, i , and the ambient temperature, T . The maximum
JMAX JA
A
e
125 C (plastic) or 150 C (ceramic), and the typical junction-to-ambient thermal resistance of the J package when board mounted is 80 C/W. For
allowable power dissipation at any temperature is P
(T
)/i or the number given in the Absolute Maximum Ratings, whichever is lower. For this
A JA
D
JMAX
e
the N package, this number increases to 100 C/W and for the V package this number is 120 C/W.
device, T
JMAX
§
§
§
§
Note 4: For current switching applications, both I
§
must go to ground or the ‘‘Virtual Ground’’ of an operational amplifier. The linearity error is
and I
OUT1
. For example, if V
OUT2
d
e
10V then a 1 mV offset, V , on I
OS
degraded by approximately V
OS
V
or I
will introduce an additional 0.01% linearity error.
OUT2
REF
REF
OUT1
Note 5: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 6: Guaranteed, but not 100% production tested. These limits are not used to calculate outgoing quality levels.
e
e
g
g
Note 7: Guaranteed at V
REF
10 V
DC
and V
1 V .
DC
REF
Note 8: The unit ‘‘FSR’’ stands for ‘‘Full Scale Range.’’ ‘‘Linearity Error’’ and ‘‘Power Supply Rejection’’ specs are based on this unit to eliminate dependence on a
particular V value and to indicate the true performance of the part. The ‘‘Linearity Error’’ specification of the DAC0830 is ‘‘0.05% of FSR (MAX)’’. This
REF
guarantees that after performing a zero and full scale adjustment (see Sections 2.5 and 2.6), the plot of the 256 analog voltage outputs will each be within
c
0.05%
V
REF
of a straight line which passes through zero and full scale.
Note 9: Boldface tested limits apply to the LJ and LCJ suffix parts only.
b
9
3
c
e
e
REF
c
10V corresponds to a zero error of (100 10
c c
20 10 ) 100/10 which is 0.02% of FS.
Note 10: A 100nA leakage current with R
20k and V
fb
Note 11: The entire write pulse must occur within the valid data interval for the specified t , t , t , and t to apply.
S
W
DS DH
Note 12: Typicals are at 25 C and represent most likely parametric norm.
§
Note 13: Human body model, 100 pF discharged through a 1.5 kX resistor.
4
Switching Waveform
TL/H/5608–2
Definition of Package Pinouts
Control Signals (All control signals level actuated)
Chip Select (active low). The CS in combina-
feedback resistor for the external op amp which is
used to provide an output voltage for the DAC.
This on-chip resistor should always be used (not
an external resistor) since it matches the resistors
which are used in the on-chip R-2R ladder and
tracks these resistors over temperature.
CS:
tion with ILE will enable WR .
1
Input Latch Enable (active high). The ILE in
ILE:
combination with CS enables WR .
1
Write 1. The active low WR is used to load the
WR :
1
1
digital input data bits (DI) into the input latch.
V
V
:
Reference Voltage Input. This input connects an
external precision voltage source to the internal R-
REF
The data in the input latch is latched when WR
is high. To update the input latchÐCS and WR
must be low while ILE is high.
1
1
2R ladder. V can be selected over the range of
REF
10 to 10V. This is also the analog voltage in-
a
b
put for a 4-quadrant multiplying DAC application.
WR :
2
Write 2 (active low). This signal, in combination
with XFER, causes the 8-bit data which is avail-
able in the input latch to transfer to the DAC
register.
:
Digital Supply Voltage. This is the power supply
a
CC
a
pin for the part. V can be from 5 to 15V
CC
.
DC
a
Operation is optimum for 15V
.
DC
XFER:
Transfer control signal (active low). The
XFER will enable WR .
GND:
The pin 10 voltage must be at the same ground
potential as I and I for current switching
2
OUT1 OUT2
applications. Any difference of potential (V
10) will result in a linearity change of
pin
OS
Other Pin Functions
DI -DI : Digital Inputs. DI is the least significant bit
0
7
0
V
pin 10
REF
(LSB) and DI is the most significant bit (MSB).
7
OS
I
I
:
DAC Current Output 1. I
is a maximum
OUT1
OUT1
3V
for a digital code of all 1’s in the DAC register,
and is zero for all 0’s in DAC register.
e
For example, if V
offset from I
OUT1
10V and pin 10 is 9mV
the linearity change
REF
and I
OUT2
:
DAC Current Output 2. I
is a constant
constant (I full
OUT2
OUT2
will be 0.03%.
Pin 3 can be offset
change, but the logic input threshold will shift.
a
I
OUT2
e
minus I
, or I
OUT1 OUT1
g
100mV with no linearity
scale for a fixed reference voltage).
Feedback Resistor. The feedback resistor is
provided on the IC chip for use as the shunt
R
:
fb
5
Linearity Error
TL/H/5608–3
a) End point test after
zero and fs adj.
b) Best straight line
c) Shifting fs adj. to pass
best straight line test
Definition of Terms
Resolution: Resolution is directly related to the number of
switches or bits within the DAC. For example, the DAC0830
Settling Time: Settling time is the time required from a code
g
transition until the DAC output reaches within (/2LSB of
the final output value. Full-scale settling time requires a zero
to full-scale or full-scale to zero output change.
8
has 2 or 256 steps and therefore has 8-bit resolution.
Linearity Error: Linearity Error is the maximum deviation
from a straight line passing through the endpoints of the
DAC transfer characteristic. It is measured after adjusting
for zero and full-scale. Linearity error is a parameter intrinsic
to the device and cannot be externally adjusted.
Full-Scale Error: Full scale error is a measure of the output
error between an ideal DAC and the actual device output.
b
Ideally, for the DAC0830 series, full-scale is V
1LSB.
REF
e
10V and unipolar operation, V
FULL-SCALE
e
For
V
REF
b
e
10.0000V 39mV 9.961V. Full-scale error is adjustable to
zero.
National’s linearity ‘‘end point test’’ (a) and the ‘‘best
straight line’’ test (b,c) used by other suppliers are illustrated
above. The ‘‘end point test’’ greatly simplifies the adjust-
ment procedure by eliminating the need for multiple itera-
tions of checking the linearity and then adjusting full scale
until the linearity is met. The ‘‘end point test’’ guarantees
that linearity is met after a single full scale adjust. (One ad-
justment vs. multiple iterations of the adjustment.) The ‘‘end
point test’’ uses a standard zero and F.S. adjustment proce-
dure and is a much more stringent test for DAC linearity.
Differential Nonlinearity: The difference between any two
consecutive codes in the transfer curve from the theoretical
1 LSB is differential nonlinearity.
Monotonic: If the output of a DAC increases for increasing
digital input code, then the DAC is monotonic. An 8-bit DAC
which is monotonic to 8 bits simply means that increasing
digital input codes will produce an increasing analog output.
Power Supply Sensitivity: Power supply sensitivity is a
measure of the effect of power supply changes on the DAC
full-scale output.
TL/H/5608–4
FIGURE 1. DAC0830 Functional Diagram
6
Typical Performance Characteristics
Digital Input Threshold
vs. Temperature
Digital Input Threshold
vs. V
Gain and Linearity Error
Variation vs. Temperature
CC
TL/H/5608–5
DAC0830 Series Application Hints
These DAC’s are the industry’s first microprocessor com-
patible, double-buffered 8-bit multiplying D to A converters.
Double-buffering allows the utmost application flexibility
from a digital control point of view. This 20-pin device is also
pin for pin compatible (with one exception) with the
DAC1230, a 12-bit MICRO-DAC. In the event that a sys-
tem’s analog output resolution and accuracy must be up-
graded, substituting the DAC1230 can be easily accom-
system to be updated to their new analog output levels
simultaneously via a common strobe signal.
The timing requirements and logic level convention of the
register control signals have been designed to minimize or
eliminate external interfacing logic when applied to most
popular microprocessors and development systems. It is
easy to think of these converters as 8-bit ‘‘write-only’’ mem-
ory locations that provide an analog output quantity. All in-
puts to these DAC’s meet TTL voltage level specs and can
also be driven directly with high voltage CMOS logic in non-
microprocessor based systems. To prevent damage to the
chip from static discharge, all unused digital inputs should
plished. By tying address bit A to the ILE pin, a two-byte mP
0
write instruction (double precision) which automatically in-
crements the address for the second byte write (starting
e
with A
‘‘1’’) can be used. This allows either an 8-bit or the
0
12-bit part to be used with no hardware or software chang-
es. For the simplest 8-bit application, this pin should be tied
be tied to V
or ground. If any of the digital inputs are
CC
inadvertantly left floating, the DAC interprets the pin as a
logic ‘‘1’’.
to V
(also see other uses in section 1.1).
CC
Analog signal control versatility is provided by a precision R-
2R ladder network which allows full 4-quadrant multiplica-
tion of a wide range bipolar reference voltage by an applied
digital word.
1.1 Double-Buffered Operation
Updating the analog output of these DAC’s in a double-buff-
ered manner is basically a two step or double write opera-
tion. In a microprocessor system two unique system ad-
dresses must be decoded, one for the input latch controlled
by the CS pin and a second for the DAC latch which is
controlled by the XFER line. If more than one DAC is being
driven, Figure 2, the CS line of each DAC would typically be
decoded individually, but all of the converters could share a
common XFER address to allow simultaneous updating of
any number of DAC’s. The timing for this operation is
shown, Figure 3.
1.0 DIGITAL CONSIDERATIONS
A most unique characteristic of these DAC’s is that the 8-bit
digital input byte is double-buffered. This means that the
data must transfer through two independently controlled 8-
bit latching registers before being applied to the R-2R lad-
der network to change the analog output. The addition of a
second register allows two useful control features. First, any
DAC in a system can simultaneously hold the current DAC
data in one register (DAC register) and the next data word in
the second register (input register) to allow fast updating of
the DAC output on demand. Second, and probably more
important, double-buffering allows any number of DAC’s in a
It is important to note that the analog outputs that will
change after a simultaneous transfer are those from the
DAC’s whose input register had been modified prior to the
XFER command.
7
DAC0830 Series Application Hints (Continued)
TL/H/5608–6
FIGURE 3
The ILE pin is an active high chip select which can be de-
coded from the address bus as a qualifier for the normal CS
signal generated during a write operation. This can be used
to provide a higher degree of decoding unique control sig-
nals for a particular DAC, and thereby create a more effi-
cient addressing scheme.
one controlling the DAC’s to take over control of the data
bus and control lines. If this second system were to use the
same addresses as those decoded for DAC control (but for
a different purpose) the ILE function would prevent the
DAC’s from being erroneously altered.
In a ‘‘Stand-Alone’’ system the control signals are generat-
ed by discrete logic. In this case double-buffering can be
controlled by simply taking CS and XFER to a logic ‘‘0’’, ILE
Another useful application of the ILE pin of each DAC in a
multiple DAC system is to tie these inputs together and use
this as a control line that can effectively ‘‘freeze’’ the out-
puts of all the DAC’s at their present value. Pulling this line
low latches the input register and prevents new data from
being written to the DAC. This can be particularly useful in
multiprocessing systems to allow a processor other than the
to a logic ‘‘1’’ and pulling WR low to load data to the input
1
latch. Pulling WR low will then update the analog output. A
2
logic ‘‘1’’ on either of these lines will prevent the changing
of the analog output.
8
DAC0830 Series Application Hints (Continued)
TL/H/5608–7
e
ILE LOGIC ‘‘1’’; WR2 and XFER GROUNDED
FIGURE 4
1.2 Single-Buffered Operation
In microprocessor controlled system where maximum
data throughput to the DAC is of primary concern, or when
only one DAC of several needs to be updated at a time, a
single-buffered configuration can be used. One of the two
internal registers allows the data to flow through and the
other register will serve as the data latch.
a
be met or erroneous data can be latched. This hold time is
defined as the length of time data must be held valid on the
digital inputs after a qualified (via CS) WR strobe makes a
low to high transition to latch the applied data.
If the controlling device or system does not inherently meet
these timing specs the DAC can be treated as a slow mem-
ory or peripheral and utilize a technique to extend the write
strobe. A simple extension of the write time, by adding a
wait state, can simultaneously hold the write strobe active
and data valid on the bus to satisfy the minimum WR pulse-
width. If this does not provide a sufficient data hold time at
the end of the write cycle, a negative edge triggered one-
shot can be included between the system write strobe and
the WR pin of the DAC. This is illustrated in Figure 5 for an
exemplary system which provides a 250ns WR strobe time
with a data hold time of less than 10ns.
Digital signal feedthrough (see Section 1.5) is minimized if
the input register is used as the data latch. Timing for this
mode is shown in Figure 4.
Single-buffering in a ‘‘stand-alone’’ system is achieved by
strobing WR low to update the DAC with CS, WR and
1
XFER grounded and ILE tied high.
2
1.3 Flow-Through Operation
Though primarily designed to provide microprocessor inter-
face compatibility, the MICRO-DAC’s can easily be config-
ured to allow the analog output to continuously reflect the
state of an applied digital input. This is most useful in appli-
cations where the DAC is used in a continuous feedback
control loop and is driven by a binary up-down counter, or in
function generation circuits where a ROM is continuously
providing DAC data.
The proper data set-up time prior to the latching edge (LO to
HI transition) of the WR strobe, is insured if the WR pulse-
width is within spec and the data is valid on the bus for the
duration of the DAC WR strobe.
1.5 Digital Signal Feedthrough
When data is latched in the internal registers, but the digital
inputs are changing state, a narrow spike of current may
flow out of the current output terminals. This spike is caused
by the rapid switching of internal logic gates that are re-
sponding to the input changes.
Simply grounding CS, WR , WR , and XFER and tying ILE
2
1
high allows both internal registers to follow the applied digi-
tal inputs (flow-through) and directly affect the DAC analog
output.
1.4 Control Signal Timing
There are several recommendations to minimize this effect.
When latching data in the DAC, always use the input regis-
When interfacing these MICRO-DAC to any microprocessor,
there are two important time relationships that must be con-
sidered to insure proper operation. The first is the minimum
WR strobe pulse width which is specified as 900 ns for all
valid operating conditions of supply voltage and ambient
temperature, but typically a pulse width of only 180ns is
ter as the latch. Second, reducing the V
CC
supply for the
a
a
DAC from 15V to 5V offers a factor of 5 improvement in
the magnitude of the feedthrough, but at the expense of
internal logic switching speed. Finally, increasing C (Figure
C
8) to a value consistent with the actual circuit bandwidth
requirements can provide a substantial damping effect on
any output spikes.
e
the guaranteed minimum data hold time of 50ns should
adequate if V
CC
15V . A second consideration is that
DC
9
DAC0830 Series Application Hints (Continued)
TL/H/5608–8
FIGURE 5. Accommodating a High Speed System
2.0 ANALOG CONSIDERATIONS
The fundamental purpose of any D to A converter is to pro-
vide an accurate analog output quantity which is representa-
tive of the applied digital word. In the case of the DAC0830,
Figure 6. The MOS switches operate in the current mode
with a small voltage drop across them and can therefore
switch currents of either polarity. This is the basis for the 4-
quadrant multiplying feature of this DAC.
the output, I
, is a current directly proportional to the
OUT1
product of the applied reference voltage and the digital input
word. For application versatility, a second output, I , is
provided as a current directly proportional to the comple-
ment of the digital input. Basically:
2.2 Basic Unipolar Output Voltage
OUT2
To maintain linearity of output current with changes in the
applied digital code, it is important that the voltages at both
of the current output pins be as near ground potential
ea
V
Digital Input
256
REF
e
e
c
c
(0V ) as possible. With V
10V every millivolt ap-
I
I
;
DC
REF
OUT1
OUT2
15 kX
pearing at either I
or I
will cause a 0.01% linearity
OUT1
OUT2
b
255 Digital Input
V
REF
error. In most applications this output current is converted to
a voltage by using an op amp as shown in Figure 7.
15 kX
256
The inverting input of the op amp is a ‘‘virtual ground’’ creat-
ed by the feedback from its output through the internal 15
where the digital input is the decimal (base 10) equivalent of
the applied 8-bit binary word (0 to 255), V is the voltage
REF
kX resistor, R . All of the output current (determined by the
digital input and the reference voltage) will flow through R
fb
to the output of the amplifier. Two-quadrant operation can
at pin 8 and 15 kX is the nominal value of the internal resist-
ance, R, of the R-2R ladder network (discussed in Section
2.1).
fb
be obtained by reversing the polarity of V thus causing
REF
to flow into the DAC and be sourced from the output
Several factors external to the DAC itself must be consid-
ered to maintain analog accuracy and are covered in subse-
quent sections.
I
OUT1
of the amplifier. The output voltage, in either case, is always
c
equal to I
OUT1
ence voltage.
R
and is the opposite polarity of the refer-
fb
2.1 The Current Switching R-2R Ladder
The analog circuitry, Figure 6, consists of a silicon-chromi-
um (SiCr or Si-chrome) thin film R-2R ladder which is depos-
ited on the surface oxide of the monolithic chip. As a result,
there are no parasitic diode problems with the ladder (as
there may be with diffused resistors) so the reference volt-
The reference can be either a stable DC voltage source or
b
a
an AC signal anywhere in the range from 10V to 10V.
The DAC can be thought of as a digitally controlled attenua-
tor: the output voltage is always less than or equal to the
applied reference voltage. The V
terminal of the device
REF
b
a
age, V
device is 5V
, can range 10V to 10V even if V for the
REF CC
presents a nominal impedance of 15 kX to ground to exter-
nal circuitry.
.
DC
The digital input code to the DAC simply controls the posi-
tion of the SPDT current switches and steers the available
Always use the internal R resistor to create an output volt-
fb
age since this resistor matches (and tracks with tempera-
ture) the value of the resistors used to generate the output
ladder current to either I
or I
as determined by the
OUT2
OUT1
logic input level (‘‘1’’ or ‘‘0’’) respectively, as shown in
current (I
).
OUT1
10
DAC0830 Series Application Hints (Continued)
FIGURE 7
TL/H/5608–9
2.3 Op Amp Considerations
The op amp used in Figure 7 should have offset voltage
nulling capability (See Section 2.5).
This configuration features several improvements over ex-
isting circuits for bipolar outputs with other multiplying
DACs. Only the offset voltage of amplifier 1 has to be nulled
to preserve linearity of the DAC. The offset voltage error of
the second op amp (although a constant output voltage er-
ror) has no effect on linearity. It should be nulled only if
absolute output accuracy is required. Finally, the values of
the resistors around the second amplifier do not have to
match the internal DAC resistors, they need only to match
and temperature track each other. A thin film 4-resistor net-
work available from Beckman Instruments, Inc. (part no.
694-3-R10K-D) is ideally suited for this application. These
The selected op amp should have as low a value of input
bias current as possible. The product of the bias current
times the feedback resistance creates an output voltage er-
ror which can be significant in low reference voltage appli-
cations. BI-FET op amps are highly recommended for use
with these DACs because of their very low input current.
Transient response and settling time of the op amp are im-
portant in fast data throughput applications. The largest sta-
bility problem is the feedback pole created by the feedback
resistance, R , and the output capacitance of the DAC.
fb
b
This appears from the op amp output to the ( ) input and
includes the stray capacitance at this node. Addition of a
resistors are matched to 0.1% and exhibit only 5 ppm/ C
§
resistance tracking temperature coefficient. Two of the four
available 10 kX resistors can be paralleled to form R in
Figure 9 and the other two can be used independently as
the resistances labeled 2R.
lead capacitance, C in Figure 8, greatly reduces overshoot
C
and ringing at the output for a step change in DAC output
current.
2.5 Zero Adjustment
Finally, the output voltage swing of the amplifier must be
greater than V to allow reaching the full scale output
voltage. Depending on the loading on the output of the am-
For accurate conversions, the input offset voltage of the
output amplifier must always be nulled. Amplifier offset er-
rors create an overall degradation of DAC linearity.
REF
g
plifier and the available op amp supply voltages (only 12
volts in many development systems), a reference voltage
less than 10 volts may be necessary to obtain the full ana-
log output voltage range.
The fundamental purpose of zeroing is to make the voltage
appearing at the DAC outputs as near 0V as possible.
DC
This is accomplished for the typical DAC Ð op amp connec-
tion (Figure 7) by shorting out R , the amplifier feedback
fb
nulling potentiometer of the
2.4 Bipolar Output Voltage with a Fixed Reference
resistor, and adjusting the V
OS
op amp until the output reads zero volts. This is done, of
course, with an applied digital code of all zeros if I is
The addition of a second op amp to the previous circuitry
can be used to generate a bipolar output voltage from a
fixed reference voltage. This, in effect, gives sign signifi-
cance to the MSB of the digital input word and allows two-
quadrant multiplication of the reference voltage. The polarity
of the reference can also be reversed to realize full 4-quad-
OUT1
). The short around
driving the op amp (all one’s for I
OUT2
is then removed and the converter is zero adjusted.
R
fb
c
e
g
g
circuit is shown in Figure 9.
g
rant multiplication:
V
Digital Code
V . This
OUT
REF
11
DAC0830 Series Application Hints (Continued)
t
s
C
C
(O to Full Scale)
22 pF
22 pF
10 pF
4 ms
5 ms
2 ms
b
STOR ADDED FROM INPUT TO
INSURE STABILITY
b
(DIGITAL CODE 128)
e
V
OUT
V
REF
128
TL/H/5608–10
V
l
REF
l
e
1 LSB
128
Input Code
MSB ÀÀÀÀÀÀÀÀÀÀLSB
IDEAL V
OUT
a
b
V
REF
V
REF
*THESE RESISTORS ARE AVAILABLE FROM
BECKMAN INSTRUMENTS, INC. AS THEIR
PART NO. 694-3-R10K-D
b
b
a
1 LSB
REF
1
1
1
0
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
V
1 LSB
/2
V
REF
V
l
l
b
V
REF
0
/2
REF
0
l
l
b
a
1 LSB
1 LSB
REF
V
V
l
l
l
REF
l
a
b
b
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1 LSB
1 LSB
2
2
b
a
V
REF
V
REF
l
l
l
l
FIGURE 9
2.6 Full-Scale Adjustment
In the case where the matching of R to the R value of the
fb
manner from the standard current switching configuration.
The reference voltage is connected to one of the current
g
R-2R ladder (typically 0.2%) is insufficient for full-scale
accuracy in a particular application, the V voltage can be
output terminals (I
OUT1
for true binary digital control, I
OUT2
REF
adjusted or an external resistor and potentiometer can be
added as shown in Figure 10 to provide a full-scale adjust-
ment.
is for complementary binary) and the output voltage is taken
from the normal V pin. The converter output is now a
as a function
REF
voltage in the range from 0V to 255/256 V
REF
of the applied digital code as shown in Figure 11.
The temperature coefficients of the resistors used for this
adjustment are an important concern. To prevent degrada-
tion of the gain error temperature coefficient by the external
resistors, their temperature coefficients ideally would have
to match that of the internal DAC resistors, which is a highly
impractical constraint. For the values shown in Figure 10, if
the resistor and the potentiometer each had a temperature
g
coefficient of 100 ppm/ C maximum, the overall gain error
temperature coefficent would be degraded a maximum of
§
0.0025%/ C for an adjustment pot setting of less than 3%
§
of R
.
fb
2.7 Using the DAC0830 in a Voltage Switching
Configuration
TL/H/5608–11
FIGURE 10. Adding Full-Scale Adjustment
The R-2R ladder can also be operated as a voltage switch-
ing network. In this mode the ladder is used in an inverted
12
DAC0830 Series Application Hints (Continued)
TL/H/5608–12
FIGURE 11. Voltage Mode Switching
gain error on the voltage difference between V
This configuration offers several useful application advan-
tages. Since the output is a voltage, an external op amp is
not necessarily required but the output impedance of the
DAC is fairly high (equal to the specified reference input
resistance of 10 kX to 20 kX) so an op amp may be used
for buffering purposes. Some of the advantages of this
mode are illustrated in Figures 12, 13, 14 and 15.
and the
CC
voltage applied to the normal current output terminals. This
is a result of the voltage drive requirements of the ladder
switches. To ensure that all 8 switches turn on sufficiently
(so as not to add significant resistance to any leg of the
ladder and thereby introduce additional linearity and gain
errors) it is recommended that the applied reference voltage
a
be kept less than
positive than V
5V
DC
and V
be at least 9V more
CC
There are two important things to keep in mind when using
this DAC in the voltage switching mode. The applied refer-
ence voltage must be positive since there are internal para-
. These restrictions ensure less than
REF
0.1% linearity and gain error change. Figures 16, 17 and 18
characterize the effects of bringing V and V closer
REF
CC
sitic diodes from ground to the I
and I terminals
OUT2
OUT1
together as well as typical temperature performance of this
voltage switching configuration.
which would turn on if the applied reference went negative.
There is also a dependence of conversion linearity and
TL/H/5608–13
Voltage switching mode eliminates output signal inversion and therefore a
D
#
e
b
1
V
2.5V
#
#
OUT
need for a negative power supply.
128
#
J
Zero code output voltage is limited by the low level output saturation volt-
#
&
Slewing and settling time for a full scale output change is
1.8 ms
age of the op amp. The 2 kX pull-down resistor helps to reduce this volt-
age.
V
of the op amp has no effect on DAC linearity.
#
OS
FIGURE 13. Obtaining a Bipolar Output from a Fixed
Reference with a Single Op Amp
FIGURE 12. Single Supply DAC
13
DAC0830 Series Application Hints (Continued)
TL/H/5608–14
a
Only a single 15V supply required
#
#
#
Non-interactive full-scale and zero code output adjustments
s
t
a
5VDC and 0V.
V
and V
must be
MIN
MAX
1
e
b
V
MIN
Incremental Output Step
D
(V
).
#
#
MAX
256
255
256
e
b
a
)
MIN
V
(V
V
V
OUT
MAX
MIN
256
FIGURE 15. Single Supply DAC with Level Shift and Span-
Adjustable Output
Gain and Linearity Error
Variation vs. Supply Voltage
Gain and Linearity Error
Variation vs. Reference Voltage
Gain and Linearity Error
Variation vs. Temperature
TL/H/5608–15
FIGURE 16
FIGURE 17
FIGURE 18
Note: For these curves, V
is the voltage ap-
) with pin 12 (I
REF
plied to pin 11 (I
grounded.
)
OUT2
OUT1
14
DAC0830 Series Application Hints (Continued)
2.8 Miscellaneous Application Hints
These converters are CMOS products and reasonable care
should be exercised in handling them to prevent catastroph-
ic failures due to static discharge.
Overall noise reduction and reference stability is of particu-
lar concern when using the higher accuracy versions, the
DAC0830 and DAC0831, or their advantages are wasted.
Conversion accuracy is only as good as the applied refer-
ence voltage so providing a stable source over time and
temperature changes is an important factor to consider.
3.0 GENERAL APPLICATION IDEAS
The connections for the control pins of the digital input reg-
isters are purposely omitted. Any of the control formats dis-
cussed in Section 1 of the accompanying text will work with
any of the circuits shown. The method used depends on the
overall system provisions and requirements.
A ‘‘good’’ ground is most desirable. A single point ground
distribution technique for analog signals and supply returns
keeps other devices in a system from affecting the output of
the DACs.
The digital input code is referred to as D and represents the
decimal equivalent value of the 8-bit binary input, for exam-
ple:
b
During power-up supply voltage sequencing, the 15V (or
12V) supply of the op amp may appear first. This will
b
cause the output of the op amp to bias near the negative
supply potential. No harm is done to the DAC, however, as
the on-chip 15 kX feedback resistor sufficiently limits the
Binary Input
Pin 13
MSB
Pin 7
D
current flow from I
to one diode drop below ground.
when this lead is internally clamped
OUT1
LSB Decimal Equivalent
1
1
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
1
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
1
0
1
0
0
0
0
255
128
16
2
Careful circuit construction with minimization of lead lengths
around the analog circuitry, is a primary concern. Good high
frequency supply decoupling will aid in preventing inadver-
tant noise from appearing on the analog output.
0
Applications
DAC Controlled Amplifier (Volume Control)
Capacitance Multiplier
TL/H/5608–16
b
V
IN
(256)
256
e
e
C
1
a
1
V
C
#
#
#
OUT
EQUIV
D
D
#
J
e
When D 0, the amplifier will go open loop and the output will saturate.
Maximum voltage across the equivalent capacitance is
#
#
b
Feedback impedance from the input to the output varies from 15 kX to
V
(op amp)
256
O MAX
limited to
%
as the input code changes from full-scale to zero.
a
1
D
C
is used to improve settling time of op amp.
#
2
15
Applications (Continued)
Variable f , Variable Q , Constant BW Bandpass Filter
O
O
TL/H/5608–17
KD
a
a
256
KD (2R
R
R (K
Q
1)
0
Q
1)
; 3dbBW
e
e
; Q
O
e
f
#
O
a
2qR C
256
R
(K
1)
2qR C(2R
)
R1
0
a
1
Q
1
Q
R
R
6
e
e
e
e
and R
1
e
R of DAC 15k
where C
C
C; K
1
2
5
e
e
e
R
1
H
1 for R
IN
R
#
#
O
4
&
range can be extended to 255 to 1 by replacing R with a
Range of f and Q is
O
16 to 1 for circuit shown. The
1
second DAC0830 driven by the same digital input word.
s
Q product should be 200 kHz.
c
Maximum f
#
O
DAC Controlled Function Generator
TL/H/5608–18
DAC controls the frequency of sine, square, and triangle outputs.
D
#
#
e
e
e
of square wave output and R 3 R .
1
f
for V
OMAX
V
0MIN
2
256(20k)C
e
255 to 1 linear frequency range; oscillator stops with D
0
#
#
Trim symmetry and wave-shape for minimum sine wave distortion.
16
Applications (Continued)
Two Terminal Floating 4 to 20 mA Current Loop Controller
TL/H/5608–19
1
D
R
R
2
e
a
a
1
I
V
OUT
REF
R
256 R
Ð
( Ð
(
1
fb
3
DAC0830 linearly controls the current flow from the input terminal to the
#
e
e
output terminal to be 4 mA (for D 0) to 19.94 mA (for D 255).
Circuit operates with a terminal voltage differential of 16V to 55V.
#
#
P
adjusts the magnitude of the output current and P adjusts the zero
1
to full scale range of output current.
2
Digital inputs can be supplied from a processor using opto isolators on
each input or the DAC latches can flow-through (connect control lines to
pins 3 and 10 of the DAC) and the input data can be set by SPST toggle
switches to ground (pins 3 and 10).
#
DAC Controlled Exponential Time Response
TL/H/5608–20
Output responds exponentially to input changes and automatically stops
e
#
#
#
when V
V
IN
OUT
Output time constant is directly proportional to the DAC input code and
capacitor C
Input voltage must be positive (See section 2.7)
17
Ordering Information
a
0 C to 70
§
b
a
40 C to 85 C
b
a
55 C to 125 C
Temperature Range
§
§
§
§
§
0.05% FSR
0.1% FSR
0.2% FSR
DAC0830LCN
DAC0830LCM
DAC0830LCV
DAC0832LCV
DAC0830LCJ
DAC0830LJ
Non
Linearity
DAC0831LCN
DAC0832LCN
DAC0832LCM
DAC0832LCJ
DAC0832LJ
Package Outline
N20AÐMolded DIP M20B Small Outline V20A Chip Carrier
J20AÐCeramic DIP
Physical Dimensions inches (millimeters)
Ceramic Dual-In-Line Package (J)
Order Number DAC0830LCJ,
DAC0830LJ, DAC0832LJ or DAC0832LCJ
NS Package Number J20A
18
Physical Dimensions inches (millimeters) (Continued)
Molded Small Outline Package (M)
Order Number DAC0830LCM
or DAC0832LCM
NS Package Number M20B
Molded Dual-In-Line Package (N)
Order Number DAC0830LCN,
DAC0831LCN or DAC0832LCN
NS Package Number N20A
19
Physical Dimensions inches (millimeters) (Continued)
Molded Chip Carrier (V)
Order Number DAC0830LCV
or DAC0832LCV
NS Package Number V20A
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
National Semiconductor
Corporation
National Semiconductor
Europe
National Semiconductor
Hong Kong Ltd.
National Semiconductor
Japan Ltd.
a
1111 West Bardin Road
Arlington, TX 76017
Tel: 1(800) 272-9959
Fax: 1(800) 737-7018
Fax:
(
49) 0-180-530 85 86
@
13th Floor, Straight Block,
Ocean Centre, 5 Canton Rd.
Tsimshatsui, Kowloon
Hong Kong
Tel: (852) 2737-1600
Fax: (852) 2736-9960
Tel: 81-043-299-2309
Fax: 81-043-299-2408
Email: cnjwge tevm2.nsc.com
a
a
a
a
Deutsch Tel:
English Tel:
Fran3ais Tel:
Italiano Tel:
(
(
(
(
49) 0-180-530 85 85
49) 0-180-532 78 32
49) 0-180-532 93 58
49) 0-180-534 16 80
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
相关型号：
DAC0832LCD
IC PARALLEL, 8 BITS INPUT LOADING, 1 us SETTLING TIME, 8-BIT DAC, CDIP20, D20A, Digital to Analog Converter
NSC
©2020 ICPDF网 联系我们和版权申明