DDU224F-150M [ETC]
Delay Line ; 延迟线\n
| 型号： | DDU224F-150M |
| 厂家： | 
ETC |
| 描述： | Delay Line
|
| 文件： | 总4页 (文件大小：63K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DDU224F
Ò
10-TAP, TTL-INTERFACED
FIXED DELAY LINE
(SERIES DDU224F)
data
delay
3
devices, inc.
FEATURES
PACKAGES
·
·
·
·
·
Ten equally spaced outputs
Very narrow device (SIP package)
Stackable for PC board economy
Input & outputs fully TTL interfaced & buffered
10 T2L fan-out capability
1 2 3 4 5 6 7 8 9 10 11 12 13 14
VCC N/C IN T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 GND
DDU224F-xx Commercial
DDU224F-xxM Military
FUNCTIONAL DESCRIPTION
PIN DESCRIPTIONS
The DDU224F-series device is a 10-tap digitally buffered delay line. The
signal input (IN) is reproduced at the outputs (T1-T10), shifted in time by
an amount determined by the device dash number. The nominal tap-to-
tap delay increment is given by 1/10 of the dash number. For dash
numbers less than 50, the total delay of the line is measured from T1 to
IN
Signal Input
T1-T10 Tap Outputs
VCC +5 Volts
GND Ground
T10, with the nominal value given by 9 times the increment. The inherent delay from IN to T1 is nominally
3.5ns. For dash numbers greater than or equal to 50, the total delay of the line is measured from IN to
T10, with the nominal value given by the dash number.
DASH NUMBER SPECIFICATIONS
SERIES SPECIFICATIONS
Part
Number
Total
Delay (ns)
9 ± 2.0 *
Delay Per
Tap (ns)
1.0 ± 0.5
2.0 ± 1.0
2.5 ± 1.0
5.0 ± 2.0
10.0 ± 3.0
15.0 ± 3.0
20.0 ± 3.0
25.0 ± 3.0
30.0 ± 3.0
40.0 ± 4.0
50.0 ± 5.0
·
·
·
·
Minimum input pulse width: 20% of total delay
Output rise time: 2ns typical
Supply voltage: 5VDC ± 5%
Supply current: ICCL = 50ma typical
ICCH = 15ma typical
Operating temperature: 0° to 70° C
Temp. coefficient of total delay: 100 PPM/°C
DDU224F-10
DDU224F-20
DDU224F-25
DDU224F-50
DDU224F-100
DDU224F-150
DDU224F-200
DDU224F-250
DDU224F-300
DDU224F-400
DDU224F-500
18 ± 2.0 *
22.5 ± 2.0 *
50 ± 2.5
100 ± 5.0
150 ± 7.5
200 ± 10.0
250 ± 12.5
300 ± 15.0
400 ± 20.0
500 ± 25.0
·
·
* Total delay is referenced to first tap output
Input to first tap = 3.5ns ± 1ns
NOTE: Any dash number between 10 and 500 not
shown is also available.
Ó1997 Data Delay Devices
Doc #97015
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
1
1/29/97
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DDU224F
APPLICATION NOTES
Delay Devices if your application requires device
testing at a specific input condition.
HIGH FREQUENCY RESPONSE
The DDU224F tolerances are guaranteed for
input pulse widths and periods greater than those
specified in the test conditions. Although the
device will function properly for pulse widths as
small as 20% of the total delay and periods as
small as 40% of the total delay (for a symmetric
input), the delays may deviate from their values
at low frequency. However, for a given input
condition, the deviation will be repeatable from
pulse to pulse. Contact technical support at Data
POWER SUPPLY BYPASSING
The DDU224F relies on a stable power supply to
produce repeatable delays within the stated
tolerances. A 0.1uf capacitor from VCC to GND,
located as close as possible to the VCC pin, is
recommended. A wide VCC trace and a clean
ground plane should be used.
3.5ns
10%
10%
10%
10%
10%
10%
10%
10%
10%
VCC IN
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 GND
Functional diagram for dash numbers < 50
10%
10%
10%
10%
10%
10%
10%
10%
10%
10%
VCC IN
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 GND
Functional diagram for dash numbers >= 50
Doc #97015
1/29/97
DATA DELAY DEVICES, INC.
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
2
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DDU224F
DEVICE SPECIFICATIONS
TABLE 1: ABSOLUTE MAXIMUM RATINGS
PARAMETER
DC Supply Voltage
Input Pin Voltage
Storage Temperature
Lead Temperature
SYMBOL
VCC
VIN
TSTRG
TLEAD
MIN
-0.3
-0.3
-55
MAX
7.0
VDD+0.3
150
UNITS NOTES
V
V
C
300
C
10 sec
TABLE 2: DC ELECTRICAL CHARACTERISTICS
(0C to 70C, 4.75V to 5.25V)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
High Level Output Voltage
VOH
2.5
3.4
V
VCC = MIN, IOH = MAX
VIH = MIN, VIL = MAX
VCC = MIN, IOL = MAX
VIH = MIN, VIL = MAX
Low Level Output Voltage
VOL
0.35
0.5
V
High Level Output Current
Low Level Output Current
High Level Input Voltage
Low Level Input Voltage
Input Clamp Voltage
Input Current at Maximum
Input Voltage
High Level Input Current
Low Level Input Current
Short-circuit Output Current
Output High Fan-out
IOH
IOL
VIH
VIL
VIK
IIHH
-1.0
20.0
mA
mA
V
V
V
2.0
-60
0.8
-1.2
0.1
VCC = MIN, II = IIK
VCC = MAX, VI = 7.0V
mA
IIH
IIL
IOS
20
-0.6
-150
25
VCC = MAX, VI = 2.7V
VCC = MAX, VI = 0.5V
VCC = MAX
mA
mA
mA
Unit
Load
Output Low Fan-out
12.5
PACKAGE DIMENSIONS
.200
MAX.
1
2
3
4
5
6
7
8
9
10 11 12 13 14
1.450 TYP.
.010
TYP.
.320
MAX.
.100
MIN.
.100
TYP.
.020 TYP.
.010
TYP.
1.300 TYP.
DDU224F-xx (Commercial)
DDU224F-xxM (Military)
Doc #97015
1/29/97
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
3
Powered by ICminer.com Electronic-Library Service CopyRight 2003
DDU224F
DELAY LINE AUTOMATED TESTING
TEST CONDITIONS
INPUT:
OUTPUT:
Ambient Temperature: 25oC ± 3oC
Supply Voltage (Vcc): 5.0V ± 0.1V
Load:
Cload
1 FAST-TTL Gate
5pf ± 10%
:
Input Pulse:
High = 3.0V ± 0.1V
Threshold: 1.5V (Rising & Falling)
Low = 0.0V ± 0.1V
Source Impedance:
Rise/Fall Time:
50W Max.
3.0 ns Max. (measured
between 0.6V and 2.4V )
PWIN = 1.5 x Total Delay
PERIN = 10 x Total Delay
Pulse Width:
Period:
NOTE: The above conditions are for test only and do not in any way restrict the operation of the device.
PRINTER
COMPUTER
SYSTEM
REF
T1
PULSE
GENERATOR
OUT
IN
T2
T3
T4
T5
T6
T7
T8
T9
T10
IN
TIME INTERVAL
COUNTER
TRIG
TRIG
DEVICE UNDER
TEST (DUT)
Test Setup
PERIN
PWIN
VIH
TRISE
TFALL
INPUT
SIGNAL
2.4V
1.5V
0.6V
2.4V
1.5V
0.6V
VIL
TRISE
TFALL
OUTPUT
SIGNAL
VOH
1.5V
1.5V
VOL
Timing Diagram For Testing
Doc #97015
1/29/97
DATA DELAY DEVICES, INC.
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
4
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