DM560P [ETC]
V.90 Integrated Data/Fax/Voice/Speakerphone Modem Device Set; 集成的V.90数据/传真/语音/扬声器调制解调器设备设置
| 型号： | DM560P |
| 厂家： | 
ETC |
| 描述： | V.90 Integrated Data/Fax/Voice/Speakerphone Modem Device Set |
| 文件： | 总43页 (文件大小：243K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DM560P
V.90 Integrated Data/Fax/Voice/Speakerphone Modem Device Set
The DM560P modem reference design is pre-
approved for FCC part 68 and provides minimum
design cycle time, with minimum cost to insure the
maximum amount of success.
General Description
The DM560P integrated modem is a four chipset
design that provides a complete solution for state-
of-the-art, voice-band Plain Old Telephone Service
(POTS) communication. The modem provides for
Data (up to 56,000bps), Fax (up to 14,400bps),
Voice and Full Duplex Speaker-phone functions to
comply with various international standards.
The simplified modem system, shown in figure
below, illustrates the basic interconnection between
the MCU, DSP, AFE and other basic components of
a modem. The individual elements of the DM560P
are:
The design of the DM560P is optimized for desktop
personal computer applications and it provides a low
cost, highly reliable, maximum integration, with the
minimum amount of support required. The DM560P
modem can operate over a dial-up network (PSTN)
or 2 wire leased lines.
•
•
•
•
DM6580 Analog Front End (AFE). 28-pin PLCC
package
DM6581 ITU-T V.90 Transmit Digital Signal
Processor (TX DSP). 100-pin QFP package
DM6582 ITU-T V.90 Receive Digital Signal
Processor (RX DSP). 100-pin QFP package
DM6583 Modem Controller (MCU) built in Plug &
Play (PnP). 100-pin QFP package
The modem integrates auto dial and answer
capabilities, synchronous and asynchronous data
transmissions, serial and parallel interfaces, various
tone detection schemes and data test modes.
Block Diagram
Ring
Detector
LED
40.32MHz
Address &
Data Bus
S C L K
DM658
0
DM658
1
TX DSP
DM658
DIT
RxIN
TxA1
TxA2
D O T
TFS
DIR
3
M S C L K
Micro
Lin
e
DAA
Controller
Unit
D O R
RF S
Analog
29.4912
M H z
Front End
TxBCLK
TxSCLK*2
RxBCLK
RxSCLK
20.16MHz
TxDCLK
DM658
2
ISA Bus
PnP
Speaker
Driver
S P K R
RX DSP
V.24
Interface
TxD
RxD
Microphone
Driver
RxDCLK
V.24
Interface
Preliminary
1
Version: DM560P-DS-P07
August 11, 2000
DM560P
V.90 Integrated Data/Fax/Voice/Speakerphone Modem Device Set
3. Dual Port RAM
4. Interrupt
DM6581/82 Absolute Maximum Ratings
DM6581/82 Electrical Characteristics
DM6581/82 Timing Diagrams
30
30
31
31
32
Table of Contents
General Description
Block Diagram
Features
1
1
3
Chip 3: DM6580 Analog Front End
Chipset
Chip 1: DM6583 Modem Controller Unit with PnP
DM6580 Description
DM6580 Block Diagram
DM6580 Features
DM6580 Pin Configuration
DM6580 Pin Description
DM6580 Functional Description
DM6580 Absolute Maximum Ratings
DM6580 DC Characteristics
33
33
34
34
35
35
37
37
DM6583 Description
4
DM6583 Block Diagram
4
DM6583 Features
4
DM6583 Pin Configuration
5
DM6583 Pin Description
6
DM6583 Functional Description
1. Operating Mode Selection
2. Micro-controller (8032) Reference
3. Micro-controller Register Description
4. UART (16550A) Emulation Registers
5. Plug and Play (PnP) Module
DM6583 Absolute Maximum Ratings
DM6583 Electrical Characteristics
DM6583 Timing Diagrams
8
8
8
8
DM6580 AC Characteristics & Timing Diagrams 37
DM6580 Performance
37
9
16
24
24
25
Package Information
Ordering Information
Company Overview
Contacts
38
40
40
40
Chip 2: DM6581 ITU-T V.90 TX DSP
Chip 3: DM6582 ITU-T V.90 RX DSP
DM6581/82 Description
DM6581/82 Block Diagram
DM6581/82 Features
DM6581/82 Pin Configuration
DM6581/82 Pin Description
DM6581/82 Functional Description
1. System Clock
26
26
26
27
28
29
29
29
Appendix A-1 Internal Card Application Circuit 41
Appendix A-2 Internal Card Reference B.O.M. 42
Appendix B Copy Of FCC Approval Certificate 43
2. Serial Port
2
Preliminary
Version: DM560P-DS-P07
August 11, 2000
DM560P
V.90 Integrated Data/Fax/Voice/Speakerphone Modem Device Set
Set
Features
■ Compatibility
- TIA/EIA 578 Fax Class 1 command set
- ITU-T V.90 (56000 to 28000 bps)
- ITU-T V.34 (33600 to 2400 bps)
- CCITT V.32bis (14400, 12000, 9600, 7200,
4800bps)
- CCITT V.32 (9600, 7200, 4800bps)
- CCITT V.22bis (2400, 1200bps)
- CCITT V.22 (1200bps)
- TIA/EIA IS-101 Voice command set
■ Video-ready modem interface V.80(Developing)
■ V.8bis (Developing)
■ Integrated UART 16550
- CCITT V.23 (1200/75bps)
- Bell 212A (1200bps)
- Bell 103 (300bps)
■ Parallel and Serial interfaces
- 6, 7 and 8 bit character support
- Even, odd, mark and none parity detection and
generation
■ Fax
- 1 and 2 stop bit support
- Auto DTE data speed detection through “AT”
- CCITT V.17 (14400, 12000, 7200bps)
- CCITT V.29 (9600, 7200bps)
- CCITT V.27ter (4800, 2400bps)
- CCITT V.21 Channel 2 (300bps)
- Group III, Class 1
■ Caller identification (Caller ID) support
■ Speakerphone
■ Selectable world wide call progress tone detection
■ 16 Bit over-sampling codec
■ Data Error Correction
■ Compromise and adaptive equalizer providing
- MNP Class 4
- CCITT V.42 LAPM
channel impairment compensation
■ Plug and Play (PnP) support
■ Data Compression
■ Enhanced 8032 compatible micro-controller
■ Power Management (power down mode)
■ 8 selectable interrupts
- MNP Class5
- CCITT V.42bis
■ Voice compression
■ Access up to 256K bytes external program
memory
- 2 and 4 bit ADPCM
- IMA ADPCM (Developing)
- 8 Bit PCM
■ Access up to 64K bytes external data memory
■ NVRAM to store two user configurable, selectable
profiles with three programmable telephone
numbers
■ DTE Interface
- DTE speed up to 115200bps
■ Full duplex data mode test capabilities
- Analog loop test
■ Enhanced T” command set and S registers
- TIA/EIA 602, ITU V.25 ter AT command
Chipset
The DM560P integrated modem device set contains 4 VLSI devices as described below:
1. DM6583 Modem Controller Unit with PnP for ISA
2. DM6580 Analog Front End (AFE)
3. DM6581 ITU-T V.90 Transmit Digital Signal Processor (TX DSP)
4. DM6582 ITU-T V.90 Receive Digital Signal Processor (RX DSP)
Preliminary
3
Version: DM560P-DS-P07
August 11, 2000
DM560P
V.90 Integrated Data/Fax/Voice/Speakerphone Modem Device Set
Chip 1: Modem Controller Unit with PnP for ISA
The DM6583 MCU performs general modem control
functions, and is also designed to provide Plug and
Play capability for ISA bus systems. The Plug and
Play logic supports software or automatic Plug and
Play selectable I/Os to allow users to configure the
internal modem card without jumpers.
DM6583 Description
The DM6583 Modem Control Unit is designed for
use in high speed internal and external modem
applications. The DM6583 interface is compatible
with the DM6581/DM6582 Transmit and Receive
Digital Signal Processors. The DM6583 incorporates
a 80C32 micro-controller, a virtual 16550A UART
with FIFO mode, and Plug & Play control logic.
DM6583 Block Diagram
Mode Selection
PC Data Bus
PnP Control
Logic
Virtual 16550
UART
PC Address Bus
8032
Micro-Controller
External ROM,
RAM Interface
IRQ & R/W Control
RS 232 Interface
Modem Control
Interface
I/O Control Logic
•
•
Conflict free I/O base address selection
Virtual 16550A UART compatible parallel
interface
Fully programmable serial interface:
- 6, 7 or 8-bit characters
- Even, odd, mark and none parity bit generation
and detection
- 1 and 2 stop bit generation
- Baud rate generation
DM6583 Features
•
•
•
•
•
•
Control interface support
Supports parallel and serial interfaces
Includes a 80C32 micro-controller
256K bytes maximum external program memory
64K bytes maximum external data memory
Provides automatic Plug and Play or software
configuration capabilities
•
•
8 selectable Interrupts
- Includes I/O control logic for modem control
interface
4
Preliminary
Version: DM560P-DS-P07
August 11, 2000
DM560P
V.90 Integrated Data/Fax/Voice/Speakerphone Modem Device Set
DM6583 Pin Configuration
UD0
UD1
UD2
UD3
UD4
UD5
1
80
79
D4
2
D5
3
D6
78
77
4
D7
5
76
75
74
CA0
CA1
CA2
CA3
CA4
CA5
CA6
CA7
GND
CA8
CA9
CA10
CA11
CA12
CA13
CA14
CA15
IRQ3
/RD
6
7
UD6
UD7
/IOR
GND
/IOW
/AEN
A11
A10
A9
8
73
72
9
10
11
12
13
14
15
16
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DM6583
A8
A7
17
18
A6
A5
19
20
21
22
23
24
25
26
27
28
29
30
A4
A3
A2
A1
A0
/WR
/PSEN
ALE/P
TXD
RXD
V
DD
IRQ4
IRQ5
IRQ7
V
DD
IRQ10
RESET
/LCS
Preliminary
5
Version: DM560P-DS-P07
August 11, 2000
DM560P
V.90 Integrated Data/Fax/Voice/Speakerphone Modem Device Set
DM6583 Pin Description
Pin No.
1 - 8
Pin Name
UD0 - UD7
I/O
I/O
Description
Data Bus Signal, for internal modem:
These signals are connected to the data bus of the PC I/O. They are
used to transfer data between the PC and the DM6583.
Modem Control Output, for external modem:
Memory address mapping of the controller is E800H.
I/O Read:
9
/IOR
GND
/IOW
/AEN
I
P
I
An active low input signal used to read data from the DM6583.
Ground
10, 41, 68,
85, 96
11
I/O Write:
An active low input signal used to write data to the DM6583.
Address Enable:
12
I
This is an active low signal to enable the system address for
DM6583.
13 - 24
A11 - A0
I
System Address:
These signals are connected to the bus of PC I/O. They are used to
select DM6583 I/O ports.
A0~A7:Modem Control Input for external modem. Memory address
mapping of the controller is E800H.
+5V Power Supply
25, 36, 52,
100
VDD
P
26, 27, 28,
29, 33, 34,
35, 59
IRQ4, IRQ5,
IRQ7, IRQ10,
IRQ11, IRQ12,
IRQ15, IRQ3
O
Interrupt Request:
These are the interrupt request pins. Only one pin, which is
decoded from Configuration Register can be active. The active pin
will go high when an interrupt request is generated from the
DM6583.
30
RESET
I
Reset:
An active high signal used to reset the DM6583.
Crystal Oscillator Input
Crystal Oscillator Output
Controller Program Write Enable:
This pin is used to enable FLASH ROM programming. In
configurations with no FLASH memory, this pin is not connected.
Loop Current Detection. Modem Input Control:
This pin is mapped to bit0 of address D000H.
RX DSP Register Select Output:
31
32
37
XTAL1
XTAL2
/PWR
I
O
O
51
39
/LCS
/RUCS
I
O
O
Memory address mapping of the controller is E400H.
Bank Switch Control:
40,38
CA16,CA17
These signals are used to switch external program memory
between banks.
CA16 CA17
Bank 0
Bank 1
Bank 2
Bank 3
0
1
0
1
0
0
1
1
42
T0
I
Controller Counter 0 Input
6
Preliminary
Version: DM560P-DS-P07
August 11, 2000
DM560P
V.90 Integrated Data/Fax/Voice/Speakerphone Modem Device Set
DM6583 Pin Description (continued)
Pin No.
43
Pin Name
T1
I/O
I
Description
Controller Counter 1 Input
44
/RI
I
Ring Signal Input
45
46
47
/DTR
/OH
/VOICE
I
O
O
DTR Input Pin (P1.1)
Hook Relay Control (P1.2)
Voice Relay Control. Modem Control Output (memory map is bit
3 of DAA)
48-50
53
EEPROM 1-3
RXD
I/O
I
EEPROM Control Pins (P1.4-P1.6)
Controller Serial Port Data Input
54
55
TXD
ALE/P
O
O
Controller Serial Port Data Output
Controller Address Latch Enable:
Output pulse for latching the low byte of the address during
accesses to the external memory.
56
/PSEN
O
Controller Program Store Enable:
This output goes low during a fetch from external program memory.
Controller External Data Memory Write Control
Controller External Data Memory Read Control
Controller Address Bus
57
58
60 - 67
69 - 76
77 - 84
86
87
88
89, 90
/WR
/RD
CA15 - CA8
CA7 - CA0
D7 - D0
TXRCLK
RXRCLK
/POR
VOICE Se1 1
VOICE Se1 2
A12 - A15
O
O
O
O
I/O
I
I
O
O
Controller Address Bus
Controller Data Bus
Transmitter Baud Rate Clock Input (Controller INT 0)
Receiver Baud Rate Clock Input (Controller INT 1)
DSP Reset Output
Modem Control Output (Memory map is bit 1-2 of DAA at memory
address D000H)
91 - 94
95
I
I
System Address:
These signals are connected to the bus of the PC I/O. They are
used to select the DM6583 I/O ports.
PnP Mode Enable:
/PNPEN
This pin selects PnP mode. When connected to ground, the
DM6583 will enter PnP mode when it receives the PnP initiation key
sequence. When disconnected, an internal pull up will disable the
Plug and Play function.
97
98
99
/TUCS
PS1
O
O
I
TX DSP Register Select Output:
Memory address mapping of the controller is F000H.
Modem Control Port Select Output:
Memory address mapping of the controller is D800H.
Select Pin: Used to select internal or external operation.
0: internal modem
EXT/INTB
1: external modem
Preliminary
7
Version: DM560P-DS-P07
August 11, 2000
DM560P
V.90 Integrated Data/Fax/Voice/Speakerphone Modem Device Set
Micro-controller Power Down Mode
DM6583 Functional Description
An instruction that sets the register PD (PCON.1) will
cause the 80C32 to enter power down mode. There
are three ways to wake up the 80C32
(1) Positive pulse signal occurring at the reset pin of
the 80C32
(2) Negative pulse occurring at /RI (P1.0) of the
80C32
(3) Programming the PnP Wake Up Controller
Register.
1. Operating Mode Selection
The DM6583 MCU can be used in both internal and
external modem applications. When operating as an
internal modem, the EXT/INTB input (pin 99) must
be attached to ground. When the DM6583 is
operating as an external modem, the EXT/INTB
input (pin 99) must attached to VDD.
2. Micro-controller Program Memory
The DM6583 supports two bank switch control pins
to switch external program memory among four
banks. The DM6583 can access a total of 256K of
external program memory.
Enhanced Internal direct Memory
There are two 128 byte banks of internal direct
memory in the 80C32. The system uses the lower
128 bytes under normal conditions. Switching to the
upper bank is achieved by loading register 8FH.1
(SFR of the 80C32) with 1. Switching to the lower
bank can be achieved by loading the same register
with 0.
Address mapping:
bank0: 00000H - 0FFFFH
bank1: 10000H - 1FFFFH
bank2: 20000H - 2FFFFH
bank3: 30000H - 3FFFFH
For bank switching, three instructions must be
included in software.
Reflash Program Memory
By setting 8F.2H the system can switch program and
data memory. If the system uses FLASH memory as
program memory this function is used to reflash
program code by downloading the program to data
memory then switching them.
Switch to bank1:
CLR P1.3
SETB P1.7
JMP BANK 1 ADDRESS
Switch to bank2:
CLR P1.7
Example:
SETB 8FH.2
LJMP 0000H
SETB P1.3
JMP BANK 2 ADDRESS
Switch to bank3:
CLR P1.7
Micro-controller Register Description
UART Clock Register:
Address D4000H Reset State: 06H
Write Only
CLR P1.3
JMP BANK 3 ADDRESS
Return to bank 0:
SETB P1.7
bit7 bit6 bit5 bit4 bit3 bit2 Bit1 bit0
X
dat6 dat5 dat4 dat3 dat2 dat1
0
SETB P1.3
JMP
BANK 0 ADDRESS
* For detailed information about the micro-controller,
refer to the Programmer's Guide to 8032.
8
Preliminary
Version: DM560P-DS-P07
August 11, 2000
DM560P
V.90 Integrated Data/Fax/Voice/Speakerphone Modem Device Set
UART Clock
Modem Output Port Register: Address D000H
The internal clock of the virtual UART logic is fixed at
1.8432MHz. The clock is derived from the MSCLK
signal from the DM6582 DSP, or an external 30Mhz
crystal. The UART 1.8432MHz clock will be obtained
by division. When the operating frequency of the
DM6583 controller changes, the divider should be
changed accordingly. This divider is specified by the
Configuration Register which can be written by the
DM6583 controller. The address mapping of the
register is D400H: (DM6583 controller memory
mapping)
Write only
bit7 bit6 bit5 bit4 bit3
bit2 bit1 bit0
/Voice Voice Voice /POR
-sel2 -Sel1
These 4 bits control the DM6583 output ports.
PnP Isolation & Resource Data Port: Address
F800H
Write only
The PnP isolation and resource data can be byte-
sequentially written to the corresponding memory
through this register.
Bit 0: Always 0.
Auto-configuration Register: Address F400H
Bit 6-1: define the clock divider range from 2 to 64
(even number).
bit2 bit1 bit0 IRQ bit5 bit4 bit3 I/O
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
3
4
5
7
0
0
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
03F8-03FF(COM1)
02F8-02FF(COM2)
03E8-03EF(COM3)
02E8-02EF(COM4)
03F0-03F7(COM5)
02F0-02F7(COM6)
03E0-03E7(COM7)
02E0-02E7(COM8)
Bit 7: Not used.
UART Baud Generator Divisor Latch Register:
Address EC00H
10 1
11 1
12 1
15 1
Read only
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
dat7 dat6 dat5 dat4 dat3 dat2 dat1 dat0
By reading this register, the micro-controller can
monitor the value of the low byte divisor latch of the
virtual UART baud generator (see DLL in next
section) and determine the baud rate clock itself.
The default I/O base and IRQ data stored in 93C46 is
loaded to this register by the micro-controller. The
micro-controller can also get the current I/O base
and IRQ information settings by performing a read
from this register. The configuration determined by
this register will be disabled when the register
detects the Initiation Key described in the next
section.
Modem Status Control Register (MSCR):
Address E000H
Write only
bit7 bit6 bit5 bit4 bit3 bit2 bit1
bit0
Bit 6: This bit is set to inform micro-controller that the
current I/O base and IRQ data should be stored to
93C46 as the default setting for the next power-on
reset through programming the Auto-configuration
Register. This bit will be cleared by micro-controller.
0
0
0
0
/CTS /DSR /DCD /RI
This register contains information about the line
status of the modem. The available signals are Ring
Detect (/RI), Carrier Detect (/DCD), Data Set Ready
(/DSR) and Clear To Send (/CTS).
Bit 7: When bit 7 is set, it enables the hardware
configuration to be set according to bit 0-bit 5
(Jumperless mode) and loads the proper value into
the PnP Registers including I/O and Interrupt
Configuration Registers. This bit will be reset, when it
receives PnP Initiation Key sequence.
Preliminary
9
Version: DM560P-DS-P07
August 11, 2000
DM560P
V.90 Integrated Data/Fax/Voice/Speakerphone Modem Device Set
Auto-configuration Register: Address F400H
(continued)
HDLC CNTL/STATUS Register: Address DC04H
Bit0: TxReady0
* When a reset condition occurs, the I/O and
Interrupt configuration registers must be reset to the
default value according to bit 0 - bit 5.
0: indicates the data in the TxFiFo has deceased
to zero and the HDLC circuit has transferred
the 1st 7eH pattern.
1: indicates that the TxFiFo data is greater than or
equal to the threshold value.
RxDataBits Register: Address DC00H
Write only
Once the RxDataBit set to 1, the data in the RxBuffer
will be transferred to RxFiFo. The transfer bit number
is the same as the programming value ofRxDataBits
Register.
Bit1: Rxdata
0: all the data in the RxBuffer has been read.
1: Programed by software to indicate that all data
in the RxDataBits register has been written to
the RxBuffer.
RxBuffer: Address DC01H
Write only
Bit2: TxFiFo Threshold
Receive data will be written to the RxBuffer and will
be input to the RxHDLC circuit. The RxBuffer is 16
bytes wide.
0: TxFiFo threshold No. = 11
1: TxFiFo threshold No. = 16
Bit3: TxFiFo Status
RxFiFo: Address DC01H
Read only
0: data No. in TxFiFo >= threshold
1: data No. in TxFiFo <= threshold
After the data has been passed from the RxBuffer to
the RxHDLC circuit, the RxHDLC circuit will remove
the 7eH patterns and transfer the results to the
RxFiFo. There RxFiFo is 21 bytes wide.
Bit4: Txdata
0: A write action to TxDataBites register will clear
this bit.
1: Bit No. in TxBuffer = TxDataBits register.
TxDataBits Register: Address DC02H
Write only
Bit5: RxFiFo empty
Data written to TxDataBits will be presented to the
TxFiFo. The data in TxFiFo will be transferred to
TXHDLC circuit. The transfer bit number is the same
as the value of TxDataBits register. If the TxFiFo is
empty, a 7e pattern will be loaded to the TxFiFo. If
TxFiFo is not empty and the data frame has the
pattern of five consecutive “1” , then the TXHDLC
circuit will insert “0” automatically.
0: data bytes No. in RxFiFo <>0
1: data bytes No. in RxFiFo = 0
Bit6: Reset
0: Normal state
1: reset HDLC circuit
In_ buffer register: Address DC08
write only
TxFiFo Register: Address DC03H
Write only
The original HDLC frame data will be loaded to the
TxFiFo, presented to the input of the TxHDLC circuit.
The TxFiFo is 21 bytes wide.
Controller write the original data to this temp buffer.
Out _ buffer register: Address DC08H
read only
Controller read the result data from this buffer
Status/Rst register: Address DC09H
Bit0: data ready flag (read only)
1: data has been load to out _ buffer. (clear
automatically by a read from out_ buffer)
0: data hasn’t been load to out _ buffer.
Bit1: frame end flag (read only)
1: Indicate end of HDLC frame (clear by a reset
action)
TxBuffer: Address DC03H
Read only
According to TxDataBits, the TxHDLC circuit will
transfer the same number data bits to the TxBuffer.
The TxBuffer is 16 bytes wide.
Bit2: fram ready flag (read only)
1: CRC check ok.
0: CRC check fail.
Bit3: In _ buffer empty flag
10
Preliminary
Version: DM560P-DS-P07
August 11, 2000
DM560P
V.90 Integrated Data/Fax/Voice/Speakerphone Modem Device Set
Interrupt Identification Register (IIR): Address 2
1: In _ buffer empty (clear automatically by a
write to In _buffer)
0: In _ buffer not empty
Reset State 01h, Read only
Bit7 Bit6 bit5 bit4 bit3
bit2
D2:
bit1
D1:
bit0
D0:
Bit7: reset bit(write only)
FIFO
0
0
0
D3:
1: software reset
(4)CRCL register: Address DC0AH (read only)
(5)CRCH register: Address DC0BH (read only)
Enable
INTD2 INTD1 INTD0
int
Pending
In order to provide minimum software overhead
during data transfers, the virtual UART prioritizes
interrupts into four levels as follows: Receiver Line
Status (priority 1), Receiver Data Available (priority
2), Character Timeout Indication (priority 2, FIFO
mode only), Transmitter Holding Register Empty
(priority 3), and Modem Status (priority 4).
UART (16550A) Emulation Registers
Receiver Buffer (Read), Transmitter Holding
Register (Write): Address: 0 (DLAB=0)
Reset State 00h
bit7 bit6 bit5 bit4 bit3 Bit2 bit1 bit0
dat7 dat6 dat5 dat4 dat3 Dat2 dat1 dat0
The IIR register gives prioritized information
regarding the status of interrupt conditions. When
accessed, the IIR indicates the highest priority
interrupt that is pending.
When this register address is read, it contains the
parallel received data. Data to be transmitted is
written to this register.
Interrupt Enable Register (IER): Address 1
Reset State 00h, Write Only
bit7 bit6 bit Bit4 bit3
5
Bit 0: This bit can be used in either a prioritized
interrupt or polled environment to indicate
whether an interrupt is pending. When this bit
is a logic 0, an interrupt is pending, and the IIR
contents may be used as a pointer to the
appropriate interrupt service routine. When bit
0 is a logic 1, no interrupt is pending, and
polling (if used) continues.
bit2
bit1
bit0
0
0
0
0
Enable Enable Enable Enable
Modem Line TX RX
Status Status Holding Data
Intr
Intr Registe
Intr
r
Intr
This 8-bit register enables the four types of interrupts
as described below. Each interrupt source can
activate the INT output signal if enabled by this
register. Resetting bits 0 through 3 will disable all
UART interrupts.
Bit 1-2: These two bits of the IIR are used to identify
the highest priority interrupt pending, as
indicated in the table below.
Bit 3: In character mode, this bit is 0. In FIFO mode,
this bit is set, along with bit 2, when a timeout
interrupt is pending.
Bit 0: This bit enables the Received Data Available
and timeout interrupts in the FIFO mode when
set to logic 1.
Bit 4-6: Not used
Bit 1: This bit enables the Transmitter Holding
Register Empty Interrupt when set to logic 1.
Bit 7: FIFO always enabled.
Bit 2: This bit enables the Receiver Line Status
Interrupt when set to logic 1.
Bit 3: This bit enables the MODEM Status Interrupt
when set to logic 1.
Bit 4-7: Not used
Preliminary
11
Version: DM560P-DS-P07
August 11, 2000
DM560P
V.90 Integrated Data/Fax/Voice/Speakerphone Modem Device Set
Interrupt Identification Register (IIR): Address 2 (continued)
D3 D2 D1 D0 Priority Level Interrupt Type
Condition
Reset
0
0
0
1
0
1
1
0
-
-
-
-
Highest
Receiver Line
Status
Overrun Error, Parity Error, Reads the Line Status
Framing Error or Break
Interrupt
Register
0
1
1
1
0
0
0
0
Second
Second
Receiver Data
Available
Receiver Data Available or Reads the Receiver Buffer
Trigger Level Reached
Register or the FIFO has
Dropped Below the
threshold value
Character Timeout No characters have been Reads The Receiver Buffer
Indication
read from or written to the Register
Rx FIFO during
programming time interval,
and the Rx FIFO is not
empty
0
0
0
0
1
0
0
0
Third
Transmitter
Holding Register for transmission
Empty
Ready to accept new data Reads the IIR Register or (if
source of interrupt) Writes
To The Transmitter Holding
Register
Fourth
Modem Status
Clear to Send, Data Set
Ready, Ring Indicator or
Data Carrier Detected
Reads the Modem Status
Register
12
Preliminary
Version: DM560P-DS-P07
August 11, 2000
DM560P
V.90 Integrated Data/Fax/Voice/Speakerphone Modem Device Set
FIFO Control Register (FCR): Address 2
WLS1
WLS0
Word Length
5 bits
0
0
1
1
0
1
0
1
Reset State 00h , write only
6 bits
7 bits
8 bits
bit7
RCVR RCVR
Trig Trig
(MSB) (LSB)
bit6 bit5 bit4 bit3
DMA TxFIFO RxFIFO FIFO
Mode Reset Reset Enable
bit2
bit1
bit0
0
0
Bit 0-1: WLS0-1 specifies the number of bits in each
transmitted and received serial character.
This is a write only register at the same location as
the IIR, which is a read only register. This register is
used to enable the FIFOs, clear the FIFOs, set the
RxFIFO trigger level, and select the type of DMA
signal.
Bit 2: STB specifies the number of stop bits in each
transmitted character. If bit 2 is a logic 0, one
stop bit is generated in the transmitted data. If
bit 2 is a logic 1 when a 5-bit word length is
selected via bits 0 and 1, one and a half stops
are generated. If bit 2 isa logic 1 when either a
6-, 7- or 8-bit word length is selected, two stop
bits are generated. The Receiver checks the
first Stop-bit only, regardless of the number of
Stop bits selected.
Bit 0: FIFO Enable, This bit is always high
Bit 1: Writing a 1 to FCR1 clears all bytes in the
RxFIFO and resets the counter logic to 0.
Bit 2: Writing a 1 to FCR2 clears all bytes in the
TxFIFO and resets the counter logic to 0.
Bit 3: Logic 1 indicates that the PC has enabled
parity generation and checking.
Bit 3: Setting FCR3 to 1 will cause the RXRDY and
TXRDY pins to change from mode 0 to mode 1
if FCR0 = 1.
Bit 4: Logic 1 indicates that the PC is requesting an
even number of logic 1s (even parity
Bit 4-5: Reserved
generation) to be transmitted or checked.
Logic 0 indicates that the PC is requesting odd
parity generation and checking.
Bit 6-7: FCR6, FCR7 are used to set the trigger level
for the RxFIFO interrupt.
Bit 5: When bits 3, 4 and 5 are logic 1, the parity bit
is transmitted and checked by the receiver as
logic 0. If bits 3 and 5 are 1 and bit 4 is logic 0,
then the parity is transmitted and checked as
logic 1.
FCR6
FCR7
RxFIFO Trigger Level
0
0
1
0
1
0
01
04
08
Line Control Register (LCR): Address 3
Bit 6: This is a Break Control bit. When it is set to
logic 1, a break condition is indicated.
Reset State 00h, Write Only
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
DLAB SBRK STP EPS PEN STB WLS1 WLS0
Bit 7: The Divisor Latch Access bit must be set to
logic 1 to access the Divisor Latches of the
baud generator during a read or write
This register is available to maintain compatibility
with the standard 16550 register set, and provides
information to the internal hardware that is used to
determine the number of bits per character.
operation. It must be set to logic 0 to access
the Receiver Buffer, the Transmitter Holding
Register, or the Interrupt Enable Register.
Preliminary
13
Version: DM560P-DS-P07
August 11, 2000
DM560P
V.90 Integrated Data/Fax/Voice/Speakerphone Modem Device Set
Bit 3: This bit is the Framing Error (FE) indicator. Bit 3
Modem Control Register (MCR): Address 4
indicates that the received character did not have a
valid stop bit. Bit 3 is set to a logic 1 whenever the stop
bit following the last data bit or parity bit is detected as
a zero bit (spacing level). The FE bit is reset whenever
the CPU reads the contents of the Line Status
Register. The FE error condition is associated with the
particular character in the FIFO to which it applies.
This error is revealed to the CPU when its associated
character is at the top of the FIFO.
Reset State 00h
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
0
0
0
0
0
0
RTS DTR
Bit 0: This bit asserts a Data Terminal Ready
condition that is readable via port P1.1 of the micro-
controller 80C32. When bit 0 is set to logic 1, the P1.1
is forced to logic 0. When bit 0 is reset to logic 0, the
P1.1 is forced to logic 1.
Bit 4: This bit is a Break Interrupt (BI) indicator. Bit 4
is set to logic 1 whenever the received data input is
held in the Spacing (logic 0) state for longer than a full
word transmission time (that is, the total time of Start
bit + data bits + Parity + Stop bits). The BI indicator is
reset whenever the CPU reads the contents of the
Line Status Register. The BI error condition is
Bit 1: This bit asserts a Request To Send condition
that is readable via port P3.4 of the micro-controller
80C32. When bit 1 is set to logic 1, the P3.4 is forced
to logic 0. When bit 1 is reset to logic 0, the P3.4 is
forced to logic 1.
associated with the particular character in the FIFO to
which it applies. This error is revealed to the CPU
when its associated character is at the top of the FIFO.
Line Status Register (LSR): Address 5
Reset State 60h, Read only
bit7 bit6
RCV ETEMT THRE BI
bit5
bit4 bit3 bit2 bit1 bit0
FE PE OE DR
Bit 5: This bit is a Transmitter Holding Register Empty
indicator. Bit 5 indicates that UART is ready to accept
a new character for transmission. In addition, this bit
causes the UART to issue an interrupt to the CPU
when the Transmit Holding Register Empty Interrupt
Enable is set high. The THRE bit is reset to logic 0
when the host CPU loads a character into the
Transmit Holding register. In the FIFO mode, this bit is
set when the TxFIFO is empty, and is cleared when at
least 1 byte is written to the TxFIFO.
This register provides status information to the host
PC concerning character transfer. Bit 1-4 indicates
error conditions that produce a Receiver Line Status
interrupt whenever any of the corresponding
conditions are detected. The Line Status Register is
valid for read operations only.
Bit 0: Set to logic 1 when a received character is
available in the RxFIFO. This bit is reset to logic 0
when the RxFIFO is empty.
Bit 6: This bit is the Transmitter Empty indicator. Bit 6
is set to a logic 1 whenever the Transmitter Holding
Register (THR) is empty, and is reset to a logic 0
whenever the THR contains a character. In FIFO
mode, this bit is set to 1 whenever the transmit FIFO is
empty.
Bit 1: An Overrun error will occur only after the
RxFIFO is full and the next character has overwritten
the unread FIFO data. This bit is reset upon reading
the Line Status Register.
Bit 7: In character mode, this bit is 0. In FIFO mode,
this bit is set when there is at least one parity error,
framing error, or break indication in the FIFO. If there
are no subsequent errors in the FIFO, LSR7 is cleared
when the CPU reads the LSR.
Bit 2: A logic 1 indicates that a received character
does not have the correct even or odd parity as
selected by the Parity Select bit. This error is set when
the corresponding character is at the top of the
RxFIFO. It will remain set until the CPU reads the
LSR.
14
Preliminary
Version: DM560P-DS-P07
August 11, 2000
DM560P
V.90 Integrated Data/Fax/Voice/Speakerphone Modem Device Set
Modem Status Register (MSR): Address 6
Reset State bit 0-3 : low , bit 4-7: Input Signal
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
Scratch Register (SCR): Address 7
Reset State 00h
This 8-bit Read/Write Register does not control the
UART in any way. It is intended as a Scratch Pad
Register to be used by the programmer to hold data
temporarily.
DCD RI DSR CTS DDCD TERI DDSR DCTS
This 8-bit register provides the current state of the
control lines from the Modem to the CPU. In addition,
four bits of the Modem Status Register provide change
information. These bits are set to a logic 1 whenever a
control input from the Modem changes state. They are
reset to logic 0 whenever the CPU reads the Modem
Status Register.
Divisor Latch (DLL): Address 0 (DLAB = 1)
Reset State 00h
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
DAT7 DAT6 DAT5 DAT4 DAT3 DAT2 DAT1 DAT0
This register contains baud rate information from the
host PC. The PC sets the Divisor Latch Register
values.
Bit 0: This bit is the Delta Clear to Send (DCTS)
indicator. Bit 0 indicates that the CTS (MSR Bit 4) has
changed state since the last time it was read by the
CPU.
Divisor Latch (DLM): Address 1 (DLAB = 1)
Reset State 00h
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
DAT7 DAT6 DAT5 DAT4 DAT3 DAT2 DAT1 DAT0
Bit 1: This bit is the Delta Data Set Ready (DDSR)
indicator. Bit 1 indicates that the DSR (MSR Bit 5) has
changed state since the last time it was read by the
CPU.
This register contains baud rate information from the
host PC.
Bit 2: This bit is the Trailing Edge of Ring indicator. Bit
2 indicates that the RI (MSR Bit 6) has changed from a
low to a high state.
Note: Two 8-bit latches (DLL-DLM) store the divisor in
16-digit binary format. The desired baud rate can be
obtained by dividing the 115200Hz clock by the
divisor.
Bit 3: This bit is the Delta Data Carrier Detect (DDCD)
indicator. Bit 3 indicates that the DCD (MSR Bti 7) has
changed state.
Desired
Divisor
Baud Rate Value
Note: Whenever bit 0, 1, 2 or 3 is set to a logic 1, a
Modem Status Interrupt is generated.
50
75
110
150
300
600
1200
2400
4800
9600
19200
38400
57600
115200
2304
1536
1047
768
384
192
96
48
24
12
6
Bit 4: This bit reflects the value of MSR Bit 4 (CTS).
Bit 5: This bit reflects the value of MSR Bit 5 (DSR).
Bit 6: This bit reflects the value of MSR Bit 6 (RI).
Bit 7: This bit reflects the value of MSR Bit 7 (DCD).
3
2
1
Preliminary
15
Version: DM560P-DS-P07
August 11, 2000
DM560P
V.90 Integrated Data/Fax/Voice/Speakerphone Modem Device Set
Plug and Play (PnP) Module
Auto-configuration Ports
Three 8-bit I/O ports are defined for Plug and Play
read/write operations. They are called Auto-
configuration ports as listed below.
The Plug and Play Register could be directly accessed
without the need to write to the ADDRESS port before
each access. The ADDESS port is also the write
destination of the initiation key, which will be described
later.
Plug and Play Registers
Port
Type
Location
The Plug and Play Registers may be divided into Card
Registers and Logical Device Registers. According to
the Plug & Play specification, if a PnP card contains
more than one logical device, there are one more
copies of Logical Device Registers in the PnP card.
However, the DM6583A contains only one logical
device, the Card Register and Logical Device
Registers are unique for each card. Those PnP
registers or bits not defined below are all read with
value = 0.
ADDRESS W
0279H
(Printer status port)
0A79H
(Printer status port + 0800H)
Relocatable in range
0203H to 03FFH
WRITE_
DATA
READ_
DATA
W
R
To access the Plug and Play Register, a host should
follow this procedure: Write a target register address
(Register Index), choose a port (WRITE_DATA or
READ_DATA), then enter data.
Card Control Registers
Index
Name
Type
Definition
00H
Set RD_DATA port
W
The location of the READ_DATA port is determined by writing to this
register. Bits [7:0] become ISA I/O read port address bits [9:2]. Address
bits [1:0] of the READ_DATA port are always 1.
01H
02H
Serial Isolation
Config Control
R
A read to this register causes a PnP card in the Isolation state to compare
one bit of the card serial ID. This process is described in more detail in the
next section.
Bit [0] - Reset Command Setting
W
This bit will reset all logical devices and restore configuration registers to
their power-up values. The CSN is preserved.
Bit [1] - Wait for Key Command Setting
This bit makes the PnP card return to the Wait for Key state. The CSN is
preserved.
Bit [2] - PnP Reset CSN Command Setting
This bit will reset the card CSN to 0. Note that the hardware will
automatically clear the bits without any need for software to clear them.
A write to this register will cause all cards that have a CSN that matches the
write data [7:0] to go from the Sleep state to either the 1) Isolation state if the
write data for this command is zero, or 2) Configuration state if the write
data is not zero.
03H
Wake [CSN]
W
04H
05H
Resource Data
Status
R
R
A read from this register reads the next byte of resource data. The Status
Register must be polled until bit[0] is set before this register may be read.
Bit [0], when set, indicates it is ready to read the next data byte from the
Resource Data Register.
06H Card Select Number R/W A write to this register sets a card CSN. After a serial identification process,
(CSN)
the CSN value (CSN) is uniquely assigned to each ISA PnP card so that
each card may be individually selected during a Wake[CSN] command.
16
Preliminary
Version: DM560P-DS-P07
August 11, 2000
DM560P
V.90 Integrated Data/Fax/Voice/Speakerphone Modem Device Set
Card Control Registers (continued)
Index
Name
Type
Definition
07H
Logical Device
R
00H (Only one logical device in DM6583A)
Logical Device Control Registers
Index
Name
Type
Definition
30H
Activate
R/W For each logical device, there is one Activate register that controls whether
or not the device is active on the ISA bus. Bit[0], if set, activates the logical
device. Before a logical device is activated, I/O range check must be
disabled.
31H
I/O Range Check R/W This register is used to perform a conflict check on the I/O port range
programmed for use by a logical device.
Bit[1] - This bit, when set, enables I/O range check. I/O port range check is
only valid when the logical device is inactive.
Bit[0] - If set, this bit forces logical device to respond to I/O reads within
logical device assigned I/O range with a 55H when I/O range check is in
operation. If clear, the logical device drives AAH.
Logical Device Configuration Registers
I/O Configuration Registers
Index
Name
Type
Definition
60H I/O base address bits[15:8] R/W Read/write value indicating the selected I/O Lower Limit Address Bits
[15:8] for I/O descriptor 0. If a logical device indicates it uses only 10
bits for decoding, then bits [15:10] need not to be supported.
61H
I/O base address bits[7:3] R/W Read/write value indicating the selected I/O Lower Input Address Bits
[7:3] for I/O descriptor 0.
Interrupt Configuration Registers
Index Name Type Definition
70H
IRQ level
R/W Read/write value indicating a selected Interrupt Level Bits[3:0] Select which
ISA interrupt level is used. A value of 1 selects IRQ1, 15 selects IRQ15, etc.
IRQ0 is not a valid interrupt selection.
71H IRQ type bits [7:0]
R
Read/write value indicating which type of interrupt is used for the IRQ
selected above Bit[1] - Level, 1 = high, 0 = low Bit[0] - Type, 1= level, 0 =
edge for DM6583A, this register is read only with value = 02H.
Preliminary
17
Version: DM560P-DS-P07
August 11, 2000
DM560P
V.90 Integrated Data/Fax/Voice/Speakerphone Modem Device Set
Vender Define Register
Index Name
Type
R/W
Definition
F0H
Auto Configuration
The I/O base address and IRQ can be configured by CPU through
this register. (It can also be configured by micro-controller. See
previous section).
F1H
F2H
IRQ Status Enable
IRQ Status
W
R
Before reading IRQ lines status, bit 0 must be set in order to load IRQ
lines status to IRQ Status register, bit 1 enable Pull Low resistor.
This register responds to IRQ lines status to determine which
interrupt has been used by the system. bit 0: IRQ 3 bit 1: IRQ 4 bit 2:
IRQ 5 bit 3: IRQ 7 bit 4: IRQ 10 bit 5: IRQ11 bit 6: IRQ12 bit 7: IRQ15.
When 80C32 enter power down mode, set bit0 of this register to wake
up 80C32. This bit will be cleared automatically.
F3H
Wake up controller
W
DM6583 Configuration Modes
This is achieved by a predefined series of writes (32
The DM6583A will power-on in jumperless mode.
The default configuration is set by loading the default
value stored in 93C46 to the Auto-configuration
register. These values can be modified by software
via the logical device configuration registers in DM
Jumperless mode. This updated value of the new
configuration is only valid temporarily and will be lost
after an active PC Hardware Reset. Permanent
changes of the default configuration will be done by
informing micro-controller to modify the contents of
the 93C46 via the Auto-configuration Register.
I/O writes) to the Address port, which is called the
Initiation Key. When the proper series of the I/O
writes is detected, the Plug and Play read/write data
ports are enabled. The Write sequence will be reset
and must be issued from the beginning if any data
mismatch occurs. The exact sequence for the
Initiation Key is listed below in hexadecimal notion.
PnP Initiation Key
6A, B5, DA, ED, F6, FB, 7D, BE, DF, 6F, 37, 1B, 0D,
86, C3, 61, B0, 58, 2C, 16, 8B, 45, A2, D1, E8, 74,
3A, 9D, CE, E7, 73, 39
The Plug and Play logic can operate through two
configuration modes: One is DM Jumperless mode,
the other PnP mode. There are two operating
methods between the two modes: First, setting hard
configuration through Initiation Key sequences,
second, setting hard configuration according to the
register that is used, I/O Configuration Register or
Auto-configuration Register.
DM Initiation Key (Jumperless)
68, 34, 1A, 8D, CB, E3, 71, B8, 5C, 2E, 97, 4B, 25,
92, C9, E4, 72, B9, DC, 6E, B7, 5B, 2D, 96, CB, 65,
B2, D9, EC, 76, BB, 5D
Isolation Protocol
A simple algorithm is used to isolate each Plug and
Play card. This algorithm uses the signals on the ISA
bus and requires lock-step operation between the
Plug and Play hardware and the isolation software.
The Initiation Key for Plug and Play
The Plug and Play logic is available upon powering
up however, must be enabled by software.
18
Preliminary
Version: DM560P-DS-P07
August 11, 2000
DM560P
V.90 Integrated Data/Fax/Voice/Speakerphone Modem Device Set
STATE
ISOLATION
READ FROM SERIAL ISOLATION REGISTER
YES
GET ONE BIT FROM SERIAL IDENTIFIER
N O
ID BIT = "1H"
DRIVE "55H" ON SD[7:0]
LEAVE SD[7:0]
IN HIGH-IMPEDANCE
N O
SD[1:0] = "01"
YES
WAIT FOR NEXT READ FROM SERIAL ISOLATION REGISTER
LEAVE SD[7:0]
IN HIGH IMPEDANCE
DRIVE
"AAH" ON
SD[7:0]
N O
SD[1:0] = "10"
AFTER I/O READ COMPLETES
FETCH NEXT ID BIT FROM
SERIAL IDENTIFIER
ID = 0
OTHER CARD ID = 1
YES
READ ALL 72 BITS
FROM SERIAL
IDENTIFIER
STATE
SLEEP
N O
YES
ONE CARD
ISOLATED
Serial Identifier
The first 32-bit field is a vendor identifier. The other
32-bits can be any value, such as a serial number, part
of a LAN address, or a static number, as long as no
two cards in a single system will ever have the same
64-bit number. The serial identifier is accessed bit-
serially by isolation logic, and is used to differentiate
the cards.
The key element of the Plug and Play isolation
protocol is that each card contains a unique number
called a serial identifier. The serial identifier is a 72-bit
unique, non-zero number composed of two 32 bit
fields and an 8-bit checksum.
Checksum
BYTE
Serial Number
BYTE BYTE BYTE BYTE BYTE BYTE
7:0 7:0 7:0 7:0 7:0 7:0
Vendor ID
BYTE
7:0
BYTE
7:0
7:0
Table 2. Shifting of Serial Identifier
The shift order for all Plug and Play serial isolation and resource data is defined as bit [0], bit [1], and so on through
bit [7].
Preliminary
19
Version: DM560P-DS-P07
August 11, 2000
DM560P
V.90 Integrated Data/Fax/Voice/Speakerphone Modem Device Set
Hardware Protocol
Software Protocol
The isolation protocol can be invoked by the Plug
and Play software at any time. The Initiation Key will
put all cards into configuration mode. The hardware
on each card expects 72 pairs of I/O read accesses
to the READ_DATA port. The card response to
these reads depends on the value of each bit of the
serial identifier, which is examined one bit at a time,
as shown in Table 2.
The Plug and Play software sends the Initiation Key
to all Plug and Play cards to place them into
configuration mode. The software is then ready to
perform the isolation protocol.
The Plug and Play software generates 72 pairs of I/O
read cycles from the READ_DATA port. The
software checks the data returned from each pair of
I/O reads for the 55H or AAH driven by the hardware.
If both 55H or AAH are read back, then the software
assumes that the hardware has a "1" bit in that
position. All other bits are assumed to be a "0."
If the current bit of the serial identifier is a "1," then
the card will drive the data bus to 55H to complete
the first I/O read cycle. If the bit is a “0,” then the card
puts its data bus driver into high impedance. All
cards in high impedance will check the data bus
during the I/O read cycle to sense if another card is
driving SD[1:0] to "01." During the second I/O read,
the card(s) that drove the 55H will now drive a AAH.
After 64 bits have been read, the software generates
a checksum using the received data. The checksum
is compared with the checksum read back in the last
8 bits of the sequence.
All high impedance cards will check the data bus to
sense if another card is driving SD [1:0] to "10."
There are two other special considerations for
software protocol. During an iteration, it is possible
that the 55H and AAH combination is never
detected. It is also possible that the checksum does
not match. If either of these cases occurs on the first
iteration, it must be assumed that the READ_DATA
port is in conflict. If a conflict is detected, then the
READ_DATA port will be relocated. The above
process is repeated until a non-conflicting location
for the READ_DATA port is found. The entire range
between 203H and 3FFH is available; however, in
practice, it is expected that only a few locations will
be tried before software determines that no Plug and
Play cards are present.
During subsequent iterations, the occurrence of
either of these two special cases should be
interpreted as the absence of any further Plug and
Play cards (i.e. the last card was found in the
previous iteration). This terminates the isolation
protocol.
If a high impedance card senses another card driving
the data bus with the appropriate data during both
cycles, it ceases to participate in the current iteration
of card isolation. Such cards, which lose out, will
participate in future iterations of the isolation
protocol.
Note: During each read cycle, the Plug and Play
hardware drives the entire 8-bit data bus, but checks
only the lower 2 bits. If a card is driving the bus or is
in high impedance state and does not sense another
card driving the bus, then it should prepare for the
next pair of I/O reads. The card shifts the serial
identifier by one bit, using the shifted bit to decide its
response. The above sequence is repeated for the
entire 72-bit serial identifier.
At the end of this process, one card remains. This
card is assigned a handle referred to as the Card
Select Number (CSN) that will be used later to select
the card. Cards that have been assigned a CSN will
not participate in subsequent iterations of the
Note: The software must delay 1 msec prior to
starting the first pair of isolation reads, and wait 250
msec between each sub-sequence pair of isolation
reads. This delay gives the ISA card time to access
information from slow storage devices.
isolation protocol. Cards must be assigned a CSN
before they will respond to the other PnP commands.
20
Preliminary
Version: DM560P-DS-P07
August 11, 2000
DM560P
V.90 Integrated Data/Fax/Voice/Speakerphone Modem Device Set
Plug and Play Isolation Sequence
Configuration. The state transitions for the Plug and
Play ISA card are shown below:
The Plug and Play isolation sequence is divided into
four states: Wait for Key, Sleep, Isolation, and
POWER UP
RETDRV OR
RESET COMMAND
STATE
ACTIVE COMMANDS
NO ACTIVE
COMMANDS
WAIT FOR KEY
STATE
SLEEP
ACTIVE COMMANDS
RESET
RESET CSN
WAIT FOR KEY
WAKE(CSN)
WAKE=0
& CSN=0
WAKE<>0
& WAKE=CSN
LOSE SERIAL ISOLATION OR
WAKE<>CSN
WAKE<>CSN
STATE
ACTIVE COMMANDS
STATE
ACTIVE COMMANDS
RESET
RESET CSN
RESET
SET CSN
WAIT FOR KEY
WAKE(CSN)
RESET CSN
ISOLATION
CONFIG
WAIT FOR KEY
SET RD_DATA PORT
SERIAL ISOLATION
WAKE(CSN)
RESOURCE DATA
STATUS
LOGICAL DIVICE
I/O RANGE CHECK
ACTIVATE
SET CSN
CONFIGURATION REGISTERS
Plug and Play ISA Card State Transitions
Notes:
1. CSN = Card Select Number.
2. RSTDRV causes a state transition from the current state to Wait for Key and sets all CSNs to zero.
3. The Wait for Key command causes a state transition from the current state to Wait for Key.
4. The Reset CSN commands include PnP Reset CSN and DM Reset CSN commands.
PnP Reset CSN initializes all ISA PnP card CSNs to zero. The DM Reset CSN command initializes all DM6583
PnP card CSNs to zero.
Preliminary
21
Version: DM560P-DS-P07
August 11, 2000
DM560P
V.90 Integrated Data/Fax/Voice/Speakerphone Modem Device Set
next, isolation data, and then resource data port.
Isolation and Resource Data
The DM6583 has a built in 64-byte SRAM that can
be accessed by the micro-controller and PnP
Isolation and Resource Data Registers. Through
port F800H, the micro-controller can load serial data
and part of the resource data to SRAM byte by byte.
It is important to note that the length of the data
frame to be programmed should be loaded first,
When a read from the PnP resource data register
occurs, the data stored in SRAM will be sent to the
ISA data bus, and the data pointer will be advanced
by 1. When the data pointer is equivalent to the data
length, the next data read will change the pointer
value to the beginning of resource data block and
repeat the process for the other fixed resource data.
Resource Data Block ={ 30,47,01,f8, 02,f8, 02,08, 08, 22, 08, 00
30,47,01,f8, 03,f8, 03,08, 08, 22, 10, 00
30,47,01,e8,03,e8,03,08, 08, 22, 10, 00
30,47,01,e8,02,e8,02,08, 08, 22, 08, 00
30,47,01,e8,03,e8,03,08, 08, 22, 20, 00
30,47,01,e8,02,e8,02,08, 08, 22, 20, 00
30,47,01,e8,03,e8,03,08, 08, 22, b8, 9c
30,47,01,e8,02,e8,02,08, 08, 22, b8, 9c
30,47,01,f8, 03,f8, 03,08, 08, 22, b8, 9c
30,47,01,f8, 02,f8, 02,08, 08, 22, b8, 9c
30,47,01,00,02,f8, 03,08, 08, 22, b8, 9c
38,79}
* The data pointer will return to 1 when a Hardware Reset or Software Wake[CSN] occurs.
On powering up, the modem card detects RSTDRV,
sets CSN to 0, loads the isolation data and resource
data into the built-in 64-byte SRAM, programs the
Auto-configuration Register, configures the hardware
from the Auto-configuration Register, and then enters
the Wait for Key state. There is a required 2 msec
delay from either a RSTRDV or a PnP Reset
The first time the cards enter the Isolation state, it is
necessary to set the READ_DATA port address using
the Set RD_DATA port command. The software
should then use isolation protocol to check the
selected READ_DATA port address and to see if it is
in conflict with any other device.
command to any Plug and Play access to allow a card
to load this information via internal micro-controller.
Next, 72 pairs of reads are performed to the Serial
Isolation Register to isolate a card, as previously
described. When the checksum read from the card is
valid, it means the card is already isolated. The
isolated card remains in the Isolation state, while all
other cards fail the isolation protocol and are returned
to the Sleep state. The CSN on the isolated card is set
to a unique number, causing this card to change to the
Configuration state. Sending a Wake[0] command
causes this card to change back to Sleep state, and all
cards with a CSN value of zero to change to the
Isolation state. This entire process will repeat until no
Plug and Play cards are detected.
Cards in the Wait For Key state will not acknowledge
any access to their auto-configuration ports until the
Initiation Key is detected and they ignore all ISA
access to their Plug and Play interface. When the
cards have received the initiation key, they enter the
Sleep state. In this state, the cards listen for a Wake
[CSN] command with the write data set to 00H. This
Wake[CSN] command will set all cards to the Isolation
state and reset the serial identifier/resource data
pointer to the beginning.
22
Preliminary
Version: DM560P-DS-P07
August 11, 2000
DM560P
V.90 Integrated Data/Fax/Voice/Speakerphone Modem Device Set
Reading Resource Data
Each PnP card supports a resource data structure
stored in a non-volatile device (e.g. 93C46) that
describes the resources requested by the card. The
Plug and Play resource management software will
arbitrate resources and setup the logical device
configuration registers according to the resource data.
Card resource data may only be read from cards in the
Configuration state. A card may get to the
Configuration state by one of two different methods: 1)
A card enters the Configuration state in response to
the card "winning" the serial isolation protocol and
having a CSN assigned, or 2) the card receives a
Wake[CSN] command that matches the card CSN.
As described above, all Plug and Play cards function
as if both of their serial identifiers and resource data
come from the same serial device. Similarly, the
pointer to the serial device is reset in response to any
Wake[CSN] command. This implies that if a card
enters the Configuration state directly from Sleep state
in response to a Wake[CSN] command, the 9-byte
serial identifier must be read first before the card
resource data is accessed. Then the Vendor ID and
Unique Serial Number is valid. However, the
checksum byte, when read in this way, is not valid. For
a card that enters Configuration state / Isolation state,
the first read of the Resource Data Register will report
resource data.
Card resource data is read by first polling the Status
register and waiting for bit[0] to be set. When this bit is
set, one byte of resource data is ready to be read from
the Resource Data Register. After the Resource Data
Register is read, the Status Register must be polled
before reading the next byte of resource data. This
process will repeat until all resource data is read.
The above operation implies that the hardware is
responsible for accumulating 8 bits of data in the
Resource Data Register. When this operation is
complete, the status bit [0] is set. When a read is
performed on the Resource Data Register, status bit
[0] is cleared, eight more bits are shifted into the
Resource Data Register, and the status bit[0] is set
again.
Preliminary
23
Version: DM560P-DS-P07
August 11, 2000
DM560P
V.90 Integrated Data/Fax/Voice/Speakerphone Modem Device Set
*Comments
Stresses above those listed under "Absolute
DM6583 Absolute Maximum Ratings*
Maximum Ratings" may cause permanent damage to
this device. These are stress ratings only. Functional
operation of this device at these or any other
conditions above those indicated in the operational
sections of this specification is not implied or intended.
Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Power Supply Voltage -0.5V to +7.0V
o
o
Case Temperature
0 C to 85 C
o
o
Storage Temperature -65 C to 150 C
Applied Voltage On Any Pin
- 0.5V ≤ VIN ≤ VDD+0.5V
o
o
DM6583 DC Electrical Characteristics (VDD = 5V, GND = 0V; Tc = 0 C to 85 C)
Symbol
VDD
IDD
Parameter
Operating Voltage
Operating Current
Input High Voltage
Min.
4.75
Typ.
5.0
90
Max.
5.25
Unit
V
mA
V
Conditions
VIH
2.0
VIL
IiL
Input Low Voltage
0.8
10
V
A
V
V
pF
V
V
mA
mA
Input Leakage Current
Output High Voltage
Output Low Voltage
Input Capacitance
Reset Schmitt VIL
Reset Schmitt VIH
-10
2.4
VIN = 0, 5.25V
IOH = -0.5mA
IOL = 1.5mA
VOH
VOL
CIN
0.4
0.8
10.0
VILRESET
VIHRESET
IOH
2.8
UD Data Bus Output High Current
UD Data Bus Output Low Current
-15.0
VOH = 2.4V
VOL = 0.4V
IOL
24.0
o
o
DM6583 AC Electrical Characteristics (VDD = 5V, GND = 0V; Tc = 0 C to 85 C )
Symbol
TAW
TWC
TDOW
TDS
TDH
TAR
TRC
Parameter
IOW Delay from Address
Write Cycle
IOW Strobe Width
Data Setup Time
Data Hold Time
IOR Delay from Address
Read Cycle
Min.
30
280
100
30
30
30
280
125
Typ.
Max.
Unit
Ns
Ns
Ns
Ns
Ns
Ns
ns
Conditions
TDIW
TDDD
THZ
IOR Strobe Width
Delay from IOR to Data Valid
IOR to Floating Data Delay
ns
ns
ns
125
100
100pF loading
100pF loading
0
24
Preliminary
Version: DM560P-DS-P07
August 11, 2000
DM560P
V.90 Integrated Data/Fax/Voice/Speakerphone Modem Device Set
DM6583 Timing Diagrams
Write Cycle
VALID
A15 - A0
t
AW
tWC
/IOW
/IOR
t
DOW
tDS
VALID
t
DH
DATA UD7-UD0
Read Cycle
A15 - A0
VALID
t
AR
tRC
/IOR
t
DIW
/IOW
t
HZ
t
DDD
DATA UD7-UD0
VALID
Preliminary
25
Version: DM560P-DS-P07
August 11, 2000
DM560P
V.90 Integrated Data/Fax/Voice/Speakerphone Modem Device Set
used to boost the clock from 40.32MHz to 80.64MHz
Chip 2: DM6581/DM6582 ITU-T V.90 TX
and RX Digital Signal Processor
Description
or 89.74MHz. This 80.64MHz/89.74MHz clock is
used as the clock source of DSP core processor. A
16-byte dual port SRAM is utilized to provide the
communication between DSP and the DM6583.
There are two dedicated serial ports that provide the
link between the DSP and the DM6580. The
DM6581/DM6582 are bonded-out in a 100-pin QFP
package for mass production, and provide the most
economical package.
DM6581/82 Description
The DM6581/DM6582 are application specific Digital
Signal Processors (DSP) dedicated to V.90 modem
operation. They are used in pairs. The primary
component of these devices is a 22.43Mips DSP
core processor. The basic clock frequency of this
device is 40.32MHz. An internal built PLL circuit is
DM6581/82 Block Diagram
OSCI
Program
R A M
Timing
Logical & PLL
R O M
O S C O
PMA[0:15]
PMD[0:23]
MSCLK
CODEC_CLK
DSP Core
Serial Port
DMA[0:13]
DMD[0:15]
Dual Port
R A M
Data
R A M
DM6581/82 Features
•
•
•
•
•
Clock Generator for codec chip
Built in PLL
Built in Co-Processor
Power Down Mode
Eye Pattern Register
•
DM6581 for TX data-pump, DM6582 for the RX
data-pump
•
•
•
Built in program ROM
2 serial ports to interface with codec
16 byte dual port RAM
26
Preliminary
Version: DM560P-DS-P07
August 11, 2000
DM560P
V.90 Integrated Data/Fax/Voice/Speakerphone Modem Device Set
DM6581/82 Pin Configuration
RD_SP2
FR_SP2
AVDD
1
80
79
NC
2
NC
3
NC
78
77
OSCO
OSCI
4
NC
5
76
75
74
/IRQ3
/IRQ2
/IRQ1
/IRQ0
NC
DGND
6
7
TXDCLK
AGND
8
73
72
9
RXDCLK
CODEC_CLK
RXD
10
11
12
13
14
15
16
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DGND
NC
/RESET
DGND
NC
V
DD
TXD
/URD
/UWR
UAR3
UAR2
UAR1
UAR0
/UCS
UD0
NC
DM6581/6582
NC
NC
17
18
NC
19
20
21
22
23
24
25
26
27
28
29
30
NC
NC
DGND
NC
UD1
UD2
NC
UD3
VDD
UD4
NC
NC
NC
NC
NC
NC
UD5
UD6
UD7
DGND
MSCLK
Preliminary
27
Version: DM560P-DS-P07
August 11, 2000
DM560P
V.90 Integrated Data/Fax/Voice/Speakerphone Modem Device Set
DM6581/82 Pin Description
Pin No.
Pin Name
I/O
Description
Data Input Pin Of Serial Port 2:
1
RD_SP2
I
The serial data is sampled at the falling edge of the SCLK. The
MSB is coming immediately after falling of FR_SP2 signal.
Frame Signal For Serial Port 2:
2
FR_SP2
I/O
This pin is used to indicate a data transfer. It remains in a low
state until the rising edge of SCLK is detected. A high to low
transition initiates a data transfer.
Analog Power For PLL Circuit
Oscillator Output Pin
Oscillator Input Pin:
3
4
5
AVDD
OSCO
OSCI
P
O
I
A 40.32MHz crystal and feedback resister should be connected
between OCSI and OSCO.
Analog Ground For PLL Circuit
Transmit Data Rate Clock:
8
7
AGND
TXDCLK
P
I
This pin is used as reference clock of TXD pin.
Digital Ground
6, 29, 60, 68, 71,
DGND
P
I
84, 94, 95
Receive Data Rate Clock:
9
RXDCLK
This pin is used as reference clock of RXD pin.
20.16MHz Clock Output For DM6580 Chip
Modem Received Data
10
11
CODEC_CLK
RXD
O
O
Shifted out to the EIA port through this pin according to the rising
edge of RXDCLK.
Digital Power
Modem Transmit Data
12, 42, 57, 90
13
VDD
TXD
P
I
Shifted into DM6581/DM6582 from EIA port through this pin at the
rising edge of TXDCLK.
Read Indication Of Dual Port RAM, low active.
Write Indication Of Dual Port RAM, low active.
Dual Port RAM Address Bus Input
This address bus can access 16 bytes dual port RAM.
Dual Port RAM Chip Select Pin, low active.
Data Bus Of The Dual Port RAM
Clock Output Pin
14
15
16 - 19
/URD
/UWR
UAR3 - UAR0
I
I
I
20
21 - 28
30
/UCS
UD0 - UD7
MSCLK
I
I/O
O
The frequency of this clock 40.32MHz.
Output Port Bit F
Output Pin for Eye Pattern
Output Pin for Frame Signal of Eye Pattern
Output Port Bit C
No Connection
31
32
33
P0.F
Eye_SD
Eye_FR
P0.C
O
O
O
O
-
34
35 - 41, 43 - 56,
58, 59, 61 - 67,
70, 72, 77 - 83,
85 - 89
NC
28
Preliminary
Version: DM560P-DS-P07
August 11, 2000
DM560P
V.90 Integrated Data/Fax/Voice/Speakerphone Modem Device Set
DM6581/82 Pin Description (continued)
Pin No.
Pin Name
I/O
Description
Reset Pin Of DSP Chip, low active.
Interrupt 0 Input
Interrupt 1 Input
Interrupt 2 Input
Interrupt 3 Input
These three pins define the testing mode operation of DM6581/
DM6582 as followed:
69
73
74
75
76
/RESET
/IRQ0
/IRQ1
/IRQ2
/IRQ3
I
I
I
I
I
I
91, 92, 93
TEST, TEST1,
TEST2
When Test=0
Test1 0,PLL output clock is 80.64 MHZ.
1,PLL output clock is 89.74 MHZ.
When Test=1:
Reserved for mass production testing mode.
All these 3 pins are pulled low internally.
Frame Signal Of Serial Port 1
96
97
FR_SP1
TD_SP1
I/O
O
Data Output Pin Of Serial Port 1
The serial data is clocked out through this pin according to the rising
edge of SCLK. The MSB is sent immediately after the falling edge of the
FR_SP1 signal.
Data Input Pin Of The Serial Port 1
The serial data is sampled at the falling edge of the SCLK. The MSB is
coming immediately after the falling of FR_SP1 signal.
Reference Clock For Serial Port 1 And Serial Port 2
Data Output Pin Of Serial Port 2
98
RD_SP1
I
99
100
SCLK
TD_SP2
I
O
The serial data is clocked out through this pin according to the rising
edge of SCLK. The MSB is sent immediately after the falling edge of the
FR_SP2 signal.
DM6581/82 Functional Description
System Clock
Serial Port
Reference Oscillator Clock
There are two serial ports to provide the interface with
CODEC chip. The serial port 1 (SP1) transfers 32 bits
in each frame while the serial port 2 can transfer 64
bits in each frame. The frame signal of each serial port
can be configured as either input signal or output
signal by the Serial Port Control Register (SPC).
The reference frequency is provided by an external
40.32 MHz crystal oscillator. This is the clock source
of the Data Pump.
DSP Clock
This DSP clock is the output of an internal PLL
frequency synthesizer and its frequency can be
selected by Test1 pin. (see pin description )
CODEC Clock
This clock is output via the CODEC_CLK Pin as the
reference clock of the codec chip. This clock is derived
from dividing reference oscillator clock by two.
Preliminary
29
Version: DM560P-DS-P07
August 11, 2000
DM560P
V.90 Integrated Data/Fax/Voice/Speakerphone Modem Device Set
Power Down Mode
Dual Port RAM
The 16 X 8 dual port RAM allows easy system
Power Down mode is selected by bit 7 in register E.
This bit is write-only and can only be accessed by the
controller. Power Down mode is entered by setting the
PWD bit. A reset must occur to return to normal
operation.
expansion by adding another DSP or micro-processor.
Address 2000h ~ 200Fh are reserved for this dual port
RAM. The 8 bit dual port RAM data corresponds to the
MSBs of the data bus (bit 15 ~ bit 8) of the DSP core.
Upon reading the dual port RAM, the 8 LSB contents
(bit 7 to bit 0) are all 0. For the convenience of
PWD = 0: Normal Operation
PWD = 1: Power Down Mode.
description, the micro-controller port is referred to as B
port and the DSP port is referred to as A port.
Bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
PWD Bit6 Bit5 Bit4 Mode Bit2 Bit1
F-
Empty
Interrupt
The DSP core provides 4 nested interrupt inputs:
IRQ3, IRQ2, IRQ1, IRQ0. IRQ3 is the highest priority
input and IRQ0, the lowest. In the V.90 and V.32
application, the IRQ3, IRQ2 and IRQ1 are defined as
external interrupts triggered from the pin IRQ3B,
IRQ2B, IRQ1B respectively.
Eye Pattern Registers
The Eye Pattern Registers are memory mapped as
shown below.
Address
3000
3001
Symbol
Eye_X_Reg
Eye_Y_Reg
R/W
W
W
CoProcessor
The coprocessor is implemented to provide the
functions of echo cancellation for the DM6581
(TXDSP) and adaptive equalization for the DM6582
(RXDSP).
When data is loaded into the Eye_Y_Reg the Eye_FR
pin will be driven low for 16 SCLK periods. The
contents on the Eye_X/Y_Reg will be shifted out on
the Eye_SD pin on the rising edge of SCLK when
Eye_FR is Low.
DM6581/82 Functional Description (continued)
Eye Pattern Timings
SCLK
1
Eye_FR
2
Eye_SD
Symbol
Parameter
Eye_FR active after SCLK High
Eye_FR active after SCLK High
Min.
0
0
Typ.
Max.
20
20
Unit
ns
ns
Conditions
1
2
30
Preliminary
Version: DM560P-DS-P07
August 11, 2000
DM560P
V.90 Integrated Data/Fax/Voice/Speakerphone Modem Device Set
*Comments
DM6581/82 Absolute Maximum Ratings*
Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage
to this device. These are stress ratings only.
Functional operation of this device at these or any
other conditions above those indicated in the
operational sections of this specification is not
implied or intended. Exposure to absolute maximum
rating conditions for extended periods may affect
device reliability.
Power supply voltage -0.5V to +7.0V
o
o
Case temperature 0 C to 85 C
o
o
Storage temperature -65 C to 150 C
Applied voltage on any pin
-0.5V ≤ VIN ≤ VDD+0.5V
o
o
DM6581/82 DC Electrical Characteristics (VDD = 5V, GND = 0V; Tc = 0 C to 85 C)
Symbol
VDD
IDD
VIH
VIL
IiL
VOH
VOL
Parameter
Operating Voltage
Min.
4.75
Typ.
5.0
85
Max.
5.25
100
Unit
V
mA
V
V
uA
V
V
Conditions
Operating Current
Input High Voltage
Input Low Voltage
Input Leakage Current
Output High Voltage
Output Low Voltage
2.2
0.8
10
-10
2.4
VIN = 0, 5.25V
IOH = 2.5mA
IOL = 2.5mA
0.4
DM6581/82 AC Electrical Characteristics
o
o
(VDD = 5V, GND = 0V; Tc = 0 C to 85 C, PLL out frequency = 90MHz, CL = 50pF)
Serial Port Timing
Symbol
Parameter
SCLK Period
SCLK Low Width
SCLK High Width
SCLK Rise Time
SCLK Fall Time
Frame Delay Time
Frame To SCLK Hold
RD Valid Before SCLK Low
RD Hold Time
Min.
49
20
Typ.
Max.
Unit
Conditions
1
2
3
4
5
6
7
8
9
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
5
5
20
17
5
15
10
TD Delay Time
20
Preliminary
31
Version: DM560P-DS-P07
August 11, 2000
DM560P
V.90 Integrated Data/Fax/Voice/Speakerphone Modem Device Set
4
5
1
2
3
SCLK
6
7
FR_SP1
FR_SP2
8
9
RD_SP1
RD_SP2
First Bus
10
Last Bus
11
TD_SP1
TD_SP2
Hiz
First Bus
Last Bus
Dual Port RAM Timing
Symbol
Parameter
/URD Read Period
Min.
100
50
Typ.
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Conditions
1
2
3
4
5
6
7
8
9
Address Valid Before /URD Low
/URD to /UCS Delay Time
Data Hold Time After /URD High
Data Bus High Z After /URD High
/URD Low To Data Valid
7
4
20
25
/UWR Period
100
50
50
Data Setup Time /UWR High
Address Valid Before /UWR Low
/UWR To /UCS Delay
10
11
7
Data Hold Time After /UWR High
0
UAR[3..0]
/UCS
3
4
1
2
/URD
UD[0..7]
6
5
32
Preliminary
Version: DM560P-DS-P07
August 11, 2000
DM560P
V.90 Integrated Data/Fax/Voice/Speakerphone Modem Device Set
The DM6580 offers wide-band transmit and receive
Chip 3 : DM6580 Analog Front End
Description
filters so that the voice band signal is transmitted or
received without amplitude distortion and with
minimum group delay. In order to support multi-mode
modem standards, such as V.90, V.34+, V.32bis,
V.32, V.22bis, V.22, V.23, V.21, Bell 212A, Bell 103,
V.17, V.29, V.27ter, programmable baud and data
rate clock generators are provided. For asymmetric
channel usage, the transmit and receive clock
generators are independent. In order to enhance
echo-cancellation, the receive clock is synchronized
with the transmit clock and the best receive timing
sample is reconstructed by a reconstruction filter.
The Transmit Digital Phase Lock Loop (DPLL) is
self-tuning to provide a master, slave or free-running
mode for the data terminal interface. A receive DPLL
that is step programmable by the host DSP is
implemented to get the best samples for the relevant
signal processing.
DM6580
The DM6580 is a single chip Analog Front End
(AFE) designed to be implemented in voice grade
modems for data rates up to 56000bps. The
DM6580 is an essential part the complete modem
device set. The AFE converts the analog signal into
digital form and transfers the digital data to the DSP
through the serial port. All the clock information
needed in a modem device is also generated in the
DM6580. Differential analog outputs are provided to
achieve the maximum output signal level. An audio
monitor with programmable volume levels is built in
to monitor the on-line signal. Inside the device, a
16-bit ADC and a 16-bit DAC with over-sampling and
noise-shaping techniques is implemented to
maximize performance.
DM6580 Block Diagram
TxSCLK*2
TxDCLK
ExtCLK
RxSCLK
RxDCLK
Rx Clock
System
Tx Clock
System
CLKIN
SCLK
Divider
Control
Registers
RFS
DOR
TxA1
TxA2
LPF &
Attenuator
Digital
Interface
Tx Filter &
DAC
DIR
TFS
V
V
V
REFP
CM
DOT
Voltage Reference
REFN
DIT
0/-6 dB
RxIN
Rx Filter &
ADC
Audio Amplifier
SPKR
Digital
Reconstruction
Filter
Power-on
Detector
Preliminary
33
Version: DM560P-DS-P07
August 11, 2000
DM560P
V.90 Integrated Data/Fax/Voice/Speakerphone Modem Device Set
DM6580 Features
Signal Processor (DSP)
•
•
•
•
•
16-bit
Dynamic range : 86dB
Total harmonic distortion : -86dB
Separate transmit and receive clocks
Symbol rate : 75, 300, 600, 1200, 1600, 2400,
2743, 2800, 3000, 3200, 3429, 8000Hz
Data rate V.34 : 75, 300, 600, 1200, 2400, 4800,
7200, 9600, 12000, 14400, 16800, 19200, 21600,
24000, 26400, 28800, 31200, 33600 bps
Data rate V.90 : up to 56000 bps
A/D and D/A converters
•
Separate transmit digital phase lock loop and
receive digital phase lock loop
Full echo cancellation capability
Differential analog output
Single-ended analog input
Single power supply voltage : +5V
Low power consumption
•
•
•
•
•
•
•
•
Dual synchronous serial interface to host Digital
DM6580 Pin Configuration
DOR
5
6
7
25
24
23
AGNDT
DIR
V
V
V
REFP
CM
DGND
DM6580
SCLK
DOT
DIT
REFN
8
22
AGNDR
9
21
20
19
TXA1
TXA2
10
11
TFS
34
Preliminary
Version: DM560P-DS-P07
August 11, 2000
DM560P
V.90 Integrated Data/Fax/Voice/Speakerphone Modem Device Set
DM6580 Pin Description
Pin No.
Pin Name
RXDCLK
VDD
RXSCLK
RFS
I/O
O
P
O
I
Description
1
2
3
4
5
6
Receive Data Clock
Digital Power
Receive Sample Clock
Receive Frame Synchronization
Data Output For Receiver
DOR
DIR
O
I
Data Input For Receiver
7
8
9
DGND
SCLK
DOT
P
O
O
I
Digital Ground
Serial Clock Synchronized With All Serial Data
Data Output For Transmitter
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
DIT
Data Input For Transmitter
TFS
I
Transmit Frame Synchronization
Transmit Sample Clock * 2
Transmit Data Clock
Master Clock Input (20.16MHz = 40.32MHz / 2 )
Codec Reset Input
External Transmit Data Clock
Internal Reference Voltage. Connect 0.1uF to DGND
Analog VDD For The Transmitter Analog Circuitry (+5VDC)
Transmit Negative Analog Output
Transmit Positive Analog Output
Analog Receiver Circuitry Signal Return Path
Negative Reference Voltage, VCM - 1V
Common Mode Voltage Output, 2.5V
Positive Reference Voltage, VCM + 1V
Analog Transmitter Circuitry Signal Return Path
Receive Analog Input
TXSCLK*2
TXDCLK
CLKIN
/RESET
EXTCLK
Vr
AVDDT
TXA2
TXA1
AGNDR
VREFN
VCM
VREFP
AGNDT
RXIN
O
O
I
I
I
O
I
O
O
P
O
O
O
P
I
AVDDR
SPKR
I
O
Analog VDD For The Receiver Analog Circuitry (+5VDC)
Speaker Driver
DM6580 Functional Description
In this chip, we could roughly divide it into two major
parts : digital portion and analog portion. The
functional blocks are described separately in this
section. The analog circuits include a sigma-delta
modulator/demodulator, decimation/interpolation
filters, a speaker driver, low-pass filter and certain
logic circuits. The digital circuits is composed of Tx/Rx
clock generator/PLL, serial port, serial/parallel
conversions and control registers. All the clock
information the analog circuits need should be
provided by the digital clock system since the best
sampling instant of A/D and D/A depends on the
received signal and transmit signals. The data format
of A/D and D/A is 2's complement.
The master clock (FQ) is obtained from an external
signal connected to CLKIN. The different transmit and
receive clocks are obtained by master clock frequency
division in several programmable counters. The Tx
and Rx clocks can be synchronized on external
signals by performing the phase shifts in the frequency
division process. Two independent digital phase
locked loops are implemented using this principle, one
for transmit clock system, the other, receive clock. The
tracking of the transmit clock is automatically done by
the transmit DPLL circuit. The receive DPLL circuit is
controlled by the host processor and it is actually an
adjustable phase shifter.
Preliminary
35
Version: DM560P-DS-P07
August 11, 2000
DM560P
V.90 Integrated Data/Fax/Voice/Speakerphone Modem Device Set
DM6580 Register Description
Register
TxCR0
TxCR1
TxCR2
TxTest
RxCR0
RxCR1
RxCR2
RxTest
D11
D10
D9
X2
Q1
D8
X1
D
D7
X0
M1
F0
D6
N3
M0
W
D5
N2
D4
N1
F
D3
N0
Y
D2
R0
D1
S
D0
T
Programmed
Functions
Tx Data Rate
Clock
R1
X3
Q0
U2
U1
U0
VF
Tx Baud
sample Clock
Miscellaneous
control
Vol1 Vol2
F1
ATT
LTX
LC
SST
EMX
Reserved
R1
H2
H1
D
H0
M1
N3
M0
N2
Q0
N1
P
N0
Y
R0
U2
S
T
Rx Data Rate
Clock
Rx Baud
SampleClock
Rx Phase Shift
Control
Q1
RST
-6dB
U1
U0
LL
PS4
PS3
PS2
PS1
PS0
AP2
AP1
AP0
Reserved
*Comments
DM6580 Absolute Maximum Ratings*
Stresses above those listed under “Absolute
Maximum Ratings” may cause permanent damage
to the device. These are stress ratings only.
Functional operation of this device at these or any
other conditions above those indicated in the
operational section of this specification is not implied
or intended. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Power supply voltage -0.5V to +7.0V
o
o
Case temperature 0 C to 85 C
o
o
Storage temperature -65 C to 150 C
Applied voltage on any pin
-0.5V ≤ VIN ≤ VDD+0.5V
o
o
DM6580 DC Electrical Characteristics (VDD = 5V, Tc = 0 C to 85 C)
Symbol
Parameter
Min.
Typ.
Max. Un
Conditions
it
VDD
VCM
IDD
Operating Voltage
Output Common Mode Voltage
Supply Current
4.75
5
2.5
25
5.25
V
V
m
A
VIL
VIH
VOL
VOH
IiL
Input Low Voltage
0.8
0.4
10
V
V
V
V
µA
pF
V
Input High Voltage
Output Low Voltage
Output High Voltage
Input leakage Current
Input Capacitance
Differential Reference Voltage
Output
Output Common Mode Offset
2.2
2.4
-10
VI=0V,5.25V
±1
5
2
CIN
VREF
1.9
2.1
200
VCMD_OUT
-200
m
V
V
m
V
=(TxA1+TxA2)/2-VCM
VDIF_OUT
VOFF_OUT
Differential Output Voltage
Differential Output DC Offset
Voltage
3 *VREF
TxA1-TxA2 ≤ 3*VREF
VDC (TXA1)-VDC (TXA2)
-100
100
36
Preliminary
Version: DM560P-DS-P07
August 11, 2000
DM560P
V.90 Integrated Data/Fax/Voice/Speakerphone Modem Device Set
o
o
DM 6580 DC Electrical Characteristics (VDD = 5V, Tc = 0 C to 85 C) (continued)
RIN
ROUT
Input Resistance RxIN
Output Resistance TxA1, TxA2,
SPKR
100
kΩ
kΩ
1
2
RL
CL
Load Resistance TxA1, TxA2,
SPKR
Load Capacitance TxA1, TxA2,
SPKR
20
kΩ
50
pF
DM6580 AC Characteristics (VDD = 5V, Tc= 0oC to 85oC)
Serial Port Timing
Symbol
Parameter
SCLK Period
SCLK Low Width
SCLK High Width
SCLK Rise Time
SCLK Fall Time
FS To SCLK Setup
FS To SCLK Hold
DI To SCLK Setup
DI To SCLK Hold
SCLK High To DO Valid
SCLK To DO Hiz
Min.
49
24
Typ.
Max.
Unit
Conditions
1
2
3
4
5
6
7
8
9
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
24
5
5
17
17
5
5
10
11
8
8
4
5
1
2
3
SCLK
6
7
FS
DI
8
9
First Bus
Last Bus
10
11
Hiz
DO
First Bus
Last Bus
DM6580 Performance
o
o
(VDD= 5V, Tc= 0 C to 85 C , FQ= 20.16MHz, Measurement Band = 220Hz to 3.6KHz, RX DPLL Free Running)
Symbol
Gabs
THD
DR
PSRR
Parameter
Min. Typ. Max. Unit
Conditions
Absolute Gain At 1KHz
Total Harmonic Distortion
Dynamic Range
-0.5
0.5
dB
dB
dB
dB
dB
RX signal: VIN= 2.5 VPP, f = 1KHz
Tx signal: VOUT (diff)= 5 VPP, f = 1KHz
f = 1KHz
f = 1KHz, VAC = 200m VPP
Transmit channel to receive channel
-84
86
50
95
Power Supply Rejection Ratio
CTxRx Crosstalk
Preliminary
37
Version: DM560P-DS-P07
August 11, 2000
DM560P
V.90 Integrated Data/Fax/Voice/Speakerphone Modem Device Set
Package Information
unit: inches/mm
QFP 100L Outline Dimensions
H
D
D
100
81
1
80
30
51
31
50
b
e
G D
G
D
See Detail
Seating Plane
F
L
y
1
L
Detail F
Symbol
Dimensions In Inches
0.130 Max.
Dimensions In mm
3.30 Max.
A
A1
A2
0.004 Min.
0.10 Min.
0.1120.005
2.850.13
+0.004
-0.002
+0.004
-0.002
+0.10
-0.05
+0.10
-0.05
b
0.012
0.31
c
0.006
0.15
D
E
0.5510.005
0.7870.005
0.026 0.006
0.742 NOM.
0.693 NOM.
0.929 NOM.
0.7400.012
0.9760.012
0.0470.008
0.0950.008
0.006 Max.
0° ~ 12°
14±0.13
20±0.13
0.65±0.15
18.85 NOM.
17.60 NOM.
23.60 NOM.
18.8±0.31
24.79±0.31
1.19±0.20
2.41±0.20
0.15 Max.
0° ~ 12°
e
F
GD
GE
HD
HE
L
L1
y
θ
Note:
1. Dimensions D&E do not include resin fins.
2. Dimensions GD & GE are for PC Board surface mount pad pitch
design reference only.
3. All dimensions are based on metric system.
38
Preliminary
Version: DM560P-DS-P07
August 11, 2000
DM560P
V.90 Integrated Data/Fax/Voice/Speakerphone Modem Device Set
PLCC 28L Outline Dimensions
unit: inches/mm
D
H
D
1
28
26
4
5
25
11
19
12
18
c
e
b
b
1
Seating Plane
y
G
D
Symbol
Dimensions In Inches
0.185 Max.
Dimensions In mm
4.70 Max.
A
A1
A2
0.020 Min.
0.51 Min.
0.1500.005
3.810.13
b1
0.028 +0.004
-0.002
0.71 +0.10
-0.05
b
0.018 +0.004
-0.002
0.46 +0.10
-0.05
c
0.010 +0.004
-0.002
0.25 +0.10
-0.05
D
E
0.4530.010
0.4530.010
0.0500.006
0.4100.020
0.4100.020
0.4900.010
0.4900.010
0.1000.010
0.006 Max.
11.51±0.25
11.51±0.25
1.27±0.15
10.41±0.51
10.41±0.51
12.45±0.25
12.45±0.25
2.54±0.25
0.15 Max.
e
GD
GE
HD
HE
L
y
Note:
1. Dimensions D and E do not include resin fins.
2. Dimensions GD & GE are for PC Board surface mount pad pitch
design reference only.
3. All dimensions are based on metric system.
Preliminary
39
Version: DM560P-DS-P07
August 11, 2000
DM560P
V.90 Integrated Data/Fax/Voice/Speakerphone Modem Device Set
DAVICOM’s terms and conditions printed on the order
acknowledgment govern all sales by DAVICOM.
DAVICOM will not be bound by any terms inconsistent
with these unless DAVICOM agrees otherwise in
writing. Acceptance of the buyers’ orders shall be
based on these terms.
Ordering Information
Part Number
DM6580L
DM6581F
DM6582F
DM6583F
Pin Count
Package
PLCC
QFP
QFP
QFP
28
100
100
100
Company Overview
Disclaimer
DAVICOM Semiconductor, Inc. develops and
manufactures integrated circuits for integration into
data communication products. Our mission is to
design and produce IC products that are the industry’s
best value for Data, Audio, Video, and
Internet/Intranet applications. To achieve this goal, we
have built an organization that is able to develop
chipsets in response to the evolving technology
requirements of our customers while still delivering
products that meet their cost requirements.
The information appearing in this publication is
believed to be accurate. Integrated circuits sold by
DAVICOM Semiconductor are covered by the
warranty and patent indemnification provisions
stipulated in the terms of sale only. DAVICOM makes
no warranty, express, statutory, implied or by
description regarding the information in this
publication or regarding the information in this
publication or regarding the freedom of the described
chip(s) from patent infringement. FURTHER,
DAVICOM MAKES NO WARRANTY OF
MERCHANTABILITY OR FITNESS FOR ANY
PURPOSE. DAVICOM reserves the right to halt
production or alter the specifications and prices at any
time without notice. Accordingly, the reader is
cautioned to verify that the data sheets and other
information in this publication are current before
placing orders. Products described herein are
intended for use in normal commercial applications.
Applications involving unusual environmental or
reliability requirements, e.g. military equipment or
medical life support equipment, are specifically not
recommended without additional processing by
DAVICOM for such applications. Please note that
application circuits illustrated in this document are for
reference purposes only.
Products
We offer only products that satisfy high performance
requirements and which are compatible with major
hardware and software standards. Our currently
available and soon to be released products are based
on our proprietary designs and deliver high quality,
high performance chipsets that comply with modem
communication standards and Ethernet networking
standards.
Contact Windows
For additional information about DAVICOM products, contact the sales department at:
Headquarters
Davicom USA
Hsin-chu Office:
Taipei Sales & Marketing Office:
8F, No. 3, Lane 235, Bao-chiao
Rd., Hsin-tien City, Taipei, Taiwan,
R.O.C.
TEL: 886-2-29153030
FAX: 886-2-29157575
Sunnyvale, California
1135 Kern Ave., Sunnyvale,
CA94085, U.S.A.
TEL: 1-408-7368600
FAX: 1-408-7368688
3F, No. 7-2, Industry E. Rd., IX,
Science-based Park,
Hsin-chu City, Taiwan, R.O.C.
TEL: 886-3-5798797
FAX: 886-3-5798858
Email: sales@davicom8.com
Email: sales@davicom.com.tw
WARNING
Conditions beyond those listed for the absolute maximum may destroy or damage the products. In addition, conditions for sustained
periods at near the limits of the operating ranges will stress and may temporarily (and permanently) affect and damage structure,
performance and/or function.
40
Preliminary
Version: DM560P-DS-P07
August 11, 2000
DM560P
V.90 Integrated Data/Fax/Voice/Speakerphone Modem Device Set
Appendix A-1 Internal Card Application Circuit(For Reference Only)
< This page is intentionally left blank >
Preliminary
41
Version: DM560P-DS-P07
August 11, 2000
DM560P
V.90 Integrated Data/Fax/Voice/Speakerphone Modem Device Set
Appendix A-2 Internal Card Reference B.O.M.(For Reference Only)
< This page is intentionally left blank >
42
Preliminary
Version: DM560P-DS-P07
August 11, 2000
DM560P
V.90 Integrated Data/Fax/Voice/Speakerphone Modem Device Set
Appendix B Copy Of FCC Approval Certificate(For Reference Only)
< This page is intentionally left blank >
Preliminary
43
Version: DM560P-DS-P07
August 11, 2000
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