DP83265_技术文档

PRELIMINARY

February 1991

DP83265 BSI^TMDevice

(FDDI System Interface)

General Description

Features

Y

32-bit wide Address/Data path with byte parity

The DP83265 BSI device implements an interface between

the National FDDI BMAC^TMdevice and a host system. It

provides a multi-frame, MAC-level interface to one or more

MAC Users.

Y

Programmable transfer burst sizes of

words

4 or 8 32-bit

Y

Interfaces to low-cost DRAMs or directly to system bus

2 Output and 3 Input Channels

The BSI device accepts MAC User requests to receive and

transmit multiple frames (Service Data Units). On reception

(Indicate), it receives the byte stream from the BMAC de-

vice, packs it into 32-bit words and writes it to memory. On

transmission (Request), it unpacks the 32-bit wide memory

data and sends it a byte at a time to the BMAC device. The

host software and the BSI device communicate via regis-

ters, descriptors, and an attention/notify scheme using clus-

tered interrupts.

Supports Header/Info splitting

Bridging support

Efficient data structures

Programmable Big or Little Endian alignment

Full Duplex data path allows transmission to self

Confirmation status batching services

Receive frame filtering services

Operates from 12.5 MHz to 25 MHz synchronously with

host system

TL/F/10791–1

FIGURE 1. FDDI Chip Set Block Diagram

TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.

BSI^TM, BMAC^TM, CDD^TM, CRD^TMand PLAYER^TMare trademarks of National Semiconductor Corporation.

C

1995 National Semiconductor Corporation

TL/F/10791

RRD-B30M105/Printed in U. S. A.

Table of Contents

5.0 CONTROL INFORMATION

1.0 FDDI CHIP SET OVERVIEW

5.1 Overview

2.0 ARCHITECTURE DESCRIPTION

2.1 Interfaces

5.2 Operation Registers

5.3 Control and Event Register Descriptions

5.4 Pointer RAM Registers

5.5 Limit RAM Registers

2.2 Data Structures

2.3 Map Engine

5.6 Descriptors

3.0 FEATURE OVERVIEW

5.7 Operating Rules

3.1 32-Bit address/Data Path to Host Memory

3.2 Multi-Channel Architecture

3.3 Support for Header/Info Splitting

3.4 MAC Bridging Support

5.8 Pointer RAM Register Descriptions

5.9 Limit RAM Register Descriptions

5.10 BSI Device Descriptors

3.5 Confirmation Status Batching Services

3.6 Receive Frame Filtering Services

3.7 Two Timing Domains

6.0 SIGNAL DESCRIPTIONS

6.1 Pin Organization

6.2 Control Interface

3.8 Clustered Interrupts

6.3 BMAC Device Indicate Interface

6.4 BMAC Device Request Interface

6.5 ABus Interface

4.0 FUNCTIONAL DESCRIPTION

4.1 Overview

6.6 Electrical Interface

4.2 Operation

4.3 Bus Interface Unit

2

1.0 FDDI Chip Set Overview

National Semiconductor’s FDDI chip set consists of five

components as shown in Figure 1-1. For more information

about the other devices in the chip set, consult the appropri-

ate data sheets and application notes.

DP83261 BMAC^TMDevice

Media Access Controller

The BMAC device implements the Timed Token Media Ac-

cess Control protocol defined by the ANSI FDDI X3T9.5

MAC Standard.

DP83231 CRD^TMDevice

Clock Recovery Device

The Clock Recovery Device extracts a 125 MHz clock from

Features

All of the standard defined ring service options

#

the incoming bit stream.

Full duplex operation with through parity

#

Features

PHY Layer loopback test

Supports all FDDI Ring Scheduling Classes (Synchro-

nous, Asynchronous, etc.)

#

Supports Individual, Group, Short, Long and External

Addressing

#

Crystal controlled

#

Clock locks in less than 85 ms

#

Generates Beacon, Claim, and Void frames internally

Extensive ring and station statistics gathering

Extensions for MAC level bridging

#

DP83241 CDD^TMDevice

Clock Distribution Device

From a 12.5 MHz reference, the Clock Distributon Device

synthesizes the 125 MHz, 25 MHz, and 12.5 MHz clock re-

quired by the BSI, BMAC, and PLAYER devices.

Separate management port that is used to configure and

control operation

Multi-frame streaming interface

#

DP83265 BSI^TMDevice

System Interface

The BSI Device implements an interface between the

DP83251/55 PLAYER^TMDevice

Physical Layer Controller

The PLAYER device implements the Physical Layer (PHY)

protocol as defined by the ANSI FDDI PHY X3T9.5 Stan-

dard.

BMAC device and a host system.

Features

32-bit wide Address/Data path with byte parity

Features

4B/5B encoders and decoders

#

Programmable transfer burst sizes of 4 or 8 32-bit words

#

Framing logic

#

Interfaces to low-cost DRAMs or directly to system bus

#

Elasticity Buffer, Repeat Filter and Smoother

#

Provides 2 Output and 3 Input Channels

#

Line state detector/generator

#

Supports Header/Info splitting

#

Link error detector

#

Efficient data structures

#

Configuration switch

#

Programmable Big or Little Endian alignment

#

Full duplex operation

#

Full duplex data path allows transmission to self

#

Separate management port that is used to configure and

control operation

#

Confirmation status batching services

#

Receive frame filtering services

In addition, the DP83255 contains an additional

PHY Data.request and PHY Data.indicate port required

for concentrators and dual attach stations.

Operates from 12.5 MHz to 25 MHz synchronously with

host system

Ð

3

2.0 Architecture Description

The BSI device is composed of three interfaces and the

Map Engine.

The Control Bus Interface is separate from the BMAC de-

vice and ABus Interfaces to allow independent operation of

the Control Bus.

The three interfaces are the BMAC device, the ABus, and

the Control Bus. They are used to connect the BSI device to

the BMAC device, Host System, and external Control Bus.

The host uses the Control Bus to access the BSI device’s

internal registers, and to manage the attention/notify logic.

The Map Engine manages the operation of the BSI device.

2.2 DATA STRUCTURES

2.2.1 Data Types

2.1 INTERFACES

The BSI device connects to external components via three

interfaces: the BMAC device Interface, the ABus Interface,

and the Control Bus Interface (see Figure 2-1).

The architecture of the BSI device defines two basic kinds

of objects: Data Units and Descriptors. A Data Unit is a

group of contiguous bytes which forms all or part of a frame

(Service Data Unit). A Descriptor is a two-word (64-bit) con-

trol object that provides addressing information and control/

status information about BSI device operations.

2.1.1 BMAC Device Interface

The BSI device connects to the BMAC device via the

MA Indicate (receive) and MA Request (transmit) Inter-

faces, as shown in Figure 2-1.

Ð

Data and Descriptor objects may consist of one or more

parts, where each part is contiguous and wholly contained

within a 1k or 4k memory page. A single-part object consists

of one Only Part; a multiple-part object consists of one First

Part, zero or more Middle Parts, and one Last Part. In De-

scriptor names, the object part is denoted in a suffix, pre-

ceded by a dot. Thus an Input Data Unit Descriptor (IDUD),

which describes the last Data Unit of a frame received from

the ring, is called an IDUD.Last.

Received Data is transferred from the BMAC device to

the BSI device via the MA Indicate Interface. The

Ð

MA Indicate Interface consists of a parity bit (odd parity)

Ð

and byte-wide data along with flag and control signals.

Transmit Data is transferred from the BSI device to

the BMAC device via the MA Request Interface. The

Ð

MA Request Interface consists of a parity bit (odd parity)

Ð

and byte-wide data along with flag and control signals.

A single-part Data Unit is stored in contiguous locations

within a single 4k byte page in memory. Multiple-part Data

Units are stored in separate, and not necessarily contiguous

4k byte pages. Descriptors are stored in contiguous loca-

tions in Queues and Lists, where each Queue or List occu-

pies a single 1k byte or 4k byte memory page, aligned on

the queue-size boundary. For both Queues and Lists, an

access to the next location after the end of a page will auto-

matically wrap-around and access the first location in the

page.

2.1.2 ABus Interface

The BSI device connects to the Host System via the ABus

Interface. The ABus Interface consists of four bits of parity

(odd parity) and 32 bits of multiplexed address and data

along with transfer control and bus arbitration signals.

2.1.3 Control Bus Interface

The Control Bus Interface connects the BSI device to the

external Control Bus.

TL/F/10791–2

FIGURE 2-1. BSI Device Interfaces

4

2.0 Architecture Description (Continued)

Data Units (MAC Service Data Units) are transferred be-

tween the BSI device and BMAC device via five simplex

Channels, three used for Indicate (receive) data and two for

Request (transmit) data. Parts of frames received from the

ring and copied to memory are called Input Data Units

(IDUs); parts of frames read from memory to be tansmitted

to the ring are called Output Data Units (ODUs).

Every Output Data Unit part is described by an Output Data

Unit Descriptor (ODUD). Output Data Unit Descriptors are

fetched from memory so that frame parts can be assembled

for transmission.

Every Input Data Unit part is described by an Input Data Unit

Descriptor (IDUD). Input Data Unit Descriptors are generat-

ed on Indicate Channels to describe where the BSI device

wrote each frame part and to report status for the frame.

Descriptors are transferred between the BSI device and

Host via the ABus, whose operation is for the most part

transparent to the user. There are five Descriptor types rec-

ognized by the BSI device: Input Data Unit Descriptors

(IDUDs), Output Data Unit Descriptors (ODUDs), Pool

Space Descriptors (PSPs), Request Descriptors (REQs),

and Confirmation Message Descriptors (CNFs).

Request Descriptors (REQs) are written by the user to spec-

ify the operational parameters for BSI device Request oper-

ations. Request Descriptors also contain the start address

of part of a stream of ODUDs and the number of frames

represented by the ODUD stream part (i.e., the number of

ODUD.Last descriptors). Typically, the user will define a sin-

gle Request Object consisting of multiple frames of the

same request and service class, frame control, and expect-

ed status.

Input and Output Data Unit Descriptors describe a single

Data Unit part, i.e., its address (page number and offset),

its size in bytes, and its part (Only, First, Middle, or

Last). Frames consisting of a single part are described by

Confirmation Messages (CNFs) are created by the BSI de-

vice to record the result of a Request operation.

a

Descriptor.Only; frames consisting of multiple parts

are described by a Descriptor.First, zero or more Descrip-

tor.Middles, and a Descriptor.Last.

Pool Space Descriptors (PSPs) describe the location and

size of a region of memory space available for writing Input

Data Units.

Request (transmit) and Indicate (receive) data structures

are summarized in Figures 2-2 and 2-3.

TL/F/10791–3

FIGURE 2-2. BSI Device Request Data Structures

5

2.0 Architecture Description (Continued)

TL/F/10791–4

FIGURE 2-3. BSI Device Indicate Data Structures

2.3 MAP ENGINE

2.2.2 Descriptor Queues and Lists

The BSI device utilizes 10 Queues and two Lists. These

queues and lists are circular. There are six Queues for Indi-

cate operations, and four Queues and two Lists for Request

operations. Each of the three Indicate Channels has a Data

Queue containing Pool Space Descriptors (PSPs), and a

Status Queue containing Input Data Unit Descriptors

(IDUDs). Each Request Channel has a Data Queue contain-

ing Request Descriptors (REQs), a Status Queue containing

Confirmation Messages (CNFs), and a List containing Out-

put Data Unit Descriptors (ODUDs).

The Map Engine, which manages the operation of the BSI,

is comprised of seven basic blocks: Indicate Machine, Re-

quest Machine, Status/Space State Machine, Operation

RAM, Pointer RAM, Limit RAM, and Bus Interface Unit. An

internal block diagram of the BSI device is shown in Figure

2-4.

2.3.1 Indicate Machine

The Indicate Block accepts Service Data Units (frames)

from the BMAC device in the byte stream format (MA Indi-

cate).

Ð

During Indicate and Request operations, Descriptor Queues

and Lists are read and written by the BSI device, using reg-

isters in the Pointer and Limit RAM Register files. The Point-

er RAM Queue and List Pointer Registers point to a location

from which a Descriptor will be read (PSPs, REQs, and

ODUDs) or written (IDUDs and CNFs).

Upon receiving the data, the Indicate Block performs the

following functions:

Decodes the Frame Control field to determine the frame

type

#

Sorts the received frames onto Channels according to

the Sort Mode

#

For each Queue Pointer Register there is a corresponding

Queue Limit Register in the Limit RAM Register file, which

holds the Queue’s limit as an offset value in units of 1 De-

scriptor (8 bytes). The address in the Queue Pointer is incre-

mented before a Descriptor is read and after a Descriptor is

written, then compared with the value in the corresponding

Queue Limit Register. When a Descriptor is accessed from

the location defined by the Queue Limit Register, an atten-

tion is generated, informing the host that the Queue is emp-

ty. When a pointer value is incremented past the end of the

page, it wraps to the beginning of the page.

Filters identical MAC frames

#

Copies the received frames to memory according to

Copy Criteria

#

Writes status for the received frames to the Indicate

Status Queue

#

Issues interrupts to the host at host-defined status break-

points

#

2.3.2 Request Machine

The Request Machine presents Service Data Units (MAC

frames) to the BMAC device in the byte stream format

2.2.3 Storage Allocation

(MA Request).

Ð

The Request Machine performs the following functions:

The maximum unit of contiguous storage allocation in exter-

nal memory is a Page. All BSI device addresses consist of a

16-bit page number and a 12-bit offset.

Reads frames from host memory and assembles them

onto Request Channels

#

The BSI device uses a page size of 1K or 4k bytes for stor-

age of Descriptor Queues and Lists (as selected by the

user), and a page size of 4K bytes for storage of Data Units.

A single page may contain multiple Data Units, and multiple-

part Data Units may span multiple disjoint or contiguous

pages.

Prioritizes active requests

#

Transmits frames to the BMAC device

#

Writes status for transmitted and returning frames

#

Issues interrupts to the host on user-defined group

boundaries

#

6

2.0 Architecture Description (Continued)

TL/F/10791–5

FIGURE 2-4. BSI Device Internal Block Diagram

2.3.3 Status/Space Machine

3. Confirmation Message Descriptor stream

4. Request Descriptor stream

The Status/Space Machine is used by both the Indicate Ma-

chine and the Request Machine.

The BIU arbitrates between the Subchannels and issues a

Bus Request when any Subchannel requests service. The

priority of Subchannel bus requests is generally as follows,

from highest priority to lowest priority:

The Status/Space Machine manages all descriptor Queues

and writes status for received and transmitted frames.

2.3.4 Bus Interface Unit

1. Output Data Unit reads (highest priority)

2. Input Data Unit writes

The Bus Interface Unit (BIU) is used by both the Indicate

and Request Blocks. It manages the ABus Interface, provid-

ing the BSI device with a 32-bit data path to local or system

memory.

3. Input Data Unit Descriptor writes

4. Confirmation Message Descriptor writes

5. Pool Space Descriptor reads

6. Mailbox reads/writes

The Bus Interface Unit controls the transfer of Data Units

and Descriptors between the BSI device and Host memory

via the ABus.

7. Pointer RAM and Limit RAM Service functions (lowest

priority)

Data and Descriptors are transferred between the BSI de-

vice and Host memory in streams, where a stream is a flow

of logically related information (i.e., a single type of data or

descriptor object) in one direction (either to or from host

Addresses for Subchannel accesses are contained in the

Pointer RAM Registers.

memory). Each Channel supports

a subset of object

2.3.5 Pointer RAM

streams, via Subchannels. The three Indicate Channels

each support three Subchannels:

The Pointer RAM Block is used by both the Indicate and

Request Machines. It contains pointers to all Data Units and

Descriptors manipulated by the BSI device, namely, Input

and Output Data Units, Input and Output Data Unit Descrip-

tors, Request Descriptors, Confirmation Messages, and

Pool Space Descriptors.

1. Input Data Unit stream

2. Input Data Unit Descriptor stream

3. Pool Space Descriptor stream

The two Request Channels each support four Subchannels:

1. Output Data Unit stream

2. Output Data Unit Descriptor stream

7

3.2 MULTI-CHANNEL ARCHITECTURE

2.0 Architecture Description

(Continued)

The BSI device provides three Input Channels and two Out-

put Channels, which are designed to operate independently

and concurrently. They are separately configured by the

user to manage the reception or transmission of a particular

kind of frame (for example, synchronous frames only).

The Pointer RAM Block is accessed by clearing the PTOP

(Pointer RAM Operation) bit in the Service Attention Regis-

ter, which causes the transfer of data between the Pointer

RAM Register and a mailbox location in memory.

3.3 SUPPORT FOR HEADER/INFO SPLITTING

2.3.6 Limit RAM

In order to support high performance protocol processing,

the BSI device can be programmed to split the header and

information portions of (non-MAC/SMT) frames between

two Indicate Channels. Frame bytes from the Frame Control

field (FC) up to the user-defined header length are copied

onto Indicate Channel 1, and the remaining bytes (info) are

copied onto Indicate Channel 2.

The Limit RAM Block is used by both the Indicate and Re-

quest Machines. It contains data values that define the lim-

its of the ten Queues maintained by the BSI device.

Limit RAM Registers are accessed by clearing the LMOP

(Limit RAM Operation) bit in the Service Attention Register,

which causes the transfer of data between the Limit RAM

Register and the Limit Data and Limit Address Registers.

3.4 MAC BRIDGING SUPPORT

Support for bridging and monitoring applications is provided

by the Internal/External Sorting Mode. All frames matching

the external address (frames requiring bridging) are sorted

onto Indicate Channel 2, MAC and SMT frames matching

the internal (BMAC device) address are sorted onto Indicate

Channel 0, and all other frames matching the BMAC de-

vice’s internal address (short or long) are sorted onto Indi-

cate Channel 1.

3.0 Feature Overview

The BSI device implements a system interface for the FDDI

BMAC Device. It is designed to provide a high-performance,

low-cost interface for a variety of hosts.

On the system side, the BSI device provides a simple yet

powerful bus interface and memory management scheme to

maximize system efficiency. It is capable of interfacing to a

variety of host busses/environments. The BSI device pro-

3.5 CONFIRMATION STATUS BATCHING SERVICES

vides

a 32-bit wide multiplexed address/data interface,

which can be configured to share a system bus to main

memory or communicate via external shared memory. The

system interface supports virtual addressing using fixed-size

pages.

The BSI device provides confirmation status for transmitted

and returning frames. Interrupts to the host are generated

only at status breakpoints, which are defined by the user on

a per Channel basis when the Channel is configured for

operation.

On the network side, the BSI device performs many func-

tions which greatly simplify the interface to the BMAC de-

vice, and provides many services which simplify network

management and increase system performance and reliabil-

ity. The BSI device is capable of batching confirmation and

indication status, filtering out MAC frames with the same

information field, and performing network monitoring func-

tions.

The BSI device further reduces host processing time by

separating received frame status from the received data.

This allows the CPU to quickly scan for errors when decid-

ing whether to copy the data to memory. If the status were

embedded in the data stream, all the data would need to be

read contiguously to find the Status Indicator.

3.6 RECEIVE FRAME FILTERING SERVICES

3.1 32-BIT ADDRESS/DATA PATH TO HOST MEMORY

To increase performance and reliability, the BSI device can

be programmed to filter out identical (same FC and Info

field) MAC or SMT frames received from the ring. Filtering

unnecessary frames reduces the fill rate of the Indicate

FIFO, reduces CPU frame processing time, and avoids un-

necessary memory bus transactions.

The BSI device provides a 32-bit wide synchronous multi-

plexed address/data interface, which permits interfacing to

a

standard multi-master system bus operating from

12.5 MHz to 25 MHz, or to local memory, using Big or Little

Endian byte ordering. The memory may be static or dynam-

ic. For maximum performance, the BSI device utilizes burst

mode transfers, with four or eight 32-bit words to a burst. To

assist the user with the burst transfer capability, the three

bits of the address which cycle during a burst are output

demultiplexed. Maximum burst speed is one 32-bit word per

clock, but slower speeds may be accommodated by insert-

ing wait states.

3.7 TWO TIMING DOMAINS

To provide maximum performance and system flexibility, the

BSI device utilizes two independent clocks, one for the MAC

(ring) Interface, and one for the system/memory bus. The

BSI device provides a fully synchronized interface between

these two timing domains.

The BSI device can operate within any combination of cach-

ed/non-cached, paged or non-paged memory environ-

ments. To provide this capability, all data structures are con-

tained within a page, and bus transactions never cross a

page. The BSI device performs all bus transactions within

aligned blocks to ease the interface to a cached environ-

ment.

3.8 CLUSTERED INTERRUPTS

The BSI device can be operated in a polled or interrupt-driv-

en environment. The BSI device provides the ability to gen-

erate attentions (interrupts) at group boundaries. Some

boundaries are pre-defined in hardware; others are defined

by the user when the Channel is configured. This interrupt

scheme significantly reduces the number of interrupts to the

host, thus reducing host processing overhead.

8

4.0 Functional Description (Continued)

The BSI device is composed of the Map Engine and Inter-

faces to the Control Bus (Control Bus Interface), the BMAC

device (BMAC Device Interface) and the ABus (Abus Inter-

face).

whether they are synchronous or asynchronous, high-priori-

ty asynchronous or low-priority asynchronous, whether their

address matches an internal (BMAC device) or external ad-

dress, or the header and Information fields of all non-MAC/

SMT frames.

In this section, the Map Engine is described in detail to pro-

vide an in-depth look at the operation of the BSI device.

The Synchronous/Asynchronous Sort Mode is intended for

use in end-stations or applications using synchronous trans-

mission.

4.1 OVERVIEW

The Map Engine consists of two major blocks, the Indicate

Machine and the Request Machine. These blocks share the

Bus Interface Unit, Status/Space Machine, Pointer RAM,

and Limit RAM blocks.

With High-priority/Low-priority sorting, high-priority asyn-

chronous frames are sorted onto Indicate Channel 1 and

low-priority asynchronous frames are sorted onto Indicate

Channel 2. The most-significant bit of the three-bit priority

field within the FC field determines the priority. This Mode is

intended for end stations using two priority levels of asyn-

chronous transmission.

The Map Engine provides an interface between the BMAC

FDDI Protocol chip and a host system. The Map Engine

transfers FDDI frames (Service Data Units) between the

FDDI device and host memory.

With External/Internal sorting, frames matching the internal

address (in the BMAC device) are sorted onto Indicate

Channel 1 and frames matching an external address (when

the EA input is asserted) are sorted onto Indicate Channel

2. This mode is intended for bridges or ring monitors, which

would utilize the ECIP/EA/EM pins with external address

matching circuitry.

4.1.1 Indicate Machine

On the Receive side (from the ring) the Indicate Machine

sequences through the incoming byte stream from the

BMAC device. Received frames are sorted onto Indicate

Channels and a decision is made whether or not to copy

them to host memory. The Indicate Machine uses the con-

trol signals provided by the BMAC device Receive State

Machine on the MAC Indicate Interface.

The proper use of the ECIP, EA, and EM pins is as follows.

External address matching circuitry must assert ECIP some-

where from the assertion of FCRCVD (from the BMAC de-

vice) up to the clock cycle before the assertion of

INFORCVD (from the BMAC device). Otherwise, the BSI de-

vice assumes that no external address comparison is taking

place. ECIP must be negated for at least one cycle to com-

plete the external comparison. If it has not been deasserted

before EDRCVD (from the BMAC device) the frame is not

copied. EA and EM are sampled on the clock cycle after

ECIP is negated. ECIP is ignored after it is negated until

FCRCVD is asserted again.

4.1.2 Request Machine

On the Transmit side (to the ring) the Request Machine pre-

pares one or more frames from host memory for transmis-

sion to the BMAC device. The Request Machine provides all

the control signals to drive the BMAC device Request Inter-

face.

4.2 OPERATION

4.2.1 Indicate Operation

The Indicate Block accepts data from the BMAC device as a

byte stream.

Note that this design allows ECIP to be a positive or nega-

tive pulse. To confirm frames in this mode, (typically with

Source Address Transparency enabled), EM must be as-

serted within the same timeframe as EA.

Upon receiving the data, the Indicate Block performs the

following functions:

With the Header/Info Sort Mode, Indicate Channels 1 and 2

receive all non-MAC/SMT frames that are to be copied, but

between them split the frame header (whose length is user-

defined) and the remaining portions of the frame (Info). Indi-

cate Channel 1 copies the initial bytes up until the host-de-

fined header length is reached. The remainder of the

frame’s bytes are copied onto Indicate Channel 2. Only one

IDUD stream is produced (on Indicate Channel 1), but both

PSP Queues are used to determine where the IDUs will be

written. When a multi-part IDUD is produced, the Indicate

Status field is used to determine which parts point to the

header and which point to the Info. This Mode is intended

for high-performance protocol processing applications.

Decodes the Frame Control field to determine the frame

type

#

Sorts the received frames onto Channels according to

the Sort Mode

#

Filters identical MAC frames

#

Copies the received frames to memory according to

Copy Criteria

Writes status for the received frames to the Indicate

Status Queue

#

Issues interrupts to the host on host-defined status

breakpoints

#

The Indicate Machine decodes the Frame Control (FC) field

to determine the type of frame. Ten types of frames are

recognized: Logical Link Control (LLC), Restricted Token,

Unrestricted Token, Reserved, Station Management (SMT),

SMT Next Station Addressing, MAC Beacon, MAC Claim,

Other MAC, and Implementer.

The Indicate Machine filters identical MAC and SMT frames

when the SKIP bit in the Indicate Mode Register is set, and

the Indicate Configuration Register’s Copy Control field (2

bits) for Indicate Channel 0 is set to 01 or 10.

Received frames are copied to memory based on the

AFLAG and MFLAG, ECIP, EA, and EM input signals from

external address matching logic, input signals from the

BMAC device, as well as the Indicate Channel’s Copy Con-

trol field. Received frames are written as a series of Input

Data Units to the current Indicate page. Each frame is

aligned to the start of a currently-defined, burst-size memory

block (16 or 32 bytes as programmed in the Mode Regis-

ter’s SMLB bit). The first word contains the FC only, copied

The Indicate Machine sorts incoming frames onto Indicate

Channels according to the frame’s FC field, the state of the

AFLAG signal from the BMAC device, and the host-defined

sorting mode programmed in the Sort Mode field of the Indi-

cate Mode Register. SMT and MAC Service Data Units

(SDUs) are always sorted onto Indicate Channel 0. On Indi-

cate Channels 1 and 2, frames can be sorted according to

9

4.0 Functional Description (Continued)

into all bytes of the first word written, with the DA, SA and

INFO fields aligned to the first byte of the next word. The

format differs according to the setting of the Mode Regis-

ter’s BIGEND (Big Endian) bit, as shown in Figure 4-1.

Breakpoint bits (Breakpoint on Burst End, Breakpoint on

Service Opportunity, and Breakpoint on Threshold) in the

Indicate Mode Register, and enabling the breakpoints to

generate an attention by setting the corresponding Break-

point bit in the Indicate Notify Register.

Byte 0

Bit 31

Byte 3

Bit 0

When an Indicate exception occurs, the current frame is

marked complete, status is written into an IDUD.Last, and

the Channel’s Exception (EXC) bit in the Indicate Attention

Register is set.

Big Endian Indicate Data Unit Format

FC

DA0

FC

SA1

DA1

SA0

When an Indicate error (other than a parity error) is detect-

ed, the Channel’s Error (ERR) bit in the State Attention Reg-

ister is set. The host must reset the INSTOP Attention bit to

restart processing on the Indicate Channel.

Byte 3

Bit 31 Little Endian Indicate Data Unit Format

Byte 0

Bit 0

When parity checking is enabled and a parity error is detect-

ed in a received frame, it is recorded in the Indicate Status

field of the IDUD, and the BMAC device Parity Error (PBE)

bit in the Status Attention Register is set.

FC

SA1

SA0

DA1

DA0

FIGURE 4-1. Indicate Data Unit Formats

(Short Addresses)

4.2.2 Request Operation

The Request Block transmits frames from host memory to

the BMAC device. Data is presented to the BMAC device as

a byte stream.

For each Input Data Unit, the Indicate Machine creates an

Input Data Unit Descriptor (IDUD), which contains status in-

formation about the IDU, its size (byte count), and its loca-

tion in memory. For IDUs that fit within the current Indicate

page, an IDUD.Only Descriptor is created. For IDUs that

span more than one page, a multi-part IDUD is created, i.e.,

when a frame crosses a page boundary, the BSI device

writes an IDUD.First; if another page is crossed, an

IDUD.Middle will be written; and at the frame end, an

IDUD.Last is written. IDUDs are written to consecutive loca-

tions in the Indicate Status Queue for the particular Indicate

Channel, up to the host-defined queue limit.

The Request Block performs the following functions:

Prioritizes active requests to transmit frames

#

Requests the BMAC device to obtain a token

#

Transmits frames to the BMAC device

#

Writes status for transmitted and returning frames

#

Issues interrupts to the host on user-defined group

boundaries

#

The Request Machine processes requests by reading Re-

quest Descriptors from the REQ Queue, then assembling

frames of the specified service class, frame control and ex-

pected status for transmission to the BMAC device. Re-

quest and ODUD Descriptors are checked for consistency,

and the Request Class is checked for compatibility with the

current ring state. When an inconsistency or incompatibility

is detected, the request is aborted.

The Indicate Machine copies IDUs and IDUDs to memory as

long as there are no exceptions or errors, and the Channel

has data and status space. When a lack of either data or

status space is detected on a particular Channel, the Indi-

cate Machine stops copying new frames for that Channel

(only). It will set the No Status Space attention bit in the No

Space Attention Register when it runs out of Status Space.

It will set the Low Data Space bit in the No Space Attention

Register when the last available PSP is prefetched from the

Indicate Channel PSP Queue. The host allocates more data

space by adding PSPs to the tail of the PSP Queue and then

updating the PSP Queue Limit Register, which causes the

BSI device to clear the Low Data Space attention bit and

resume copying (on the same Channel). The host allocates

more status space by updating the IDUD Queue Limit Regis-

ter and then explicitly clearing the Channel’s No Status

Space bit, after which the Indicate Machine resumes copy-

ing.

When a consistency failure occurs, the Request is terminat-

ed with appropriate status. The Request Machine then lo-

cates the end of the current object (REQ or ODUD). If the

current Descriptor is not the end (Last bit not set), the Re-

quest Machine will fetch subsequent Descriptors until it de-

tects the end, then resume processing with the next Des-

criptor.First or Descriptor.Only.

Requests are processed on both Request Channels simul-

taneously. Their interaction is determined by their priorities

(Request Channel 0 has higher priority than Request Chan-

nel 1) and the Hold and Preempt/Prestage bits in the Re-

quest Channel’s Request Configuration Register. An active

Request Channel 0 is always serviced first, and may be pro-

grammed to preempt Request Channel 1, such that uncom-

mitted Request Channel 1’s data already in the request

FIFO will be purged and then refetched after servicing Re-

quest Channel 0. When prestaging is enabled, the next

frame is staged before the token arrives. Prestaging is al-

ways enabled for Request Channel 0, and is a programma-

ble option on Request Channel 1.

The BSI device provides the ability to group incoming

frames and then generate interrupts (via attentions) at

group boundaries. To group incoming frames, the BSI de-

vice defines status breakpoints, which identify the end of a

group (burst) of related frames. Status breakpoints can be

enabled to generate an attention.

The breakpoints for Indicate Channels are defined by the

host in the Indicate Mode, Indicate Notify, and Indicate

Threshold registers. Status breakpoints include Channel

change, receipt of a token, SA change, DA change, MAC

Info change, and the fact that a user-specified number of

frames have been copied on a particular Indicate Channel.

When a REQ.First is loaded, the Request Machine com-

mands the BMAC device to capture a token of the type

specified in the REQ Descriptor, and concurrently fetches

the first ODUD. If prestaging is enabled, or a service oppor-

tunity exists for this Request Channel, data from the first

Status breakpoint generation may be individually enabled

for Indicate Channels 1 and 2 by setting the corresponding

10

4.0 Functional Description (Continued)

ODU is loaded into the Request FIFO, and the BSI device

requests transmission from the BMAC device. When the

BMAC device has captured the appropriate token and the

frame is committed to transmission (the FIFO threshold has

been reached or the end of the frame is in the FIFO), trans-

mission begins. The BSI device fetches the next ODUD and

starts loading the ODUs of the next frame into the FIFO.

This continues (across multiple service opportunities if re-

quired) until all frames for that Request have been transmit-

ted (i.e., an REQ.ONLY or an REQ.LAST is detected), or an

exception or error occurs, which prematurely ends the Re-

quest.

frames are ignored by the BSI device. The frame count ends

when any of the following conditions occur:

1. All the frames have been transmitted, and the transmitted

and confirmed frame counts are equal.

2. There is a MACRST (MAC Reset).

3. The state of the ring-operation has changed.

4. A stripped frame or a frame with a parity error is received.

5. A non-matching frame is received.

6. A token is received.

When Source Address Transparency is selected (by setting

the SAT bit in the Request Configuration Register) and Full

confirmation is enabled, confirmation begins when a frame

end is detected with either MFLAG or EM asserted.

The BSI device will load REQ Descriptors as long as the

RQSTOP bit in the State Attention Register is Zero, the

REQ Queue contains valid entries (the REQ Queue Pointer

Register does not exceed the REQ Queue Limit Register),

and there is space in the CNF Queue (the CNF Queue

Pointer Register is less than the CNF Queue Limit Register).

When a non-matching frame is received, the BSI device

ends the Request, and generates the Request Complete

(RCM), Exception (EXC), and Breakpoint (BRK) attentions.

Any remaining REQs in the Request object are fetched until

a REQ.Last or REQ.Only is encountered. Processing then

resumes on the next REQ.First or REQ.Only (any other type

of REQ would be a consistency failure).

Request status is generated as a single confirmation object

(single- or multi-part) per Request object, with each confir-

mation object consisting of one or more CNF Descriptors.

The type of confirmation is specified by the host in the Con-

firmation Class field of the REQ Descriptor.

Request errors and exceptions are reported in the State

Attention Register, Request Attention Register, and the

Confirmation Message Descriptor. When an exception or er-

ror occurs, the Request Machine generates a CNF and

ends the Request. The Unserviceable Request (USR) atten-

tion is set to block subsequent Requests once one be-

comes unserviceable.

The BSI device can be programmed to generate CNF De-

scriptors at the end of the Request object (End Confirma-

tion), or at the end of each token opportunity (Intermediate

Confirmation), as selected in the E and I bits of the Request

Class Field of the REQ Descriptor. A CNF Descriptor is al-

ways written when an exception or error occurs (regardless

of the value in the Confirmation Class field), when a Re-

quest completes (for End or Intermediate Confirmation

Class), or when an enabled breakpoint occurs (Intermediate

Confirmation Class only).

4.2.3 State Machines

There are three state machines under control of the host:

the Request Machine, the Indicate Machine, and the

Status/Space Machine. Each Machine has two Modes:

Stop and Run. The Mode is determined by the setting of the

Machine’s corresponding STOP bit in the State Attention

Register. The STOP bits are set by the BSI device when an

error occurs or may be set by the user to place the Machine

in Stop Mode.

There are three basic types of confirmation: Transmitter,

Full, and None. With Transmitter Confirmation, the BSI de-

vice verifies that the Output Data Units were successfully

transmitted. With Full Confirmation, the Request Machine

verifies that the ODUs were successfully transmitted, that

the number of (returning) frames ‘‘matches’’ the number of

transmitted ODUs, and that the returning frames contain the

expected status. When the None Confirmation Class is se-

lected, confirmation is written only if an exception or error

occurs.

The BSI Control Registers may be programmed only when

all Machines are in Stop Mode. When the Status/Space

Machine is in Stop Mode, only the Pointer RAM and Limit

RAM Registers may be programmed.

When the Indicate and Request Machines are in Stop

Mode, all indicate and request operations are halted. When

the Status/Space Machine is in Stop Mode, only the PTOP

and LMOP service functions can be performed.

For Full Confirmation, a matching frame must meet the fol-

lowing criteria:

1. The frame has a valid Ending Delimiter (ED).

2. The selected bits in the FC fields of the transmitted and

received frames are equal (the selected bits are specified

in the FCT bit of the Request Configuration Register).

4.3 BUS INTERFACE UNIT

4.3.1 Overview

The ABus provides a 32-bit wide synchronous multiplexed

address/data bus for transfers between the host system

and the BSI device. The ABus uses a bus request/bus grant

protocol that allows multiple bus masters, supports burst

transfers of 16 and 32 bytes, and supports virtual and physi-

cal addressing using fixed-size pages. The BSI is capable of

operating directly on the system bus to main memory, or

connected to external shared memory.

3. The frame is My SA (MFLAG or both SAT & EM assert-

Ð

ed).

4. The frame matches the values in the Expected Frame

Status Register.

5. FCS checking is disabled or FCS checking is enabled and

the frame has a valid FCS.

6. All bytes from FC to ED have good parity (when the

FLOW bit in the Mode Register is set, i.e., parity checking

is enabled).

All bus signals are synchronized to the master bus clock.

The maximum burst speed is one, 32-bit word per clock, but

slower speeds may be accommodated by inserting wait

states. The user may use separate clocks for the ring (FDDI

MAC) and system (ABus) interfaces. The only restriction is

that the ABus clock must be at least as fast as the ring clock

The confirmed frame count starts after the first Request

burst frame has been committed by the BMAC device, and

when a frame with My SA is received. Void and My Void

Ð

11

4.0 Functional Description (Continued)

(LBC). It is important to note that all ABus outputs change

and all ABus inputs are sampled on the rising edge of

AB CLK.

Ð

Burst transfers are always word-aligned on a 16- or 32-byte

(burst-size) address boundary. Burst transfers will never

cross a burst-size boundary. If a 32-byte transfer size is cho-

sen, the BSI device will perform both 16-byte and 32-byte

bursts, whichever is most efficient (least number of clocks

to load/store all required data).

Addressing Modes

The Bus Interface Unit has two Address Modes, as selected

by the user: Physical Address Mode and Virtual Address

Mode. In Physical Address Mode, the BSI device emits the

memory address and immediately begins transferring the

data. In Virtual Address Mode, the BSI device inserts two

clock cycles and TRI-STATE^TMs the address between emit-

ting the virtual address and starting to transfer the data. This

allows virtual-to-physical address translation by an external

MMU.

The Bus Interface Unit can operate in either Big Endian or

Little Endian Mode. The bit and byte alignments for both

modes are shown in Figure 4-2. Byte 0 is the first byte re-

ceived from the ring or transmitted to the ring.

Bus Arbitration

The ABus is a multi-master bus, using a simple Bus Re-

quest/Bus Grant protocol that allows an external Bus Arbi-

ter to support any number of bus masters, using any arbitra-

tion scheme (e.g., rotating or fixed priority). The protocol

provides for multiple transactions per tenure, and bus mas-

ter preemption.

The BSI device interfaces to byte-addressable memory, but

always transfers information in words. The BSI device uses

a word width of 32 data bits plus 4 (1 per byte) parity bits.

Parity may be ignored.

The BSI device asserts a Bus Request, and assumes mas-

tership when Bus Grant is asserted. If the BSI device has

another transaction pending, it will keep Bus Request as-

serted, or reassert it before the completion of the current

transaction. If Bus Grant is (re)asserted before the end of

the current transaction, the BSI device retains mastership

and runs the next transaction. This process may be repeat-

ed indefinitely.

Bus Transfers

The bus supports several types of transactions. Simple

reads and writes involve a single address and data transfer.

Burst reads and writes involve a single address transfer fol-

lowed by multiple data transfers. The BSI device provides

the incrementing address bits during the burst transaction.

Burst sizes are selected dynamically by the BSI.

On Indicate Channels, when 8-word bursts are enabled, all

transactions will be 8 words until the end of the frame; the

last transfer will be 4 or 8 words, depending on the number

of remaining bytes. If only 4-word bursts are allowed, all

Indicate Data transfers are 4 words.

If the Bus Arbiter wishes to preempt the BSI device, it deas-

serts Bus Grant. The BSI device will complete the current

bus transaction, then release the bus. From preemption to

a

bus release is a maximum of (11 bus clocks

(8 times the

number of memory wait states)) bus clocks. For example, in

a 1 wait-state system, the BSI device will release the bus

within a maximum of 19 bus clocks.

On Request Channels, the BSI will use 4- or 8-word bursts

to access all data up to the end of the ODU. If 8-word bursts

are enabled, the first access will be an 8-word burst if the

ODU begins less than 4 words from the start of an 8-word

burst boundary. If 8-word bursts are not allowed, or if the

ODU begins 4 or more words from the start of an 8-word

burst boundary, a 4-word burst will be used. The BSI will

ignore unused bytes if the ODU does not start on a burst

boundary. At the end of an ODU, the BSI will use the small-

est transfer size (1, 4, or 8 words) which completes the ODU

read. To coexist in a system that assumes implicit wrap-

around for the addresses within a burst, the BSI device nev-

er emits a burst that will wrap the 4- or 8-word boundary.

Big-Endian Byte Order

[

D 31

]

[ ]

D 0

Word

Halfword 0

Halfword 1

Byte 2 Byte 3

Byte 0

Byte 1

Little-Endian Byte Order

[

D 31

]

[ ]

D 0

A Function Code identifying the type of transaction is output

by the BSI device on the upper four address bits during the

address phase of a data transfer. This can be used for more

elaborate external addressing schemes, for example, to di-

rect control information to one memory and data to another

(e.g., an external FIFO). To assist the user with the burst

transfer capability, the BSI device also outputs three demul-

tiplexed address bits during a burst transfer. These indicate

the next word within a burst to be accessed.

Word

Halfword 1

Byte 3 Byte 2

FIGURE 4-2. ABus Byte Orders

Halfword 0

Byte 1 Byte 0

Parity

There are two options for parity: one for systems using pari-

ty, the other for systems not using parity. Parity checking on

the ABus can be disabled by clearing the FLOW bit in the

Mode Register. When parity is enabled (FLOW bit is set), it

operates in flow-through mode on the main datapath, that

is, parity is not checked at the ABus but simply flows be-

tween the ABus and the BMAC device interface, and is

checked by the BMAC device as it is received. When the

FLOW bit is set, parity checking is also enabled on the Con-

trol Bus and MAC Indicate Interfaces.

Byte Ordering

The basic addressable quantum is a byte, so request data

may be aligned to any byte boundary in memory. All infor-

mation is accessed in 32-bit words, however, so the BSI

device ignores unused bytes when reading.

Descriptors must always be aligned to a word address

boundary. Input Data Units are always aligned to a burst-

size boundary. Output Data Units may be any number of

bytes, aligned to any byte-address boundary, but operate

most efficiently when aligned to a burst-size boundary.

The BSI device generates parity on all addresses output on

the ABus.

12

4.0 Functional Description (Continued)

Bandwidth

two Burst FIFOs, each containing two banks of 32 bytes,

which provide ABus bursting capability.

The ABus supports single reads and writes, and burst reads

and writes. With physical addressing, back-to-back single

reads/writes can take place every four clock cycles. Burst

transactions can transfer 8, 32-bit words (32 bytes) every 11

clock cycles. With a 25 MHz clock this yields a peak band-

width of 72.7 Mbytes/sec.

The amount of latency covered by the Data FIFO plus one

of the banks of the Burst FIFO must meet the average and

maximum bus latency of the external memory. With a new

byte every 80 ns from the ring, a 64-byte FIFO provides

e

64 x 80

5.12 ms maximum latency.

To allow the bus to operate at high frequency, the protocol

defines all signals to be both asserted and deasserted by

the bus master and slaves. Having a bus device actively

deassert a signal guarantees a high-speed inactive tran-

sition. If this were not defined, external pull-up resistors

would not be able to deassert signals fast enough. The pro-

tocol also reduces contention by avoiding cases where two

bus devices simultaneously drive the same line.

To assist latency issues, the BSI device can completely

empty or fill the Burst FIFO in one bus tenure by asserting

Bus Request for multiple transactions. Since one bank of

the Burst FIFO is 8 words deep, if 8-word bursts are en-

abled, that half of the Burst FIFO can be emptied in one

transaction. If the second half of the burst FIFO is also full, it

can be emptied in the same bus tenure by again granting

the bus to the BSI device.

The BSI device operates synchronously with the ABus

clock. In general, operations will be asynchronous to the

ring, since most applications will use a system bus clock

that is asynchronous to the ring. The BSI device is designed

to interface either directly to the host’s main system bus or

to external shared memory. When interfaced to the host’s

bus, there are two parameters of critical interest: latency

and bandwidth.

The BSI device may be preempted at any time by removing

Bus Grant, which causes the BSI device to complete the

current transaction and release the bus. There will be a

maximum of 11 clocks (plus any memory wait states) from

preemption to bus release (fewer if 8-word bursts are not

enabled).

4.3.2 Bus States

An ABus Master has eight states: idle (Ti), bus request

(Tbr), virtual address (Tva), MMU translate (Tmmu), physical

address (Tpa), data transfer (Td), wait (Tw) and recovery

(Tr). The ABus Master state diagram is shown in Figure 4-3.

Data moves between the Request and Indicate Channels

and the ABus via four FIFOs, two in the receive path (Indi-

cate) and two in the transmit path (Request). On the BMAC

Device Interface, there are two, 16 x 32 bit data FIFOs for

Indicate and Request data. On the ABus Interface, there are

An ABus Slave has five states: idle (Ti), selected (Ts), data

transfer (Td), wait (Tw), and recovery (Tr).

13

4.0 Functional Description (Continued)

14

4.0 Functional Description (Continued)

Master States

cle). If the slave can drive data at the rate of one word per

clock (in a burst), it keeps AB ACK asserted.

Ð

Following the final Td/Tw state, the BIU enters a Tr state to

allow time to turn off or turn around bus transceivers.

The Ti state exists when no bus activity is required. The BIU

does not drive any of the bus signals when it is in this state

(all are released). If the BIU requires bus service, it may

assert Bus Request.

A bus retry request is recognized in any Td/Tw state. The

BIU will go to a Tr state and then rerun the transaction when

it obtains a new Bus Grant. The whole transaction is retried,

i.e., all words of a burst. Additionally, no other transaction

will be attempted before the interrupted one is retried. The

BIU retries indefinitely until either the transaction completes

successfully, or a bus error is signaled.

When a transaction is run, the BIU enters Tbr and asserts

Bus Request, then waits for Bus Grant to be asserted.

The state following Tbr is either Tva or Tpa. In Virtual Ad-

dress Mode, the BIU enters Tva and drives the virtual ad-

dress and size lines onto the bus. In Physical Address

Mode, Tpa occurs next (see Section 4.3.3).

Bus errors are recognized in Td/Tw states.

Following a Tva state is a Tmmu state. During this cycle the

external MMU is performing a translation of the virtual ad-

dress emitted during Tva.

4.3.3 Physical Addressing Bus Transactions

Bus transactions in Physical Address Mode are shown in

Figure 4-4 through 4-7. BSI device signals are defined in

Chapter 6.

Following a Tmmu state (when using virtual addressing) or a

Tbr state (when using physical addressing), is the Tpa state.

During the Tpa state, the BSI device drives the read/write

strobes and size signals. In physical address mode, it also

Single Read

drives AB AD with address. In virtual address mode, the

Ð

BSI device TRI-STATEs AB BD so the host CPU or MMU

Ð

can drive the address.

Tbr:

BSI device asserts AB BR to indicate it wishes to

Ð

perform a transfer. Host asserts AB BG. Moves to

Ð

Tpa on the next clock.

Following the Tpa state, the BIU enters the Td state to

transfer data words. Each data transfer may be extended

indefinitely by inserting Tw states. A slave acknowledges by

Tpa:

BSI device drives AB A and AB AD with the ad-

Ð

Ð Ð

AB SIZ 2:0 , negates AB BR if another transac-

Ð

dress, asserts AB AS, drives AB RW and

[

]

tion is not required.

Ð

asserting AB ACK and transferring data in a Td state (cy-

Ð

TL/F/10791–7

FIGURE 4-4. ABus Single Read, Physical Addressing, 0 W–S, 1 W–S, Bus Handover

15

4.0 Functional Description (Continued)

Td:

BSI device negates AB AS, asserts AB DEN,

Ð Ð

samples AB ACK and AB ERR. Slave asserts

Tpa: BSI device drives AB A and AB AD with the ad-

Ð Ð

dress, asserts AB AS, drives AB RW and

Ð Ð

AB ACK, drives AB ERR, drives AB AD (with

Ð Ð

[ ]

AB SIZ 2:0 , and negates AB BR if another trans-

Ð Ð

Ð

data) when ready. The BSI device samples a valid

action is not required.

AB ACK, capturing the read data. Tw states may

Ð

occur after Td.

Td:

Tr:

BSI device negates AB AS, asserts AB DEN,

Ð

drives AB AD with the write data and starts sam-

Ð

Tr:

BSI

device

[

negates

AB SIZ 2:0 , releases AB A, and AB AS. Slave

AB RW,

AB DEN,

pling AB ACK and AB ERR. Slave captures

Ð

Ð Ð

AB AD data, asserts AB ACK, drives AB ERR.

]

deasserts AB ACK and AB ERR, releases

Ð

Tw states may occur after Td if the slave deasserts

Ð

AB AD.

Ð

AB ACK.

Ð

BSI

device

[

negates

AB SIZ 2:0 , releases AB A, AB AD, AB AS.

AB RW,

AB DEN,

Ð

Single Write

]

Slave deasserts AB ACK and AB ERR, and stops

Ð

driving AB AD with data.

Ð

Tbr: BSI device asserts AB BR to indicate it wishes to

Ð

perform a transfer. Host asserts AB BG. Moves to

Tpa on the next clock.

Ð

TL/F/10791–8

FIGURE 4-5. ABus Single Write, Physical Addressing, 0 W–S, 1 W–S, Bus Handover

16

4.0 Functional Description (Continued)

Burst Read

Td:

BSI device asserts AB DEN, samples AB ACK

Ð Ð

and AB ERR, increments the address on AB A.

Tbr: BSI device asserts AB BR to indicate it wishes to

Ð Ð

Slave asserts AB ACK, drives AB ERR, and

Ð

perform a transfer. Host asserts AB BG. Moves to

Tpa on the next clock.

Ð Ð

drives AB AD (with data) when ready. BSI device

Ð

samples a valid AB ACK, capturing the read data.

Ð

Tw states may occur after Td. Td state is repeated

four or eight times (according to the burst size). On

the last Td state, the BSI device negates AB AS.

Ð

Tpa: BSI device drives AB A and AB AD with the ad-

Ð

Ð Ð

AB SIZ 2:0 , and negates AB BR if another trans-

Ð

dress, asserts AB AS, drives AB RW and

[

]

action is not required.

Ð

Tr:

BSI

device

[

negates

AB SIZ 2:0 , and releases AB

AB RW,

AB DEN,

Ð

and AB AS.

Ð

]

Slave deasserts AB ACK and AB ERR, and re-

A

Ð

leases AB AD.

Ð

TL/F/10791–9

FIGURE 4-6. ABus Burst Read, Physical Addressing, 16 Bytes, 1 W–S

17

4.0 Functional Description (Continued)

Burst Write

Td:

BSI device asserts AB DEN, drives AB AD with

Ð Ð

the write data, samples AB ACK and AB ERR, in-

Tbr: BSI device asserts AB BR to indicate it wishes to

Ð Ð

crements the address on AB A. Slave captures

Ð

perform a transfer. Host asserts AB BG. Moves to

Tpa on the next clock.

Ð

AB AD data, asserts AB ACK, drives AB ERR.

Ð

BSI device samples a valid AB ACK. Tw states may

Ð

Tpa: BSI device drives AB A and AB AD with the ad-

Ð

Ð Ð

AB SIZ 2:0 , and negates AB BR if another trans-

Ð

dress, asserts AB AS, drives AB RW and

occur after Td. Td state is repeated as required for

the complete burst. On the last Td state, the BSI

device negates AB AS.

Ð

[

]

action is not required.

Ð

Tr:

BSI

device

[

negates

AB SIZ 2:0 , releases AB A and AB AS. Slave

AB RW,

AB DEN,

Ð

]

deasserts AB ACK and AB ERR, and stops driv-

Ð

ing AB AD with data.

Ð

TL/F/10791–10

FIGURE 4-7. ABus Burst Write, Physical Addressing, 16 Bytes 1 W–S

18

4.0 Functional Description (Continued)

4.3.4 Virtual Addressing Bus Transactions

Single Read

Burst Read

Tbr:

BSI device asserts AB BR to indicate it wishes to

Ð

perform

a

drives AB A and AB AD when AB BG is assert-

transfer. Host asserts AB BG, BSI

Ð

Tbr:

BSI device asserts AB BR to indicate it wishes to

Ð

ed. Moves to Tva on the next clock.

Ð

perform a transfer. Host asserts AB BG, and BSI

Ð

device drives AB A and AB AD when AB BG is

Ð Ð

asserted. Moves to Tva on the next clock.

Ð

Tva:

BSI device drives AB A and AB AD with the virtu-

Ð

AB RW, drives AB SIZ 2:0 , and negates

Ð

al address for one clock, negates AB AS, asserts

Tva:

BSI device drives AB A and AB AD with the virtu-

Ð

AB RW, drives AB SIZ 2:0 , and negates

Ð

al address for one clock, negates AB AS, asserts

[

]

AB BR if another transaction is not required.

Ð

[

]

AB BR if another transaction is not required.

Ð

Tmmu: Host MMU performs an address translation during

this clock.

Tmmu: Host MMU performs an address translation during

this clock.

Tpa: Host MMU drives AB AD with the translated (phys-

Ð

ical) address. BSI device drives AB A and asserts

Ð

Tpa: Host MMU drives AB AD with the translated (phys-

Ð

ical) address, BSI device drives AB A and asserts

AB AS.

Ð

Td:

BSI device asserts AB DEN, samples AB ACK

Ð Ð

AB AS.

Ð

and AB ERR. Slave asserts AB ACK, drives

Ð Ð

AB ERR, drives AB AD (with data) when ready.

Td:

Tr:

BSI device negates AB AS, asserts AB DEN,

Ð Ð

BSI device samples a valid AB ACK, capturing the

samples AB ACK and AB ERR. Slave asserts

Ð

AB ACK, drives AB ERR, drives AB AD (with

Ð

data) when ready. BSI device samples

read data. Tw states may occur after Td. This state

is repeated four or eight times (according to burst

size). On the last Td state the BSI device negates

a valid

AB ACK, capturing the read data. Tw states may

Ð

occur after Td.

AB AS.

Ð

BSI device negates AB RW, AB DEN, and

Ð

Tr:

BSI

device

negates

AB SIZ 2:0 , releases AB A and AB AS. Slave

AB RW,

AB DEN,

Ð

[

]

AB SIZ 2:0 , releases AB A and AB AS. Slave

deasserts AB ACK and AB ERR and releases

Ð

[

]

deasserts AB ACK and AB ERR, and releases

Ð

AB AD.

Ð

AB AD.

Ð

Single Write

Burst Write

Tbr:

BSI device asserts AB BR to indicate it wishes to

Ð

Tbr:

BSI device asserts AB BR to indicate it wishes to

Ð

perform a transfer. Host asserts AB BG, BSI de-

Ð

vice drives AB A and AB AD when AB BG is

perform a transfer. Host asserts AB BG, BSI de-

Ð

vice drives AB A and AB AD when AB BG is

Ð Ð

asserted. Moves to Tva on the next clock.

Ð

Ð Ð

asserted. Moves to Tva on the next clock.

Ð

Tva:

BSI device drives AB A and AB AD with the virtu-

Ð

al address for one clock, negates AB AS, negates

Tva:

BSI device drives AB A and AB AD with the virtu-

Ð

al address for one clock, negates AB AS, negates

Ð

[

]

AB RW, and drives AB SIZ 2:0 .

Ð

Tmmu: Host MMU performs an address translation during

[

]

AB RW, drives AB SIZ 2:0 .

Ð

Tmmu: Host MMU performs an address translation during

this clock.

Tpa: Host MMU drives AB AD with the address, BSI de-

Ð

vice drives AB A asserts AB AS, and negates

Tpa: Host MMU drives AB AD with the address, BSI de-

Ð

vice drives AB A asserts AB AS, and negates

Ð Ð

AB BR if another transaction is not required.

Ð Ð

AB BR if another transaction is not required.

Ð

BSI device negates AB AS, asserts AB DEN,

Ð

BSI device asserts AB DEN, drives AB AD with

Td:

Tr:

Ð Ð

drives AB AD with the write data and starts sam-

Td:

Ð Ð

the write data and starts sampling AB ACK and

Ð

pling AB ACK and AB ERR. Slave captures

Ð

AB ERR. Slave captures AB AD data, asserts

Ð Ð

AB AD data, asserts AB ACK, and drives

Ð Ð

AB ACK and drives AB ERR. BSI device sam-

Ð

samples

Ð Ð

ples a valid AB ACK. Tw states may occur after

AB ERR.

BSI

AB ACK. Tw states may occur after Td.

device

a

valid

Ð

Td. This state is repeated as required for the com-

plete burst. On the last Td state, the BSI device

BSI

device

[

negates

AB SIZ 2:0 , releases AB A, AB AD, and

AB RW,

Ð

AB DEN,

Ð

]

Slave

Ð

negates AB AS.

Ð

AB AS.

deasserts

AB ERR, and stops driving AB AD with data.

AB ACK

and

Ð

Tr:

BSI

device

[

negates

AB SIZ 2:0 , releases AB A, AB AD, AB AS.

AB RW,

AB DEN,

Ð

]

Slave deasserts AB ACK and AB ERR, stops

Ð

driving AB AD with data.

Ð

19

5.0 Control Information

5.1 OVERVIEW

Limit Address Register (LAR) is used to program the

parameters and data used in the LMOP (Limit RAM Op-

eration) service function.

#

Control information includes the parameters that are used

to manage and operate the BSI device.

Limit Data Register (LDR) is used to program the data

used in the LMOP service function.

#

Control information is divided into four basic groups: Opera-

tion Registers, Pointer RAM Registers, Limit RAM Regis-

ters, and Descriptors. The Control information Register Ad-

dress Space is shown in Table 5-1.

Request Channel 0 Configuration Register (R0CR) is

used to program the operational parameters for Request

Channel 0.

Operation registers are accessed directly via the Control

Bus. Limit RAM Registers are accessed indirectly via the

Control Bus, using the Limit RAM Data and Limit RAM Ad-

dress Registers. The Pointer RAM Registers are accessed

indirectly via the Control Bus and ABus using the Pointer

RAM Address and Control Register, the Mailbox Address

Register, and a mailbox location in ABus memory.

Request Channel 1 Configuration Register (R1CR) is

used to program the operational parameters for Request

Channel 1.

#

Request Channel 0 Expected Frame Status Register

(R0EFSR) defines the expected frame status for frames

being confirmed on Request Channel 0.

Request Channel 1 Expected Frame Status Register

(R1EFSR) defines the expected frame status for frames

being confirmed on Request Channel 1.

5.2 OPERATION REGISTERS

The Operation Registers are divided into two functional

groups: Control Registers and Event Registers. They are

shown in Table 5-2.

Indicate Threshold Register (ITR) is used to specify a

maximum number of frames that can be copied onto an

Indicate Channel before a breakpoint is generated.

Control Registers

The Control Registers are used to configure and control the

operation of the BSI device.

Indicate Mode Register (IMR) specifies how the incom-

ing frames are sorted onto Indicate Channels, enables

frame filtering, and enables breakpoints on various burst

boundaries.

The Control Registers include the following registers:

Mode Register (MR) establishes major operating pa-

rameters for the BSI device.

#

Indicate Configuration Register (ICR) is used to pro-

gram the copy criteria for each of the Indicate Channels.

#

Pointer RAM Control and Address Register (PCAR) is

used to program the parameters for the PTOP (Pointer

RAM Operation) service function.

#

Indicate Header Length Register (IHLR) defines the

length of the frame header for use with the Header/Info

Sort Mode.

Mailbox Address Register (MBAR) is used to program

the memory address of the mailbox used in the data

transfer of the PTOP service function.

#

Table 5.1 Control Register Address Space

Read

Address

Range

Write

Description

Conditions

00–1Fh

00–15h*

0–9h**

Operation Registers

Pointer RAM Registers

Limit RAM Registers

Always

Always (Conditional)

Always

*Bits 0–4 of Pointer RAM Address and Control Register

**Bits 4–7 of Limit RAM Address Register

20

5.0 Control Information (Continued)

TABLE 5-2. Control and Event Registers

Register Name

Access Rules

Write

Register

Group

Address

Read

Always

N/A

C

E

C

E

C

E

C

00

01

02

03

04

05

06

07

08

09

0A

0B

0C

0D

0E

0F

10

11

12

13

14

15

16

Mode Register (MR)

Reserved

Always

N/A

Pointer RAM Control and Address Register (PCAR)

Mailbox Address Register (MBAR)

Master Attention Register (MAR)

Always

Data Ignored

Always

Master Notify Register (MNR)

State Attention Register (STAR)

Conditional

Always

State Notify Register (STNR)

Service Attention Register (SAR)

Conditional

Always

Service Notify Register (SNR)

No Space Attention Register (NSAR)

No Space Notify Register (NSNR)

Conditional

Always

Limit Address Register (LAR)

Always

Limit Data Register (LDR)

Always

Request Attention Register (RAR)

Request Notify Register (RNR)

Conditional

Always

Request Channel 0 Configuration Register (R0CR)

Request Channel 1 Configuration Register (R1CR)

Request Channel 0 Expected Frame Status Register (R0EFSR)

Request Channel 1 Expected Frame Status Register (R1EFSR)

Indicate Attention Register (IAR)

Always

Conditional

Always

Indicate Notify Register (INR)

Indicate Threshold Register (ITR)

INSTOP Mode

e

or EXC

1 Only

C

17

Indicate Mode Register (IMR)

Always

INSTOP Mode

Only

C

18

19

Indicate Configuration Register (ICR)

Indicate Header Length Register (IHLR)

Always

INSTOP Mode

e

or EXC

1 Only

1A–C

1F

Reserved

N/A

E

Compare Register (CMP)

Always

e

C

E

Control Register

Event Register

21

5.0 Control Information (Continued)

TABLE 5-3. Control and Event Registers Following Reset

Address

00

Register

Reset

00

Mode Register

02

Pointer RAM Control and Address Register

Mailbox Address Register

NA

*

03

04

Master Attention Register

00

05

Master Notify Registers

00

06

State Attention Register

07

State Notify Register

00

08

Service Attention Register

0F

09

Service Notify Register

00

0A

0B

0C

0D

0E

0F

10

No Space Attention Register

No Space Notify Register

FF

00

Limit Address Register

NA

00

Limit Data Register

Request Attention Register

Request Notify Register

00

Request Channel 0 Configuration Register

Request Channel 1 Configuration Register

Request Channel 0 Expected Frame Status Register

Request Channel 1 Expected Frame Status Register

Indicate Attention Register

Indicate Notify Register

NA

00

11

12

13

14

15

00

16

Indicate Threshold Register

Indicate Mode Register

NA

17

18

Indicate Configuration Register

Indicate Header Length Register

Compare Register

19

1F

e

*

NA

Initialized to a silicon Revision code upon reset. The Revision code remains until it is overwritten by the host.

Not altered upon reset.

22

5.0 Control Information (Continued)

Event Registers

The Event Registers record the occurrence of events or series of events. Events are recorded and contribute to generating the

Interrupt signal. There is a two-level hierarchy in generating this signal, as shown in Figure 5-1.

At the first level of the hierarchy, events are recorded as bits in the Attention Registers (e.g., No Space Attention Register). Each

Attention Register has a corresponding Notify Register (e.g., No Space Notify Register). When a bit in the Attention Register is

set to One and its corresponding bit in the Notify Register is also set to One, the corresponding bit in the Master Attention

Register will be set to one.

At the second level of the hierarchy, if a bit in the Master Attention Register is set to One and the corresponding bit in the Master

Notify Register is set to One, the Interrupt signal is asserted.

Bits in Conditional Write Registers (e.g., No Space Attention Register) are only written when the corresponding bits in the

Compare Register are equal to the bits to be overwritten.

TL/F/10791–11

FIGURE 5-1. Event Registers Hierarchy

Events are recorded in Attention Registers and contribute to

the Interrupt when the bit in the corresponding Notify Regis-

ter is set (see Table 5-2).

Service Notify Register (SNR) is used to enable atten-

tions in the Service Attention Register.

#

No Space Attention Register (NSAR) presents atten-

tions generated when the IDUD, PSP, or CNF Queues

run out of space or valid entries.

The Event Registers include the following registers:

Master Attention Register (MAR) collects enabled at-

#

tentions from the State Attention Register, Service Atten-

tion Register, No Space Attention Register, Request At-

tention Register, and Indicate Attention Register.

Request Attention Register (RAR) presents attentions

generated by both Request Channels.

#

Request Notify Register (RNR) is used to enable atten-

tions in the Request Attention Register.

Master Notify Register (NMR) is used to selectively en-

able attention in the Master Attention Register.

#

Indicate Attention Register (IAR) presents the atten-

tions generated by the Indicate Channels.

State Attention Register (STAR) presents attentions

for major states within the BSI device and various error

conditions.

#

Indicate Notify Register (INR) is used to enable atten-

tions in the Indicate Attention Register.

State Notify Register (STNR) is used to enable atten-

tions in the State Attention Register.

#

Compare Register (CMP) is used for comparison with a

write access of a conditional write (Attention) register.

Service Attention Register (SAR) presents attentions

for the PTOP and LMOP service functions.

#

23

5.0 Control Information (Continued)

5.3 CONTROL AND EVENT REGISTER DESCRIPTIONS

Mode Register (MR)

The Mode Register (MR) is used to program the major operating parameters for the BSI device. This register should be

programmed only at power-on, or after a software Master Reset.

This register is cleared upon reset.

Access Rules

Address

Read

Write

00h

Always

Register Bits

D7

D6

D5

D4

BIGEND

D3

D2

D1

D0

SMLB

SMLQ

VIRT

FLOW

MRST

FABCLK

TEST

Bit

Symbol

Description

D0

TEST

Test Mode: Enables test logic, in which the transmitted frames counter will cause a

service loss after four frames, instead of 255 frames.

D1

FABCLK

Fast ABus Clock: Determines the metastability delay period for synchronizing between

the ABus clock and the Ring clock (LBC). Upon reset this bit is cleared to Zero, which

selects one ABus clock period as the delay. When this bit is set to One, only (/2 of an ABus

e

clock delay is used. When AB CLK

Ð

LBC, (i.e., at 12.5 MHz and in phase), this bit

should be set. For any AB CLK greater then LBC, this bit must be Zero.

Ð

D2

D3

MRST

FLOW

Master Reset: When this bit is set, the Indicate, Request, and Status/Space Macines are

placed in Stop Mode,and BSI device registers are initialized to the values shown in Table

5-5. This bit is cleared after the reset is complete.

Flow Parity: When this bit is set, parity flows between the ABus and the BMAC device,

that is, incoming data is not checked at the ABus interface, but is checked (by the BMAC

device) as it is passed to the BMAC device. The parity check includes the frame’s FC

through ED fields. When this bit is set, Control Bus parity is also checked, and errors are

reported in the CPE bit of the State Attention Register. When this bit is Zero, no parity is

checked on the Control Bus or ABus.

e

D4

D5

D6

BIGEND

VIRT

Big Endian Data Format: Selects between the Little Endian (BIGEND

e

0) or Big Endian

(BIGEND

1) data format. SeeFigure 4-2.

e

Virtual Address Mode: Selects between virtual (VIRT

address mode on the ABus.

1) or physical (VIRT

0)

SMLQ

Small Queue: Selects the size of all Descriptor queues and lists. When SMLQ

e

0, the

size is 4k bytes; when SMLQ

4k bytes.

1, the size is 1k bytes. Note that data pages are always

e

1, the BSI device uses 1- and 4-word transfers.

D7

SMLB

Small Bursts: Selects size of bursts on ABus. When SMLB

e

0, the BSI device uses 1-,

4-, and 8-word transfers. When SMLB

24

5.0 Control Information (Continued)

Pointer RAM Control and Address Register (PCAR)

The Pointer RAM Control and Address Register (PCAR) is used to program the parameters for the PTOP (Pointer RAM

Operation) service function, in which data is written to or read from a Pointer RAM Register.

This register is not altered upon reset.

Access Rules

Address

Read

Write

02h

Always

Register Bits

D7

D6

D5

PTRW

D4

D3

D2

D1

D0

BP1

BP0

A4

A3

A2

A1

A0

Bit

Symbol

Description

D0–4

A0–4

Pointer RAM Address: These five bits contain the Pointer RAM Register address for a

subsequent PTOP service function.

D5

PTRW

PTOP Read/Write: This bit determines whether a PTOP service function will be a read

e

from the Pointer RAM Register to the mailbox in memory (PTRW

e

1), or a write to the

Pointer RAM Register from the mailbox (PTRW

0).

D6–7

BP0–1

Byte Pointer: These two bits are used to program an internal byte pointer for accesses to

the 32-bit Mailbox Address Register. They are normally set to Zero to initialize the byte

pointer for four successive writes (most-significant byte first) and are automatically

incremented after each write.

25

5.0 Control Information (Continued)

Mailbox Address Register (MBAR)

The Mailbox Address Register (MBAR) is used to program the word-aligned 28-bit memory address of the mailbox used in the

data transfer of the PTOP (Pointer RAM Operation) service function.

The address of this register is used as a window into four internal byte registers. The four byte registers are loaded by

successive writes to this address after first setting the BPR bits in the Pointer RAM Control and Address Register to Zero. The

bytes must be loaded most-significant byte first. The BSI device increments the byte pointer internally after each write or read.

Mailbox Address bits 0 and 1 forced internally to Zero.

This register is initialized to a silicon Revision code upon reset. The Revision code remains until it is overwritten by the host.

Access Rules

Address

Read

Write

03h

Always

Register Bits

7

0

[

Mailbox Address 27:24

]

[

Mailbox Address 23:16

[

Mailbox Address 15:8

]

[

Mailbox Address 7:0

]

26

5.0 Control Information (Continued)

Master Attention Register (MAR)

The Master Attention Register (MAR) collects enabled attentions from the State Attention Register, Service Attention Register,

No Space Attention Register, Request Attention Register, and Indicate Attention Register. If the Notify bit in the Master Notify

Register and the corresponding bit in the MAR are set to One, the INT is forced to LOW and thus triggers an interrupt.

Writes to the Master Attention Register are permitted, but do not change the contents.

All bits in this register are set to Zero upon reset.

Access Rules

Address

Read

Write

04h

Always

Data Ignored

Register Bits

D7

D6

D5

D4

D3

D2

D1

D0

STA

NSA

SVA

RQA

INA

RES

Bit

D0–2

D3

Symbol

RES

INA

Description

Reserved

Indicate Attention Register: Is set if any bit in the Indicate Attention Register is set.

Request Attention Register: Is set if any bit in the Request Attention Register is set.

Service Attention Register: Is set if any bit in the Service Attention Register is set.

No Space Attention Register: Is set if any bit in the No Space Attention Register is set.

State Attention Register: Is set if any bit in the State Attention Register is set.

D4

RQA

SVA

D5

D6

NSA

STA

D7

27

5.0 Control Information (Continued)

Master Notify Register (MNR)

The Master Notify Register (MNR) is used to enable attentions in the Master Attention Register (MAR). If a bit in Register MNR

and the corresponding bit in Register MAR are set to One, the INT signal is deasserted and causes an interrupt.

All bits in this register are set to Zero upon reset.

Access Rules

Address

Read

Write

05h

Always

Register Bits

D7

D6

D5

D4

D3

D2

D1

D0

STAN

NSAN

SVAN

RQAN

INAN

RES

Bit

D0–2

D3

Symbol

Description

RES

Reserved

INAN

RQAN

SVAN

NSAN

STAN

Indicate Attention Register Notify: This bit is used to enable the INA bit in Register MNR.

Request Attention Register Notify: This bit is used to enable the RQA bit in Register MNR.

Service Attention Register Notify: This bit is used to enable the SVA bit in Register MNR.

No Space Attention Register Notify: This bit is used to enable the NSA bit in Register MNR.

State Attention Register Notify: This bit is used to enable the STA bit in Register MNR.

D4

D5

D6

D7

28

5.0 Control Information (Continued)

State Attention Register (STAR)

The State Attention Register (STAR) controls the state of the Indicate, Request, and Status/Space Machines. It also records

parity, internal logic, and ABus transaction errors. Each bit may be enabled by setting the corresponding bit in the State Notify

Register.

Access Rules

Address

Read

Write

06h

Always

Conditional

Register Bits

D7

D6

D5

D4

D3

D2

D1

D0

ERR

BPE

CPE

CWI

CMDE

SPSTOP

RQSTOP

INSTOP

Bit

Symbol

Description

D0

INSTOP

Indicate Stop: This bit is set by the host to place the Indicate Machine in Stop Mode. This

bit is set by the BSI device when the Indicate state machine detects an internal error,

enters an invalid state, or when the host loads the Indicate Header Length Register with an

illegal value. This bit is set upon reset.

D1

D2

RQSTOP

SPSTOP

Request Stop: This bit is set by the host to place the Request Machine in Stop Mode. This

bit is set by the BSI device when the Request Machine detects an internal error or enters

an invalid state. It is also set when an ABus error occurs while storing a Confirmation

Status Message Descriptor (CNF). This bit is set upon reset.

Status/Space Stop: This bit is set by the host to place the Status/Space Machine in Stop

Mode. This bit is set by the BSI device when the Status/Space Machine has entered

STOP Mode because of an unrecoverable error. In STOP Mode, only PTOP or LMOP

service functions will be performed. This bit is set upon reset.

D3

D4

CMDE

CWI

Command Error: Indicates that the host performed an invalid operation. This occurs when

an invalid value is loaded into the Indicate Header Length Register (which also sets the

INSTOP attention). This bit is cleared upon reset.

Conditional Write Inhibit: Indicates that at least one bit of the previous conditional write

operation was not written. This bit is set unconditionally after each write to a conditional

write register. It is also set when the value of the Compare Register is not equal to the

value of the register that was accessed for a write before it was written. This may indicate

that the accessed register has changed since it was last read. This bit is cleared after a

successful conditional write. CWI bit does not contribute to setting the STA bit of the

Master Attention Register because its associated Notify bit is always 0. This bit is cleared

upon reset.

D5

CPE

Control Bus Parity Error: Indicates a parity error detected on CBD7–0. If there is a

Control Bus parity error during a host write, the write is suppressed. Control Bus parity

errors are reported when flow-through parity is enabled (the FLOW bit of the Mode

Register is set). This bit is cleared upon reset.

D6

D7

BPE

ERR

BMAC Device Parity Error: Indicates parity error detected on MID7–0. BMAC device

parity is always checked during a frame. This bit is cleared upon reset.

Error: This bit is set by the BSI device when a non-recoverable error occurs. These

include an ABus transaction error while writing confirmation status, an internal logic error,

or when any state machine enters an invalid state. This bit is cleared upon reset.

29

5.0 Control Information (Continued)

State Notify Register (STNR)

The State Notify Register (STNR) is used to enable bits in the State Attention Register (STAR). If a bit in Register STNR is set to

One, the corresponding bit in Register STAR will be applied to the Master Attention Register, which can be used to generate an

interrupt to the host.

All bits in this register are cleared to Zero upon reset.

Access Rules

Address

Read

Write

07h

Always

Register Bits

D7

D6

D5

D4

D3

CMDEN

D2

D1

D0

ERRN

BPEN

CPEN

CWIN

SPSTOPN

RQSTOPN

INSTOPN

Bit

D0

D1

D2

D3

D4

D5

D6

D7

Symbol

Description

INSTOPN

RQSTOPN

SPSTOPN

CMDEN

CWIN

Indicate Stop Notify: This bit is used to enable the INSTOP bit in Register STAR.

Request Stop Notify: This bit is used to enable the RQSTOP bit in Register STAR.

Status/Space Stop Notify: This bit is used to enable the SPSTOP bit in Register STAR.

Command Error Notify: This bit is used to enable the CMDE bit in Register STAR.

Conditional Write Inhibit Notify: This bit is used to enable the CWI bit in Register STAR.

Control Bus Parity Error Notify: This bit is used to enable the CPE bit in Register STAR.

BMAC Device Parity Error Notify: This bit is used to enable the BPE bit in Register STAR.

Error Notify: This bit is used to enable the ERR bit in Register STAR.

CPEN

BPEN

ERRN

30

5.0 Control Information (Continued)

Service Attention Register (SAR)

The Service Attention Register (SAR) is used to present the attentions for the service functions. Each bit may be enabled by

setting the corresponding bit in the State Notify Register.

Access Rules

Address

Read

Write

08h

Always

Conditional

Register Bits

D7

D6

D5

RES

D4

D3

D2

D1

D0

RES

ABR0

ABR1

LMOP

PTOP

Bit

Symbol

Description

D0

PTOP

Pointer RAM Operation: This bit is cleared by the host to cause the BSI device to transfer

data between a Pointer RAM Register and a mailbox location in memory. The Pointer RAM

Control and Address Register contains the Pointer RAM Register address and determines

the direction of the transfer (read or write). The memory address is in the Mailbox Address

Register. This bit is set by the BSI device after it performs the data transfer.

e

or the Mailbox Address Register.

While PTOP

0 , the host must not alter the Pointer RAM Address and Control Register

D1

LMOP

Limit RAM Operation: This bit is cleared by the host to cause the BSI device to transfer

data between a Limit RAM Register and the Limit Data and Limit Address Registers. The

Limit Address Register contains the Pointer RAM Register address and determines the

direction of the transfer (read and write). This bit is set by the BSI device after it data

performs the transfer.

e

While LMOP

0, the host must not alter either the Limit Address or Limit Data Registers.

D2

D3

ABR1

ABR0

RES

Abort Request RCHN1: This bit is cleared by the host to abort a Request on RCHN1. This

bit is set by the BSI device when RQABORT ends a request on RCHN1. The host may

write a 1 to this bit, which may or may not prevent the request from being aborted. When

this bit is cleared by the host, the USR1 bit in the Request Attention Register is set and

further processing on RCHN1 is halted.

Abort Request RCHN0: This bit is cleared by the host to abort a Request on RCHN0. This

bit is set by the BSI device when RQABORT ends a request on RCHN0. The host may

write a 1 to this bit, which may or may not prevent the request from being aborted. When

this bit is cleared by the host, the USR0 bit in the Request Attention Register is set and

further processing on RCHN0 is halted.

D4–7

Reserved

31

5.0 Control Information (Continued)

Service Notify Register (SNR)

The Service Notify Register (SNR) is used to enable attentions in the Service Attention Register (SAR). If a bit in Register SNR is

set to One, the corresponding bit in Register SAR will be applied to the Master Attention Register, which can be used to

generate an interrupt to the host.

All bits in this register are set to Zero upon reset.

Access Rules

Address

Read

Write

09h

Always

Register Bits

D7

D6

D5

D4

D3

ABR0N

D2

D1

D0

RES

ABR1N

LMOPN

PTOPN

Bit

D0

Symbol

PTOPN

LMOPN

ABR1N

ABR0N

RES

Description

Pointer RAM Operation Notify: This bit is used to enable the PTOP bit in Register SAR.

Limit RAM Operation Notify: This bit is used to enable the LMOP bit in Register SAR.

Abort Request RCHN1 Notify: This bit is used to enable the ABR1 bit in Register SAR.

Abort Request RCHN0 Notify: This bit is used to enable the ABR0 bit in Register SAR.

Reserved

D1

D2

D3

D4–7

32

5.0 Control Information (Continued)

No Space Attention Register (NSAR)

The No Space Attention Register (NSAR) presents the attentions generated when the CNF, PSP, or IDUD Queues run out of

space. The host may set any attention bit to cause an attention for test purposes only, though this should not be done during

normal operation.

The No Data Space attentions are set and cleared by the BSI device automatically. The No Status Space attentions are set by

the BSI device, and must be cleared by the host.

Upon reset this register is set to 0xffh.

Access Rules

Address

Read

Write

0Ah

Always

Conditional

Register Bits

D7

D6

D5

D4

D3

D2

D1

D0

NSR0

NSR1

LDI0

NSI0

LDI1

NSI1

LDI2

NSI2

Bit Symbol

Description

D0 NSI2

D1 LDI2

No Status Space on ICHN2: This bit is set by the BSI device upon a Reset, or when an IDUD has been written to

the next-to-last available entry in the Indicate Channel’s IDUD Status Queue. When this occurs, the BSI device

stops copying on ICHN2 and the last IDUD is written with special status. This bit (as well as the USR Attention bit)

must be cleared by the host before the BSI device will resume copying on this Channel.

Low Data Space on ICHN2: This bit is set by the BSI device upon a Reset, or when a PSP is prefetched from

ICHN2’s last PSP Queue location (as defined by the PSP Queue Limit Register). Note that the amount of warning

is dependent on the length of the frame. There will always be one more page (4k bytes) available for the BSI

device when this attention is generated. Another FDDI maximum-length frame (after the current one) will not fit in

this space. If SPS fetching was stopped because there were no more PSP entries, fetching will resume

automatically when the PSP Queue Limit Register is updated.

D2 NSI1

D3 LDI1

No Status Space on ICHN1: This bit is set by the BSI device upon a Reset, or when an IDUD has been written to

the next-to-last available entry in the Indicate Channel’s IDUD Status Queue. When this occurs, the BSI device

stops copying on ICHN1 and the last IDUD is written with special status. This bit (as well as the USR Attention bit)

must be cleared by the host before the BSI device will resume copying on this Channel.

Low Data Space on ICHN1: This bit is set by the BSI device upon a Reset, or when a PSP is prefetched from

ICHN1’s last PSP Queue location (as defined by the PSP Queue Limit Register). Note that the amount of warning

is dependent on the length of the frame. There will always be one more page (4k bytes) available for the BSI

device when this attention is generated. Another FDDI maximum-length frame (after the current one) will not fit in

this space. If PSP fetching was stopped because there were no more PSP entries, fetching will resume

automatically when the PSP Queue Limit Register is updated.

D4 NSI0

D5 LDI0

No Status Space on ICHN0: This bit is set by the BSI device upon a Reset, or when an IDUD has been written to

the next-to-last available entry in the Indicate Channel’s IDUD Status Queue. When this occurs, the BSI device

stops copying on ICHN0 and the last IDUD is written with special status. This bit (as well as the USR Attention bit)

must be cleared by the host before the BSI device will resume copying on this Channel.

Low Data Space on ICHN0: This bit is set by the BSI device upon a Reset, or when a PSP is prefetched from

ICHN0’s last PSP Queue location (as defined by the PSP Queue Limit Register). Note that the amount of warning

is dependent on the length of the frame. There will always be one more page (4k bytes) available for the BSI

device when this attention is generated. Another FDDI maximum-length frame (after the current one) will not fit in

this space. If PSP fetching was stopped because there were no more PSP entries, fetching will resume

automatically when the PSP Queue Limit Register is updated.

D6 NSR1

No Status Space on RCHN1: This bit is set by the BSI device upon a Reset, or when it has written a CNF

Descriptor to the next-to-last Queue location. Due to internal pipelining, the BSI device may write up to two more

CNFs to the Queue after this attention is generated. Thus the Host must set the CNF Queue Limit Register to be

one less than the available space in the Queue. This bit (as well as the USR attention bit) must be cleared by the

Host before the BSI device will continue to process requests on RCHN1.

D7 NSR0

No Status Space on RCHN0: This bit is set by the BSI device upon a Reset, or when it has written a CNF

Descriptor to the next-to-last Queue location. Due to internal pipelining, the BSI device may write up to two more

CNFs to the Queue after this attention is generated. Thus the Host must set the CNF Queue Limit Register to be

one less than the available space in the Queue. This bit (as well as the USR attention bit) must be cleared by the

Host before the BSI device will continue to process requests on RCHN0.

33

5.0 Control Information (Continued)

No Space Notify Register (NSNR)

The No Space Notify Register (NSNR) is used to enable attentions in the No Space Attention Register (NSAR). If a bit in

Register NSNR is set to One, the corresponding bit in Register NSAR will be applied to the Master Attention Register, which can

be used to generate an interrupt to the host.

All bits in this register are set to Zero upon reset.

Access Rules

Address

Read

Write

0Bh

Always

Register Bits

D7

D6

D5

LDI0N

D4

D3

D2

D1

D0

NSR0N

NSR1N

NSI0N

LDI1N

NSI1N

LDI2N

NSI2N

Bit

D0

D1

D2

D3

D4

D5

D6

D7

Symbol

Description

NSI2N

LDI2N

NSI1N

LDI1N

NSI0N

LDI0N

NSR1N

NSR0N

No Status Space on ICHN2 Notify: This bit is used to enable the NSI2 in Register NSAR.

Low Data Space on ICHN2 Notify: This bit is used to enable the LDI2 in Register NSAR.

No Status Space on ICHN1 Notify: This bit is used to enable the NSI1 in Register NSAR.

Low Data Space on ICHN1 Notify: This bit is used to enable the LDI1 in Register NSAR.

No Status Space on ICHN0 Notify: This bit is used to enable the NSI0 in Register NSAR.

Low Data Space on ICHN0 Notify: This bit is used to enable the LDIO in Register NSAR.

No Status Space on RCHN1 Notify: This bit is used to enable the NSR1 in Register NSAR.

No Status Space on RCHN0 Notify: This bit is used to enable the NSR0 in Register NSAR.

34

5.0 Control Information (Continued)

Limit Address Register (LAR)

The Limit Address Register (LAR) is used to program the parameters for a LMOP (Limit RAM Operation) service function.

This register is not altered upon reset.

Access Rules

Address

Read

Write

0Ch

Always

Register Bits

D7

D6

D5

LRA1

D4

D3

D2

D1

D0

LRA3

LRA2

LRA0

LMRW

RES

LRD8

Bit

Symbol

Description

D0

LRD8

Limit RAM Data Bit 8: This bit contains the most-significant data bit read or written from

the addressed Limit RAM Register.

D1–2

D3

RES

Reserved

LMRW

LMOP Read/Write: This bit determines whether a LMOP service function will be a read

e

0).

e

(LMRW

1) or write (LMRW

D4–7

LRA0–3

Limit RAM Register Address: Used to program the Limit RAM Register address for a

subsequent LMOP service function.

35

5.0 Control Information (Continued)

Limit Data Register (LDR)

The Limit Data Register (LDR) is used to contain the 8 least-significant Limit RAM data bits transferred in a LMOP service

function. (The most-significant data bit is in the Limit Address register.)

This register is not altered upon reset.

Access Rules

Address

Read

Write

0Dh

Always

Register Bits

D7

D6

D5

D4

LRD4

D3

D2

D1

D0

LRD7

LRD6

LRD5

LRD3

LRD2

LRD1

LRD0

Bit

Symbol

Description

D0–7

LRD0–7

Limit RAM Data Bits 0–7: These bits contain the least-significant data bits read from or

written to a Limit RAM Register in a LMOP service function.

36

5.0 Control Information (Continued)

Request Attention Register (RAR)

The Request Attention Register (RAR) is used to present exception, breakpoint, request complete, and unserviceable request

attentions generated by each Request Channel. Each bit may be enabled by setting the corresponding bit in the Request Notify

Register.

All bits in this register are set to Zero upon reset.

Access Rules

Address

Read

Write

0Eh

Always

Conditional

Register Bits

D7

D6

D5

EXCR0

D4

D3

D2

D1

D0

USRR0

RCMR0

BRKR0

USRR1

RCMR1

EXCR1

BRKR1

Bit

Symbol

Description

D0

BRKR1

EXCR1

RCMR1

Breakpoint on RCHN1: Is set by the BSI device when a CNF Descriptor is written on

RCHN1. No action is taken by the BSI device if the host sets this bit.

D1

D2

Exception on RCHN1: Is set by the BSI device when an exception occurs on RCHN1. No

action is taken by the BSI device if the host sets this bit.

Request Complete on RCHN1: Is set by the BSI device when it has completed

processing a Request object on RCHN1, an error occurs, or a completion exception

occurs. No action is taken if the Host sets this bit.

D3

USRR1

Unserviceable Request on RCHN1: Is set by the BSI device when a Request cannot be

processed on RCHN1. This occurs when the Request Class is inappropriate for the current

ring state, or when there is no CNF status space, or when the host aborts a request by

clearing the ABR bit in the Service Attention Register. While this bit is set, no requests will

be processed on RCHN1. The host must clear this bit to resume request processing.

D4

D5

D6

BRKR0

EXCR0

RCMR0

Breakpoint on RCHN0: Is set by the BSI device when a CNF Descriptor is written on

RCHN0. No action is taken by the BSI device if the host sets this bit.

Exception on RCHN0: Is set by the BSI device when an exception occurs on RCHN0. No

action is taken by the BSI device if the host sets this bit.

Request Complete on RCHN0: Is set by the BSI device when it has completed

processing a Request object on RCHN0, an error occurs, or a completion exception

occurs. No action is taken if the Host sets this bit.

D7

USRR0

Unserviceable Request on RCHN0: Is set by the BSI device when a Request cannot be

processed on RCHN0. This occurs when the Request Class is inappropriate for the current

ring state, or when there is no CNF status space, or when the host aborts a request by

clearing the ABR bit in the Service Attention Register. While this bit is set, no requests will

be processed on RCHN0. The host must clear this bit to resume request processing.

37

5.0 Control Information (Continued)

Request Notify Register (RNR)

The Request Notify Register (RNR) is used to enable attentions in the Request Attention Register (RAR). If a bit in Register

RNR is set to One, the corresponding bit in Register RAR will be applied to the Master Attention Register, which can be used to

generate an interrupt to the host.

All bits in this register are set to Zero upon reset.

Access Rules

Address

Read

Write

0Fh

Always

Register Bits

D7

D6

D5

EXCR0N

D4

BRKR0N

D3

D2

D1

D0

USRR0N

RCMR0N

USRR1N

RCMR1N

EXCR1N

BRKR1N

Bit

D0

D1

D2

Symbol

Description

BRKR1N

EXCR1N

RCMR1N

Breakpoint on RCHN1 Notify: This bit is used to enable the BRKR1 bit in Register RAR.

Exception on RCHN1 Notify: This bit is used to enable the EXCR1 bit in Register RAR.

Request Complete on RCHN1 Notify: This bit is used to enable the RCMR1 bit in

Register RAR.

D3

USRR1N

Unserviceable Request on RCHN1 Notify: This bit is used to enable the USRR1 bit in

Register RAR.

D4

D5

D6

BRKR0N

EXCR0N

RCMR0N

Breakpoint on RCHN0 Notify: This bit is used to enable the BRKR0 bit in Register RAR.

Exception on RCHN0 Notify: This bit is used to enable the EXCR0 bit in Register RAR.

Request Complete on RCHN0 Notify: This bit is used to enable the RCMR0 bit in

Register RAR.

D7

USRR0N

Unserviceable Request on RCHN0 Notify: This bit is used to enable the USRR0 bit in

Register RAR.

38

5.0 Control Information (Continued)

Request Channel 0 and 1 Configuration Registers (R0CR and R1CR)

The two Request Configuration Registers (R0CR and R1CR) are programmed with the operational parameters for each of the

Request Channels. These registers may only be altered between Requests, i.e., while the particular Request Channel does not

have a Request loaded.

These registers are not altered upon reset.

Access Rules

Address

Read

Write

10-11h

Always

Register Bits

D7

D6

D5

D4

HLD

D3

D2

D1

D0

TT1

TT0

PRE

FCT

SAT

VST

FCS

Bit

Symbol

Description

D0

FCS

Frame Check Sequence Disable: When this bit is set, the BSI device asserts the FCST

signal throughout the request. This may drive the BMAC device FCST pin, or also the SAT

or SAIGT pins, depending on the application. This bit is normally used to program the

BMAC device not to concatenate its generated FCS to the transmitted frame. The Valid

FCS bit in the Expected Frame Status Register independently determines whether a frame

needs a valid FCS to meet the matching frame criteria.

D1

D2

VST

SAT

Void Stripping: When this bit is set, the BSI device asserts the STRIP output signal out

throughout the request. This may drive the BMAC device STRIP (Void Strip) pin, or also

the SAT pin, depending on the application.

Source Address Transparency: When this bit is set, the BSI device asserts the SAT

output signal throughout the request. This may drive the BMAC device’s SAT and/or

SAIGT pins, depending on the application. When SAT is set, Full Confirmation requires the

use of the EM (External SA Match) signal.

D3

FCT

Frame Control Transparency: When this bit is set, the FC will be sourced from the ODU

e

(not the REQ.First Descriptor). When Full Confirmation is enabled and FCT

the FC in returning frames must match the FC field in the REQ Descriptor; if FCT

the C, L and r bits must match.

0, all bits of

e

1, only

Note that since the BSI device decodes the REQ.F Descriptor FC field to determine

whether to assert RQCLM/RQBCN, FC transparency may be used to send Beacons or

Claims in any ring non-operational state, as long as the FC in the REQ Descriptor is not set

to Beacon or Claim. By programming a Beacon or Claim FC in the REQ Descriptor, then

using FC transparency, any type of frame may be transmitted in the Beacon or Claim state.

D4

HLD

Hold: When this bit is set, the BSI device will not end a service opportunity until the

Request is complete. When this bit is Zero, the BSI device ends the service opportunity on

the Request Channel when all of the following conditions are met:

1. There is no valid request active on the Request Channel.

2. The service class is non-immediate.

3. There is no data in the FIFO.

4. There is no valid REQ fetched by the BSI device.

e

prestaging is enabled on RCHN1, regardless of the state of the PRE bit (except for

This bit also affects Prestaging on RCHN1 (Request Channel 1). When HLD

0,

e

Immediate service classes). When HLD

1, prestaging is determined by the PRE bit. This

option can potentially waste ring bandwidth, but may be required (particularly on RCHN0,

Request Channel 0) if a small guaranteed service time is required.

When using the Repeat option, HLD is required for small frames. If HLD is not used, the

other Request Channel will be checked for service before releasing the token between

frames. This may not be the desired action, particularly if there is a request on RCHN1 that

needs servicing after the completion of RCHN0’s Repeated Request.

39

5.0 Control Information (Continued)

Request Channel 0 and 1 Configuration Registers (R0CR and R1CR) (Continued)

Symbol

Bit

Description

D5

PRE

Preempt/Prestage: When this bit is set, preemption is enabled for RCHN0, and prestaging is enabled for

RCHN1 (prestaging is always enabled for RCHN0). When this bit Zero, preemption is disabled and prestaging is

enabled only on RCHN0.

When preemption is enabled, RCHN0 preempts a (non-committed) frame of RCHN1 already in the FIFO,

causing it to be purged and refetched after RCHN0’s request has been serviced. When the Request Machine is

servicing a request on RCHN1 and a request on RCHN0 becomes active, if preemption is enabled on RCHN0,

the Request Machine will finish transmitting the current frame on RCHN1, then release the token and move

back to the start state. This has the effect of reprioritizing the Request Channels, thus ensuring that frames on

RCHN0 are transmitted at the next service opportunity. When RCHN0 has been serviced, transmission will

continue on RCHN1 with no loss of data.

When prestaging is enabled, the next frame for RCHN1 is staged (ODUs are loaded into the FIFO before the

token arrives). If prestaging is not enabled, the Request Machine waits until the token is captured before

staging the first frame. Once the token is captured, the Request Machine begins fetching data, and when the

FIFO threshold has been reached, transmits the data on that Request Channel. For requests with an Immediate

service class, prestaging is not applicable.

When this bit is Zero, preemption is disabled for RCHN0, and requests on RCHN1 will not be prestaged unless

the HLD bit is Zero, in which case RCHN1 will prestage data regardless of the setting of the PRE bit.

Note that when prestaging is not enabled on RCHN1, data is not staged until the token is captured. Since there

is no data in the FIFO (if there is no active request on RCHN0), the BSI device will immediately release the

token if the HLD option is not set.

D6–7

TT0–1 Transmit Threshold: Determines the threshold on the output data FIFO before the BSI device requests

transmission.

TT1

0

TT0

0

Threshold Value

8 Words

0

1

16 Words

1

0

Reserved

1

Reserved

40

5.0 Control Information (Continued)

Request Channel 0 and 1 Expected Frame Status Registers (R0EFSR and R1EFSR)

The Expected Frame Status Registers (R0EFSR and R1EFSR) define the matching criteria used for Full Confirmation of

returning frames on each Request Channel. A returning frame must meet the programmed criteria to be counted as a matching

frame.

These registers are not altered upon reset.

Access Rules

Address

Read

Write

12–13h

Always

Register Bits

D7

D6

D5

EE1

D4

D3

D2

D1

D0

VDL

VFCS

EE0

EA1

EA0

EC1

EC0

Bit

Symbol

Description

D0–1 EC0–1

D2–3 EA0–1

D4–5 EE0–1

Expected C Indicator:

EC1

EC0

Value

0

1

0

1

0

1

Any

R

S

R or S

Expected A Indicator:

EA1

EA0

Value

Any

R

0

1

0

1

0

1

S

R or S

Expected E Indicator:

EE1

0

EE0

0

Value

Any

R

0

1

0

S

1

R or S

D6

D7

VFCS

VDL

Valid FCS: When this bit is set, returning frames must have a valid FCS field to meet the confirmation criteria.

Valid Data Length: When this bit is set, returning frames must have a valid VDL field to meet the confirmation

criteria.

41

5.0 Control Information (Continued)

Indicate Attention Register (IAR)

The Indicate Attention Register (IAR) is used to present exception and breakpoint attentions generated by each Indicate

Channel. An Attention bit is set by hardware when an exception or breakpoint occurs on the corresponding Indicate Channel.

Each bit may be enabled by setting the corresponding bit in the Indicate Notify Register.

Access Rules

Address

Read

Write

14h

Always

Conditional

Register Bits

D7

D6

D5

D4

D3

D2

D1

D0

RES

EXCI0

BRKI0

EXCI1

BRKI1

EXCI2

BRKI2

Bit

Symbol

Description

D0

BRKI2

Breakpoint on ICHN2: Is set when a breakpoint is detected on Indicate Channel 2. No

action is taken if the host sets this bit.

D1

EXCI2

Exception on ICHN2: Is set by the BSI device when an exception occurs on Indicate

Channel 2. May be set by the host to disable copying on ICHN2, which is convenient when

updating the Indicate Header Length and Indicate Threshold registers. While this bit is set,

copying is disabled on ICHN2.

D2

D3

BRKI1

EXCI1

Breakpoint on ICHN1: Is set when a breakpoint is detected on Indicate Channel 1. No

action is taken if the host sets this bit.

Exception on ICHN1: Is set by the BSI device when an exception occurs on Indicate

Channel 1. May be set by the host to disable copying on ICHN1, which is convenient when

updating the Indicate Header Length and Indicate Threshold registers. While this bit is set,

copying is disabled on ICHN1.

D4

D5

BRKI0

EXCIO

Breakpoint on ICHN0: Is set when a breakpoint is detected on ICHN0. No action is taken

if the host sets this bit.

Exception on ICHN0: Is set by the BSI device when an exception occurs on Indicate

Channel 0. May be set by the host to disable copying on ICHN0, which is convenient when

updating the Indicate Header Length and Indicate Threshold registers. While this bit is set,

copying is disabled on ICHN0.

D6–7

RES

Reserved

42

5.0 Control Information (Continued)

Indicate Notify Register (INR)

The Indicate Notify Register (INR) is used to enable attentions in the Indicate Attention Register (IAR). If a bit in Register INR is

set to One, the corresponding bit in Register IAR will be applied to the Master Attention Register, which can be used to generate

an interrupt to the host.

All bits in this register are set to Zero upon reset.

Access Rules

Address

Read

Write

15h

Always

Register Bits

D7

D6

D5

D4

BRK0N

D3

D2

D1

D0

RES

EXC0N

EXC1N

BRK1N

EXC2N

BRK2N

Bit

D0

Symbol

BRK2N

EXC2N

BRK1N

EXC1N

BRK0N

EXC0N

RES

Description

Breakpoint on ICHN2 Notify: This bit is used to enable the BRK2 bit in Register IAR.

Exception on ICHN2 Notify: This bit is used to enable the EXC2 bit in Register IAR.

Breakpoint on ICHN1 Notify: This bit is used to enable the BRK1 bit in Register IAR.

Exception on ICHN1 Notify: This bit is used to enable the EXC1 bit in Register IAR.

Breakpoint on ICHN0 Notify: This bit is used to enable the BRK0 bit in Register IAR.

Exception on ICHN0 Notify: This bit is used to enable the EXC0 bit in Register IAR.

Reserved

D1

D2

D3

D4

D5

D6–7

43

5.0 Control Information (Continued)

Indicate Threshold Register (ITR)

The Indicate Threshold Register (ITR) specifies the maximum number of frames that can be received on Indicate Channel 1 or

Indicate Channel 2 before an attention will be generated. This register may be written only when the INSTOP bit in the State

Attention Register is set, or when the Indicate Channel’s corresponding EXC bit in the Indicate Attention Register is set.

This register is not altered upon reset.

Access Rules

Address

Read

Write

e

1 Only

16h

Always

INSTOP Mode or EXC

Register Bits

D7

D6

D5

D4

THR4

D3

D2

D1

D0

THR7

THR6

THR5

THR3

THR2

THR1

THR0

Bit

Symbol

Description

D0–7

THR0–7

Threshold Data Bits 0–7: The value programmed in this register is loaded into an internal

counter every time the Indicate Channel changes. Each valid frame copied on the current

Channel decrements the counter. When the counter reaches Zero, a status breakpoint

attention is generated (i.e., the Channel’s BRK bit in the Indicate Attention Register is set)

if the Channel’s Breakpoint on Threshold (BOT) bit in the Indicate Mode Register is set.

Loading the Indicate Threshold Register with Zero generates a breakpoint after 256

consecutive frames are received on any one Indicate Channel.

44

5.0 Control Information (Continued)

Indicate Mode Register (IMR)

The Indicate Mode Register (IMR) defines configuration options for all three Indicate Channels, including the sort mode, frame

filtering, and status breakpoints.

This register may be written only when the INSTOP bit in the State Attention Register is set. It may be written with its current

value any time, which is useful for one-shot sampling.

This register is not altered upon reset.

Access Rules

Address

Read

Write

17h

Always

INSTOP Mode Only

Register Bits

D7

D6

SM0

D5

D4

D3

D2

D1

D0

SM1

SKIP

RES

BOT1

BOT2

BOB

BOS

Bit

Symbol

Description

D0

BOS

Breakpoint on Service Opportunity: Enables the end of a service opportunity to

generate an Indicate breakpoint attention (i.e., set the Channel’s BRK bit in the Indicate

Attention Register). Service opportunities include receipt of a Token, a MAC Frame, or a

ring operational change following some copied frames.

D1

BOB

Breakpoint on Burst: Enables the end of a burst to generate an Indicate breakpoint

attention (i.e., set the Channel’s BRK bit in the Indicate Attention Register). End of burst

includes Channel change, DA change, SA change, or MAC INFO change. A Channel

change is detected from the FC field of valid, copied frames. A DA change is detected

when a frame’s DA field changes from our address to any other. A SA change is detected

when a frame’s SA field is not the same as the previous one. A MAC INFO breakpoint

occurs when a MAC frame does not have the identical first four bytes of INFO as the

previous frame. This breakpoint always sets the BRK bit (i.e., this breakpoint is always

enabled).

D2

D3

BOT2

BOT1

Breakpoint on Threshold for ICHN2: Enables the value in the Indicate Threshold

Register to be used to generate an Indicate breakpoint attention on Indicate Channel 2,

(i.e., set the BRK2 bit in the Indicate Attention Register).

Breakpoint on Threshold for ICHN1: Enables the value in the Indicate Threshold

Register to be used to generate an Indicate breakpoint attention on ICHN1, (i.e., set the

BRK1 bit in the Indicate Attention Register.

D4

D5

RES

SKIP

Reserved

Skip Enable: Enables filtering on Indicate Channel 0 when the Copy Control field for

ICHN0 in the Indicate Configuration Register is set to 01 or 10. When this bit is set, only

the unique MAC and SMT frames received on Indicate Channel 0 will be copied to

memory, i.e., those having an FC field or first four bytes of the Information field that differs

from the previous frame.

A write to the Indicate Mode Register disables filtering.

45

5.0 Control Information (Continued)

Indicate Mode Register (IMR) (Continued)

Bit

Symbol

Description

SM0–1

D6–7

Sort Mode: These bits determine how the BSI device sorts Indicate data onto Indicate Channels 1 and 2.

(Indicate Channel 0 always receives SMT and MAC frames.)

SM1

SM0

ICHN2

Asynchronous

External

ICHN1

Synchronous

Internal

0

1

0

1

0

1

Info

Header

Low Priority

High Priority

The Synchronous/Asynchronous Sort Mode is intended for use in end-stations or applications using

synchronous transmission.

The Internal/External Sorting Mode is intended for bridging or monitoring applications. MAC/SMT frames

matching the internal (BMAC device) address are sorted onto ICHN0, and all other frames matching the

BMAC device’s internal address (short or long) are sorted onto ICHN1. All frames matching the external

address (frames requiring bridging) are sorted onto ICHN2 (including MAC/SMT). This sorting mode

utilizes the EM, EA, and ECIP input signals with external address matching circuitry. External address

circuitry must assert ECIP sometime from the assertion of FCRCVD up to the clock before the assertion of

INFORCVD. Otherwise, the BSI device assumes no external address comparison is taking place. ECIP

must be negated before EDRCVD; if not, the frame is not copied. EA and EM are sampled on the clock

after ECIP is negated. ECIP is ignored after it is negated, until FCRCVD is asserted again. To confirm

transmitted frames in this mode (typically using SAT), EM must be asserted within the same time frame as

EA. Note that internal matches have precedence over external matches.

The Header/Info Sort Mode is intended for high performance protocol processing. MAC/SMT frames are

sorted onto ICHN0, while all other frames are sorted onto ICHN1 and ICHN2. Frame bytes from the FC up

to the programmed header length are copied onto ICHN1. The remaining bytes (info) are copied onto

ICHN2. Only one stream of IDUDs is produced (on ICHN1), but both Indicate Channel’s PSP queues are

used for space (i.e., PSPs from ICHN1 for header space, and PSPs from ICHN2 for info space). Frames

a

may comprise a header only, or a header info. For frames with info, multi-part IDUD objects are

produced. For multi-part IDUDs, the Indicate Status field in the IDUD is used to determine which part of

the IDUD object points to the end of the header. The remainder of the IDUD object points to the Info.

For example, if page crosses occur while writing the header and while writing out the Info, the BSI Device

will generate a four part IDUD object (IDUD.First, IDUD.Middle, IDUD.Middle, IDUD.Last). The IDUD.First

will have a status of ‘‘page cross’’. The first IDUD.Middle will have a status of ‘‘end of header’’. The next

IDUD.Middle will have a status of ‘‘page boundary crossed’’. The IDUD.Last will have an ‘‘end of frame’’

status.

The High Priority/Low Priority Sort Mode is intended for end stations using two priority levels of

asynchronous transmission. The priority is determined by the most-significant z-bit of the FC

e

1xx high-priority).

(zzz

0xx

low-priority; zzz

46

5.0 Control Information (Continued)

Indicate Configuration Register (ICR)

The Indicate Configuration Register (ICR) is used to program the copy criteria for each of the Indicate Channels.

This register is not altered upon reset.

Access Rules

Address

Read

Write

18h

Always

Register Bits

D7

D6

D5

D4

D3

D2

D1

D0

CC0

RES

CC1

RES

CC2

Bit

Symbol

Description

D0–1

CC2

Copy Control ICHN2:

CC1

CC0

Copy Mode

0

1

0

1

0

1

Do Not Copy

Copy if (AFLAG

E

(

ECIP & EA)) & MFLAG

l

E

ECIP & EA)) MFLAG

l

Copy Promiscously.

D2

RES

CC1

Reserved

D3–4

Copy Control ICHN1:

CC4

CC3

Copy Mode

0

1

0

1

0

1

Do Not Copy

E

Copy if (AFLAG

(

ECIP & EA)) & MFLAG

l

E

ECIP & EA)) MFLAG

l

Copy Promiscuously.

D5

RES

CC0

Reserved

D6–7

Copy Control ICHN0:

CC7

CC6

Copy Mode

0

1

0

1

0

1

Do Not Copy

E

Copy if (AFLAG

(

ECIP & EA)) & MFLAG

l

E

ECIP & EA)) MFLAG

l

Copy Promiscuously.

47

5.0 Control Information (Continued)

Indicate Header Length Register (IHLR)

The Indicate Header Length Register (IHLR) defines the length (in words) of the frame header, for use with the Header/Info Sort

Mode.

The Indicate Header Length Register must be initialized before setting the Sort Mode to Header/Info. This register may be

changed while the INSTOP bit in the State Attention Register or the EXC bit in the Indicate Attention Register is set.

This register is not altered upon reset.

Access Rules

Address

Read

Write

e

1 Only

19h

Always

INSTOP Mode or EXC

Register Bits

D7

D6

D5

D4

HL4

D3

D2

D1

D0

HL7

HL6

HL5

HL3

HL2

HL1

HL0

Bit

Symbol

Description

D0–7

HL0–7

Header Length: Specifies the length (in words) of the frame header, for use with the

Header/Info Sort Mode. The frame FC is written as a separate word, and thus counts as

one word. For example, to split after four bytes of header data in a frame with long

addresses, this register is programmed with the value 05 (1 word FC, 1.5 DA, 1.5 SA,

1 HDR DATA). IHLR must not be loaded with a value less than 4. If it is, the BSI device

Ð

sets the Command Error (CMDE) and Indicate Stop (INSTOP) attentions.

48

5.0 Control Information (Continued)

Compare Register (CMP)

The Compare Register (CMP) is used in comparison with a write access of a conditional write register. The Compare Register is

loaded on a read of any of the conditional event Attention Registers or by directly writing to it.

All bits in this register are set to Zero upon reset.

Access Rules

Address

Read

Write

1Fh

Always

Register Bits

D7

D6

D5

D4

CMP4

D3

D2

D1

D0

CMP7

CMP6

CMP5

CMP3

CMP2

CMP1

CMP0

Bit

Symbol

CMP0–7

Description

D0–7

Compare: These bits are compared to bits D0–7 of the accessed register, and only the

bits in the Attention Register that have the same current value as the corresponding bit in

the Compare register will be updated with the new value.

49

5.0 Control Information (Continued)

5.4 POINTER RAM REGISTERS

Descriptors include the following:

Pointer RAM Registers contain pointers to all data and De-

scriptors manipulated by the BSI device, namely, Input and

Output Data Units, Input and Output Data Unit Descriptors,

Request Descriptors, Confirmation Messages, and Pool

Space Descriptors. Pointer RAM Registers are shown in Ta-

ble 5-4.

Input Data Unit Descriptors (IDUDs) specify the loca-

tion, size, part, and status information for Input Data

Units.

#

Output Data Unit Descriptors (ODUDs) specify the lo-

#

cation and size of Output Data Units. For multi-ODUD

frames, they also specify which part of the frame is point-

ed to by the ODUD.

5.5 LIMIT RAM REGISTERS

Pool Space Descriptors (PSPs) describe the location

and size of a region of memory space available for writ-

ing Indicate data.

#

The Limit RAM Registers are used by both the Indicate and

Request machines. Limit RAM Registers contain data val-

ues that define the limits of the ten queues maintained by

the BSI device. Limit RAM Registers are shown in Table

5-5.

Request Descriptors (REQs) describe the location of a

stream of Output Data Unit Descriptors and contain oper-

ational parameters

#

5.6 DESCRIPTORS

Confirmation Status Messages (CNFs) describe the re-

sult of a Request operation.

#

Descriptors are used to observe and control the operation

of the BSI device. They contain address, status, and control

information about Indicate and Request operations. De-

scriptors are stored in lists and wrap-around queues in

memory external to the BSI device and accessed via the

ABus.

5.7 OPERATING RULES

Multi-Byte Register Ordering

When referring to multi-byte fields, byte 0 is always the most

significant byte. When referring to bits within a byte, bit 7 is

the most significant bit and bit 0 is the least significant bit.

When referring to the contents of a byte, the most signifi-

cant bit is always referred to first.

50

5.0 Control Information (Continued)

TABLE 5-4. Pointer RAM Registers

Access Rules

Group

Address

Register Name

Read

Always

N/A

Write

Always

N/A

00

01

02

03

04

05

06

07

08

09

0A

0B

0C

0D

0E

0F

10

11

12

13

14

15

ODU Pointer RCHN1 (OPR1)

ODUD List Pointer RCHN1 (OLPR1)

CNF Queue Pointer RCHN1 (CQPR1)

REQ Queue Pointer RCHN1 (RQPR1)

ODU Pointer RCHN0 (OPR0)

ODUD List Pointer RCHN0 (OLPR0)

CNF Queue Pointer RCHN0 (CQPR0)

REQ Queue Pointer RCHN0 (RQPR0)

IDU Pointer ICHN2 (IPI2)

P

O

I

IDUD Queue Pointer ICHN2 (IQPI2)

PSP Queue Pointer ICHN2 (PQPI2)

Next PSP ICHN2 (NPI2)

N

T

E

R

IDU Pointer ICHN1 (IPI1)

IDUD Queue Pointer ICHN1 (IPQI1)

PSP Queue Pointer ICHN1 (PQPI1)

Next PSP ICHN1 (NPI1)

R

A

M

IDU Pointer ICHN0 (IPI0)

IDUD Queue Pointer ICHN0 (IQPI0)

PSP Queue Pointer ICHN0 (PQPI0)

Next PSP ICHN0 (NPI0)

IDUD Shadow Register (ISR)

ODUD Shadow Register (OSR)

Reserved

16-

1F

TABLE 5-5. Limit RAM Registers

Register Name

Access Rules

Group

Address

Read

Always

N/A

Write

Always

N/A

0

1

REQ Queue Limit RCHN1 (RQLR1)

CNF Queue Limit RCHN1 (CQLR1)

REQ Queue Limit RCHN0 (RQLR0)

CNF Queue Limit RCHN0 (CQLR0)

IDUD Queue Limit ICHN2 (IQLI2)

PSP Queue Limit ICHN2 (PQLI2)

IDUD Queue Limit ICHN1 (IQLI1)

PSP Queue Limit ICHN1 (PQLI1)

IDUD Queue Limit ICHN0 (IQLI0)

PSP Queue Limit ICHN0 (PQLI0)

Reserved

2

L

I

3

M

I

4

T

5

6

R

A

7

M

8

9

A–F

51

5.0 Control Information (Continued)

PSP Queue Pointer Register: Points to the next available

PSP. Initialized by the host with the start address of the PSP

Queue, after the Queue has been initialized with valid PSP

Descriptors. As each PSP is read from memory, this register

is loaded with the address in the Next PSP Register.

5.8 POINTER RAM REGISTER DESCRIPTIONS

The Pointer RAM Register set contains 32, 28-bit registers.

Registers 23 through 31 are reserved, and user access of

these locations produces undefined results.

Pointer RAM Registers are read and written by the host

using the Pointer RAM Operation (PTOP) service function

and are accessed directly by BSI device hardware during

Indicate and Request operations.

Next PSP Register: Written by the BSI device with the PSP

fetched from the PSP Queue.

Indicate Shadow Register: Written by the BSI device with

the start address of the last IDU copied to memory.

During Indicate and Request operations, Pointer RAM regis-

ters are used as addresses for ABus accesses of data and

Descriptors, i.e., the subchannel addresses for loads

(reads) of streams of PSPs, ODUs, ODUDs, and REQs, and

for stores (writes) of streams of IDUs, IDUDs, and CNFs.

Request Shadow Register: Written by the BSI device with

the address of the current ODUD.

See Table 5-4 for Summary including address and access

rules.

Pointer RAM Registers include the following:

5.9 LIMIT RAM REGISTER DESCRIPTIONS

ODU Pointer: Contains the address of an Output Data Unit.

During Request operations, this register is loaded by the BSI

device from the Location Field of its Output Data Unit De-

scriptor.

The Limit RAM Register set contains 16, 9-bit registers.

Registers 11 through 15 are reserved, and used access of

these locations produces undefined results.

The Limit RAM registers contain data values that define the

limits of each of the ten queues maintained by the BSI de-

vice.

ODUD List Pointer: Loaded by the BSI device from the

Location Field of the REQ Descriptor when it is read from

memory. The address is incremented by the BSI device as

each ODUD is fetched from memory.

Limit RAM Registers are read and written by the host using

the Limit RAM Operation (LMOP) service function when the

Status/Space Machine is in STOP Mode, and are read di-

rectly by BSI device hardware during Indicate and Request

operations.

CNF Queue Pointer: Contains the current CNF Status

Queue address. This register is written by the user after he

has allocated space for the CNF Queue. During Request

operations, this register is incremented by the BSI device

after each CNF is written to the CNF Queue.

Limit RAM Registers include the following:

REQ Queue Limit: Defines the last valid REQ written by the

host.

REQ Queue Pointer: Initialized by the host with the start

address of the REQ Descriptor Queue after the Queue has

been initialized. During Request operations, the address is

incremented by the BSI device as each REQ is fetched.

CNF Queue Limit Register: Defines the last Queue loca-

tion where a CNF may be written by the BSI device. Due to

pipelining, the BSI device may write up to two CNFs after it

detects a write to the next-to-last CNF entry (and generates

a No Status Space Attention). For this reason, the host must

always define the CNF queue limit to be one Descriptor less

than the available space.

IDU Pointer: Written by the BSI device with the Location

Field of the PSP Descriptor when it is read from memory.

IDUD Queue Pointer: Points to the Queue location where

IDUDs will be stored. Written by the user after he has allo-

cated space for the IDUD Status Queue. Incremented by

the BSI device as IDUDs are written to consecutive loca-

tions in the Queue.

IDUD Queue Limit Register: Defines the last Queue loca-

tion where an IDUD may be written by the BSI device.

PSP Queue Limit: Defines the last valid PSP written by the

host.

See Table 5-5 for Summary including address and access

rules.

52

5.0 Control Information (Continued)

5.10 BSI DEVICE DESCRIPTORS

Input Data Unit Descriptor (IDUD)

Input Data Unit Descriptors (IDUDs) are generated on Indicate Channels to describe where the BSI device wrote each frame

part and to report status for the frame.

For multi-part IDUDs, intermediate status is written in each IDUD, and when a status event occurs, definitive status is written in

the last IDUD.

A detailed description of the encodings of the Indicate Status bits is given in Table 5-6.

31

30

29

28

27

24 23

16

15

VC

14

13 12

0

IS

FRA

FRS

RES

CNT

Word 0

Word 1

F–L

RES

LOC

Word 0

Bit

Symbol

CNT

Description

D0–12

Byte Count: Number of bytes in the SDU.

D13–14

D15

RES

Reserved

VC

VCOPY: Reflects the state of the VCOPY signal sent to the BMAC device for this

frame.

0: VCOPY was negated.

1: VCOPY was asserted.

D16–23

FRS

C

Frame Status: This field is valid only for Full Confirmation, and if the frame ended

with an ED.

D16–17

D18–19

D20–21

C Indicator:

00: none

01:

10:

11:

R

S

T

A

E

A Indicator:

00: none

01:

10:

11:

R

S

T

E Indicator:

00: none

01:

10:

11:

R

S

T

D22

D23

VFCS

VDL

Valid FCS:

0: FCS field was invalid

1: FCS field was valid

Valid Data Length:

0: Data length was invalid

1: Data length was valid

53

5.0 Control Information (Continued)

5.10 BSI DEVICE DESCRIPTORS (Continued)

Input Data Unit Descriptor (IDUD) (Continued)

Word 0 (Continued)

Bit

Symbol

Description

D24–27

FRA

Frame Attributes

D24- TC

25

Termination Condition: This field is valid only for Full Confirmation.

00: Other (e.g., MAC Reset/token).

01: ED.

10: Format error.

11: Frame stripped.

D26 AFLAG

AFLAG: Reflects the state of the AFLAG input signal, which is sampled by the BSI device at

INFORCVD.This field is valid only for Full Confirmation.

0: External DA match.

1: Internal DA match.

D27 MFLAG MFLAG: Reflects the state of the MFLG input signal, which is sampled by the BSI device at INFORCVD.

This field is valid only for Full Confirmation.

0: Frame sent by another station.

1: Frame sent by this station.

D28–31

IS

Indicate Status: The values in this field are prioritized, with the highest number having the highest

priority. A detailed description of the encodings is given in Table 5-6.

IS3

IS2 IS1 IS0 Meaning

Non-end Frame Status

0

1

0

1

0

1

Last IDU of queue, page-cross.

Page boundary crossed.

End of header.

Page-cross with header-end.

Normal-end Frame Status

0

1

0

1

0

1

0

1

Intermediate (no breakpoints).

Burst boundary.

Threshold.

Service opportunity.

Copy Abort due to No Space

1

0

1

0

1

0

1

No data space.

No header space.

Good header, info not copied.

Not enough info space.

Error

1

0

1

0

1

0

1

FIFO overrun.

Bad frame (no VDL or no VFCS).

Parity error.

Internal error.

Word 1

Bit

Symbol

Description

D0–27

LOC

Location: 28-bit memory address of the start of an IDU. For the first IDU of a frame, the address is of

e

]

[

the fourth FC byte of the burst-aligned frame (i.e., bits 1:0

11). For subsequent IDUs, the address

e

]

[

is of the first byte of the IDU (i.e, bits 1:0

00).

D28–29

D30–31

RES

F–L

Reserved

First/Last Tag: Identifies the IDU object part, i.e., Only, First, Middle, or Last.

54

5.0 Control Information (Continued)

TABLE 5-6. Indicate Status Field (IS) of IDU Descriptor

NON-END FRAME STATUS

[

]

0000

Last IDUD of Queue, with a Page Cross: The last available location of the ICHN’s IDUD queue was written. Since there

was a page cross, there was more data to be written. Since there was no more IDUD space, the remaining data was not

written. Note that this code will not be written in a IDU.Middle, so that a Zero IS field with Zero F–L tags can be utilized by

software as a null descriptor.

[

]

0001

Page Cross: Must be an IDUD.FIRST or IDUD.MIDDLE. This is part of a frame that filled up the remainder of the current

page, requiring a new page for the remainder of the data.

[

]

0010

Header End: This refers to the last IDU of the header portion of a frame.

0011

Page Cross and Header End: The occurrence of a page cross and header end.

NORMAL-END FRAME STATUS

[

]

0100

0101

0110

0111

Intermediate: A frame ended normally, and there was no breakpoint.

Burst Boundary: A frame ended normally, and there was a breakpoint because a burst boundary was detected.

Threshold: The copied frame threshold counter was reached when this frame was copied, and the frame ended normally.

Service Opportunity: This (normal end) frame was preceeded by a token or MACRST, a MAC frame was received, or there

was a ring-op change. Any of these events marks a burst boundary.

NO SPACE COPY ABORT

[

]

1000

1001

1010

1011

Insufficient Data Space: Not all the frame was copied because there was insufficient data space. This code is only written

in non-Header/Info Sort Mode.

Insufficient Header Space: The frame copy was aborted because there was insufficient header space (in Header/Info

Sort Mode).

Successful Header Copy, Frame Info Not Copied: There was sufficient space to copy the header, but insufficient data

space to copy info, or insufficient IDU space (on ICHN2), or both. No info was copied.

No Info Space: The frame’s header was copied. When copying the data, there was insufficient data and/or IDU space.

ERROR

[

]

1100

1101

1110

1111

FIFO Overrun: The Indicate FIFO had an overrun while copying this frame.

Bad Frame: The frame did not have a valid data length, or had invalid FCS, or both.

Parity Error: There was a parity error during this frame.

Internal Error: There was an internal logic error during this frame.

55

5.0 Control Information (Continued)

REQ Descriptor (REQ)

The BSI device checks for the following inconsistencies

when the REQ is loaded from memory:

Request Descriptors (REQs) contain the part, byte address,

and size of one or more Output Data Unit Descriptors. They

also contain parameters and commands to the BSI device

associated with Request operations.

1. REQ.F with invalid Confirmation Class (as shown in the

Table 5-8).

e

2. REQ.First with Request Class

0.

Multiple REQ Descriptors (parts) may be grouped as one

Request Descriptor object by the host software, with the

REQ.First defining the parameters for the entire Request

object. Also, multiple Output Data Unit Descriptors may be

grouped contiguously, to be described by a single REQ De-

scriptor.

3. REQ.First, when the previous REQ was not a REQ.Last

or REQ.Only.

4. REQ which is not a REQ.First, when the previous REQ

was a REQ.Last or a REQ.Only.

When an inconsistency is detected, the BSI device aborts

the Request, and reports the exception in the Request

Status field of the CNF Descriptor.

Each REQ part is fetched by the BSI device from the Re-

quest Channel’s REQ Descriptor Queue, using the REQ

Queue Pointer Register. Each Request Channel processes

one Request Descriptor, per service opportunity, until a

REQ.Last is encountered.

The encodings of the RQCLS and CNFCLS bits are de-

scribed in more detail in Tables 5-7 and 5-8 respectively.

31

30

29

28

27

24

23

16

15

12

11

8

7

0

Word 0

Word 1

RES

F–L

UID

SIZE

CNFCLS

RQCLS

FC

RES

LOC

Word 0

Bit

Symbol

Description

D0–7

FC

Frame Control: Frame control field to be used unless FC transparency is enabled. This field is

decoded to determine whether to assert RQCLM or RQBCN. This decoding is always active, i.e.,

regardless of frame control transparency. This field is also used for comparing received frames

when confirming (without FC transparency).

D8–11

RQCLS

Request/Release Class: This field encodes the Request Class for the entire Request object, and is

thus only sampled on a REQ.First or REQ.Only. The field is asserted on the RQRCLS output signals

to the BMAC device when requesting a token. If the Request Class is incompatible with the current

ring state, the BSI device sets the RCHN’s USR bit in the Request Attention Register. The encoding

of this field is shown in Table 5-7.

D12–15

CNFCLS

E

Confirmation Class: This field encodes the Confirmation Class for the entire Request object, and is

only sampled on a REQ.First or REQ.Only. The encoding of this field is shown in Table 5-8.

D12

End: Enables confirmation on completion of request.

0: CNFs on completion disabled.

1: CNFs on completion enabled.

D13

D14

D15

I

Intermediate: Enables Intermediate Confirmation.

0: Intermediate CNFs disabled.

1: Intermediate CNFs enabled.

F

R

Full/Transmitter: Selects between Transmitter and Full Confirmation.

0: Transmitter confirm.

1: Full confirm.

Repeat: Enables repeated transmission of the first frame of the request until the request is aborted.

This may be used when sending BEACON or CLAIM frames.

0: Fetch all frames of REQ.

1: Repeat transmission of first frame of REQ.

A Request may use Repeat on RCHN1, and have a Request loaded on RCHN0, but not vice-versa.

Specifically, when a Request with the Repeat option is loaded on RCHN0, RCHN1 must not have

any REQs active or visible to the BSI device. Thus REQs on RCHN1 may be queued externally but

the queue’s Limit Register must not be set at or after that point. Requests with the Repeat option

should only be used on one Request Channel at a time, and preferably on RCHN0.

56

5.0 Control Information (Continued)

REQ Descriptor (REQ) (Continued)

Word 0 (Continued)

Bit

Symbol

Description

D16–23

SIZE

Size: Count of number of frames represented by the ODUD stream pointed to by LOC. REQ Descriptors

with a frame count are permitted, and are typically used to end a Request, without having to send data.

e

For example, to end a restricted dialogue, a REQ.Last with SIZE

command the BMAC device to capture and release the specified classes of token. The response of the

0 will cause the Request Machine to

e

BSI device to REQs with SIZE

0 is as follows:

1. REQ.First: BSI device latches the REQ Descriptor fields, then fetches the next REQ. REQRCLS is

asserted, but RQRDY remains deasserted.

2. REQ.Middle: BSI device fetches the next REQ.

3. REQ.Only: BSI device requests the capture of the appropriate token. When it is captured, the BSI

asserts RQFINAL and ends the request.

4. REQ.Last: BSI device captures the token, asserts RQFINAL, then marks the request complete.

D24–29

D30–31

UID

User Identification: Contains the UID field from the current REQ.First or REQ.Only.

RES

Reserved

Word 1

Bit

Symbol

Description

[

]

[

Location: Bits 27:2 are the memory word address of ODUD stream. Bits 1:0 are expected to be 00,

]

D0–27

LOC

and are not checked.

D28–29

D30–31

RES

F–L

Reserved

First/Last Tag: Identifies the ODUD stream part, i.e., Only, First, Middle, or Last.

57

5.0 Control Information (Continued)

TABLE 5-7. REQ Descriptor Request Class Field Encodings

RQCLS

Value

RQCLS

Name

Class

Type

Token

Issue

THT

Notes

Capture

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

None

Ð

E

none

non-r

non

Apr1

Async pri1

Reserved

Sync

non-r

Reserved

Syn

D

E

D

any

capt

1

4

Imm

Immed

none

non-r

restr

non-r

restr

none

non-r

restr

non-r

restr

non-r

restr

non-r

restr

non-r

restr

ImmN

ImmR

Asyn

Immed

Async

Rbeg

Restricted

Async

2, 3

2

Rend

Rcnt

2

AsynD

RbegD

RendD

RcntD

Restricted

2, 3

2

D

2

e

restricted, capt captured

E

enabled, D

disabled, non-r

non-restricted, restr

Note 1: Synchronous Requests are not serviced when bit BCNR of the Ring Event Latch Register is set.

Note 2: Restricted Requests are not serviced when bit BCNR, CLMR, or OTRMAC of the Ring Event Latch Register is set.

Note 3: Restricted Dialogues only begin when a Non-Restricted token has been received and transmitted.

Note 4: Immediate Requests are serviced when the ring is Non-Operational. These requests are serviced from the Data state if neither signal RQCLM nor RQBCN

is asserted. If signal RQCLM is asserted, Immediate Requests are serviced from the Claim State. If signal RQBCN is asserted, Immediate Requests are serviced

from the Beacon State. RQCLM and RQBCN do not cause transitions to the Claim and Beacon States.

TABLE 5-8. REQ Descriptor Confirmation Class Field Encodings

[

]

[ ]

[

]

R

F

I

E

Confirmation Class

Invalid (consistency failure)

x

0

x

0

1

0

1

0

1

Invalid (consistency failure)

None: Confirmation only on exception

Tend: Transmitter confirm, CNF on exception or completion

Tint: Transmitter confirm, CNF on exception,

completion or intermediate

0

1

0

1

Fend: Full Confirm, CNF on exception or completion

Fint: Full Confirm, CNF on exception,

completion or intermediate

1

0

1

NoneR: Confirmation only on exception, repeat frame

TendR: Transmitter confirm, CNF on exception

or completion, repeat frame

1

0

1

0

1

TintR: Transmitter confirm, CNF on exception, completion

or intermediate, repeat frame

FendR: Full confirmation, CNF on exception or

completion, repeat frame

FintR: Full Confirmation, CNF on exception,

completion, or intermediate, repeat frame

58

5.0 Control Information (Continued)

Output Data Unit Descriptor (ODUD)

An Output Data Unit Descriptor (ODUD) contains the part, byte address and size of an Output Data Unit. During Request

operations, ODUDs are fetched by the BSI device from a list in memory, using the address in the ODUD List Pointer Register (in

the Pointer RAM).

ODUDs may have a zero byte count, which is useful for fixed protocol stacks. One layer may be called, and if it has no data to

add to the frame, it may add an ODUD with a zero byte count to the list.

The BSI device checks for the following inconsistencies when an ODUD is loaded from memory:

1. ODUD.First, when the previous ODUD was not an ODUD.Last or ODUD.Only.

2. ODUD which is not an ODUD.First, when the previous ODUD was an ODUD.Last or ODUD.Only.

3. ODUD.First with zero byte count.

When an inconsistency is detected, the BSI device aborts the Request, and reports the exception in the Request Status field of

the CNF Descriptor.

ODUDs must contain at least 4 bytes (for short addresses).

31

30

29

28

27

13

12

0

RES

CNT

Word 0

Word 1

F–L

RES

LOC

Word 0

Bit

Symbol

Description

D0–12

CNT

Byte Count: Number of bytes in the ODU. The size may be Zero, which is useful for fixed

protocol stacks.

D13–31

RES

Reserved

Word 1

Bit

Symbol

LOC

Description

Location: Memory byte address of SDU.

D0–27

D28–29

D30–31

RES

Reserved

F–L

First/Last Tag: Identifies the Output Data Unit part, i.e., Only, First, Middle, or Last.

59

5.0 Control Information (Continued)

Confirmation Status Message Descriptor (CNF)

A Confirmation Status Message (CNF) describes the result of a Request operation.

A more detailed description of the encoding of the RS bits is given in Table 5-9.

31

30

29

28

27

24

23

16

15

8

7

0

RS

FRA

FRS

FC

TFC

CS

CFC

RES

Word 0

Word 1

F–L

UID

Word 0

Bit

Symbol

Description

D0–7

CFC

Confirmed Frame Count: Number of confirmed frames. Valid only for Full

Confirmation.

D8–15

TFC

FRS

C

Transmitted Frame Count: Number of frames successfully transmitted by the

BSI device and BMAC device. Valid for all confirmation classes.

D16–23

Frame Status: This field is valid only for Full Confirmation, and if the frame

ended with an ED.

D16–17

D18–19

D20–21

C Indicator:

00: None

01:

10:

11:

R

S

T

A

E

A Indicator:

00: None

01:

10:

11:

R

S

T

E Indicator:

00: None

01:

10:

11:

R

S

T

D22

D23

VFCS

VDL

Valid FSC:

0: FSC Field was Invalid.

1: FSC Field was Valid.

Valid Data Length:

0: Data Length was Invalid.

1: Data Length was Valid.

D24–27

FRA

TC

Frame Attributes: This field is valid only for Full Confirmation.

D24–25

Terminating Condition:

00: Other (e.g., MAC Reset/token).

01: Ed.

10: Format Error.

11: Frame Stripped.

D26

D27

AFLAG

MFLAG

AFLAG: Reflects the state of the AFLAG input signal, which is sampled by the

BSI device at INFORCVD.

0: No DA Match.

1: DA Match.

MFLAG: Reflects the state of the MFLAG input signal, which is sampled by the

BSI device at INFORCVD.

0: Frame Sent by another Station.

1: Frame Sent by this Station.

60

5.0 Control Information (Continued)

Confirmation Status Message Descriptor (CNF) (Continued)

Word 0 (Continued)

Bit

Symbol

Description

D28–31 RS

Request Status: This field represents a priority encoded status value, with the highest number having the

highest priority. This field is described in Table 5–9.

RS3

RS2

RS1

RS0

Meaning

Intermediate

0

1

0

1

0

None

0

Preempted

Part Done

0

Breakpoints

0

1

0

1

0

Service Loss

Reserved

0

Completion

0

1

0

1

0

Completed BEACON

Completed OK

Exception Completion

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Bad Confirmation

Underrun

1

Host Abort

1

Bad Ringop

MAC Abort

1

Timeout

1

MAC Reset

Consistency Failure

Error

1

Internal or Fatal ABus Error

61

5.0 Control Information (Continued)

Confirmation Status Message Descriptor (CNF) (Continued)

Word 1

Bit

Symbol

RES

CS

Description

D0–7

D8–15

Reserved

Confirmation Status

D8–9

FT

Frame Type: This field reflects the type of frame that ended Full Confirmation.

00: Any Other.

01: Token.

10: Other Void.

00: My Void.

D10

D11

F

Full Confirm: This bit is set when the Request was for Full Confirmation.

U

Unexpected Frame Status: This bit is set when the frame status does not

match the value programmed in the Request Expected Frame Status Register.

This applies only to Full Confirmation.

D12

D13

D14

D15

P

E

R

T

Parity: This bit is set when a parity error is detected in a received frame. Parity is

checked from FC to ED inclusive if the FLOW bit in the Mode Register is set.

Exception: This bit is set when an exception occurs. The RCHN’s EXC bit in the

Request Attention Register is also set.

Ring-Op: This bit is set when the ring enters a bad operational state after

transmission but before all returning frames have been confirmed.

Transmit Class:

0: Restricted.

1: Non-Restricted.

D16–23

D24–29

D30–31

FC

Frame Control: Frame Control field of the last frame of the last confirmed burst.

Valid only for Full Confirmation.

UID

F–L

User Identification: Contains the UID field copied from the current REQ.FIRST

or REQ.ONLY.

First/Last Tag: Identifies the CNF part, i.e., Only, First, Middle, or Last.

62

5.0 Control Information (Continued)

TABLE 5–9. Request Status (RS) Field of CNF Descriptor

INTERMEDIATE

[

]

0000

None: Non status is written. This may be used by software to identify a NULL or invalid CNF.

[

]

0001

Preempted: RCHN1 was preempted by RCHN0. RCHN1 will be serviced following RCHN0.

Part None: The BSI device is servicing a Request, but it cannot hold onto a token, and the last frame of a

Request.part has been transmitted.

0010

BREAKPOINTS

[

]

0011

Service Loss: The THT expired during a Request with THT enabled. Only occurs for Intermediate Confirmation.

0100

Reserved

COMPLETION

[

]

0101

0110

Completed BEACON: When transmitting from the BEACON state, this status is returned when the BMAC device

receives a My Beacon. When transmitting from the CLAIM state, this status is returned when the BMAC device

Ð

wins the CLAIM process.

]

Completed OK: Normal completion with good status.

EXCEPTION COMPLETION

[

]

0111

Bad Confirmation: There was an error during confirmation, causing the Request to complete with this status, or one

of higher priority. Confirmation errors include MACRST, ring-operational change, receiving an Other Void or My

Ð Ð

Void or token, receiving a bad frame, or receiving a frame that did not match the programmed expected frame status.

[

]

1000

Underrun: There was no data in the request data FIFO when it was required to be presented to the BMAC device.

1001

Host Abort: The host aborted the Request on this Request Channel, either directly by clearing the ABT bit in the

Service Attention Register or indirectly by having insufficient entries in the CNF queue.

[

]

1010

Bad Ringop: A Request was loaded with a Request Class inappropriate for the current ring operational state.

1011

MAC Device Abort: The BMAC device aborted the Request and asserted TXABORT. This could be from an

interface parity error, or because the transmitted frame failed the FC check, or because the BMAC device received a

MAC frame while transmitting in the BEACON state. This status is also returned when the BMAC device receives an

Other Beacon while the BSI device is transmitting in the BEACON state, or when the CLAIM process is lost while

Ð

the BSI device is transmitting in the CLAIM state.

[

]

1100

1101

1110

Timeout: The TRT expired during a Request with THT disabled. The Request is aborted.

MAC Reset: The BMAC device asserted MACRST.

Consistency Failure: There was an inconsistency within the REQ or ODUD stream.

ERROR

[

]

1111

Internal or Fatal ABus Error: There was an internal logic error or a fatal ABus error while writing a CNF.

63

5.0 Control Information (Continued)

Pool Space Descriptor (PSP)

Pool Space Descriptors (PSPs) contain the address and size (in bytes) of a free space in host memory available for writing Input

Data Units. When PSPs are read by the BSI device, the address field of the PSP is loaded into the Indicate Channel’s IDU

Pointer Register, and is used as the subchannel address for the IDU memory write.

31

30

29

28

27

13

12

0

RES

CNT

Word 0

Word 1

F–L

LOC

Word 0

Bit

Symbol

CNT

Description

D0–12

Byte Count: Number of bytes in the available memory area (up to 4k bytes).

D13–31

RES

Reserved

Word 1

Bit

Symbol

Description

D0–27

LOC

Location: Memory byte address of memory area available for writing IDUs. Normally the

page offset will be Zero to simplify space management.

D30–31

RES

Reserved

64

6.0 Signal Descriptions

6.1 PIN ORGANIZATION

The BSI device pinout is organized into five groups:

Control Interface: Used for host microprocessor access to the BSI device.

BMAC Device Indicate Interface: Pins for receiving and processing incoming frames from the DP82361 BMAC device.

BMAC Device Request Interface: Pins for transmitting frames to the BMAC device.

ABus Interface: Pins for transferring data and data information between system memory and the BSI device.

Electrical Interface: Pins associated with power supply, clocking, and scan test.

TL/F/10791–12

FIGURE 6-1. DP83265 160-Pin Pinout

Order Number DP83265VF

See NS Package Number VF160A

65

6.0 Signal Descriptions (Continued)

DP83265 Pinout Description

Pin Description I/O Pin Description

Pin Description

I/O

I

I/O

Core

O

Pin Description

I/O

1

2

3

4

5

6

7

8

9

AB ACK

Ð

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

LBC1

LBC3

LBC5

GND

NC

I

81

V

121 AB AD7

Ð

CC

AB ERR

Ð

I

82 GND

122 AB BP1

Ð

AB A4

Ð

O

83 RQBCN

84 RQCLM

85 FCST

123 AB AD8

Ð

AB A3

Ð

O

124 GND

AB A2

Ð

O

125

V

CC

AB RW

Ð

NC

86

V

CC

126 AB AD9

Ð

I/O

AB DEN

Ð

GND

NC

87 GND

88 STRIP

89 SAT

127 AB AD10

Ð

V

O

128 AB AD11

Ð

CC

GND

ECIP

EA

I

O

129 AB AD12

Ð

10 AB SIZ2

Ð

O

I

90 RST

I

130 AB AD13

Ð

11 AB SIZ1

Ð

O

EM

I

91 RW

I

131 AB AD14

Ð

12 AB SIZ0

Ð

O

MRQ0

MRQ1

MRQ2

MRQ3

O

92 CE

I

OD

I

132 AB AD15

Ð

13 AB BR

Ð

O

93 INT

133 AB BP2

Ð

14 AB BG

Ð

I

94 ACK

95 CBA0

96 CBA1

97 CBA2

98 CBA3

99 CBA4

100 CBD0

101 CBD1

102 CBD2

103 CBD3

134 GND

15 FCRCVD

16 MIDS

I

135

V

CC

I

V

CC

I

136 AB AD16

Ð

I/O

Core

I/O

17 AFLAG

18 MFLAG

19 SAMESA

20 INFORCVD

21 SAMEINFO

22 EDRCVD

23 VFCS

I

GND

I

137 AB AD17

Ð

I

MRQ4

O

I

138 AB AD18

Ð

I

MRQ5

I

139 AB AD19

Ð

I

MRQ6

I/O

140 GND

I

MRQ7

141

V

CC

I

MRP

142 AB AD20

Ð

I

TXRINGOP

TXCLASS

TXABORT

TXED

143 AB AD21

Ð

24 VDL

I

104

V

CC

144 AB AD22

Ð

25 TKRCVD

26 FOERROR

27 FRSTRP

28 VCOPY

29 MACRST

30 MIP

I

105 GND

106 CBD4

107 CBD5

108 CBD6

109 CBD7

110 CBP

145 AB AD23

Ð

I

I/O

146 GND

I

MRDS

I

147

V

CC

O

TXRDY

TXPASS

RQABORT

RQFINAL

RQEOF

RQSEND

I

148 AB BP3

Ð

I/O

I

149 AB AD24

Ð

I

O

150 AB AD25

Ð

31 MID7

I

111 AB BP0

Ð

151 AB AD26

Ð

32 MID6

I

112 AB AD0

Ð

152 AB AD27

Ð

33 MID5

I

113 AB AD1

Ð

153 AB AD28

Ð

34 MID4

I

V

CC

114

V

CC

154 AB AD29

Ð

35 MID3

I

GND

115 GND

155 AB AD30

Ð

36 MID2

I

RQRDY

O

116 AB AD2

Ð

I/O

156 GND

37 MID1

I

RQRCLS0

RQRCLS1

RQRCLS2

RQRCLS3

117 AB AD3

Ð

157

V

CC

38 MID0

I

118 AB AD4

Ð

158 AB AD31

Ð

I/O

39

V

Core

119 AB AD5

Ð

159 AB AB

Ð

CC

40 GND

120 AB AD6

Ð

160 AB CLK

Ð

66

6.0 Signal Descriptions (Continued)

6.2 CONTROL INTERFACE

The Control Interface operates asynchronously to the operation of the BMAC device and ABus interfaces.

The ACK and INT signals are open drain to allow wire ORing.

Ý

Symbol

CBP

110

I/O

Description

Control Bus Parity: Odd parity on CBD7–0.

Control Bus Data: Bidirectional Data bus.

CBD7–0

109-106,

103–100

CBA4–0

CE

99–95

92

I

Control Bus Address: Address of a particular BSI device register.

Control Bus Enable: Handshake signal used to begin a Control

Interface access. Active low signal.

R/W

ACK

INT

91

94

93

90

I

Read/Write: Determines current direction of a Control Interface

access.

OD

I

Acknowledge: Acknowledges that the Control Interface access has

been performed. Active low, open drain signal.

Interrupt: Indicates presence of one or more enabled conditions.

Active low, open drain signal.

RST

Reset: Causes a reset of BSI device state machines and registers.

67

6.0 Signal Descriptions (Continued)

6.3 BMAC Device Indicate Interface

The BMAC Device Indicate Interface signals provide data and control bytes as received from the BMAC device. Each Indicate

Data byte is also provided with odd parity.

MID7–0 signals are valid on the rising edge of the Local Byte Clock signal (provided by the Clock Recovery Device).

Data:

Ý

Symbol

I/O

Description

MIP

30

I

MAC Indicate Parity: This is connected directly to the corresponding BMAC device

pin of similar name. Odd parity on MID7–0. Only valid with Data and Status

indicators.

MID7–0

31–38

I

MAC Indicate Data: This is connected directly to the corresponding BMAC device

pin of similar name.

Data: The BMAC device indicates data is being presented on MID7–0 during the

time when RCSTART is asserted until one of the following signals is asserted:

EDRCVD, TKRCVD, FOERROR, or MACRST.

Status: The BMAC device indicates Status Indicators are being presented on

MID7–0 when EDRCVD or TKRCVD is asserted.

Frame Sequencing:

The Frame Sequencing signals apply to the data available at the MAC Indicate Interface (MIP and MID7–0). The Frame

Sequencing signals can be used to control the latching of appropriate Frame Status.

Ý

Symbol

I/O

Description

FCRCVD

15

I

Frame Control Received: This is connected directly to the corresponding BMAC

device pin of similar name. The BMAC device indicates that the Frame Control Field

has been received.

INFORCVD

EDRCVD

20

I

Information Field Received: This is connected directly to the corresponding

BMAC device pin of similar name. The BMAC device indicates that four bytes of the

Information Field have been received. It is asserted by the BMAC device on the

fourth byte of the INFO field and remains active until the next JK symbol pair is

received.

22

16

I

EDFS Received: This is connected directly to the corresponding BMAC device pin

of similar name. The BMAC device indicates that the End of Frame Sequence has

been received.

MIDS

MAC Indicate Data Strobe: Asserted by BMAC device to indicate valid data. This

signal should be tied to V for FDDI-I, and used for FDDI-II.

CC

Frame Information:

Ý

Symbol

I/O

Description

AFLAG

17

18

19

I

My Destination Address Recognized: This is connected directly to the

corresponding BMAC device pin of similar name. The BMAC device indicates that

an internal address match occurred on the Destination Address field. It is reset

when the next JK symbol pair is received.

MFLAG

I

My Source Address Recognized: This is connected directly to the corresponding

BMAC device pin of similar name. The BMAC device indicates that the received

Source Address field matched the MLA or MSA BMAC device registers. It is reset

when the next JK symbol pair is received.

SAMESA

Same Source Address: This is connected directly to the corresponding BMAC

device pin of similar name. The BMAC device indicates that the SA of the current

frame is the same as the previous frame, that the frames were not MAC frames, and

that the frames are the same size. It is reset when the next KJ symbol pair is

received.

SAMEINFO

21

I

Same MAC Information: This is connected directly to the corresponding BMAC

device pin of similar name. The BMAC device indicates that the first four bytes of

the IF of the current frame are the same as the previous frame, that the frames were

MAC frames, and that their address lengths are the same. SAMEINFO is asserted

along with INFORCVD. It is reset when the next JK symbol pair is received.

68

6.0 Signal Descriptions (Continued)

Frame Status:

Ý

Symbol

VDL

I/O

Description

24

I

Valid Data Length: The BMAC device indicates a valid data length for the current

frame.

VFCS

23

I

Valid Frame Check Sequence: The BMAC device indicates a valid FCS for the

current frame.

TKRCVD

FRSTRP

FOERROR

MACRST

25

27

26

29

I

Token Received: The BMAC device indicates that a complete token was received.

Frame Stripped: The BMAC device indicates that the current frame was stripped.

Format Error: The BMAC device indicates a standard-defined format error.

MAC Reset: The BMAC device indicates an internal error, MAC frame, MAC reset,

or hardware or software reset.

EA

50

I

External AFlag: This signal is used by external address matching to signal that a

Destination Address (DA) match has occurred. Assuming that the proper timing of

EA and ECIP are met, the assertion of EA will cause the BSI device to copy this

frame. EA is sampled on the cycle after ECIP is deasserted. The sample window is

from FCRCVD to EDRCVD.

EM

51

28

49

I

O

I

External MFlag: This signal is used by external address matching logic to signal a

Source Address (SA) match. It is sampled on the clock cycle after ECIP is

deasserted.

VCOPY

ECIP

Valid Copy: Affects the setting of the transmitted Cx (Copied Indicator).

The value of VCOPY is used to determine the value of the transmitted Cx. VCOPY

must be asserted one byte time before EDRCVD is asserted.

External Compare in Progress: This signal is asserted to indicate that external

address comparison has begun. It is deasserted to indicate that the comparison has

completed. EA and EM are sampled upon the deassertion of ECIP. ECIP must be

asserted during the period from the assertion of FCRVCD (by the BMAC device) to

the assertion of INFORCVD (by the BMAC device) in order for the BSI to recognize

an external comparison. It must be deasserted for at least one cycle for the external

comparison to complete. If ECIP has not been deasserted before EDRCVD (from

the BMAC device), the BSI device will not copy this frame. ECIP may be

implemented as a positive or negative pulse.

69

6.0 Signal Descriptions (Continued)

6.4 BMAC Device Request Interface

The BMAC Device Request Interface signals provide data and control bytes to the BMAC device as received from the Host

System. Each Request Data byte is also provided with odd parity.

Ý

Symbol

I/O

Description

MRP

62

O

MAC Request Parity: This is connected directly to the corresponding BMAC device

pin of similar name. Odd parity on MRD7–0.

MRD7–0

61–58,

55–52

O

MAC Request Data: This is connected directly to the corresponding BMAC device

pin of similar name. The BMAC device indicates data is being presented on

MRD7–0.

Service Parameters:

Ý

Symbol

I/O

Description

RQRCLS3–0

80–77

O

Request Class: This is connected directly to the corresponding BMAC device pin of

similar name. The BMAC device indicates the service class parameters for this

l

request. When RQRCLS 0, the BMAC device Transmitter will capture a usable

token for non-immediate requests) and assert TXRDY. The service opportunity

continues as long as the token is usable with the current service parameters, even if

e

after the current frame (even if RQRCLS subsequently becomes non-Zero).

RQRDY is not asserted. When RQRCLS

0, the service opportunity will terminate

RQCLM

RQCBN

84

83

O

Request CLAIM: This is connected directly to the corresponding BMAC device pin

of similar name. The BMAC device indicates that this request is to be serviced in the

Transmit CLAIM state. Ignored for non-immediate requests.

Request BEACON: This is connected directly to the corresponding BMAC device

pin of similar name. The BMAC device indicates that this request is to be serviced in

the Transmit BEACON state. Ignored for non-immediate requests.

70

6.0 Signal Descriptions (Continued)

Frame Options:

Ý

Symbol

STRIP

SAT

I/O

O

Description

88

Void Strip: Connected to STRIP and possibly SAT on the BMAC device.

89

85

O

Source Address Transparency: Connected to SAIGT on the BMAC device and to

SAT on the BMAC device if STRIP is not.

FCST

O

Frame Check Sequence Transparency: This is connected directly to the

corresponding BMAC device pin of similar name. When selected, the BMAC device

will not append FCS to the end of the Information field.

Request Handshake:

Ý

Symbol

I/O

Description

TXPASS

69

I

Transmit Pass: This is connected directly to the corresponding BMAC device pin of

similar name. The BMAC device indicates the absence of a service opportunity. This

could result from an unusable request class, waiting for a token, timer expiration, or

MAC Reset. TXPASS is always asserted between service opportunities. It is

deasserted when TXRDY is asserted at the beginning of a service opportunity.

TXRDY

68

I

Transmit Ready: This is connected directly to the corresponding BMAC device pin

of similar name. The BMAC device indicates that the BMAC device transmitter is

ready for another frame. For a non-immediate request, a useable token must be

held in order to transmit frames.

TXRDY is asserted by the BMAC device when:

a. a usable token is being held, or

b. an immediate request becomes serviceable, or

c. after frame transmission if the current service opportunity is still usable for

another frame.

TXRDY is deasserted when TXPASS or TXACK is asserted.

RQRDY

76

73

O

Request Ready: This is connected directly to the corresponding BMAC device pin

of similar name. The BMAC device indicates that the BMAC device transmitter

should attempt to use a service opportunity.

If RQRDY is asserted within 6 byte times after TXRDY is asserted, the BMAC device

b

transmitter will wait at least L Max plus one Void frame (4.16 ms 4.80 ms) for

Ð

RQSEND to be asserted before releasing the token.

RQSEND

Request Send: This is connected directly to the corresponding BMAC device pin of

similar name. The BMAC device indicates that the BMAC device transmitter should

send the next frame. The MRD7–0 signals convey the FC byte when this signal is

asserted.

If RQSEND is asserted within 6 byte times after TXRDY is asserted, the BMAC

device transmitter will send the frame with a minimum length preamble. If RQSEND

is not asserted within L Max plus one Void frame after RQRDY has been asserted

Ð

b

(4.16 ms 4.60 ms), the token may become unusable due to timer expiration.

RQSEND may only be asserted when TXRDY and RQRDY are asserted and

RQFINAL is deasserted.

RQSEND must be deasserted not later than one byte time after TXRDY is

deasserted

MRDS

67

72

I

MAC Request Data Strobe: This is connected directly to the corresponding BMAC

device pin of similar name. The BMAC device indicates that data on MRD7–0 is

valid. This signal should be connected to the TXACK on the BMAC device.

RQEOF

O

Request EOF: This is connected directly to the corresponding BMAC device pin of

similar name. The BMAC device indicates that MRD7–0 conveys the last data byte

when asserted. Normally, this is the last byte of the INFO field of the frame

(exceptions: FCS transparency, invalid frame length).

RQEOF causes TXACK to be deasserted and is ignored when TXACK is not

asserted.

71

6.0 Signal Descriptions (Continued)

Request Handshake: (Continued)

Ý

Symbol

I/O

Description

RQABORT

70

O

Request Abort: This is connected directly to the corresponding BMAC device pin of

similar name. The BMAC device indicates that the current frame should be aborted.

Normally this causes the BMAC device transmitter to generate a Void, CLAIM, or

BEACON frame.

RQABORT causes TXACK to be deasserted and is ignored when TXACK is not

asserted.

RQFINAL

71

O

Request Final: This is connected directly to the corresponding BMAC device pin of

similar name. The BMAC device indicates that the final frame of the request has

been presented to the BMAC device Interface.

When asserted, the Issue Token Class (as opposed to the Capture Token Class)

becomes the new Token Class (TXCLASS). RQFINAL may only be asserted when

RQRDY is asserted and RQSEND is deasserted. RQFINAL is ignored unless

RQRDY has been asserted for at least one byte time and the service parameters

have been valid for at least three byte times.

RQFINAL must be deasserted not later than two byte times after TXPASS is

deasserted.

TXED

66

65

I

Transmit End Delimiter: This is connected directly to the corresponding BMAC

device pin of similar name. The BMAC device indicates that the ED is being

transmitted.

TXABORT

Transmit Abort: This is connected directly to the corresponding BMAC device pin

of similar name. The BMAC device indicates that the MAC Transmitter aborted the

current frame.

Transmit Status:

Ý

Symbol

I/O

Description

TXRINGOP

63

I

Transmit Ring Operational: This is connected directly to the corresponding BMAC

device pin of similar name. The BMAC device indicates the state of the MAC

Transmitter.

TXCLASS

64

I

Transmit Token Class: This is connected directly to the corresponding BMAC

device pin of similar name. The BMAC device indicates the class of the current

token.

72

6.0 Signal Descriptions (Continued)

6.5 ABus Interface

The ABus Interface signals provide a 32-bit multiplexed address/data bus for transfers between the host system and the BSI

device. The ABus uses a bus request/bus grant protocol that allows for multiple bus masters, supports burst transfers of 4 or 8

32-bit words, and permits both physical and virtual addressing using fixed-size pages.

Address and Data:

Ý

Symbol

I/O

Description

AB BP3–0

Ð

148, 133,

122, 111

I/O

ABus Byte Parity: These TRI-STATE signals contain the BSI device-generated parity

for each address byte of AB AD, such that AB BP0 is the parity for AB AD7–0,

Ð

AB BP1 is the parity for AB AD15–8, etc.

Ð

AB AD31–0

Ð

158,

I/O

ABus Address and Data: These TRI-STATE signals are the multiplexed ABus address

and data lines. During the address phase of a cycle, AB AD27–0 contain the 28-bit

address, and AB AD31–28 contain a 4-bit function code identifying the type of

Ð

transaction, encoded as follows:

155–149,

145–142,

139–136,

132–126,

123,

Ð

[

AB AD 31:28

]

Transaction Type

RSAP1 ODU Load

Ð

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

RSAP1 ODUD Load/CNF Store

RSAP1 REQ Load

RSAP0 ODU Load

RSAP0 ODUD Load/CNF Store

RSAP0 REQ Load

ISAP2 IDU Store

121–116,

113–112

ISAP2 IDUD Store

ISAP2 PSP Load

ISAP1 IDU Store

ISAP1 IDUD Store

ISAP1 PSP Load

ISAP0 IDU Store

ISAP0 IDUD Store

ISAP0 PSP Load

PTR RAM Load/Store

AB A4–2

Ð

3–5

O

ABus Burst Address: These TRI-STATE signals contain the word address during burst-

mode accesses. They are driven from Tpa to the last Td state, negated in the following

Tr state, then released. Note that the address presented allows external pipelining for

optimum memory timing.

73

6.0 Signal Descriptions (Continued)

Bus Control:

Ý

Symbol

I/O

Description

AB AS

Ð

159

O

ABus Address Strobe: When asserted, This TRI-STATE signal indicates that data on AB AD is valid.

Ð

When this signal is inactive and AB ACK is asserted, the next cycle is a Tr state, in which the bus arbiter

Ð

can sample all bus requests, then issue a bus grant in the following cycle.

AB RW

Ð

6

7

O

ABus Read/Write: This TRI-STATE signal determines the current direction of an ABus access.

AB DEN

Ð

ABus Data Enable: This TRI-STATE signal indicates that data on AB AD31–0 is valid.

Ð

AB SIZ2–0 10–12

Ð

ABus Size: These TRI-STATE signals indicate the size of the transfer on AB AD31–0, encoded as

Ð

follows:

Transfer

AB SIZ2

Ð

AB SIZ1

Ð

AB SIZ0

Ð

Size

0

1

0

1

0

1

0

1

0

1

0

1

0

1

4 Bytes

Reserved

16 Bytes

32 Bytes

Reserved

AB ACK

Ð

1

2

I

ABus Acknowledge: Indicates a bus slave’s response to a bus master. The meaning of this signal

depends on the state of ABus Error (AB ERR), as described below.

Ð

AB ERR

Ð

ABus Error: This signal is asserted by a bus slave to cause a transaction retry or transaction abort.

Together with AB ACK, the encoding is as follows:

Ð

AB ACK

Ð

AB ERR

Ð

Definition

1

0

1

0

1

Insert Wait States

Bus Error

Transaction Retry

Acknowledge

Bus Arbitration:

Symbol

Ý

I/O

O

Description

AB BR

Ð

13

14

ABus Bus Request: This signal is used by a bus master to request use of the ABus.

ABus Bus Grant: This signal is asserted by external bus arbitration logic to grant

use of the ABus to the BSI device. When AB BG is deasserted, the BSI device

AB BG

Ð

I

Ð

completes the current transaction and releases the bus. If AB BG is asserted at

Ð

the start of a transaction (Tbr), the BSI device will run a transaction.

AB CLK

Ð

160

I

ABus Clock: All ABus operations are synchronized to the rising edge of AB CLK.

Ð

74

6.0 Signal Descriptions (Continued)

6.6 ELECTRICAL INTERFACE

Ý

Symbol

I/O

Description

LBC5, 3, 1

43–41

I

Local Byte Clock: 12.5 MHz clock with a 60/40 duty-cycle. Generated by CDD.

[

]

g

Positive Power Supply: 5V, 10% relative to GND.

V

CC

13

8, 39, 56

74, 81, 86,

104, 114,

125, 135,

141, 147, 157

[

GND 13

]

9, 40, 57

75, 82, 87,

105, 115, 124,

134, 140, 146,

156

Power Supply Return.

GND

NC

44, 47

Must be grounded.

45, 46, 48

No Connect: Must be left unconnected.

75

Physical Dimensions inches (millimeters)

Order Number DP83265VF

NS Package Number VF160A

LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL

SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or

systems which, (a) are intended for surgical implant

into the body, or (b) support or sustain life, and whose

failure to perform, when properly used in accordance

with instructions for use provided in the labeling, can

be reasonably expected to result in a significant injury

to the user.

2. A critical component is any component of a life

support device or system whose failure to perform can

be reasonably expected to cause the failure of the life

support device or system, or to affect its safety or

effectiveness.

National Semiconductor

Corporation

National Semiconductor

Europe

National Semiconductor

Hong Kong Ltd.

National Semiconductor

Japan Ltd.

a

1111 West Bardin Road

Arlington, TX 76017

Tel: 1(800) 272-9959

Fax: 1(800) 737-7018

Fax:

(

49) 0-180-530 85 86

@

13th Floor, Straight Block,

Ocean Centre, 5 Canton Rd.

Tsimshatsui, Kowloon

Hong Kong

Tel: (852) 2737-1600

Fax: (852) 2736-9960

Tel: 81-043-299-2309

Fax: 81-043-299-2408

Email: cnjwge tevm2.nsc.com

a

Deutsch Tel:

English Tel:

Fran3ais Tel:

Italiano Tel:

(

49) 0-180-530 85 85

49) 0-180-532 78 32

49) 0-180-532 93 58

49) 0-180-534 16 80

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.


型号：	DP83265
厂家：	ETC
描述：	电信集成电路
文件：	总76页 (文件大小：536K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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