DPS1MX16MKH3-20I [ETC]
x16 SRAM Module ; X16 SRAM模块\n
| 型号： | DPS1MX16MKH3-20I |
| 厂家： | 
ETC |
| 描述： | x16 SRAM Module
|
| 文件： | 总8页 (文件大小：747K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
16 Megabit High Speed CMOS SRAM
DPS1MX16MKn3
SLCC Stack
DESCRIPTION:
The DPS1MX16MKn3 High Speed SRAM ‘’STACK’’ modules are a
revolutionary new memory subsystem using Dense-Pac
Microsystems’ ceramic Stackable Leadless Chip Carriers (SLCC).
Available in straight leaded, ‘’J’’ leaded or gullwing leaded
packages. The module packs 16-Megabits of low-power CMOS
static RAM in an area as small as 0.549 in2, while maintaining a
total height as low as 0.269 inches.
The DPS1MX16MKn3 STACK modules contain four individual
512K x 8 SRAMs, each packaged in a hermetically sealed SLCC,
making the modules suitable for commercial, industrial and
military applications.
Straight
Leaded
Stack
By using SLCCs, the ‘’Stack’’ family of modules offer a higher board
density of memory than available with conventional through-hole,
surface mount or hybrid techniques.
FEATURES:
·
Organizations Available:
1Meg x 16 or 2 Meg x 8
·
Access Times: 20*, 25, 30, 35, 45ns
·
Fully Static Operation
- No clock or refresh required
‘’J’’ Leaded
Stack
·
Single +5V Power Supply, ±10% Tolerance
TTL Compatible
Common Data Inputs and Outputs
·
·
·
Low Data Retention Voltage:
Packages Available:
SLCC Stack
2.0V min.
·
Straight Leaded Stack
‘’J’’ Leaded Stack
Gullwing Leaded Stack
Gullwing
Leaded
Stack
Commercial and Industrial Grade only.
*
FUNCTIONAL BLOCK DIAGRAM
PIN NAMES
Address Inputs
Data Input/Output
Low Chip Enables
Write Enable
Output Enables
Power (+5V)
Ground
A0 - A18
I/O0 - I/O15
CE0 - CE3
WE
OE0, OE1
VDD
VSS
N.C.
No Connect
30A129-04
REV. E
This document contains information on a product that is currently released
to production at Dense-Pac Microsystems, Inc. Dense-Pac reserves the
right to change products or specifications herein without prior notice.
1
This Material Copyrighted By Its Respective Manufacturer
DPS1MX16MKn3
Dense-Pac Microsystems, Inc.
TRUTH TABLE
Supply
PIN-OUT DIAGRAM
Mode
CE
WE
OE I/O Pin
Current
Not Selected
DOUT Disable
Read
H
L
L
X
H
H
L
X
H
L
High-Z Standby
High-Z Active
DOUT Active
Write
L
X
DIN
Active
H = HIGH
L = LOW
X = Don’t Care
3
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
°C
°C
°C
V
TSTC
Storage Temperature
-65 to +150
-55 to +125
-0.5 to +7.0
-0.5 to VDD+0.5
TBIAS Temperature Under Bias
VDD Supply Voltage 1
VI/O
Input/Output Voltage 1
RECOMMENDED OPERATING RANGE 3
Symbol
Characteristic
Min. Typ.
Max. Unit
VDD Supply Voltage
4.5 5.0
5.5
VDD+0.3
0.8
V
V
V
VIH
VIL
Input HIGH Voltage 2.2
Input LOW Voltage -0.52
M/B -55 +25 +125
Operating
Temperature
TA
I
-40 +25
+25
+85
+70
oC
CAPACITANCE 4: TA = 25°C, F = 1.0MHz
C
0
Symbol
Parameter
Max. Unit Condition
CADR Address Input
CCE Chip Enable
CWE Write Enable
COE Output Enable
CI/O Data Input/Output
40
16
40
25
25
DC OUTPUT CHARACTERISTICS
pF
VIN2 = 0V
Symbol
Parameter
Conditions Min. Max. Unit
VOH HIGH Voltage IOH= -4.0mA 2.4
VOL LOW Voltage IOL=8.0mA
V
V
0.4
DC OPERATING CHARACTERISTICS: Over operating ranges
C
I
M/B
Typ.
(†)
Symbol
Characteristics
Test Conditions
Unit
Min. Max. Min. Max. Min. Max.
Input
IIN
IOUT
ICC
VIN = 0V to VDD
VI/O = 0V to VDD
-
-
-20 +20 -20 +20 -20 +20
mA
mA
Leakage Current
Output
Leakage Current
,
-20 +20 -20 +20 -20 +20
CE or OE = VIH, or WE = VIL
X8
185
X16 290
350
460
360
480
36 0
480
Operating
Supply Current
Cycle=min., Duty=100%
IOUT = 0mA
mA
Full Standby
VIN ³ VDD -0.2V or
ISB1
ISB2
IDR3
4
40
240
2.0
40
240
4.0
60
mA
Supply Current
V
IN £ VSS +0.2V
Standby Current (TTL)
Data Retention
Supply Current (3.0V)
Data Retention
Supply Current (2.0V)
Output Low Voltage
CE = VIH
80
0.6
240 mA
8.0
mA
mA
VDR = 3.0V, CE ³ VDR -0.2V
IDR2
VOL
0.4
1.2
0.4
3.2
0.4
7.2
0.4
VDR = 2.0V, CE ³ VDR -0.2V
IOUT = 8.0mA
IOUT = -4.0mA
-
-
V
V
VOH Output High Voltage
2.4
2.4
2.4
† Typical measurements made at +25oC, Cycle = min., VDD = 5.0V.
30A129-04
REV. E
2
This Material Copyrighted By Its Respective Manufacturer
Dense-Pac Microsystems, Inc.
AC TEST CONDITIONS
DPS1MX16MKn3
Figure 1. Output Load
Input Pulse Levels
0V to 3.0V
Input Pulse Rise and Fall Times
Input and Output
Timing Reference Levels
5ns
+5V
1.5V
480W
DOUT
CL*
OUTPUT LOAD
Parameters Measured
100pF except tLZ, tHZ, tOHZ, tOLZ, and tWHZ
Load
1
2
CL
255W
5pF
tLZ, tHZ, tOHZ, tOLZ, and tWHZ
Data Retention AC Characteristics8
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
VDR
V
for Data Retention
2.0
-
-
V
CE ³ VDR -0.2V
DD
Chip Disable to
VCDR
tR
See Data Retention Waveform
See Data Retention Waveform
0
5
-
-
-
-
ns
Data Retention Time
Operation Recovery Time
ms
AC OPERATING CONDITIONS AND CHARACTERISTICS - READ CYCLE: Over operating ranges
20ns*
25ns
30ns
35ns
45ns
No. Symbol
Parameter
Unit
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
1
2
3
4
5
6
7
8
9
tRC
tAA
tCO
tOE
Read Cycle Time
Address Access Time
CE to Output Valid
Output Enable to Output Valid
CE to Output in LOW-Z 4, 5
Output Enable to Output in LOW-Z 4, 5
CE to Output in HIGH-Z 4, 5
Output Enable to Output in HIGH-Z 4, 5
Output Hold from Address Change
20
25
30
35
45
ns
45 ns
45 ns
25 ns
ns
20
20
10
25
25
12
30
30
15
35
35
20
tLZ
3
0
3
0
3
0
3
0
3
0
tOLZ
tHZ
tOHZ
tOH
ns
8
8
10
10
15
15
20
20
25 ns
25 ns
ns
0
4
0
5
0
5
0
5
0
5
AC OPERATING CONDITIONS AND CHARACTERISTICS - WRITE CYCLE 6, 7: Over operating ranges
20ns*
25ns
30ns
35ns
45ns
No. Symbol
Parameter
Unit
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
10
11
12
13
14
15
tWC
tAW
tCW
tAS
tWP
tWR
Write Cycle Time
20
13
13
0
13
0
25
15
15
0
15
0
30
20
20
0
20
0
35
25
25
0
25
0
45
35
35
0
35
0
ns
ns
ns
ns
ns
ns
Address Valid to End of Write
Chip Enable to End of Write
Address Set-Up Time **
Write Pulse Width
Write Recovery Time
16 tWHZ Write Enable to Output in HIGH-Z 4, 5
0
8
0
10
0
12
0
15
0
20 ns
17
18
19
tDW
tDH
tOW
Data to Write Time Overlap
Data Hold from Write Time
Output Active from End of Write
9
0
3
10
0
3
12
0
3
15
0
3
20
0
3
ns
ns
ns
* Available in Commercial and Industrial Grade Only.
** Valid for both Read and Write Cycles.
30A129-04
REV. E
3
This Material Copyrighted By Its Respective Manufacturer
DPS1MX16MKn3
Dense-Pac Microsystems, Inc.
DATA RETENTION WAVEFORM: CE Controlled.
VDD
4.5V
2.3V
VDR1
CE ³ VDD -0.2V
CE
0V
READ CYCLE
ADDRESS
CE
OE
DATA I/O
WRITE CYCLE 1: CE Controlled.
ADDRESS
CE
WE
DATA IN
DATA OUT
4
30A129-04
REV. E
This Material Copyrighted By Its Respective Manufacturer
Dense-Pac Microsystems, Inc.
DPS1MX16MKn3
WRITE CYCLE 2: WE Controlled. OE is HIGH. 8
ADDRESS
CE
WE
DATA IN
DATA OUT
WRITE CYCLE 3: WE Controlled. OE is LOW. 8
ADDRESS
CE
WE
DATA IN
DATA OUT
30A129-04
REV. E
5
This Material Copyrighted By Its Respective Manufacturer
DPS1MX16MKn3
Dense-Pac Microsystems, Inc.
(52 - PIN LEADLESS STACK) MECHANICAL DRAWING
(52 - PIN STRAIGHT LEADED STACK) MECHANICAL DRAWING
30A129-04
REV. E
6
This Material Copyrighted By Its Respective Manufacturer
Dense-Pac Microsystems, Inc.
DPS1MX16MKn3
(52 - PIN ‘’J’’ LEADED STACK) MECHANICAL DRAWING
(52 - PIN GULLWING LEADED STACK) MECHANICAL DRAWING
30A129-04
REV. E
7
This Material Copyrighted By Its Respective Manufacturer
DPS1MX16MKn3
Dense-Pac Microsystems, Inc.
ORDERING INFORMATION
NOTES:
1. All voltages are with respect to VSS.
2. -2.0V min. for pulse width less than 20ns (VIL min. = -0.5V at DC level).
3. Stresses greater than those under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
4. This parameter is guaranteed and not 100% tested.
5.
Transition is measured at the point of ±500mV from steady state voltage.
6. When OE and CE are LOW and WE is HIGH, I/O pins are in the output state,and input signals of opposite
phase to the outputs must not be applied.
7. The outputs are in a high impedance state when WE is LOW.
8. CE and WE can initiate and terminate WRITE Cycle.
WAVEFORM KEY
Data Valid
Transition from
HIGH to LOW
Transition from
LOW to HIGH
Data Undefined
or Don’t Care
Dense-Pac Microsystems, Inc.
7321 Lincoln Way u Garden Grove, California 92841-1428
(714) 898-0007 u (800) 642-4477 (Outside CA) u FAX: (714) 897-1772 u http://www.dense-pac.com
30A129-04
REV. E
8
This Material Copyrighted By Its Respective Manufacturer
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