DRC-11522-113L [ETC]
Digital-to-Resolver Converter ; 数字 - 旋转变压器转换器\n
| 型号： | DRC-11522-113L |
| 厂家： | 
ETC |
| 描述： | Digital-to-Resolver Converter
|
| 文件： | 总6页 (文件大小：75K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DRC-11522
TWO-CHANNEL DIGITAL-TO-RESOLVER
CONVERTER
FEATURES
DESCRIPTION
The DRC-11522 is a dual 16-bit digital- plays directly. The output line-to-line
to-resolver (D/R) converter. Each chan- voltage can be scaled by pin program-
nel is independent from the other with ming. Other features include buffered
the exception of the 16 digital lines. reference input, and a wide operating
The DRC-11522 allows the user to pro- temperature range.
16-Bit Resolution
•
•
•
•
•
Pin Programmable Gain Control
Two Channels in One 36-Pin DDIP
Accuracy: to ±± ꢀinꢁ
gram the gain of the resolver output.
APPLICATIONS
Packaged in a 36-pin double DIP, the
DRC-11522 is two digital-to-resolver Because of its high reliability, small
converters in one hybrid module. size and low power consumption, the
Using an AC reference input, the DRC- DRC-11522 is ideal for the most strin-
11522 is a digital-to-resolver convert- gent and severe industrial and military
er. When using a DC reference input, ground or avionics applications. All
the unit can be used as a hybrid digital- units are available with MIL-PRF-
to-sin/cos DC converter. With the refer- 38534 processing.
0ꢁ1% Scale Factor Variation with
Angle
DC-Coupled Reference
•
•
•
ence input proportional to the radius
vector, the DRC-11522 converts polar Among the many possible applications
High Reliability CꢀOS D/R Chip
to rectangular coordinates.
are computer-based systems in which
digital information is processed, such
The circuit design in the DRC-11522 as simulators, flight trainers, flight
allows for higher accuracy and instrumentation, fire control systems,
reduces the output scale factor varia- radar and navigation systems.
tion so that the output can drive dis-
8-Bit/±-Byte Double-Buffered
Transparent Latches
SIN A
SIN B
OUTPUT
AMPLIFIERS
OUTPUT
AMPLIFIERS
COS A
COS B
REFERENCE CONDITIONER
-
REFERENCE CONDITIONER
-
+C
+S
+C
+S
REF
REF
D/R CONVERTER
HIGH ACCURACY
LOW SCALE FACTOR
VARIATION
D/R CONVERTER
HIGH ACCURACY
LOW SCALE FACTOR
VARIATION
+
+
GC1-A
GC2-A
GC1-B
GC2-B
TRANSPARENT
LATCH
TRANSPARENT
LATCH
TRANSPARENT
LATCH
TRANSPARENT
LATCH
LL-A LL-B
LA-A LM-A
LM-B LA-B
+15 V
-15 V
GND
DIGITAL INPUT
FIGURE 1ꢁ DRC-115±± BLOCK DIAGRAꢀ
1988, 1999 Data Device Corporation
©
TABLE 1ꢁ SPECIFICATIONS (for each channel)
Apply over temperature range, power supply ranges, reference voltage, and frequency range, and 10% harmonic distortion in the reference.
PARAꢀETER
VALUE
16 bits (0.33 arc minutes)
DESCRIPTION/REꢀARKS
MSB = 180° LSB = 0.0055°
RESOLUTION
ACCURACY
Output Accuracy
±8 minutes to ±1 minute
(see ordering info)
±1 LSB maꢀ
Accuracy applies over operating temp. range
Differential Linearity
Radius accuracy
±0.03%
Simultaneous amplitude variation in both
outputs as a function of digital angle
DYNAꢀICS
Output Settling Time
Less than 20 µsec for any digital step change.
For any analog or digital step change
DIGITAL INPUT
Logic Type
Natural binary angle parallel positive logic CMOS
and TTL compatible.
Inputs are CMOS transient protected. Each input
has a 20 µA maꢀ pull down to GND.
Logic “0”
Logic “1”
Load Current
-0.3 V-dc to 1.25 V-dc
+2.0 V-dc to +5.5 V-dc
20 µA maꢀ to GND
20 µA to VL
Eꢀternal logic voltage not needed. TTL compatible.
Bits 1-16
LL, LM, LA (See timing Diagram, FIGURE 2)
REFERENCE INPUT
Type
Frequency Range
Voltage
Programmable (See TABLE 2.)
DC to 10 kHz with reduced accuracy.
0 to ±10 peak AC or DC
DC to 1000 Hz
3.5 V ±10%
Input Impedance
10 M Ohm min
Operational Amplifier Buffer
ANALOG OUTPUT
Type
Resolver
Output Current
2 mA rms maꢀ
Maꢀ Output Voltage (Tracks
Reference Input Voltage)
Converter Gain (K)
Transformation Ratio Tol.
Scale Factor Variation
DC Offset
K * V * Sin θ also K * V * Cos θ
±10 V peak AC or DC
See TABLE 2.
in
in
0.5, 1.0, or 2.0 ±1%
±0.2% maꢀ
±0.1% maꢀ
±10 mV typical, ±25 mV maꢀ
Each Line to GND
POWER SUPPLIES
Voltage
Maꢀ Voltage Without Damage
Current or Impedance
±15 VDC ±10%
±18 VDC
±±0 mA maꢀ
For ±10 V peak output
TEꢀPERATURE RANGES (CASE)
Operating
-1 Option
-3 Option
Storage
-55°C to +125°C
0°C to +70°C
-60°C to +135°C
PHYSICAL CHARACTERISTICS
Type
Size
36-pin double DIP
0.78 ꢀ 1.9 ꢀ 0.21 inch
(2.0 ꢀ ±.8 ꢀ 0.53 cm)
0.6 oz (17g) maꢀ
Weight
±
TECHNICAL INFORꢀATION
DIGITAL INPUTS
TABLE 3ꢁ PINOUTS
FUNCTION PIN
PIN
FUNCTION
1
2
3
±
5
6
7
8
LL-B
19
20
21
22
23
2±
25
26
27
28
29
30
31
32
33
3±
35
36
Bit 16 (LSB)
Bit 15
Bit 1±
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit ±
Bit 3
Bit 2
Bit 1 (MSB)
LM-A
LM-B
COS A
SIN A
GC1-B
GC2-B
Ref B
GC1-A
GC2-A
Ref A
COS B
SIN B
NC
+15 V
-15 V
LA-B
LA-A
LL-A
For each channel, the 16-bit digital angle is double buffered with
transparent latches (See FIGURE 1). The latch controls have
internal pull-up current sources to +5 V, this puts the latches in
the transparent mode when they are not connected.
Angle is determined by adding the logic bits. The enable inputs
are LL (1st Latch LSBs), LM (1st Latch MSBs), and LA (2nd
Latch All); see FIGURE 2 for timing.
9
10
11
12
13
1±
15
16
17
18
OUTPUT SCALING AND REFERENCE LEVEL
ADJUSTꢀENT
The DRC-11522 operates like a multiplying D/A converter in that
the voltage of each output line is directly proportional to the ref-
erence voltage. The maꢀimum line-to-line levels are determined
by the output amplifiers and are programmable for a gain of 0.5,
1.0, or 2.0 (See TABLE 2.).
GND
NOTE: Functions LL, LM, LA both A and B may be left unconnected
when not used.
TABLE ±ꢁ PROGRAꢀꢀABLE GAIN
TABLE 4ꢁ PIN DEFINITIONS
GC1-A
(PIN 7)
GC±-A
GAIN
PIN
GND
DEFINITION
(PIN 8)
(K)
Power Supply Ground
Digital Ground
Analog Signal Ground
GND
OPEN
OPEN
OPEN
GND
OPEN
0.5
1.0
2.0
B1-B16
LM-A
Digital Input bits B1, = MSB = 180 degrees
High Byte Enable (B1-B8) for MSB’s 8-bit Input register of
channel A. Logic high enables, low holds.
High Byte Enable (B1-B8) for MSB’s 8-bit Input register
channel B Logic high enables, low holds.
Low Byte Enable (B9-B16) for LSB’s 8-bit Input register of
channel A. Logic high enables, low holds
Low Byte Enable (B9-B16) for LSB’s 8-bit Input register of
channel B. Logic high enables, low holds.
Channel A Load Converter. Logic high transfers Channel A
input registers data into 16-bit holding register. When
low, Channel A is in hold mode.
Channel B Load Converter. Logic high transfers Channel B
input registers data into 16-bit holding register. When
low, Channel B is in hold mode.
Power Supply Voltage.
Power Supply Voltage.
GC1-B
(PIN ±)
GC±-B
GAIN
(PIN 5)
(K)
LM-B
LL-A
LL-B
LA-A
OUTPUT PHASING AND OUTPUT SCALE FACTOR
The analog output signals have the following phasing:
sin = (REF * K) A [1 + A(θ)] sin θ
o
cos = (REF * K) A [1 + A(θ)] cos θ
o
LA-B
The output amplifiers simultaneously track reference voltage
fluctuations because they are proportional to (REF * K). The
+15 V
-15 V
transformation ratio A is determined by the programmable gain
o
CAUTION:
REVERSAL OF POWER SUPPLIES
WILL DAꢀAGE THE CONVERTERꢁ
Channel A reference voltage Input
Channel B reference voltage input
Channel A gain programming pin
Channel A gain programming pin
Channel B gain programming pin
Channel B gain programming pin
Analog output of Channel A
inputs (0.5, 1.0, or 2.0). The maꢀimum variation in A from all
o
causes is 0.1%. The term A(θ) represents the variation of the
amplitude with the digital signal input angle. A(θ), which is called
the scale factor variation, is a smooth function of (θ) without dis-
continuities and is less than ±0.1% for all values of (θ) The total
Ref-A
Ref-B
GC1-A
GC2-A
GC1-B
GC2-B
Sin A
Cos A
Sin B
Cos B
maꢀimum variation in A [1 + A(θ)] is therefore ±0.2%.
o
Because the amplitude factor (REF * K) A [1 + A(θ)] varies
o
Analog output of Channel A
Analog output of Channel B
Analog output of Channel B
simultaneously on all output lines, it is not a source of error when
the DRC-11522 is driving a ratiometric system. However, if the
outputs are used independently, as in ꢀ-y plotters, the amplitude
variations must be taken into account.
3
200 ns min.
TRANSPARENT
LATCHED
DATA 1-16 BITS
50 ns min.
100 ns min.
FIGURE ±ꢁ LL, Lꢀ, AND LA TIꢀING DIAGRAꢀ
DOT
IDENTIFIES
PIN 1
0.09 ±0.01
(2.3 ±0.25)
1.700 ±0.005
(±3.2 ±0.13)
0.775 ±0.005
(19.7 ±0.13)
0.600 ±0.005
(15.2 ±0.13)
BOTTOꢀ VIEW
0.086 TYP
RADIUS
0.10 ±0.01
(2.5 ±0.3)
1.895 ±0.005
(±8.1 ±0.13)
0.21 MAX
(5.3)
SEATING
PLANE
SIDE VIEW
0.055 (1.±)
RAD TYP
0.015 MAX
(0.39)
0.100 TYP(2.5±)
TOL. NON-
CUMULATIVE
0.25 MIN
(6.±)
0.018 (0.±6)
DIAM TYP
Notes:
1. Dimensions shown are in inches (millimeters)
2. Lead identification numbers are for reference only.
3. Lead cluster shall be centered within ±0.010 (±2.5±) of outline dimensions.
Lead spacing dimensions apply only at seating plane.
±. Pin material meets solderability requirements of MIL-STD-202E, Method 208C.
5. Package is Kovar with electroless nickel plating.
6. Case is electrically floating.
FIGURE 3ꢁ DRC-115±± ꢀECHANICAL OUTLINE (36-PIN DOUBLE DIP)
4
ORDERING INFORꢀATION
DRC-11522-X XX X
Supplemental Process Requirements:
S = Pre-Cap Source Inspection
L = Pull Test
Q = Pull Test and Pre-Cap Inspection
K = One Lot Date Code
W = One Lot Date Code and PreCap Source
Y = One Lot Date Code and 100% Pull Test
Z = One Lot Date Code, PreCap Source and 100% Pull Test
Blank = None of the Above
Accuracy:
3 = ±± minutes
± = ±2 minutes
Process Requirements:
0 = Standard DDC Processing, no Burn-In (See table below.)
1 = MIL-PRF-3853± Compliant
2 = B*
3 = MIL-PRF-3853± Compliant with PIND Testing
± = MIL-PRF-3853± Compliant with Solder Dip
5 = MIL-PRF-3853± Compliant with PIND Testing and Solder Dip
6 = B* with PIND Testing
7 = B* with Solder Dip
8 = B* with PIND Testing and Solder Dip
9 = Standard DDC Processing with Solder Dip, no Burn-In (See table below.)
Temperature Grade/Data Requirements:
1 = -55°C to +125°C
2 = -±0°C to +85°C
3 = 0°C to +70°C
± = -55°C to +125°C with Variables Test Data
5 = -±0°C to +85°C with Variables Test Data
8 = 0°C to +70°C with Variables Test Data
*Standard DDC Processing with burn-in and full temperature test — see table below.
STANDARD DDC PROCESSING
ꢀIL-STD-883
TEST
ꢀETHOD(S)
CONDITION(S)
INSPECTION
SEAL
2009, 2010, 2017, and 2032
—
101±
1010
A and C
TEMPERATURE CYCLE
CONSTANT ACCELERATION
BURN-IN
C
A
2001
1015, Table 1
—
5
The information in this data sheet is believed to be accurate; however, no responsibility is
assumed by Data Device Corporation for its use, and no license or rights are
granted by implication or otherwise in connection therewith.
Specifications are subject to change without notice.
105 Wilbur Place, Bohemia, New York 11716-2±82
For Technical Support - 1-800-DDC-5757 extꢁ 7389 or 7413
Headquarters - Tel: (631) 567-5600 eꢀt. 7389 or 7±13, Faꢀ: (631) 567-7358
West Coast - Tel: (71±) 895-9777, Faꢀ: (71±) 895-±988
Southeast - Tel: (703) ±50-7900, Faꢀ: (703) ±50-6610
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Ireland - Tel: +353-21-3±1065, Faꢀ: +353-21-3±1568
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Sweden - Tel: +±6-(0)8-5±±900±±, Faꢀ +±6-(0)8-7550570
Japan - Tel: +81-(0)3-381±-7688, Faꢀ: +81-(0)3-381±-7689
World Wide Web - http://www.ddc-web.com
U
®
DATA DEVICE CORPORATION
REGISTERED TO ISO 9001
FILE NOꢁ A5976
H-02/00-0
PRINTED IN THE U.S.A.
6
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