DS-11802D4-105Y [ETC]
Converter ; 变流器\n
| 型号： | DS-11802D4-105Y |
| 厂家： | 
ETC |
| 描述： | Converter
|
| 文件： | 总7页 (文件大小：227K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS1200
Serial RAM Chip
www.maxim-ic.com
FEATURES
PIN ASSIGNMENT
C 1024 Bits of Read/Write Memory
C Low Data Retention Current for Battery
Backup Applications
C Four Million Bits/Second Data Rate
C Single-Byte or Multiple-Byte Data Transfer
Capability
C No Restrictions on the Number of Write
Cycles
16-Pin SO (300mil)
C Low-Power CMOS Circuitry
See Mech. Drawings Section
APPLICATIONS
C Software Authorization
C Computer Identification
C System Access Control
C Secure Personnel Areas
C Calibration
PIN DESCRIPTION
VCC
- +5V
RST
- Reset
C Automatic System Setup
C Traveling Work Record
DQ
- Data Input/Output
- Clock
CLK
GND
VBAT
NC
- Ground
- Battery (+)
- No Connection
DESCRIPTION
The DS1200 serial RAM chip is a miniature read/write memory that can randomly access individual
8-bit strings (bytes) or sequentially access the entire 1024-bit contents (burst). Interface cost to a
microprocessor is minimized by on-chip circuitry, which permits data transfers with only three signals:
CLK, RST , and DQ.
Nonvolatility can be achieved by connecting a battery of 2V to 4V at the battery input VBAT. A load of
0.5ꢀꢁꢂshould be used to size the external battery for the required data retention time. If nonvolatility is
not required the VBAT pin should be grounded.
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092702
DS1200
Figure 1. ELECTRONIC TAG BLOCK DIAGRAM
Figure 2. ADDRESS/COMMAND
OPERATION
The block diagram (Figure 1) illustrates the main elements of the device: shift register, control logic,
NV RAM, and power switch. To initiate a memory cycle, RST is taken high and 24 bits are loaded into
the shift register, providing both address and command information. Each bit is input serially on the
rising edge of the CLK input. Seven address bits specify one of the 128 RAM locations. The remaining
command bits specify read/write and byte/burst mode. After the first 24 clocks, which load the shift
register, additional clocks will output data for a read or input data for a write. The number of clock pulses
equal 24 plus 8 for byte mode or 24 plus 1024 for burst mode.
For hardwired applications, active power is supplied by the VCC pin. Alternatively, for user-insertable
applications, power can be supplied by the RST pin.
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DS1200
ADDRESS/COMMAND
Each memory transfer consists of a 3-byte input called the address/command. The address/command is
shown in Figure 2. As defined, the first byte of the address/command specifies whether the memory is
written or read. If any one of the bits of the first byte of the address/command fail to meet the exact
pattern of read or write, the cycle is aborted and all future inputs to the tag are ignored until RST is
brought low and then high again to begin a new cycle. The 8-bit pattern for read is 10011101. The second
byte of the address/command describes address inputs A0 in bit 0 through A6 in bit 6. Bit 7 of the second
byte of the address/command word must be set to logic 0. If bit 7 does not equal logic 0, the cycle is
aborted and all future inputs to the tag are ignored until RST is brought low and then high again to begin
a new cycle. The third byte of the address/command (bits 0 through 6) must be set to logic 0 or the cycle
is aborted and all future inputs are ignored until RST is brought low and then high again to begin a new
cycle. Bit 7 of byte 3 of the address/command is used along with address bits A0 through A6 to define
burst mode. When A0 through A6 equals logic 0 and bit 7 of byte 3 of the address command equals logic
1, the tag will enter the burst mode after the address/command sequence is complete.
BURST MODE
Burst mode is when all address bits (A0 to A6) of the address/command are set to logic 0 and bit 7 of byte
3 to logic 1. The burst mode causes 128 consecutive bytes to be read or written. Burst mode terminates
when the RST input is driven low.
RESET AND CLOCK CONTROL
All data transfers are initiated by driving the RST input high. The RST input serves three functions.
First, RST turns on the control logic, which allows access to the shift register for the address/command
sequence. Second, the RST signal provides a power source for the cycle to follow. To meet this
requirement, a drive source for RST of 2mA at 3.8V is required. However if the VCC pin is connected to
a 5V source within nominal limits, then the RST pin is not used as a source of power and input levels
revert to normal VIH and VIL inputs with a drive current requirement of 500ꢀꢁ. Finally, the RST signal
provides a method of terminating either single byte or multiple byte data transfers. A clock cycle is a
sequence of falling edge followed by a rising edge. For data inputs, the data must be valid during the
rising edge of the clock cycle. Address/command bits and data bits are input on the rising edge of the
clock and data bits are output on the falling edge of the clock. All data transfer terminates if the RST
input is low and DQ pin goes to a high-impedance state. When data transfer to the serial RAM chip is
terminated using, RST , the transition of RST must occur while the clock is at high level to avoid
disturbing the last bit of data. Data transfer is illustrated in Figure 3.
DATA INPUT
Following the 24 clock cycles that input an address/command, a data byte is input on the rising edge of
the next eight clock cycles, assuming that the read/write and write/read bits are properly set (for data
input byte 1, bit 0 = 1; bit 1 = 0; bit 2 = 1; bit 3 = 1; bit 4 = 1; bit 5 = 0; bit 6 = 0; bit 7 = 1).
DATA OUTPUT
Following the 24 clock cycles that input the read mode, a data byte is output on the falling edge of the
next eight clock cycles (for data output byte 1, bit 0 = 0; bit 1 = 1; bit 2 = 0; bit 3= 0; bit 4 = 0; bit 5 = 1;
bit 6 = 1; bit 7 = 0).
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DS1200
Figure 3. DATA TRANSFER
NOTES:
1) Data input sampled on rising edge of clock cycle.
2) Data output changes on falling edge of clock.
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DS1200
Figure 4. READ/WRITE DATA TRANSFER
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DS1200
ABSOLUTE MAXIMUM RATING*
Voltage Range on Any Pin Relative to Ground
Operating Temperature Range
-1.0V to +7.0V
0LC to +70LC
-40LC to +70LC
Storage Temperature Range
* This is a stress rating only and functional operation of the device at these or any other conditions
beyond those indicated in the operation sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods of time can affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
(0LC to +70LC)
UNITS NOTES
PARAMETER
Logic 1
SYMBOL
VIH
MIN
2.0
TYP
MAX
V
V
1, 2, 10
1
Logic 0
VIL
-0.3
3.8
0.8
VIHE
1, 7, 11
RST Logic 1
Power Supply Voltage
Battery Voltage
VCC
4.5
2.0
5.0
5.5
4.0
V
V
1
1
VBAT
DC ELECTRICAL CHARACTERISTICS
(0LC to +70LC; VCC = 5V M 10%)
PARAMETER
Input Leakage
SYMBOL
MIN
TYP
MAX
+500
+500
UNITS NOTES
IL
ILO
µA
µA
mA
mA
kΩ
5
5
Output Leakage
Output Current at 2.4V
Output Current at 0.4V
IOH
IOL
-1
+2
40
ZRST
10
1
RST Input Resistance
DQ Input Resistance
CLK Input Resistance
Active Current
ZDQ
ZCLK
ICC1
ICC2
IRST
10
10
40
40
6
kΩ
kΩ
1
1
mA
mA
mA
8
8
Standby Current
2.5
2
7, 8, 13
RST Current
CAPACITANCE
(TA = +25°C)
UNITS NOTES
PARAMETER
SYMBOL
CIN
MIN
TYP
MAX
Input Capacitance
Output Capacitance
5
7
pF
pF
COUT
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DS1200
AC ELECTRICAL CHARACTERISTICS
(0ºC to +70ºC; VCC = 5V ± 10%)
PARAMETER
Data to CLK Setup
SYMBOL
MIN
35
TYP
MAX
UNITS NOTES
tDC
ns
ns
3, 9
3, 9
Data to CLK Hold
Data to CLK Delay
CLK Low Time
CLK High Time
CLK Frequency
CLK Rise and Fall
40
tCDH
tCDD
tCL
125
ns
3, 4, 6, 9
3, 9
125
125
DC
ns
tCH
fCLK
tR, tF
tCC
ns
3, 9
4.0
MHz
ns
3, 9
500
9
1
µs
3, 9
RST to Clock Setup
CLK to RST Hold
tCCH
40
ns
ns
3, 9
tCWH
125
3, 9, 14
RST Inactive Time
RST to I/O High-Z
tCDZ
50
ns
3, 9
NOTES:
1) All voltages and resistances are referenced to ground.
2) Input levels apply to CLK, DQ, and RST while VCC is not connected to the tag, then RST input
reverts to VIHE
.
3) Measured at VIH = 2.0 or VIL = 0.8V and 10ns maximum rise and fall time.
4) Measured at VOH = 2.4V and VOL = 0.4V.
5) For CLK, DQ, RST , and VCC at 5V.
6) Load capacitance = 50pF.
7) Applies to RST when VCC < 3.8V.
8) Measured with outputs open.
9) Measured at VIH of RST greater than or equal to 3.8V when RST supplies power.
10) Logic 1 maximum is VCC + 0.3V if the VCC pin supplies power and RST +0.3V if the RST pin
supplies power.
11) RST logic 1 maximum is VCC + 0.3V if the VCC pin supplies power and 5.5V maximum if RST
supplies power.
12) Each DS1200 is marked with a four-digit date code AABB. AA designates the year of manufacture.
BB designates the week of manufacture. The expected tDR is defined as starting at the date of
manufacture.
13) Average AC RST current can be determined using the following formula:
I
TOTAL = 2 + ILOAD DC + (4 x 10-3)(CL + 140)f
I
TOTAL and ILOAD are in mA; CL is in pF; f is in MHz.
Applying the above formula, a load capacitance of 50pF running at a frequency of 4.0MHz gives an
TOTAL current of 5mA.
I
14) When RST is supplying power, tCWH must be increased to 100ms.
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