DS2153QN [ETC]
PCM Transceiver ; PCM收发器
| 型号： | DS2153QN |
| 厂家： | 
ETC |
| 描述： | PCM Transceiver
|
| 文件： | 总87页 (文件大小：1103K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS2154
Enhanced E1 Single Chip Transceiver
www.dalsemi.com
FEATURES
PACKAGE OUTLINE
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Complete E1(CEPT) PCM-30/ISDN-PRI
transceiver functionality
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Onboard long- and short-haul line interface for
clock/data recovery and waveshaping
32-bit or 128-bit crystal-less jitter attenuator
Generates line build outs for both 120Ω=and
75Ω=lines
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Frames to FAS, CAS, and CRC4 formats
Dual onboard two-frame elastic store slip buffers
that can connect to asynchronous backplanes up to
8.192 MHz
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8-bit parallel control port that can be used directly
on either multiplexed or non-multiplexed buses
Extracts and inserts CAS signaling
Detects and generates Remote and AIS alarms
Programmable output clocks for Fractional E1,
H0, and H12 applications
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Fully independent transmit and receive
functionality
Full access to both Si and Sa bits aligned with
CRC multiframe
Four separate loopbacks for testing functions
Large counters for bipolar and code violations,
CRC4 codeword errors, FAS errors, and E bits
Pin compatible with DS2152 T1 Enhanced Single-
Chip Transceiver
1
ORDERING INFORMATION
DS2154L
DS2154LN
(0°C to 70°C)
(-40°C to +85°C)
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5V supply; low power CMOS
100-pin 14mm2 body LQFP package
DESCRIPTION
The DS2154 Enhanced Single-Chip Transceiver (ESCT) contains all of the necessary functions for
connection to E1 lines. The device is an upward compatible version of the DS2153 Single-Chip
Transceiver. The onboard clock/data recovery circuitry coverts the AMI/HDB3 E1 waveforms to a NRZ
serial stream. The DS2154 automatically adjusts to E1 22AWG (0.6 mm) twisted-pair cables from 0 to
over 2 km in length. The device can generate the necessary G.703 waveshapes for both 75-ohm coax and
120-ohm twisted cables. The onboard jitter attenuator (selectable to either 32 bits or 128 bits) can be
placed in either the transmit or receive data paths. The framer locates the frame and multiframe
boundaries and monitors the data stream for alarms. It is also used for extracting and inserting signaling
data, Si, and Sa bit information. The device contains a set of internal registers which the user can access
to control the operation of the unit. Quick access via the parallel control port allows a single controller to
handle many E1 lines. The device fully meets all of the latest E1 specifications including ITU G.703,
G.704, G.706, G.823, G.932, and I.431 as well as ETS 300 011, 300 233, 300 166, TBR 12 and TBR 13.
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DS2154
TABLE OF CONTENTS
1.0
INTRODUCTION.............................................................................................................4
New Features................................................................................................................................... 4
Block Diagram ................................................................................................................................ 5
Pin List ............................................................................................................................................ 7
Pin Description.............................................................................................................................. 10
Register Map................................................................................................................................. 15
2.0
3.0
PARALLEL PORT ........................................................................................................20
CONTROL, ID, AND TEST REGISTERS......................................................................20
SYNC/RESYNC Criteria.............................................................................................................. 22
Framers Loopback......................................................................................................................... 27
Automatic Alarm Generation........................................................................................................ 28
Power-up Sequence....................................................................................................................... 30
Remote Loopback ......................................................................................................................... 31
Local Loopback............................................................................................................................. 31
4.0
5.0
STATUS AND INFORMATION REGISTERS................................................................32
CRC 4 SYNC Counter.................................................................................................................. 35
Alarm Criteria ............................................................................................................................... 36
ERROR COUNT REGISTERS ......................................................................................40
BPV or Code Violation Counter................................................................................................... 40
CRC4 Error Counter ..................................................................................................................... 41
E-bit Counter................................................................................................................................. 41
FAS Error Counter........................................................................................................................ 42
6.0
7.0
DSO MONITORING FUNCTION...................................................................................43
SIGNALING OPERATION ............................................................................................46
Processor Based Signaling............................................................................................................ 46
Hardware Based Signaling............................................................................................................ 49
8.0
9.0
PER-CHANNEL CODE GENERATION ........................................................................51
Transmit Side Code Generation.................................................................................................... 51
Receive Side Code Generation ..................................................................................................... 53
CLOCK BLOCKING REGISTERS................................................................................54
10.0 ELASTIC STORES OPERATION .................................................................................56
11.0 ADDITIONAL (Sa) AND INTERNATIONAL (Si) BIT OPERATION..............................57
Hardware Scheme ......................................................................................................................... 57
Internal Register Scheme Based on Double-Frame ...................................................................... 57
Internal Register Scheme Based on CRC4 Multiframe ................................................................ 60
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DS2154
12.0 LINE INTERFACE FUNCTIONS...................................................................................62
Receive Clock and Data Recovery................................................................................................ 62
Transmit Waveshaping and Line Driving..................................................................................... 63
Jitter Attenuator............................................................................................................................. 64
13.0 TIMING DIAGRAMS......................................................................................................67
Synchronization Flowchart ........................................................................................................... 72
Transmit Data Flow Diagram ....................................................................................................... 73
14.0 CHARACTERISTICS ....................................................................................................74
Absolute Maximum Rating........................................................................................................... 74
DC Parameters .............................................................................................................................. 74
AC Parameters .............................................................................................................................. 75
Timing........................................................................................................................................... 77
Package Description...................................................................................................................... 85
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DS2154
1.0 INTRODUCTION
The DS2154 is a super-set version of the popular DS2153 E1 Single-Chip Transceiver offering the new
features listed below. All of the original features of the DS2153 have been retained and software created
for the original devices is transferable into the DS2154.
NEW FEATURES
Option for non-multiplexed bus operation
SECTION
1 and 2
12
Crystal-less jitter attenuation
Additional hardware signaling capability including:
Receive signaling reinsertion to a backplane multiframe sync
Availability of signaling in a separate PCM data stream
Signaling freezing
7
Interrupt generated on change of signaling data
Improved receive sensitivity: 0 dB to -43 dB
12
8
Per-channel code insertion in both transmit and receive paths
Expanded access to Sa and Si bits
11
4
RCL, RLOS, RRA, and RAIS alarms now interrupt on change of state
8.192 MHz clock synthesizer
1
Per-channel loopback
8
Addition of hardware pins to indicate carrier loss and signaling freeze
1
Line interface function can be completely decoupled from the framer/formatter to
allow:
Interface to optical, HDSL, and other NRZ interfaces
1
“tap” the transmit and receive bipolar data streams for monitoring purposes
Be able corrupt data and insert framing errors, CRC errors, etc.
Transmit and receive elastic stores now have independent backplane clocks
1
Ability to monitor one DS0 channel in both the transmit and receive paths
Access to the data streams in between the framer/formatter and the elastic stores
AIS generation in the line interface that is independent of loopbacks
Transmit current limiter to meet the 50 mA short circuit requirement
Option to extend carrier loss criteria to a 1 ms period as per ETS 300 233
Automatic RAI generation to ETS 300 011 specifications
6
1
1 and 3
12
3
3
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DS2154
DS2154 ENHANCED E1 SINGLE-CHIP TRANSCEIVER Figure 1-1
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DS2154
FUNCTIONAL DESCRIPTION
The analog AMI/HDB3 waveform off of the E1 line is transformer coupled into the RRING and RTIP
pins of the DS2154. The device recovers clock and data from the analog signal and passes it through the
jitter attenuation mux to the receive side framer where the digital serial stream is analyzed to locate the
framing/multiframe pattern. The DS2154 contains an active filter that reconstructs the analog received
signal for the non-linear losses that occur in transmission. The device has a usable receive sensitivity of 0
dB to -43 dB which allows the device to operate on cables over 2 km in length. The receive side framer
locates the FAS frame and CRC and CAS multiframe boundaries as well as detects incoming alarms
including, carrier loss, loss of synchronization, AIS, and Remote Alarm. If needed, the receive side elastic
store can be enabled in order to absorb the phase and frequency differences between the recovered E1
data stream and an asynchronous backplane clock which is provided at the RSYSCLK input. The clock
applied at the RSYSCLK input can be either a 2.048 MHz clock or a 1.544 MHz clock. The RSYSCLK
can also be a bursty clock with speeds up to 8.192 MHz.
The transmit side of the DS2154 is totally independent from the receive side in both the clock
requirements and characteristics. Data off of a backplane can be passed through a transmit side elastic
store if necessary. The transmit formatter will provide the necessary frame/multiframe data overhead for
E1 transmission. Once the data stream has been prepared for transmission, it is sent via the jitter
attenuation mux to the waveshaping and line driver functions. The DS2154 will drive the E1 line from the
TTIP and TRING pins via a coupling transformer. The line driver can handle both 75Ω=and 120Ω=lines
and it has options for high return loss applications. The line driver contains a current limiter that will
restrict the maximum current into a 1Ω=load to less than 50 mA (rms).
READER’S NOTE
This data sheet assumes a particular nomenclature of the E1 operating environment. There are 32 8-bit
timeslots in an E1 systems which are number 0 to 31. Timeslot 0 is transmitted first and received first.
These 32 timeslots are also referred to as channels with a numbering scheme of 1 to 32. Timeslot 0 is
identical to channel 1, timeslot 1 is identical to Channel 2, and so on. Each timeslot (or channel) is made
up of 8 bits which are numbered 1 to 8. Bit number 1 is the MSB and is transmitted first. Bit number 8 is
the LSB and is transmitted last. Throughout this data sheet, the following abbreviations will be used:
FAS
CAS
MF
Si
Frame Alignment Signal
Channel Associated Signaling
Multiframe
CRC4
CCS
Sa
Cyclical Redundancy Check
Common Channel Signaling
Additional bits
International bits
E-bit
CRC4 Error bits
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DS2154
PIN LIST Table 1-1
PIN
1
SYMBOL
RCHBLK
NC
TYPE
DESCRIPTION
Receive Channel Block.
O
-
2
No Connect.
3
8MCLK
NC
O
-
8.192 MHz Clock.
No Connect.
4
5
NC
-
No Connect.
6
RCL
O
-
Receive Carrier Loss.
No Connect.
7
NC
8
NC
-
No Connect.
9
NC
-
No Connect.
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
NC
-
No Connect.
BTS
I
Bus Type Select.
LIUC
8XCLK
TEST
NC
I
Line Interface Connect.
Eight Times Clock.
Test.
O
I
-
No Connect.
RTIP
RRING
RVDD
RVSS
RVSS
MCLK
XTALD
NC
I
Receive Analog Tip Input.
Receive Analog Ring Input.
Receive Analog Positive Supply
Receive Analog Signal Ground.
Receive Analog Signal Ground.
Master Clock Input.
Quartz Crystal Driver.
No Connect.
I
-
-
-
I
O
-
RVSS
-
Receive Analog Signal Ground.
Interrupt.
O
INT
NC
26
27
28
29
30
31
32
33
34
35
-
-
No Connect.
NC
No Connect.
NC
-
No Connect.
TTIP
O
-
Transmit Analog Tip Output.
Transmit Analog Signal Ground.
Transmit Analog Positive Supply.
Transmit Analog Ring Output.
Transmit Channel Block.
Transmit Link Clock.
Transmit Link Data.
TVSS
TVDD
TRING
TCHBLK
TLCLK
TLINK
-
O
O
O
I
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DS2154
PIN
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
SYMBOL
NC
TYPE
DESCRIPTION
-
I/O
I
No Connect.
TSYNC
TPOSI
TNEGI
TCLKI
TCLKO
TNEGO
TPOSO
DVDD
DVSS
TCLK
TSER
Transmit Sync.
Transmit Positive Data Input.
Transmit Negative Data Input.
Transmit Clock Input.
I
I
O
O
O
-
Transmit Clock Output.
Transmit Negative Data Output.
Transmit Positive Data Output.
Digital Positive Supply.
-
Digital Signal Ground.
I
Transmit Clock.
I
Transmit Serial Data.
TSIG
I
Transmit Signaling Input.
Transmit Elastic Store Output.
Transmit Data.
TESO
TDATA
TSYSCLK
TSSYNC
TCHCLK
NC
O
I
I
Transmit System Clock.
Transmit System Sync.
I
O
-
Transmit Channel Clock.
No Connect.
MUX
I
Bus Operation.
D0/AD0
D1/AD1
D2/AD2
D3/AD3
DVSS
DVDD
D4/AD4
D5/AD5
D6/AD6
D7/AD7
A0
I/O
I/O
I/O
I/O
-
Data Bus Bit 0 / Address/Data Bus Bit 0.
Data Bus Bit 1 / Address/Data Bus Bit 1.
Data Bus Bit 2 / Address/Data Bus Bit 2.
Data Bus Bit 3 / Address/Data Bus Bit 3.
Digital Signal Ground.
-
Digital Positive Supply.
I/O
I/O
I/O
I/O
I
Data Bus Bit 4 / Address/Data Bus Bit 4.
Data Bus Bit 5 / Address/Data Bus Bit 5.
Data Bus Bit 6 / Address/Data Bus Bit 6.
Data Bus Bit 7 / Address/Data Bus Bit 7.
Address Bus Bit 0.
A1
I
Address Bus Bit 1.
A2
I
Address Bus Bit 2.
A3
I
Address Bus Bit 3.
A4
I
Address Bus Bit 4.
A5
I
Address Bus Bit 5.
A6
I
Address Bus Bit 6.
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DS2154
PIN
73
SYMBOL
TYPE
DESCRIPTION
Address Bus Bit 7 / Address Latch Enable.
Read Input (Data Strobe).
A7/ALE
I
I
74
RD (DS)
75
I
Chip Select.
CS
76
77
NC
-
I
No Connect.
Write Input (Read/Write).
WR (R/ W )
RLINK
RLCLK
DVSS
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
O
O
-
Receive Link Data.
Receive Link Clock.
Digital Signal Ground.
Digital Positive Supply.
Receive Clock.
DVDD
-
RCLK
O
-
DVDD
Digital Positive Supply.
Digital Signal Ground.
Receive Data.
DVSS
-
RDATA
RPOSI
O
I
Receive Positive Data Input.
Receive Negative Data Input.
Receive Clock Input.
RNEGI
RCLKI
I
I
RCLKO
RNEGO
RPOSO
RCHCLK
RSIGF
O
O
O
O
O
O
O
O
O
I/O
O
I
Receive Clock Output.
Receive Negative Data Output.
Receive Positive Data Output.
Receive Channel Clock.
Receive Signaling Freeze Output.
Receive Signaling Output.
Receive Serial Data.
RSIG
RSER
RMSYNC
RFSYNC
RSYNC
RLOS/LOTC
RSYSCLK
Receive Multiframe Sync.
Receive Frame Sync.
Receive Sync.
Receive Loss of Sync / Loss Of Transmit Clock.
Receive System Clock.
NOTE:
Leave all no connect (NC) pins open circuited.
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DS2154
DS2154 PIN DESCRIPTION Table 1-2
TRANSMIT SIDE DIGITAL PINS
Transmit Clock [TCLK]. A 2.048 MHz primary clock. Used to clock data through the transmit side
formatter. Must be present for the parallel control port to operate properly. If not present, the Loss Of
Transmit Clock (LOTC) function can provide a clock.
Transmit Serial Data [TSER]. Transmit NRZ serial data. Sampled on the falling edge of TCLK when
the transmit side elastic store is disabled. Sampled on the falling edge of TSYSCLK when the transmit
side elastic store is enabled.
Transmit Channel Clock [TCHCLK]. A 256 kHz clock which pulses high during the LSB of each
channel. Synchronous with TCLK when the transmit side elastic store is disabled. Synchronous with
TSYSCLK when the transmit side elastic store is enabled. Useful for parallel to serial conversion of
channel data.
Transmit Channel Block [TCHBLK]. A user-programmable output that can be forced high or low
during any of the 32 E1 channels. Synchronous with TCLK when the transmit side elastic store is
disabled. Synchronous with TSYSCLK when the transmit side elastic store is enabled. Useful for
blocking clocks to a serial UART or LAPD controller in applications where not all E1 channels are used
such as Fractional E1, 384 kbps (H0), 768 kbps, 1920 kbps (H12) or ISDN-PRI. Also useful for locating
individual channels in drop-and-insert applications, for external per-channel loopback, and for per-
channel conditioning. See Section 9 for details.
Transmit System Clock [TSYSCLK]. 1.544 MHz or 2.048 MHz clock. Only used when the transmit
side elastic store function is enabled. Should be tied low in applications that do not use the transmit side
elastic store. Can be burst at rates up to 8.192 MHz.
Transmit Link Clock [TLCLK]. 4 kHz to 20 kHz demand clock (Sa bits) for the TLINK input. See
Section 11 for details.
Transmit Link Data [TLINK]. If enabled, this pin will be sampled on the falling edge of TCLK for data
insertion into any combination of the Sa bit positions (Sa4 to Sa8). See Section 11 for details.
Transmit Sync [TSYNC]. A pulse at this pin will establish either frame or multiframe boundaries for the
transmit side. This pin can also be programmed to output either a frame or multiframe pulse. Always
synchronous with TCLK.
Transmit Frame Sync [TSSYNC]. Only used when the transmit side elastic store is enabled. A pulse at
this pin will establish either frame or multiframe boundaries for the transmit side. Should be tied low in
applications that do not use the transmit side elastic store. Always synchronous with TSYSCLK.
Transmit Signaling Input [TSIG]. When enabled, this input will be sample signaling bits for insertion
into outgoing PCM E1 data stream. Sampled on the falling edge of TCLK when the transmit side elastic
store is disabled. Sampled on the falling edge of TSYSCLK when the transmit side elastic store is
enabled. See Section 13 for timing examples.
Transmit Elastic Store Data Output [TESO]. Updated on the rising edge of TCLK with data out of the
transmit side elastic store whether the elastic store is enabled or not. This pin is normally tied to TDATA.
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DS2154
Transmit Data [TDATA]. Sampled on the falling edge of TCLK with data to be clocked through the
transmit side formatter. This pin is normally tied to TESO.
Transmit Positive Data Output [TPOSO]. Updated on the rising edge of TCLKO with the bipolar data
out of the transmit side formatter. Can be programmed to source NRZ data via the Output Data Format
(TCR1.7) control bit. This pin is normally tied to TPOSI.
Transmit Negative Data Output [TNEGO]. Updated on the rising edge of TCLKO with the bipolar
data out of the transmit side formatter. This pin is normally tied to TNEGI.
Transmit Clock Output [TCLKO]. Buffered clock that is used to clock data through the transmit side
formatter (i.e. either TCLK or RCLKO if Loss Of Transmit Clock is enabled and in effect or RCLKI if
remote loopback is enabled). This pin is normally tied to TCLKI.
Transmit Positive Data Input [TPOSI]. Sampled on the falling edge of TCLKI for data to be
transmitted out onto the E1 line. Can be internally connected to TPOSO by tying the LIUC pin high.
Transmit Negative Data Input [TNEGI]. Sampled on the falling edge of TCLKI for data to be
transmitted out onto the E1 line. Can be internally connected to TNEGO by tying the LIUC pin high.
Transmit Clock Input [TCLKI]. Line interface transmit clock. Can be internally connected to TCLKO
by tying the LIUC pin high.
RECEIVE SIDE DIGITAL PINS
Receive Link Data [RLINK]. Updated with the full recovered E1 data stream on the rising edge of
RCLK.
Receive Link Clock [RLCLK]. 4 kHz to 20 kHz clock (Sa bits) for the RLINK output. See Section 11
for details.
Receive Clock [RCLK]. 2.048 MHz clock that is used to clock data through the receive side framer.
Receive Channel Clock [RCHCLK]. 256 kHz clock which pulses high during the LSB of each channel.
Synchronous with RCLK when the receive side elastic store is disabled. Synchronous with RSYSCLK
when the receive side elastic store is enabled. Useful for parallel to serial conversion of channel data.
Receive Channel Block [RCHBLK]. A user-programmable output that can be forced high or low during
any of the 32 E1 channels. Synchronous with RCLK when the receive side elastic store is disabled.
Synchronous with RSYSCLK when the receive side elastic store is enabled. Useful for blocking clocks to
a serial UART or LAPD controller in applications where not all E1 channels are used such as Fractional
E1, 384k bps service, 768k bps, or ISDN-PRI. Also useful for locating individual channels in drop-and-
insert applications, for external per-channel loopback, and for per-channel conditioning. See Section 9 for
details.
Receive Serial Data [RSER]. Received NRZ serial data. Updated on rising edges of RCLK when the
receive side elastic store is disabled. Updated on the rising edges of RSYSCLK when the receive side
elastic store is enabled.
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DS2154
Receive Sync [RSYNC]. An extracted pulse, one RCLK wide, is output at this pin which identifies either
frame or CAS/CRC multiframe boundaries. If the receive side elastic store is enabled, then this pin can be
enabled to be an input at which a frame or multiframe boundary pulse synchronous with RSYSCLK is
applied.
Receive Frame Sync [RFSYNC]. An extracted 8 kHz pulse, one RCLK wide, is output at this pin which
identifies frame boundaries.
Receive Multiframe Sync [RMSYNC]. An extracted pulse, one RSYSCLK wide, is output at this pin
which identifies multiframe boundaries. If the receive side elastic store is disabled, then this output will
output multiframe boundaries associated with RCLK.
Receive Data [RDATA]. Updated on the rising edge of RCLK with the data out of the receive side
framer.
Receive System Clock [RSYSCLK]. 1.544 MHz or 2.048 MHz clock. Only used when the elastic store
function is enabled. Should be tied low in applications that do not use the elastic store. Can be burst at
rates up to 8.192 MHz.
Receive Signaling Output [RSIG]. Outputs signaling bits in a PCM format. Updated on rising edges of
RCLK when the receive side elastic store is disabled. Updated on the rising edges of RSYSCLK when the
receive side elastic store is enabled. See Section 13 for timing examples.
Receive Loss of Sync / Loss of Transmit Clock [RLOS/LOTC]. A dual function output that is
controlled by the TCR2.0 control bit. This pin can be programmed to either toggle high when the
synchronizer is searching for the frame and multiframe or to toggle high if the TCLK pin has not been
toggled for 5 µs.
Receive Carrier Loss [RCL]. Set high when the line interface detects a loss of carrier. [Note: a test
mode exists to allow the DS2154 to detect carrier loss at RPOSI and RNEGI in place of detection at RTIP
and RRING].
Receive Signaling Freeze [RSIGF]. Set high when the signaling data is frozen via either automatic or
manual intervention. Used to alert downstream equipment of the condition.
8 MHz Clock [8MCLK]. 8.192 MHz output clock that is referenced to the clock that is output at the
RCLK pin.
Receive Positive Data Output [RPOSO]. Updated on the rising edge of RCLKO with the bipolar data
out of the line interface. This pin is normally tied to RPOSI.
Receive Negative Data Output [RNEGO]. Updated on the rising edge of RCLKO with the bipolar data
out of the line interface. This pin is normally tied to RNEGI.
Receive Clock Output [RCLKO]. Buffered recovered clock from the E1 line. This pin is normally tied
to RCLKI.
Receive Positive Data Input [RPOSI]. Sampled on the falling edge of RCLKI for data to be clocked
through the receive side framer. RPOSI and RNEGI can be tied together for a NRZ interface. Can be
internally connected to RPOSO by tying the LIUC pin high.
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DS2154
Receive Negative Data Input [RNEGI]. Sampled on the falling edge of RCLKI for data to be clocked
through the receive side framer. RPOSI and RNEGI can be tied together for a NRZ interface. Can be
internally connected to RNEGO by tying the LIUC pin high.
Receive Clock Input [RCLKI]. Clock used to clock data through the receive side framer. This pin is
normally tied to RCLKO. Can be internally connected to RCLKO by tying the LIUC pin high. RCLKI
must be present for the parallel control port to operate properly.
PARALLEL CONTROL PORT PINS
Interrupt [INT]. Flags host controller during conditions and change of conditions defined in the Status
Registers 1 and 2. Active low, open drain output.
3-State Control [Test]. Set high to 3-state all output and I/O pins (including the parallel control port). Set
low for normal operation. Useful in board level testing.
Bus Operation [MUX]. Set low to select non-multiplexed bus operation. Set high to select multiplexed
bus operation.
Data Bus [D0 to D7] or Address/Data Bus [AD0 to AD7]. In non-multiplexed bus operation (MUX=0),
serves as the data bus. In multiplexed bus operation (MUX=1), serves as a 8-bit multiplexed address /
data bus.
Address Bus [A0 to A6]. In non-multiplexed bus operation (MUX=0), serves as the address bus. In
multiplexed bus operation (MUX=1), these pins are not used and should be tied low.
Bus Type Select [BTS]. Strap high to select Motorola bus timing; strap low to select Intel bus timing.
This pin controls the function of the RD\(DS), ALE(AS), and WR\(R/W\) pins. If BTS=1, then these pins
assume the function listed in parenthesis ().
Read Input [RD ] (Data Strobe [ DS ]). RD and DS are active low signals when MUX=11. DS is active
high when MUX = 0. See bus timing diagrams.
Chip Select [CS]. Must be low to read or write to the device. CS is an active low signal.
A7 or Address Latch Enable [ALE] (Address Strobe [AS]). In non-multiplexed bus operation
(MUX=0), serves as the upper address bit. In multiplexed bus operation (MUX=1), serves to demultiplex
the bus on a positive-going edge.
Write Input [WR] (Read/Write [R/W]). WR is an active low signal.
LINE INTERFACE PINS
Master Clock Input [MCLK]. 2.048 MHz (± 50 ppm) clock source with TTL levels is applied at this
pin. This clock is used internally for both clock/data recovery and for jitter attenuation. A quartz crystal
of 2.048 MHz may be applied across MCLK and XTALD instead of the TTL level clock source.
Quartz Crystal Driver [XTALD]. A quartz crystal of 2.048 MHz may be applied across MCLK and
XTALD instead of a TTL level clock source at MCLK. Leave open circuited if a TTL clock source is
applied at MCLK.
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DS2154
Eight Times Clock [8XCLK]. 16.384 MHz clock that is frequency locked to the 2.048 MHz clock
provided from the clock/data recovery block (if the jitter attenuator is enabled on the receive side) or from
the TCLKI pin (if the jitter attenuator is enabled on the transmit side). Can be internally disabled via the
TEST2 register if not needed.
Line Interface Connect [LIUC]. Tie low to separate the line interface circuitry from the
framer/formatter circuitry and activate the TPOSI/TNEGI/TCLKI/RPOSI/RNEGI/ RCLKI pins. Tie high
to connect the line interface circuitry to the framer/formatter circuitry and deactivate the
TPOSI/TNEGI/TCLKI/RPOSI/RNEGI/RCLKI
pins.
When
LIUC
is
tied
high,
the
TPOSI/TNEGI/TCLKI/RPOSI/RNEGI/RCLKI pins should be tied low.
Receive Tip and Ring [RTIP and RRING]. Analog inputs for clock recovery circuitry. These pins
connect via a 1:1 transformer to either the E1 line. See Section 12 for an example.
Transmit Tip and Ring [TTIP and TRING]. Analog line driver outputs. These pins connect via a
1:1.15 or 1:1.36 step-up transformer to the E1 line. See Section 12 for an example.
SUPPLY PINS
Digital Positive Supply [DVDD]. 5.0 volts ± 5%. Should be tied to the RVDD and TVDD pins.
Receive Analog Positive Supply [RVDD]. 5.0 volts ± 5%. Should be tied to the DVDD and TVDD pins.
Transmit Analog Positive Supply [TVDD]. 5.0 volts ± 5%. Should be tied to the RVDD and DVDD
pins.
Digital Signal Ground [DVSS]. 0.0 volts. Should be tied to the RVSS and TVSS pins.
Receive Analog Signal Ground [RVSS]. 0.0 volts. Should be tied to the DVSS and TVSS pins.
Transmit Analog Ground [TVSS]. 0.0 volts. Should be tied to the RVSS and DVSS pins.
14 of 87
DS2154
DS2154 REGISTER MAP Table 1-3
ADDRESS R/W REGISTER NAME
REGISTER ABBREVIATION
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
R
R
R
R
R
R
BPV or Code Violation Count 1.
BPV or Code Violation Count 2.
CRC4 Error Count 1 / FAS Error Count 1.
CRC4 Error Count 2.
VCR1
VCR2
CRCCR1
CRCCR2
E-Bit Count 1 / FAS Error Count 2.
E-Bit Count 2.
EBCR1
EBCR2
R/W Status 1.
SR1
R/W Status 2.
SR2
R/W Recive Information.
RIR
-
-
not present.
-
not present.
-
-
not present.
-
-
not present.
-
-
not present.
-
-
-
not present.
R
Device ID Register.
IDR
R/W Receive Control 1.
R/W Receive Control 2.
R/W Transmit Control 1.
R/W Transmit Control 2.
R/W Common Control 1.
R/W Test 1.
RCR1
RCR2
TCR1
TCR2
CCR1
TEST1 (set to 00h)
IMR1
R/W Interrupt Mask 1.
R/W Interrupt Mask 2.
R/W Line Interface Control.
R/W Test 2.
IMR2
LICR
TEST2 (set to 00h)
CCR2
R/W Common Control 2.
R/W Common Control 3.
R/W Transmit Sa Bit Control.
CCR3
TSaCR
-
-
Not present.
R
R
Synchronizer Status.
Receive Non-Align Frame.
SSR
RNAF
TAF
R/W Transmit Align Frame.
R/W Transmit Non-Align Frame.
R/W Transmit Channel Blocking 1.
TNAF
TCBR1
15 of 87
DS2154
REGISTER ABBREVIATION
ADDRESS R/W REGISTER NAME
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
40
41
42
43
44
45
46
47
R/W Transmit Channel Blocking 2.
R/W Transmit Channel Blocking 3.
R/W Transmit Channel Blocking 4.
R/W Transmit Idle 1.
TCBR2
TCBR3
TCBR4
TIR1
TIR2
TIR3
TIR4
TIDR
RCBR1
RCBR2
RCBR3
RCBR4
RAF
R/W Transmit Idle 2.
R/W Transmit Idle 3.
R/W Transmit Idle 4.
R/W Transmit Idle Definition.
R/W Receive Channel Blocking 1.
R/W Receive Channel Blocking 2.
R/W Receive Channel Blocking 3.
R/W Receive Channel Blocking 4.
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Receive Align Frame.
Receive Signaling 1.
Receive Signaling 2.
Receive Signaling 3.
Receive Signaling 4.
Receive Signaling 5.
Receive Signaling 6.
Receive Signaling 7.
Receive Signaling 8.
Receive Signaling 9.
Receive Signaling 10.
Receive Signaling 11.
Receive Signaling 12.
Receive Signaling 13.
Receive Signaling 14.
Receive Signaling 15.
Receive Signaling 16.
RS1
RS2
RS3
RS4
RS5
RS6
RS7
RS8
RS9
RS10
RS11
RS12
RS13
RS14
RS15
RS16
TS1
R/W Transmit Signaling 1.
R/W Transmit Signaling 2.
R/W Transmit Signaling 3.
R/W Transmit Signaling 4.
R/W Transmit Signaling 5.
R/W Transmit Signaling 6.
R/W Transmit Signaling 7.
R/W Transmit Signaling 8.
TS2
TS3
TS4
TS5
TS6
TS7
TS8
16 of 87
DS2154
REGISTER ABBREVIATION
ADDRESS R/W REGISTER NAME
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
R/W Transmit Signaling 9.
R/W Transmit Signaling 10.
R/W Transmit Signaling 11.
R/W Transmit Signaling 12.
R/W Transmit Signaling 13.
R/W Transmit Signaling 14.
R/W Transmit Signaling 15.
R/W Transmit Signaling 16.
R/W Transmit Si Bits Align Frame.
R/W Transmit Si Bits Non-Align Frame.
R/W Transmit Remote Alarm Bits.
R/W Transmit Sa4 Bits.
TS9
TS10
TS11
TS12
TS13
TS14
TS15
TS16
TSiAF
TSiNAF
TRA
TSa4
TSa5
TSa6
TSa7
TSa8
RSiAF
RSiNAF
RRA
RSa4
RSa5
RSa6
RSa7
RSa8
TC1
R/W Transmit Sa5 Bits.
R/W Transmit Sa6 Bits.
R/W Transmit Sa7 Bits.
R/W Transmit Sa8 Bits.
R
R
R
R
R
R
R
R
Receive Si Bits Align Frame.
Receive Si Bits Non-Align Frame.
Receive Remote Alarm Bits.
Receive Sa4 Bits.
Receive Sa5 Bits.
Receive Sa6 Bits.
Receive Sa7 Bits.
Receive Sa8 Bits.
R/W Transmit Channel 1.
R/W Transmit Channel 2.
R/W Transmit Channel 3.
R/W Transmit Channel 4.
R/W Transmit Channel 5.
R/W Transmit Channel 6.
R/W Transmit Channel 7.
R/W Transmit Channel 8.
R/W Transmit Channel 9.
R/W Transmit Channel 10.
R/W Transmit Channel 11.
R/W Transmit Channel 12.
R/W Transmit Channel 13.
TC2
TC3
TC4
TC5
TC6
TC7
TC8
TC9
TC10
TC11
TC12
TC13
17 of 87
DS2154
REGISTER ABBREVIATION
ADDRESS R/W REGISTER NAME
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
R/W Transmit Channel 14.
R/W Transmit Channel 15.
R/W Transmit Channel 16.
R/W Transmit Channel 17.
R/W Transmit Channel 18.
R/W Transmit Channel 19.
R/W Transmit Channel 20.
R/W Transmit Channel 21.
R/W Transmit Channel 22.
R/W Transmit Channel 23.
R/W Transmit Channel 24.
R/W Transmit Channel 25.
R/W Transmit Channel 26.
R/W Transmit Channel 27.
R/W Transmit Channel 28.
R/W Transmit Channel 29.
R/W Transmit Channel 30.
R/W Transmit Channel 31.
R/W Transmit Channel 32.
R/W Receive Channel 1.
R/W Receive Channel 2.
R/W Receive Channel 3.
R/W Receive Channel 4.
R/W Receive Channel 5.
R/W Receive Channel 6.
R/W Receive Channel 7.
R/W Receive Channel 8.
R/W Receive Channel 9.
R/W Receive Channel 10.
R/W Receive Channel 11.
R/W Receive Channel 12.
R/W Receive Channel 13.
R/W Receive Channel 14.
R/W Receive Channel 15.
R/W Receive Channel 16.
R/W Receive Channel 17.
R/W Receive Channel 18.
TC14
TC15
TC16
TC17
TC18
TC19
TC20
TC21
TC22
TC23
TC24
TC25
TC26
TC27
TC28
TC29
TC30
TC31
TC32
RC1
RC2
RC3
RC4
RC5
RC6
RC7
RC8
RC9
RC10
RC11
RC12
RC13
RC14
RC15
RC16
RC17
RC18
18 of 87
DS2154
REGISTER ABBREVIATION
ADDRESS R/W REGISTER NAME
92
93
R/W Receive Channel 19.
R/W Receive Channel 20.
R/W Receive Channel 21.
R/W Receive Channel 22.
R/W Receive Channel 23.
R/W Receive Channel 24.
R/W Receive Channel 25.
R/W Receive Channel 26.
R/W Receive Channel 27.
R/W Receive Channel 28.
R/W Receive Channel 29.
R/W Receive Channel 30.
R/W Receive Channel 31.
R/W Receive Channel 32.
R/W Transmit Channel Control 1.
R/W Transmit Channel Control 2.
R/W Transmit Channel Control 3.
R/W Transmit Channel Control 4.
R/W Receive Channel Control 1.
R/W Receive Channel Control 2.
R/W Receive Channel Control 3.
R/W Receive Channel Control 4.
R/W Common Control 4.
RC19
RC20
94
RC21
95
RC22
96
RC23
97
RC24
98
RC25
99
RC26
9A
9B
9C
9D
9E
9F
RC27
RC28
RC29
RC30
RC31
RC32
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
TCC1
TCC2
TCC3
TCC4
RCC1
RCC2
RCC3
RCC4
CCR4
R
Transmit DS0 Monitor.
R/W Common Control 5.
Receive DS0 Monitor.
TDS0M
CCR5
R
RDS0M
TEST3 (set to 00h)
(set to 00h)
(set to 00h)
(set to 00h)
R/W Test 3.
R/W Not Used.
R/W Not Used.
R/W Not Used.
NOTES:
1. Test Registers 1, 2, and 3 are used only by the factory; these registers must be cleared (set to all 0s) on
power-up initialization to insure proper operation.
2. Register banks Bxh, Cxh, Dxh, Exh, and Fxh are not accessible.
19 of 87
DS2154
2.0 PARALLEL PORT
The DS2154 is controlled via either a non-multiplexed (MUX=0) or a multiplexed (MUX=1) bus by an
external microcontroller or microprocessor. The DS2154 can operate with either Intel or Motorola bus
timing configurations. If the BTS pin is tied low, Intel timing will be selected; if tied high, Motorola
timing will be selected. All Motorola bus signals are listed in parenthesis (). See the timing diagrams in
the A.C. Electrical Characteristics in Section 14 for more details.
3.0 CONTROL, ID AND TEST REGISTERS
The operation of the DS2154 is configured via a set of nine control registers. Typically, the control
registers are only accessed when the system is first powered up. Once the DS2154 has been initialized,
the control registers will only need to be accessed when there is a change in the system configuration.
There are two Receive Control Registers (RCR1 and RCR2), two Transmit Control Registers (TCR1 and
TCR2), and five Common Control Registers (CCR1 to CCR5). Each of the nine registers is described in
this section.
There is a device IDentification Register (IDR) at address 0FH. The MSB of this read-only register is
fixed to a 1, indicating that the DS2154 is present. The pin-for-pin compatible T1 version of the DS2154
also has an ID register at address 0FH and the user can read the MSB to determine which chip is present
since in the DS2154 the MSB will be set to a 1 and in the DS2152 it will be set to a 0. The lower 4 bits of
the IDR are used to display the die revision of the chip.
The Test Registers at addresses 15, 19, and AC hex are used by the factory in testing the DS2154. On
power-up, the Test Registers should be set to 00 hex in order for the DS2154 to operate properly.
20 of 87
DS2154
IDR: DEVICE IDENTIFICATION REGISTER (Address=0F Hex)
(MSB)
(LSB)
T1E1
0
0
0
ID3
ID2
ID1
ID0
SYMBOL
POSITION NAME AND DESCRIPTION
T1E1
ID3
IDR.7
IDR.3
T1 or E1 Chip Determination Bit.
0=T1 chip
1=E1 chip
Chip Revision Bit 3. MSB of a decimal code that represents the
chip revision.
ID2
ID1
ID0
IDR.1
IDR.2
IDR.0
Chip Revision Bit 2.
Chip Revision Bit 1.
Chip Revision Bit 0. LSB of a decimal code that represents the
chip revision.
RCR1: RECEIVE CONTROL REGISTER 1 (Address=10 Hex)
(MSB)
(LSB)
RSMF
RSM
RSIO
-
-
FRC
SYNCE
RESYNC
SYMBOL
POSITION NAME AND DESCRIPTION
RSMF
RCR1.7
RSYNC Multiframe Function. Only used if the RSYNC pin is
programmed in the multiframe mode (RCR1.6=1).
0=RSYNC outputs CAS multiframe boundaries
1=RSYNC outputs CRC4 multiframe boundaries
RSM
RSIO
RCR1.6
RCR1.5
RSYNC Mode Select.
0=frame mode (see the timing in Section 13)
1=multiframe mode (see the timing in Section 13)
RSYNC I/O Select. (Note: this bit must be set to 0 when
RCR2.1=0).
0=RSYNC is an output (depends on RCR1.6)
1=RSYNC is an input (only valid if elastic store enabled)
-
-
RCR1.4
RCR1.3
RCR1.2
Not Assigned. Should be set to 0 when written.
Not Assigned. Should be set to 0 when written.
FRC
Frame Resync Criteria.
0=resync if FAS received in error 3 consecutive times
1=resync if FAS or bit 2 of non-FAS is received in error 3
consecutive times
SYNCE
RCR1.1
RCR1.0
Sync Enable.
0=auto resync enabled
1=auto resync disabled
RESYNC
Resync. When toggled from low to high, a resync is initiated.
21 of 87
DS2154
Must be cleared and set again for a subsequent resync.
SYNC/RESYNC CRITERIA Table 3-1
FRAME OR MULTI-
FRAME LEVEL
SYNC CRITERIA
RESYNC CRITERIA
ITU SPEC.
FAS
FAS present in frame N and N +
2, and FAS not present in frame
N + 1
Three consecutive
incorrect FAS received
G.706
4.1.1
4.1.2
Alternate (RCR1.2=1)
the above criteria is met
or three consecutive
incorrect bit 2 of non-
FAS received
CRC4
CAS
Two valid MF alignment words
found within 8 ms
915 or more CRC4 code
words out of 1000
received in error
G.706
4.2 and 4.3.2
Valid MF alignment word found
and previous timeslot 16 contains alignment words
code other than all 0s received in error
Two consecutive MF
G.732
5.2
22 of 87
DS2154
RCR2: RECEIVE CONTROL REGISTER 2 (Address=11 Hex)
(MSB)
(LSB)
Sa8S
Sa7S
Sa6S
Sa5S
Sa4S
RBCS
RESE
-
SYMBOL
POSITION NAME AND DESCRIPTION
Sa8S
Sa7S
Sa6S
Sa5S
Sa4S
RBCS
RESE
-
RCR2.7
RCR2.6
RCR2.5
RCR2.4
RCR2.3
RCR2.2
RCR2.1
RCR2.0
Sa8 Bit Select. Set to 1 to have RLCLK pulse at the Sa8 bit
position; set to 0 to force RLCLK low during Sa8 bit position.
See Section 13 for timing details.
Sa7 Bit Select. Set to 1 to have RLCLK pulse at the Sa7 bit
position; set to 0 to force RLCLK low during Sa7 bit position.
See Section 13 for timing details.
Sa6 Bit Select. Set to 1 to have RLCLK pulse at the Sa6 bit
position; set to 0 to force RLCLK low during Sa6 bit position.
See Section 13 for timing details.
Sa5 Bit Select. Set to 1 to have RLCLK pulse at the Sa5 bit
position; set to 0 to force RLCLK low during Sa5 bit position.
See Section 13 for timing details.
Sa4 Bit Select. Set to 1 to have RLCLK pulse at the Sa4 bit
position; set to 0 to force RLCLK low during Sa4 bit position.
See Section 13 for timing details.
Receive Side Backplane Clock Select.
0=if RSYSCLK is 1.544 MHz
1=if RSYSCLK is 2.048 MHz
Receive Side Elastic Store Enable.
0=elastic store is bypassed
1=elastic store is enabled
Not Assigned. Should be set to 0 when written.
23 of 87
DS2154
TCR1: TRANSMIT CONTROL REGISTER 1 (Address=12 Hex)
(MSB)
(LSB)
ODF
TFPT
T16S
TUA1
TSiS
TSA1
TSM
TSIO
SYMBOL
POSITION NAME AND DESCRIPTION
ODF
TCR1.7
TCR1.6
Output Data Format.
0=bipolar data at TPOSO and TNEGO
1=NRZ data at TPOSO; TNEGO=0
TFPT
Transmit Timeslot 0 Pass Through.
0=FAS bits/Sa bits/Remote Alarm sourced internally from the
TAF and TNAF registers
1=FAS bits/Sa bits/Remote Alarm sourced from TSER
T16S
TUA1
TSiS
TCR1.5
TCR1.4
TCR1.3
Transmit Timeslot 16 Data Select.
0=sample timeslot 16 at TSER pin
1=source timeslot 16 from TS0 to TS15 registers
Transmit Unframed All 1s.
0=transmit data normally
1=transmit an unframed all 1’s code at TPOSO and TNEGO
Transmit International Bit Select.
0=sample Si bits at TSER pin
1=source Si bits from TAF and TNAF registers (in this mode,
TCR1.6 must be set to 0)
TSA1
TSM
TCR1.2
TCR1.1
Transmit Signaling All 1s.
0=normal operation
1=force timeslot 16 in every frame to all 1s
TSYNC Mode Select.
0=frame mode (see the timing in Section 13)
1=CAS and CRC4 multiframe mode (see the timing in Section
13)
TSIO
TCR1.0
TSYNC I/O Select.
0=TSYNC is an input
1=TSYNC is an output
NOTE:
See Figure 13-11 for more details about how the Transmit Control Registers affect the operation of the
DS2154.
24 of 87
DS2154
TCR2: TRANSMIT CONTROL REGISTER 2 (Address=13 Hex)
(MSB)
(LSB)
Sa8S
Sa7S
Sa6S
Sa5S
Sa4S
ODM
AEBE
PF
SYMBOL
POSITION NAME AND DESCRIPTION
Sa8S
Sa7S
Sa6S
Sa5S
Sa4S
ODM
TCR2.7
TCR2.6
TCR2.5
TCR2.4
TCR2.3
TCR2.2
Sa8 Bit Select. Set to 1 to source the Sa8 bit from the TLINK
pin; set to 0 to not source the Sa8 bit. See Section 13 for timing
details.
Sa7 Bit Select. Set to 1 to source the Sa7 bit from the TLINK
pin; set to 0 to not source the Sa7 bit. See Section 13 for timing
details.
Sa6 Bit Select. Set to 1 to source the Sa6 bit from the TLINK
pin; set to 0 to not source the Sa6 bit. See Section 13 for timing
details.
Sa5 Bit Select. Set to 1 to source the Sa5 bit from the TLINK
pin; set to 0 to not source the Sa5 bit. See Section 13 for timing
details.
Sa4 Bit Select. Set to 1 to source the Sa4 bit from the TLINK
pin; set to 0 to not source the Sa4 bit. See Section 13 for timing
details.
Output Data Mode.
0=pulses at TPOSO and TNEGO are one full TCLKO period
wide
1=pulses at TPOSO and TNEGO are 1/2 TCLKO period wide
AEBE
PF
TCR2.1
TCR2.0
Automatic E-Bit Enable.
0=E-bits not automatically set in the transmit direction
1=E-bits automatically set in the transmit direction
Function of RLOS/LOTC Pin.
0=Receive Loss of Sync (RLOS)
1=Loss of Transmit Clock (LOTC)
25 of 87
DS2154
CCR1: COMMON CONTROL REGISTER 1 (Address=14 Hex)
(MSB)
(LSB)
FLB
THDB3
TG802
TCRC4
RSM
RHDB3
RG802
RCRC4
SYMBOL
POSITION NAME AND DESCRIPTION
FLB
CCR1.7
CCR1.6
CCR1.5
CCR1.4
CCR1.3
CCR1.2
CCR1.1
CCR1.0
Framer Loopback.
0=loopback disabled
1=loopback enabled
THDB3
TG802
TCRC4
RSM
Transmit HDB3 Enable.
0=HDB3 disabled
1=HDB3 enabled
Transmit G.802 Enable. See Section 13 for details.
0=do not force TCHBLK high during bit 1 of timeslot 26
1=force TCHBLK high during bit 1 of timeslot 26
Transmit CRC4 Enable.
0=CRC4 disabled
1=CRC4 enabled
Receive Signaling Mode Select.
0=CAS signaling mode
1=CCS signaling mode
RHDB3
RG802
RCRC4
Receive HDB3 Enable.
0=HDB3 disabled
1=HDB3 enabled
Receive G.802 Enable. See Section 13 for details.
0=do not force RCHBLK high during bit 1 of timeslot 26
1=force RCHBLK high during bit 1 of timeslot 26
Receive CRC4 Enable.
0=CRC4 disabled
1=CRC4 enabled
26 of 87
DS2154
FRAMER LOOPBACK
When CCR1.7 is set to a 1, the DS2154 will enter a Framer LoopBack (FLB) mode. See Figure 1-1 for
more details. This loopback is useful in testing and debugging applications. In FLB, the DS2154 will loop
data from the transmit side back to the receive side.
When FLB is enabled, the following will occur:
1. Data will be transmitted as normal at TPOSO and TNEGO.
2. Data input via RPOSI and RNEGI will be ignored.
3. The RCLK output will be replaced with the TCLK input.
CCR2: COMMON CONTROL REGISTER 2 (Address=1A Hex)
(MSB)
(LSB)
ECUS
VCRFS
AAIS
ARA
RSERC
LOTCMC
RFF
RFE
SYMBOL
POSITION NAME AND DESCRIPTION
ECUS
VCRFS
AAIS
CCR2.7
CCR2.6
CCR2.5
CCR2.4
CCR2.3
CCR2.2
Error Counter Update Select. See Section 5 for details.
0=update error counters once a second
1=update error counters every 62.5 ms (500 frames)
VCR Function Select. See Section 5 for details.
0=count BiPolar Violations (BPVs)
1=count Code Violations (CVs)
Automatic AIS Generation.
0=disabled
1=enabled
ARA
Automatic Remote Alarm Generation.
0=disabled
1=enabled
RSERC
LOTCMC
RSER Control.
0=allow RSER to output data as received under all conditions
1=force RSER to 1 under loss of frame alignment conditions
Loss of Transmit Clock Mux Control. Determines whether the
transmit side formatter should switch to the ever-present
RCLKO if the TCLK should fail to transition (see Figure 1-1).
0=do not switch to RCLKO if TCLK stops
1=switch to RCLKO if TCLK stops
RFF
RFE
CCR2.1
CCR2.0
Receive Force Freeze. Freezes receive side signaling at RSIG
(and RSER if CCR3.3=1); will override Receive Freeze Enable
(RFE). See Section 7-2 for details.
0=do not force a freeze event
1=force a freeze event
Receive Freeze Enable. See Section 7-2 for details.
0=no freezing of receive signaling data will occur
1=allow freezing of receive signaling data at RSIG (and RSER if
CCR3.3=1).
27 of 87
DS2154
AUTOMATIC ALARM GENERATION
When either CCR2.4 or CCR2.5 is set to 1, the DS2154 monitors the receive side to determine if any of
the following conditions are present: loss of receive frame synchronization, AIS alarm (all 1s) reception,
or loss of receive carrier (or signal). If any one (or more) of the above conditions is present, then the
DS2154 will either force an AIS alarm (if CCR2.5=1) or a Remote Alarm (CCR2.4=1) to be transmitted
via the TPOSO and TNEGO pins. It is an illegal state to have both CCR2.4 and CCR2.5 set to 1 at the
same time. If CCR2.4=1, then RAI will be transmitted according to ETS 300 011 specifications and a
constant Remote Alarm will be transmitted if the DS2154 cannot find CRC4 multiframe synchronization
within 400 ms as per G.706.
28 of 87
DS2154
CCR3: COMMON CONTROL REGISTER 3 Address=1B Hex)
(MSB)
(LSB)
TESE
TCBFS
TIRFS
ESR
RSRE
THSE
TBCS
RCLA
SYMBOL
POSITION NAME AND DESCRIPTION
TESE
CCR3.7
CCR3.6
Transmit Side Elastic Store Enable.
0=elastic store is bypassed
1=elastic store is enabled
TCBFS
Transmit Channel Blocking Registers (TCBR) Function
Select.
0=TCBRs define the operation of the TCHBLK output pin
1=TCBRs define which signaling bits are to be inserted
TIRFS
ESR
CCR3.5
CCR3.4
CCR3.3
Transmit Idle Registers (TIR) Function Select. See Section 8
for details.
0=TIRs define in which channels to insert idle code
1=TIRs define in which channels to insert data from RSER (i.e.,
Per=Channel Loopback function)
Elastic Stores Reset. Setting this bit from a 1 to a 0 will force
the elastic stores to a known depth. ESR is level triggered.
Should be toggled after RSYSCLK and TSYSCLK have been
applied and are stable. Must be set and cleared again for a
subsequent reset. Do not leave this bit set high.
RSRE
Receive Side Signaling Re-Insertion Enable. See Section 7-2
for details.
0=do not reinsert signaling bits into the data stream presented at
the RSER pin
1=reinsert the signaling bits into data stream presented at the
RSER pin
THSE
CCR3.2
Transmit Side Hardware Signaling Insertion Enable. See
Section 7-2 for details.
0=do not insert signaling from the TSIG pin into the data stream
presented at the TSER pin
1=insert signaling from the TSIG pin into the data stream
presented at the TSER pin
TBCS
RCLA
CCR3.1
CCR3.0
Transmit Side Backplane Clock Select.
0=if TSYSCLK is 1.544 MHz
1=if TSYSCLK is 2.048 MHz
Receive Carrier Loss (RCL) Alternate Criteria.
0=RCL declared upon 255 consecutive 0s (125 us)
1=RCL declared upon 2048 consecutive 0s (1 ms)
29 of 87
DS2154
POWER-UP SEQUENCE
On power-up, after the supplies are stable, the DS2154 should be configured for operation by writing to
all of the internal registers (this includes the Test Registers) since the contents of the internal registers
cannot be predicted on power-up. Next, the LIRST (CCR5.7) bit should be toggled from 0 to 1 to reset
the line interface circuitry (it will take the DS2154 about 40 ms to recover from the LIRST bit being
toggled). Finally, after the RSYSCLK and TSYSCLK inputs are stable, the ESR bit should be toggled
from a 0 to a 1 and then back to 0 (this step can be skipped if the elastic stores are not being used). Both
TCLK and RCLKI must be present for the parallel control port to operate properly.
CCR4: COMMON CONTROL REGISTER 4 (Address=A8 Hex)
(MSB)
(LSB)
RLB
LLB
LIAIS
TCM4
TCM3
TCM2
TCM1
TCM0
SYMBOL
POSITION NAME AND DESCRIPTION
RLB
CCR4.7
CCR4.6
CCR4.5
Remote Loopback.
0=loopback disabled
1= loopback enabled
LLB
Local Loopback.
0=loopback disabled
1=loopback enabled
LIAIS
Line Interface AIS Generation Enable. See Figure 1-1 for
details.
0=allow normal data from TPOSI/TNEGI to be transmitted at
TTIP and TRING
1=force unframed all 1s to be transmitted at TTIP and TRING
TCM4
CCR4.4
Transmit Channel Monitor Bit 4. MSB of a channel decode
that determines which transmit channel data will appear in the
TDS0M register. See Section 6 for details.
TCM3
TCM2
TCM1
TCM0
CCR4.3
CCR4.2
CCR4.1
CCR4.0
Transmit Channel Monitor Bit 3.
Transmit Channel Monitor Bit 2.
Transmit Channel Monitor Bit 1.
Transmit Channel Monitor Bit 0. LSB of the channel decode.
30 of 87
DS2154
REMOTE LOOPBACK
When CCR4.7 is set to a 1, the DS2154 will be forced into Remote LoopBack (RLB). In this loopback,
data input via the RPOSI and RNEGI pins will be transmitted back to the TPOSO and TNEGO pins. Data
will continue to pass through the receive side framer of the DS2154 as it would normally and the data
from the transmit side formatter will be ignored. Please see Figure 1-1 for more details.
LOCAL LOOPBACK
When CCR4.6 is set to a 1, the DS2154 will be forced into Local LoopBack (LLB). In this loopback, data
will continue to be transmitted as normal through the transmit side of the DS2154. Data being received at
RTIP and RRING will be replaced with the data being transmitted. Data in this loopback will pass
through the jitter attenuator. Please see Figure 1-1 for more details.
CCR5: COMMON CONTROL REGISTER 5 (Address=AA Hex)
(MSB)
(LSB)
LIRST
-
-
RCM4
RCM3
RCM2
RCM1
RCM0
SYMBOL
POSITION NAME AND DESCRIPTION
LIRST
CCR5.7
Line Interface Reset. Setting this bit from a 0 to a 1 will initiate
an internal reset that affects the clock recovery state machine and
jitter attenuator. Normally this bit is only toggled on power-up.
Must be cleared and set again for a subsequent reset.
-
-
CCR5.6
CCR5.5
CCR5.4
Not Assigned. Should be set to 0 when written
Not Assigned. Should be set to 0 when written.
RCM4
Receive Channel Monitor Bit 4. MSB of a channel decode that
determines which receive channel data will appear in the
RDS0M register. See Section 6 for details.
RCM3
RCM2
RCM1
RCM0
CCR5.3
CCR5.2
CCR5.1
CCR5.0
Receive Channel Monitor Bit 3.
Receive Channel Monitor Bit 2.
Receive Channel Monitor Bit 1.
Receive Channel Monitor Bit 0. LSB of the channel decode.
31 of 87
DS2154
4.0 STATUS AND INFORMATION REGISTERS
There is a set of four registers that contain information on the current real time status of the DS2154,
Status Register 1 (SR1), Status Register 2 (SR2), Receive Information Register (RIR), and Synchronizer
Status Register (SSR). When a particular event has occurred (or is occurring), the appropriate bit in one
of these four registers will be set to a 1. All of the bits in these registers operate in a latched fashion
(except for the SSR). This means that if an event or an alarm occurs and a bit is set to a 1 in any of the
registers, it will remain set until the user reads that bit. The bit will be cleared when it is read and it will
not be set again until the event has occurred again (or in the case of the RSA1, RSA0, RDMA, RUA1,
RRA, RCL, and RLOS alarms, the bit will remain set if the alarm is still present).
The user will always precede a read of the SR1, SR2, and RIR registers with a write. The byte written to
the register will inform the DS2154 which bits the user wishes to read and have cleared. The user will
write a byte to one of these three registers, with a 1 in the bit positions he or she wishes to read and a 0 in
the bit positions he or she does not wish to obtain the latest information on. When a 1 is written to a bit
location, the read register will be updated with the latest information. When a 0 is written to a bit
position, the read register will not be updated and the previous value will be held. A write to the status
and information registers will be immediately followed by a read of the same register. The read result
should be logically AND’ed with the mask byte that was just written and this value should be written
back into the same register to insure that bit does indeed clear. This second write step is necessary
because the alarms and events in the status registers occur asynchronously in respect to their access via
the parallel port. This write-read-write scheme allows an external microcontroller or microprocessor to
individually poll certain bits without disturbing the other bits in the register. This operation is key in
controlling the DS2154 with higher-order software languages.
The SSR register operates differently than the other three. It is a read-only register and it reports the status
of the synchronizer in real time. This register is not latched and it is not necessary to precede a read of
this register with a write.
The SR1 and SR2 registers have the unique ability to initiate a hardware interrupt via the INT output pin.
Each of the alarms and events in the SR1 and SR2 can be either masked or unmasked from the interrupt
pins via the Interrupt Mask Register 1 (IMR1) and Interrupt Mask Register 2 (IMR2) respectively.
The interrupts caused by RUA1, RRA, RCL, and RLOS act differently than the interrupts caused by
RSA1, RDMA, RSA0, RSLIP, RMF, RAF, TMF, SEC, TAF, LOTC, RCMF, and TSLIP. The four
interrupts will force the INT pin low whenever the alarm changes state (i.e., the alarm goes active or
inactive according to the set/ clear criteria in Table 4-1). The INT pin will be allowed to return high (if no
other interrupts are present) when the user reads the alarm bit that caused the interrupt to occur If the
alarm is still present, the register bit will remain set.
The event caused interrupts will force the INT pin low when the event occurs. The INT pin will be
allowed to return high (if no other interrupts are present) when the user reads the event bit that caused the
interrupt to occur.
32 of 87
DS2154
RIR: RECEIVE INFORMATION REGISTER (Address=08 Hex)
(MSB)
(LSB)
TESF
TESE
JALT
RESF
RESE
CRCRC
FASRC
CASRC
SYMBOL
POSITION NAME AND DESCRIPTION
TESF
TESE
JALT
RIR.7
RIR.6
RIR.5
Transmit Side Elastic Store Full. Set when the transmit side
elastic store buffer fills and a frame is deleted.
Transmit Side Elastic Store Empty. Set when the transmit side
elastic store buffer empties and a frame is repeated.
Jitter Attenuator Limit Trip. Set when the jitter attenuator
FIFO reaches to within 4 bits of its limit; useful for debugging
jitter attenuation operation.
RESF
RESE
RIR.4
RIR.3
RIR.2
RIR.1
RIR.0
Receive Side Elastic Store Full. Set when the receive side
elastic store buffer fills and a frame is deleted.
Receive Side Elastic Store Empty. Set when the receive side
elastic store buffer empties and a frame is repeated.
CRCRC
FASRC
CASRC
CRC Resync Criteria Met. Set when 915/1000 code words are
received in error.
FAS Resync Criteria Met. Set when 3 consecutive FAS words
are received in error.
CAS Resync Criteria Met. Set when 2 consecutive CAS MF
alignment words are received in error.
33 of 87
DS2154
SSR: SYNCHRONIZER STATUS REGISTER (Address=1E Hex)
(MSB)
(LSB)
CSC5
CSC4
CSC3
CSC2
CSC0
FASSA
CASSA
CRC4SA
SYMBOL
POSITION NAME AND DESCRIPTION
CSC5
CSC4
CSC3
CSC2
CSC0
SSR.7
SSR.6
SSR.5
SSR.4
SSR.3
CRC4 Sync Counter Bit 5. MSB of the 6-bit counter.
CRC4 Sync Counter Bit 4.
CRC4 Sync Counter Bit 3.
CRC4 Sync Counter Bit 2.
CRC4 Sync Counter Bit 0. LSB of the 6-bit counter. The next
to LSB is not accessible.
FASSA
CASSA
CRC4SA
SSR.2
SSR.1
SSR.0
FAS Sync Active. Set while the synchronizer is searching for
alignment at the FAS level.
CAS MF Sync Active. Set while the synchronizer is searching
for the CAS MF alignment word.
CRC4 MF Sync Active. Set while the synchronizer is searching
for the CRC4 MF alignment word.
34 of 87
DS2154
CRC4 SYNC COUNTER
The CRC4 Sync Counter increments each time the 8 ms CRC4 multiframe search times out. The counter
is cleared when the DS2154 has successfully obtained synchronization at the CRC4 level. The counter
can also be cleared by disabling the CRC4 mode (CCR1.0=0). This counter is useful for determining the
amount of time the DS2154 has been searching for synchronization at the CRC4 level. ITU G.706
suggests that if synchronization at the CRC4 level cannot be obtained within 400 ms, then the search
should be abandoned and proper action taken. The CRC4 Sync Counter will rollover.
SR1: STATUS REGISTER 1 (Address=06 Hex)
(MSB)
(LSB)
RSA1
RDMA
RSA0
RSLIP
RUA1
RRA
RCL
RLOS
SYMBOL
POSITION NAME AND DESCRIPTION
RSA1
SR1.7
Receive Signaling All 1s / Signaling Change. Set when the
contents of timeslot 16 contains less than three 0s over 16
consecutive frames. This alarm is not disabled in the CCS
signaling mode. Both RSA1 and RSA0 will be set if a change in
signaling is detected.
RDMA
RSA0
SR1.6
SR1.5
Receive Distant MF Alarm. Set when bit 6 of timeslot 16 in
frame 0 has been set for two consecutive multiframes. This
alarm is not disabled in the CCS signaling mode.
Receive Signaling All 0s / Signaling Change. Set when over a
full MF, timeslot 16 contains all 0s. Both RSA1 and RSA0 will
be set if a change in signaling is detected.
RSLIP
RUA1
RRA
SR1.4
SR1.3
SR1.2
SR1.1
Receive Side Elastic Store Slip. Set when the elastic store has
either repeated or deleted a frame of data.
Receive Unframed All 1s. Set when an unframed all 1s code is
received at RPOSI and RNEGI.
Receive Remote Alarm. Set when a remote alarm is received at
RPOSI and RNEGI.
RCL
Receive Carrier Loss. Set when 255 (or 2048 if CCR3.0=1)
consecutive 0s have been detected at RTIP and RRING. [Note: a
test mode exists to allow the DS2154 to detect carrier loss at
RPOSI and RNEGI in place of detection at RTIP and RRING].
RLOS
SR1.0
Receive Loss of Sync. Set when the device is not synchronized
to the receive E1 stream.
35 of 87
DS2154
ALARM CRITERIA Table 4-1
ALARM
SET CRITERIA
CLEAR CRITERIA
ITU SPEC.
over 16 consecutive frames over 16 consecutive frames
G.732
4.2
RSA1
(one full MF) timeslot 16
contains less than three 0s
(one full MF) timeslot 16
contains three or more 0s
(receive signaling all 1s)
over 16 consecutive frames over 16 consecutive frames
G.732
5.2
RSA0
(one full MF) timeslot 16
contains all 0s
(one full MF) timeslot 16
contains at least a single 1
(receive signaling all 0s)
bit 6 in timeslot 16 of
frame 0 set to 1 for two
consecutive MF
bit 6 in timeslot 16 of frame
0 set to 0 for a two
consecutive MF
O.162
2.1.5
RDMA
(receive distant multiframe
alarm)
less than three 0s in two
frames (512 bits)
more than two 0s in two
frames (512 bits)
O.162
1.6.1.2
RUA1
(receive unframed all 1s)
bit 3 of non-align frame set bit 3 of non-align frame set
O.162
2.1.4
RRA
to 1 for three consecutive
occasions
to 0 for three consecutive
occasions
(receive remote alarm)
255 (or 2048) consecutive
0s received
in 255-bit times, at least 32
1s are received
G.775 /
G.962
RCL
(receive carrier loss)
36 of 87
DS2154
SR2: STATUS REGISTER 2 (Address=07 Hex)
(MSB)
(LSB)
RMF
RAF
TMF
SEC
TAF
LOTC
RCMF
TSLIP
SYMBOL
POSITION NAME AND DESCRIPTION
RMF
RAF
SR2.7
SR2.6
SR2.5
SR2.4
SR2.3
SR2.2
SR2.1
SR2.0
Receive CAS Multiframe. Set every 2 ms (regardless if CAS
signaling is enabled or not) on receive multiframe boundaries.
Used to alert the host that signaling data is available.
Receive Align Frame. Set every 250 µs at the beginning of
align frames. Used to alert the host that Si and Sa bits are
available in the RAF and RNAF registers.
TMF
Transmit Multiframe. Set every 2 ms (regardless if CRC4 is
enabled) on transmit multiframe boundaries. Used to alert the
host that signaling data needs to be updated.
SEC
1-Second Timer. Set on increments of 1 second based on
RCLK. If CCR2.7=1, then this bit will be set every 62.5 ms
instead of once a second.
TAF
Transmit Align Frame. Set every 250 µs at the beginning of
align frames. Used to alert the host that the TAF and TNAF
registers need to be updated.
LOTC
RCMF
TSLIP
Loss of Transmit Clock. Set when the TCLK pin has not
transitioned for one channel time (or 3.9 µs). Will force the
LOTC pin high if enabled via TCR2.0.
Receive CRC4 Multiframe. Set on CRC4 multiframe
boundaries; will continue to be set every 2 ms on an arbitrary
boundary if CRC4 is disabled.
Transmit Elastic Store Slip. Set when the elastic store has
either repeated or deleted a frame of data.
37 of 87
DS2154
IMR1: INTERRUPT MASK REGISTER 1 (Address=16 Hex)
(MSB)
(LSB)
RSA1
RDMA
RSA0
RSLIP
RUA1
RRA
RCL
RLOS
SYMBOL
POSITION NAME AND DESCRIPTION
RSA1
RDMA
RSA0
RSLIP
RUA1
RRA
IMR1.7
IMR1.6
IMR1.5
IMR1.4
IMR1.3
IMR1.2
IMR1.1
IMR1.0
Receive Signaling All 1s / Signaling Change.
0=interrupt masked
1=interrupt enabled
Receive Distant MF Alarm.
0=interrupt masked
1=interrupt enabled
Receive Signaling All 0s / Signaling Change.
0=interrupt masked
1=interrupt enabled
Receive Elastic Store Slip Occurrence.
0=interrupt masked
1=interrupt enabled
Receive Unframed All 1s.
0=interrupt masked
1=interrupt enabled
Receive Remote Alarm.
0=interrupt masked
1=interrupt enabled
RCL
Receive Carrier Loss.
0=interrupt masked
1=interrupt enabled
RLOS
Receive Loss of Sync.
0=interrupt masked
1=interrupt enabled
38 of 87
DS2154
IMR2: INTERRUPT MASK REGISTER 2 (Address=17 Hex)
(MSB)
(LSB)
RMF
RAF
TMF
SEC
TAF
LOTC
RCMF
TSLIP
SYMBOL
POSITION NAME AND DESCRIPTION
RMF
RAF
IMR2.7
IMR2.6
IMR2.5
IMR2.4
IMR2.3
IMR2.2
IMR2.1
IMR2.0
Receive CAS Multiframe.
0=interrupt masked
1=interrupt enabled
Receive Align Frame.
0=interrupt masked
1=interrupt enabled
TMF
Transmit Multiframe.
0=interrupt masked
1=interrupt enabled
SEC
1-Second Timer.
0=interrupt masked
1=interrupt enabled
TAF
Transmit Align Frame.
0=interrupt masked
1=interrupt enabled
LOTC
RCMF
TSLIP
Loss Of Transmit Clock.
0=interrupt masked
1=interrupt enabled
Receive CRC4 Multiframe.
0=interrupt masked
1=interrupt enabled
Transmit Side Elastic Store Slip Occurrence.
0=interrupt masked
1=interrupt enabled
39 of 87
DS2154
5.0 ERROR COUNT REGISTERS
There are a set of four counters in the DS2154 that record bipolar or code violations, errors in the CRC4
SMF code words, E bits as reported by the far end, and word errors in the FAS. Each of these four
counters are automatically updated on either 1-second boundaries (CCR2.7=0) or every 62.5 ms
(CCR2.7=1) as determined by the timer in Status Register 2 (SR2.4). Hence, these registers contain
performance data from either the previous second or the previous 62.5 ms. The user can use the interrupt
from the timer to determine when to read these registers. The user has a full second (or 62.5 ms) to read
the counters before the data is lost.
5.1 BPV or Code Violation Counter
Violation Count Register 1 (VCR1) is the most significant word and VCR2 is the least significant word of
a 16-bit counter that records either BiPolar Violations (BPVs) or Code Violations (CVs). If CCR2.6=0,
then the VCR counts bipolar violations. Bipolar violations are defined as consecutive marks of the same
polarity. In this mode, if the HDB3 mode is set for the receive side via CCR1.2, then HDB3 code words
are not counted as BPVs. If CCR2.6=1, then the VCR counts code violations as defined in ITU O.161.
Code violations are defined as consecutive bipolar violations of the same polarity. In most applications,
the DS2154 should be programmed to count BPVs when receiving AMI code and to count CVs when
receiving HDB3 code. This counter increments at all times and is not disabled by loss of sync conditions.
The counter saturates at 65,535 and will not rollover. The bit error rate on an E1 line would have to be
greater than 10**-2 before the VCR would saturate.
VCR1: UPPER BIPOLAR VIOLATION COUNT REGISTER 1 (Address=00 Hex)
VCR2:LOWER BIPOLAR VIOLATION COUNT REGISTER 2 (Address=01 Hex)
(MSB)
(LSB)
V15
V14
V6
V13
V5
V12
V4
V11
V3
V10
V2
V9
V1
V8
VCR1
VCR2
V7
V0
SYMBOL
V15
POSITION NAME AND DESCRIPTION
VCR1.7
VCR2.0
MSB of the 16-bit bipolar or code violation count .
LSB of the 16-bit bipolar or code violation count.
V0
40 of 87
DS2154
5.2 CRC4 Error Counter
CRC4 Count Register 1 (CRCCR1) is the most significant word and CRCCR2 is the least significant
word of a 10-bit counter that records word errors in the Cyclic Redundancy Check 4 (CRC4). Since the
maximum CRC4 count in a 1-second period is 1000, this counter cannot saturate. The counter is disabled
during loss of sync at either the FAS or CRC4 level; it will continue to count if loss of multiframe sync
occurs at the CAS level.
CRCCR1: CRC4 COUNT REGISTER 1 (Address=02 Hex)
CRCCR2: CRC4 COUNT REGISTER 2 (Address=03 Hex)
(MSB)
(LSB)
(note 1) (note 1) (note 1) (note 1) (note 1)
(note 1)
CRC2
CRC9
CRC1
CRC8
CRCCR1
CRCCR2
CRC7
CRC6
CRC5
CRC4
CRC3
CRC0
SYMBOL
CRC9
POSITION NAME AND DESCRIPTION
CRCCR1.1
CRCCR2.0
MSB of the 10-bit CRC4 error count.
LSB of the 10-bit CRC4 error count.
CRC0
NOTE:
1. The upper 6 bits of CRCCR1 at address 02 are the most significant bits of the 12-bit FAS error
counter.
5.3 E-Bit Counter
E-bit Count Register 1 (EBCR1) is the most significant word and EBCR2 is the least significant word of
a 10-bit counter that records Far End Block Errors (FEBE) as reported in the first bit of frames 13 and 15
on E1 lines running with CRC4 multiframe. These count registers will increment once each time the
received E-bit is set to 0. Since the maximum E-bit count in a 1-second period is 1000, this counter
cannot saturate. The counter is disabled during loss of sync at either the FAS or CRC4 level; it will
continue to count if loss of multiframe sync occurs at the CAS level.
EBCR1: E-BIT COUNT REGISTER 1 (Address=04 Hex)
EBCR2: E-BIT COUNT REGISTER 2 (Address=05 Hex)
(MSB)
(LSB)
(note 1)
(note 1)
EB6
(note 1)
EB5
(note 1)
EB4
(note 1)
EB3
(note 1)
EB2
EB9
EB1
EB8
EBCR1
EBCR2
EB7
EB0
SYMBOL
POSITION NAME AND DESCRIPTION
EB9
EB0
EBCR1.1
EBCR2.0
MSB of the 10-bit E-Bit count.
LSB of the 10-bit E-Bit count.
NOTE:
The upper 6 bits of EBCR1 at address 04 are the least significant bits of the 12-bit FAS error counter.
41 of 87
DS2154
5.4 FAS Error Counter
FAS Count Register 1 (FASCR1) is the most significant word and FASCR2 is the least significant word
of a 12-bit counter that records word errors in the Frame Alignment Signal in timeslot 0. This counter is
disabled during loss of synchronization conditions, (RLOS = 1). Since the maximum FAS word error
count in a 1-second period is 4000, this counter cannot saturate.
FASCR1: FAS BIT COUNT REGISTER 1 (Address=02 Hex)
FASCR2: FAS BIT COUNT REGISTER 2 (Address=04 Hex)
(MSB)
(LSB)
FAS11
FAS10
FAS4
FAS9
FAS3
FAS8
FAS2
FAS7
FAS1
FAS6
FAS0
(note 2)
(note 1)
(note 2) FASCR1
FAS5
(note 1) FASCR2
SYMBOL
FAS11
POSITION NAME AND DESCRIPTION
FASCR1.7
FASCR2.2
MSB of the 12-bit FAS error count.
LSB of the 12-bit FAS error count.
FAS0
NOTES:
1. The lower 2 bits of FASCR1 at address 02 are the most significant bits of the 10-bit CRC4 error
counter.
2. The lower 2 bits of FASCR2 at address 04 are the most significant bits of the 10-bit E-bit counter.
42 of 87
DS2154
6.0 DS0 MONITORING FUNCTION
The DS2154 has the ability to monitor one DS0 64 kbps channel in the transmit direction and one DS0
channel in the receive direction at the same time. In the transmit direction the user will determine which
channel is to be monitored by properly setting the TCM0 to TCM4 bits in the CCR4 register. In the
receive direction, the RCM0 to RCM4 bits in the CCR5 register need to be properly set. The DS0
channel pointed to by the TCM0 to TCM4 bits will appear in the Transmit DS0 Monitor (TDS0M)
register and the DS0 channel pointed to by the RCM0 to RCM4 bits will appear in the Receive (RDS0M)
register.
The TCM4 to TCM0 and RCM4 to RCM0 bits should be programmed with the decimal decode of the
appropriate E1 channel. For example, if DS0 Channel 6 (timeslot 5) in the transmit direction and DS0
Channel 15 (timeslot 14) in the receive direction needed to be monitored, then the following values would
be programmed into CCR4 and CCR5:
TCM4=0 ........................................................................................ RCM4=0
TCM3=0 ........................................................................................ RCM3=1
TCM2=1 ........................................................................................ RCM2=1
TCM1=0 ........................................................................................ RCM1=1
TCM0=1 ........................................................................................ RCM0=0
CCR4: DS0 MONITORING FUNCTION (Address=A8 Hex)
[repeated here from section 3 for convenience]
(MSB)
(LSB)
RLB
LLB
LIAIS
TCM4
TCM3
TCM2
TCM1
TCM0
SYMBOL
POSITION NAME AND DESCRIPTION
RLB
LLB
CCR4.7
CCR4.6
CCR4.5
Remote Loopback. See Section 3 for details.
Local Loopback. See Section 3 for details.
LIAIS
Line Interface AIS Generation Enable. See Section 3 for
details.
TCM4
CCR4.4
Transmit Channel Monitor Bit 4. MSB of a channel decode
that determines which transmit DS0 channel data will appear in
the TDS0M register.
TCM3
TCM2
TCM1
TCM0
CCR4.3
CCR4.2
CCR4.1
CCR4.0
Transmit Channel Monitor Bit 3.
Transmit Channel Monitor Bit 2.
Transmit Channel Monitor Bit 1.
Transmit Channel Monitor Bit 0. LSB of the channel decode
that determines which transmit DS0 channel data will appear in
the TDS0M register.
43 of 87
DS2154
TDS0M: TRANSMIT DS0 MONITOR REGISTER (Address=A9 Hex)
(MSB)
(LSB)
B1
B2
B3
B4
B5
B6
B7
B8
SYMBOL
POSITION NAME AND DESCRIPTION
B1
TDS0M.7
Transmit DS0 Channel Bit 8. MSB of the DS0 channel (first
bit to be transmitted).
B2
B3
B4
B5
B6
B7
B8
TDS0M.6
TDS0M.5
TDS0M.4
TDS0M.3
TDS0M.2
TDS0M.1
TDS0M.0
Transmit DS0 Channel Bit 7.
Transmit DS0 Channel Bit 6.
Transmit DS0 Channel Bit 5.
Transmit DS0 Channel Bit 4.
Transmit DS0 Channel Bit 3.
Transmit DS0 Channel Bit 2.
Transmit DS0 Channel Bit 1. LSB of the DS0 channel (last bit
to be transmitted).
CCR5: COMMON CONTROL REGISTER 5 (Address=AA Hex)
[repeated here from section 3 for convenience]
(MSB)
(LSB)
LIRST
-
-
RCM4
RCM3
RCM2
RCM1
RCM0
SYMBOL
POSITION NAME AND DESCRIPTION
LIRST
CCR5.7
CCR5.6
CCR5.5
CCR5.4
Line Interface Reset. See Section 3 for details.
Not Assigned. Should be set to 0 when written.
Not Assigned. Should be set to 0 when written.
-
-
RCM4
Receive Channel Monitor Bit 4. MSB of a channel decode that
determines which receive DS0 channel data will appear in the
RDS0M register.
RCM3
RCM2
RCM1
RCM0
CCR5.3
CCR5.2
CCR5.1
CCR5.0
Receive Channel Monitor Bit 3.
Receive Channel Monitor Bit 2.
Receive Channel Monitor Bit 1.
Receive Channel Monitor Bit 0. LSB of the channel decode
that determines which receive DS0 channel data will appear in
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DS2154
the RDS0M register.
RDS0M: RECEIVE DS0 MONITOR REGISTER (Address=AB Hex)
(MSB)
(LSB)
B1
B2
B3
B4
B5
B6
B7
B8
SYMBOL
POSITION NAME AND DESCRIPTION
B1
RDS0M.7
Receive DS0 Channel Bit 8. MSB of the DS0 channel (first bit
to be received).
B2
B3
B4
B5
B6
B7
B8
RDS0M.6
RDS0M.5
RDS0M.4
RDS0M.3
RDS0M.2
RDS0M.1
RDS0M.0
Receive DS0 Channel Bit 7.
Receive DS0 Channel Bit 6.
Receive DS0 Channel Bit 5.
Receive DS0 Channel Bit 4.
Receive DS0 Channel Bit 3.
Receive DS0 Channel Bit 2.
Receive DS0 Channel Bit 1. LSB of the DS0 channel (last bit to
be received).
45 of 87
DS2154
7.0 SIGNALING OPERATION
The DS2154 contains provisions for both processor-based (i.e., software based) signaling bit access and
for hardware based access. Both the processor-based access and the hardware-based access can be used
simultaneously if necessary. The processor-based signaling is covered in Section 7.1 and the hardware-
based signaling is covered in Section 7.2.
7.1 PROCESSOR-BASED SIGNALING
The Channel Associated Signaling (CAS) bits embedded in the E1 stream can be extracted from the
receive stream and inserted into the transmit stream by the DS2154. Each of the 30 voice channels has
four signaling bits (A/B/C/D) associated with it. The numbers in parenthesis () are the voice channel
associated with a particular signaling bit. The voice channel numbers have been assigned as described in
the ITU documents. Please note that this is different than the channel numbering scheme (1 to 32) that is
used in the rest of the data sheet. For example, voice channel 1 is associated with timeslot 1 (Channel 2)
and voice Channel 30 is associated with timeslot 31 (Channel 32). There is a set of 16 registers for the
receive side (RS1 to RS16) and 16 registers on the transmit side (TS1 to TS16). The signaling registers
are detailed below.
RS1 TO RS16: RECEIVE SIGNALING REGISTERS (Address=30 to 3F Hex)
(MSB)
(LSB)
RS1 (30)
RS2 (31)
RS3 (32)
RS4 (33)
RS5 (34)
RS6 (35)
RS7 (36)
RS8 (37)
RS9 (38)
RS10 (39)
RS11 (3A)
RS12 (3B)
RS13 (3C)
RS14 (3D)
RS15 (3E)
RS16 (3F)
0
0
0
0
X
Y
X
X
A(1)
B(1)
B(2)
B(3)
B(4)
B(5)
B(6)
B(7)
B(8)
B(9)
B(10)
B(11)
B(12)
B(13)
B(14)
B(15)
C(1)
C(2)
C(3)
C(4)
C(5)
C(6)
C(7)
C(8)
C(9)
C(10)
C(11)
C(12)
C(13)
C(14)
C(15)
D(1)
D(2)
D(3)
D(4)
D(5)
D(6)
D(7)
D(8)
D(9)
D(10)
D(11)
D(12)
D(13)
D(14)
D(15)
A(16)
A(17)
A(18)
A(19)
A(20)
A(21)
A(22)
A(23)
A(24)
A(25)
A(26)
A(27)
A(28)
A(29)
A(30)
B(16)
B(17)
B(18)
B(19)
B(20)
B(21)
B(22)
B(23)
B(24)
B(25)
B(26)
B(27)
B(28)
B(29)
B(30)
C(16)
C(17)
C(18)
C(19)
C(20)
C(21)
C(22)
C(23)
C(24)
C(25)
C(26)
C(27)
C(28)
C(29)
C(30)
D(16)
A(2)
A(3)
D(17)
D(18)
D(19)
D(20)
D(21)
D(22)
D(23)
D(24)
D(25)
D(26)
D(27)
D(28)
D(29)
D(30)
A(4)
A(5)
A(6)
A(7)
A(8)
A(9)
A(10)
A(11)
A(12)
A(13)
A(14)
A(15)
SYMBOL
POSITION NAME AND DESCRIPTION
X
Y
RS1.0/1/3
RS1.2
Spare Bits.
Remote Alarm Bit (integrated and reported in SR1.6).
Signaling Bit A for Channel 1.
A(1)
D(30)
RS2.7
RS16.0
Signaling Bit D for Channel 30.
46 of 87
DS2154
Each Receive Signaling Register (RS1 to RS16) reports the incoming signaling from two timeslots. The
bits in the Receive Signaling Registers are updated on multiframe boundaries so the user can utilize the
Receive Multiframe Interrupt in the Receive Status Register 2 (SR2.7) to know when to retrieve the
signaling bits. The user has a full 2 ms to retrieve the signaling bits before the data is lost. The RS
registers are updated under all conditions. Their validity should be qualified by checking for
synchronization at the CAS level. In CCS signaling mode, RS1 to RS16 can also be used to extract
signaling information. Via the SR2.7 bit, the user will be informed when the signaling registers have been
loaded with data. The user has 2 ms to retrieve the data before it is lost. The signaling data reported in
RS1 to RS16 is also available at the RSIG and RSER pins.
A change in the signaling bits from one multiframe to the next will cause the RSA1 (SR1.7) and RSA0
(SR1.5) status bits to be set at the same time. The user can enable the INT pin to toggle low upon
detection of a change in signaling by setting either the IMR1.7 or IMR1.5 bit. Once a signaling change
has been detected, the user has at least 1.75 ms to read the data out of the RS1 to RS16 registers before
the data will be lost.
S1 TO TS16: TRANSMIT SIGNALING REGISTERS (Address=40 to 4F Hex)
(MSB)
(LSB)
TS1 (40)
TS2 (41)
TS3 (42)
TS4 (43)
TS5 (44)
TS6 (45)
TS7 (46)
TS8 (47)
TS9 (48)
TS10 (49)
TS11 (4A)
TS12 (4B)
TS13 (4C)
TS14 (4D)
TS15 (4E)
TS16 (4F)
0
0
0
0
X
Y
X
X
A(1)
B(1)
B(2)
B(3)
B(4)
B(5)
B(6)
B(7)
B(8)
B(9)
B(10)
B(11)
B(12)
B(13)
B(14)
B(15)
C(1)
C(2)
C(3)
C(4)
C(5)
C(6)
C(7)
C(8)
C(9)
C(10)
C(11)
C(12)
C(13)
C(14)
C(15)
D(1)
D(2)
D(3)
D(4)
D(5)
D(6)
D(7)
D(8)
D(9)
D(10)
D(11)
D(12)
D(13)
D(14)
D(15)
A(16)
A(17)
A(18)
A(19)
A(20)
A(21)
A(22)
A(23)
A(24)
A(25)
A(26)
A(27)
A(28)
A(29)
A(30)
B(16)
B(17)
B(18)
B(19)
B(20)
B(21)
B(22)
B(23)
B(24)
B(25)
B(26)
B(27)
B(28)
B(29)
B(30)
C(16)
C(17)
C(18)
C(19)
C(20)
C(21)
C(22)
C(23)
C(24)
C(25)
C(26)
C(27)
C(28)
C(29)
C(30)
D(16)
A(2)
A(3)
D(17)
D(18)
D(19)
D(20)
D(21)
D(22)
D(23)
D(24)
D(25)
D(26)
D(27)
D(28)
D(29)
D(30)
A(4)
A(5)
A(6)
A(7)
A(8)
A(9)
A(10)
A(11)
A(12)
A(13)
A(14)
A(15)
SYMBOL
POSITION NAME AND DESCRIPTION
X
Y
TS1.0/1/3
TS1.2
Spare Bits.
Remote Alarm Bit.
A(1)
D(30)
TS2.7
Signaling Bit A for Channel 1.
Signaling Bit D for Channel 30.
TS16.0
47 of 87
DS2154
Each Transmit Signaling Register (TS1 to TS16) contains the CAS bits for two timeslots that will be
inserted into the outgoing stream if enabled to do so via TCR1.5. On multiframe boundaries, the DS2154
will load the values present in the Transmit Signaling Register into an outgoing signaling shift register
that is internal to the device. The user can utilize the Transmit Multiframe bit in Status Register 2 (SR2.5)
to know when to update the signaling bits. The bit will be set every 2 ms and the user has 2 ms to update
the TSRs before the old data will be retransmitted. ITU specifications recommend that the ABCD
signaling not be set to all 0s because they will emulate a CAS multiframe alignment word.
The TS1 register is special because it contains the CAS multiframe alignment word in its upper nibble.
The upper nibble must always be set to 0000 or else the terminal at the far end will lose multiframe
synchronization. If the user wishes to transmit a multiframe alarm to the far end, then the TS1.2 bit
should be set to a 1. If no alarm is to be transmitted, then the TS1.2 bit should be cleared. The three
remaining bits in TS1 are the spare bits. If they are not used, they should be set to 1. In CCS signaling
mode, TS1 to TS16 can also be used to insert signaling information. Via the SR2.5 bit, the user will be
informed when the signaling registers need to be loaded with data. The user has 2 ms to load the data
before the old data will be retransmitted.
Via the CCR3.6 bit, the user has the option to use the Transmit Channel Blocking Registers (TCBRs) to
determine, on a channel by channel basis, which signaling bits are to be inserted via the TSRs (the
corresponding bit in the TCBRs=1) and which are to be sourced from the TSER or TSIG pin (the
corresponding bit in the TCBRs=0). See the Transmit Data Flow diagram in Section 13 for more details.
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DS2154
7.2 HARDWARE BASED SIGNALING
7.2.1 Receive Side
In the receive side of the hardware based signaling, there are two operating modes for the signaling
buffer: signaling extraction and signaling reinsertion. Signaling extraction involves pulling the signaling
bits from the receive data stream and buffering them over a 2-multiframe buffer and outputting them in a
serial PCM fashion on a channel-by-channel basis at the RSIG output pin. This mode is always enabled.
In this mode, the receive elastic store may be enabled or disabled. If the receive elastic store is enabled,
then the backplane clock (RSYSCLK) must be 2.048 MHz. The ABCD signaling bits are output on RSIG
in the lower nibble of each channel. See the timing diagrams in Section 13 for an example. The RSIG
data is updated once a multiframe (2 ms) unless a freeze is in effect.
The other hardware based signaling operating mode called signaling re-insertion can be invoked by
setting the RSRE control bit high (CCR3.3=1). In this mode, the user will provide a multiframe sync at
the RSYNC pin and the signaling data will be re-aligned in the PCM data stream provided at the RSER
output pin according to this applied multiframe boundary. In this mode, the elastic store must be enabled
and the backplane clock (RSYSCLK) must be 2.048 MHz.
The signaling data in the 2-multiframe buffer will be frozen in a known good state upon either a loss of
synchronization (OOF event), carrier loss, or frame slip. To allow this freeze action to occur, the RFE
control bit (CCR2.0) should be set high. The user can force a freeze by setting the RFF control bit
(CCR2.1) high. Setting the RFF bit high causes the same freezing action as if a loss of synchronization,
carrier loss, or slip has occurred. The RSIGF output pin provides a hardware indication that a freeze is in
effect. The RSIGF pin will go high immediately upon detection of any of the events that can cause a
freeze to occur. The RSIGF pin will return low 3 ms to 5 ms after the event subsides. The RSIGF pin
action cannot be disabled.
The 2-multiframe buffer provides an approximate 1-multiframe delay in the signaling bits provided at the
RSIG pin (and at the RSER pin if RSRE=1 via CCR3.3). When freezing is enabled (RFE=1), the
signaling data will be held in the last known good state until the corrupting error condition subsides.
When the error condition subsides, the signaling data will be held in the old state for an additional 3 ms to
5 ms before being allowed to be updated with new signaling data.
7.2.2 Transmit Side
Via the THSE control bit (CCR3.2), the DS2154 can be set up to take the signaling data presented at the
TSIG pin and insert the signaling data into the PCM data stream that is being input at the TSER pin. The
hardware signaling insertion capabilities of the DS2154 are available whether the transmit side elastic
store is enabled or disabled. If the transmit side elastic store is enabled, the backplane clock (TSYSCLK)
must be 2.048 MHz.
When hardware signaling insertion is enabled on the DS2154 (TSRE=1), then the user must enable the
Transmit Channel Blocking Register Function Select (TCBFS) control bit (CCR3.6=1). This is needed so
that the CAS multiframe alignment word, multiframe remote alarm, and spare bits can be added to
timeslot 16 in frame 0 of the multiframe. The TS1 register should be programmed with the proper
information. If CCR3.6=1, then a 0 in the TCBRs implies that signaling data is to be sourced from TSER
(or TSIG if CCR3.2=1) and a 1 implies that signaling data for that channel is to be sourced from the
Transmit Signaling (TS) registers. See definition below.
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DS2154
TCBR1/TCBR2/TCBR3/TCBR4: DEFINITION WHEN CCR3.6=1
(MSB)
(LSB)
CH20
CH4
CH8
CH19
CH23
CH27
CH31
CH3
CH7
CH18
CH22
CH26
CH30
CH2
CH6
CH17*
CH21
CH25
CH29
CH1*
CH5
TCBR1(22)
CH24
CH28
CH32
TCBR2(23)
TCBR3(24)
TCBR4(25)
CH12
CH16
CH11
CH15
CH10
CH14
CH9
CH13
*=CH1 and CH17 should be set to 1 to allow the internal TS1 register to create the CAS Multiframe
Alignment Word and Spare/Remote Alarm bits.
The user can also take advantage of this functionality to intermix signaling data from the TSIG pin and
from the internal Transmit Signaling Registers (TS1 to TS16). As an example, assume that the user
wishes to source all the signaling data except for voice channels 5 and 10 from the TSIG pin. In this
application, the following bits and registers would be programmed as follows:
CONTROL BITS ..................................................................................................
REGISTER VALUES
TSRE=1 (CCR3.2) .......................................................................................................................................
.......................................................................... TS1=0Bh (MF alignment word, remote alarm etc.)
TCBFS=1 (CCR3.6) .....................................................................................................................................
................................................................................TCBR1=03h (source timeslot 16, frame 1 data)
T16S=1 (TCR1.5) ........................................................................................................................................
......................................................TCBR2=01h (source voice Channel 5 signaling data from TS6)
TCBR3=04h (source voice Channel 10 signaling data from TS11)
TCBR4=00h
50 of 87
DS2154
8.0 PER-CHANNEL CODE GENERATION
The DS2154 can replace data on a channel-by-channel basis in both the transmit and receive directions.
The transmit direction is from the backplane to the E1 line and is covered in Section 8.1. The receive
direction is from the E1 line to the backplane and is covered in Section 8.2.
8.1 TRANSMIT SIDE CODE GENERATION
In the transmit direction there are two methods by which channel data from the backplane can be
overwritten with data generated by the DS2154. The first method which is covered in Section 8.1.1 was a
feature contained in the original DS2153 while the second method which is covered in Section 8.1.2 is a
new feature of the DS2154.
8.1.1 Simple Idle Code Insertion and Per-Channel Loopback
The first method involves using the Transmit Idle Registers (TIR1/2/3/4) to determine which of the 32 E1
channels should be overwritten with the code placed in the Transmit Idle Definition Register (TIDR).
This method allows the same 8-bit code to be placed into any of the 32 E1 channels. If this method is
used, then the CCR3.5 control bit must be set to 0.
The Transmit Idle Registers (TIRs) have an alternate function that allow them to define a Per-Channel
LoopBack (PCLB). If the CCR3.5 control bit is set to 1, then the TIRs will determine which channels (if
any) from the backplane should be replaced with the data from the receive side or in other words, off of
the E1 line. See Figure 1-1. If this mode is enabled, then transmit and receive clocks and frame syncs
must be synchronized. One method to accomplish this would be to tie RCLK to TCLK and RFSYNC to
TSYNC. There are no restrictions on which channels can be loopback or on how many channels can be
looped back.
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DS2154
TIR1/TIR2/TIR3/TIR4: TRANSMIT IDLE REGISTERS (Address=26 to 29 Hex)
[Also used for Per-Channel Loopback]
(MSB)
(LSB)
CH8
CH16
CH24
CH32
CH7
CH15
CH23
CH31
CH6
CH14
CH22
CH30
CH5
CH13
CH21
CH29
CH4
CH12
CH20
CH28
CH3
CH11
CH19
CH27
CH2
CH10
CH18
CH26
CH1
TIR1 (26)
TIR2 (27)
TIR3 (28)
TIR4 (29)
CH9
CH17
CH25
SYMBOL
POSITION NAME AND DESCRIPTION
CH32
TIR4.7
TIR1.0
Transmit Idle Registers.
0=do not insert the Idle Code in the TIDR into this channel
CH1
1=insert the Idle Code in the TIDR into this channel
NOTE:
If CCR3.5=1, then a 0 in the TIRs implies that channel data is to be sourced from TSER and a 1 implies
that channel data is to be sourced from the output of the receive side framer (i.e., Per-Channel Loopback;
see Figure 1-1).
TIDR: TRANSMIT IDLE DEFINITION REGISTER (Address=2A Hex)
(MSB)
(LSB)
TIDR7
TIDR6
TIDR5
TIDR4
TIDR3
TIDR2
TIDR1
TIDR0
SYMBOL
POSITION NAME AND DESCRIPTION
TIDR7
TIDR0
TIDR.7
TIDR.0
MSB of the Idle Code (this bit is transmitted first)
LSB of the Idle Code (this bit is transmitted last)
8.1.2 Per-Channel Code Insertion
The second method involves using the Transmit Channel Control Registers (TCC1/2/3/4) to determine
which of the 32 E1 channels should be overwritten with the code placed in the Transmit Channel
Registers (TC1 to TC32). This method is more flexible than the first in that it allows a different 8-bit code
to be placed into each of the 32 E1 channels.
TC1 TO TC32: TRANSMIT CHANNEL REGISTERS (Address=60 to 7F Hex)
(for brevity, only channel 1 is shown; see Table 1-3 for other register address)
(MSB)
(LSB)
C7
C6
SYMBOL
C7
C5
POSITION NAME AND DESCRIPTION
TC1.7 MSB of the Code (this bit is transmitted first)
C4
C3
C2
C1
C0
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DS2154
C0
TC1.0
LSB of the Code (this bit is transmitted last)
TCC1/TCC2/TCC3/TCC4:
TRANSMIT CHANNEL CONTROL REGISTER (Address=A0 to A3 Hex)
(MSB)
(LSB)
CH8
CH7
CH15
CH23
CH31
CH6
CH14
CH22
CH30
CH5
CH13
CH21
CH29
CH4
CH12
CH20
CH28
CH3
CH11
CH19
CH27
CH2
CH10
CH18
CH26
CH1
TCC1 (A0)
CH16
CH24
CH32
CH9
CH17
CH25
TCC2 (A1)
TCC3 (A2)
TCC4 (A3)
SYMBOL
POSITION NAME AND DESCRIPTION
CH1
TCC1.0
TCC4.7
Transmit Channel 1 Code Insertion Control Bit
0=do not insert data from the TC1 register into the transmit data
stream
1=insert data from the TC1 register into the transmit data stream
CH32
Transmit Channel 32 Code Insertion Control Bit
0=do not insert data from the TC32 register into the transmit
data stream
1=insert data from the TC32 register into the transmit data
stream
8.2 RECEIVE SIDE CODE GENERATION
On the receive side, the Receive Channel Control Registers (RCC1/2/3/4) are used to determine which of
the 32 E1 channels off of the E1 line and going to the backplane should be overwritten with the code
placed in the Receive Channel Registers (RC1 to RC32).
RC1 TO RC32: RECEIVE CHANNEL REGISTERS (Address=80 to 9F Hex)
(for brevity, only channel 1 is shown; see Table 1-3 for other register addresses)
(MSB)
(LSB)
C7
C6
C5
C4
C3
C2
C1
C0
RC1 (80)
SYMBOL
POSITION NAME AND DESCRIPTION
C7
C0
RC1.7
RC1.0
MSB of the Code (this bit is sent first to the backplane)
LSB of the Code (this bit is sent last to the backplane)
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DS2154
RCC1/RCC2/RCC3/RCC4:
RECEIVE CHANNEL CONTROL REGISTER (Address=A4 to A7 Hex)
(MSB)
(LSB)
CH8
CH7
CH15
CH23
CH31
CH6
CH14
CH22
CH30
CH5
CH13
CH21
CH29
CH4
CH12
CH20
CH28
CH3
CH11
CH19
CH27
CH2
CH10
CH18
CH26
CH1
RCC1 (A4)
CH16
CH24
CH32
CH9
CH17
CH25
RCC2 (A5)
RCC3 (A6)
RCC4 (A7)
SYMBOL
POSITION NAME AND DESCRIPTION
CH1
RCC1.0
RCC4.7
Receive Channel 1 Code Insertion Control Bit
0=do not insert data from the RC1 register into the receive data
stream
1=insert data from the RC1 register into the receive data stream
CH32
Receive Channel 32 Code Insertion Control Bit
0=do not insert data from the RC32 register into the receive data
stream
1=insert data from the RC32 register into the receive data stream
9.0 CLOCK BLOCKING REGISTERS
The Receive Channel blocking Registers (RCBR1 / RCBR2 / RCBR3 / RCBR4) and the Transmit
Channel Blocking Registers (TCBR1 / TCBR2 / TCBR3 / TCBR4) control RCHBLK and TCHBLK pins
respectively. (The RCHBLK and TCHBLK pins are user programmable outputs that can be forced either
high or low during individual channels). These outputs can be used to block clocks to a USART or LAPD
controller in ISDN-PRI applications. When the appropriate bits are set to a 1, the RCHBLK and
TCHBLK pin will be held high during the entire corresponding channel time. See the timing in Section
13 for an example. The TCBRs have alternate mode of use. Via the CCR3.6 bit, the user has the option to
use the TCBRs to determine, on a channel by channel basis, which signaling bits are to be inserted via the
TSRs (the corresponding bit in the TCBRs=1) and which are to be sourced from the TSER or TSIG pins
(the corresponding bit in the TCBR=0). See Section 7 for more details about this mode of operation.
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DS2154
RCBR1/RCBR2/RCBR3/RCBR4:
RECEIVE CHANNEL BLOCKING REGISTERS (Address=2B to 2E Hex)
(MSB)
(LSB)
CH8
CH7
CH15
CH23
CH31
CH6
CH14
CH22
CH30
CH5
CH13
CH21
CH29
CH4
CH12
CH20
CH28
CH3
CH11
CH19
CH27
CH2
CH10
CH18
CH26
CH1
RCBR1 (2B)
RCBR2 (2C)
RCBR3 (2D)
RCBR4 (2E)
CH16
CH24
CH32
CH9
CH17
CH25
SYMBOL
POSITION NAME AND DESCRIPTION
CH32
RCBR4.7
Receive Channel Blocking Registers.
0=force the RCHBLK pin to remain low during this channel
time
CH1
RCBR1.0
1=force the RCHBLK pin high during this channel time
TCBR1/TCBR2/TCBR3/TCBR4:
TRANSMIT CHANNEL BLOCKING REGISTERS (Address=22 to 25 Hex)
(MSB)
(LSB)
CH8
CH7
CH15
CH23
CH31
CH6
CH14
CH22
CH30
CH5
CH13
CH21
CH29
CH4
CH12
CH20
CH28
CH3
CH11
CH19
CH27
CH2
CH10
CH18
CH26
CH1
TCBR1 (22)
TCBR2 (23)
TCBR3 (24)
TCBR4 (25)
CH16
CH24
CH32
CH9
CH17
CH25
SYMBOL
POSITION NAME AND DESCRIPTION
CH32
TCBR4.7
Transmit Channel Blocking Registers.
0=force the TCHBLK pin to remain low during this channel
time
CH1
TCBR1.0
1=force the TCHBLK pin high during this channel time
NOTE:
If CCR3.6=1, then a 0 in the TCBRs implies that signaling data is to be sourced from TSER (or TSIG if
CCR3.2=1) and a 1 implies that signaling data for that channel is to be sourced from the Transmit
Signaling (TS) registers. See definition below.
TCBR1/TCBR2/TCBR3/TCBR4: DEFINITION WHEN CCR3.6=1
(MSB)
(LSB)
CH20
CH4
CH8
CH19
CH23
CH27
CH31
CH3
CH7
CH18
CH22
CH26
CH30
CH2
CH6
CH17*
CH21
CH25
CH29
CH1*
TCBR1 (22)
TCBR2 (23)
TCBR3 (24)
TCBR4 (25)
CH24
CH28
CH32
CH5
CH9
CH12
CH16
CH11
CH15
CH10
CH14
CH13
*=CH1 and CH17 should be set to 1 to allow the internal TS1 register to create the CAS Multiframe
Alignment Word and Spare/Remote Alarm bits.
55 of 87
DS2154
10.0 ELASTIC STORES OPERATION
The DS2154 contains dual two-frame (512 bits) elastic stores, one for the receive direction, and one for
the transmit direction. These elastic stores have two main purposes. First, they can be used to rate-convert
the E1 data stream to 1.544 Mbps (or a multiple of 1.544 Mbps) which is the T1 rate. Secondly, they can
be used to absorb the differences in frequency and phase between the E1 data stream and an
asynchronous (i.e., not frequency locked) backplane clock which can be 1.544 MHz or 2.048 MHz. The
backplane clock can burst at rates up to 8.192 MHz. Both elastic stores contain full controlled slip
capability which is necessary for this second purpose. The elastic stores can be forced to a known depth
via the Elastic Store Reset bit (CCR3.4). Toggling the CCR3.4 bit forces the read and write pointers into
opposite frames. Both elastic stores within the DS2154 are fully independent and no restrictions apply to
the sourcing of the various clocks that are applied to them. The transmit side elastic store can be enabled
whether the receive elastic store is enabled or disabled and vice versa. Also, each elastic store can
interface to either a 1.544 MHz or 2.048 MHz backplane without regard to the backplane rate the other
elastic store is interfacing.
10.1 RECEIVE SIDE
If the receive side elastic store is enabled (RCR2.1=1), then the user must provide either a 1.544 MHz
(RCR2.2 =0) or 2.048 MHz (RCR2.2=1) clock at the RSYSCLK pin. The user has the option of either
providing a frame/multiframe sync at the RSYNC pin (RCR1.5=1) or having the RSYNC pin provide a
pulse on frame/multiframe boundaries (RCR1.5=0). If the user wishes to obtain pulses at the frame
boundary, then RCR1.6 must be set to 0; if the user wishes to have pulses occur at the multiframe
boundary, then RCR1.6 must be set to 1. The DS2154 will always indicate frame boundaries via the
RFSYNC output whether the elastic store is enabled or not. If the elastic store is enabled, then either CAS
(RCR1.7=0) or CRC4 (RCR1.7=1) multiframe boundaries will be indicated via the RMSYNC output. If
the user selects to apply a 1.544 MHz clock to the RSYSCLK pin, then every fourth channel of the
received E1 data will be deleted and an F-bit position (which will be forced to 1) will be inserted. Hence
Channels 1, 5, 9, 13, 17, 21, 25, and 29 (timeslots 0, 4, 8, 12, 16, 20, 24, and 28) will be deleted from the
received E1 data stream. Also, in 1.544 MHz applications, the RCHBLK output will not be active in
Channels 25 through 32 (or in other words, RCBR4 is not active). See Section 13 for timing details. If
the 512-bit elastic buffer either fills or empties, a controlled slip will occur. If the buffer empties, then a
full frame of data (256-bits) will be repeated at RSER and the SR1.4 and RIR.3 bits will be set to a 1. If
the buffer fills, then a full frame of data will be deleted and the SR1.4 and RIR.4 bits will be set to a 1.
10.2 TRANSMIT SIDE
The operation of the transmit elastic store is very similar to the receive side. The transmit side elastic
store is enabled via CCR3.7. A 1.544 MHz (CCR3.1=0) or 2.048 MHz (CCR3.1=1) clock can be applied
to the TSYSCLK input. The TSYSCLK can be a bursty clock with rates up to 8.192 MHz. If the user
selects to apply a 1.544 MHz clock to the TSYSCLK pin, then the data sampled at TSER will be stuffed
with 8 empty channels. The user must supply an 8 kHz frame sync pulse to the TSSYNC input. See
Section 13 for timing details. Controlled slips in the transmit elastic store are reported in the SR2.0 bit
and the direction of the slip is reported in the RIR.6 and RIR.7 bits.
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DS2154
11.0 ADDITIONAL (Sa) AND INTERNATIONAL (Si) BIT OPERATION
The DS2154 provides for access to both the Sa and the Si bits via three different methods. The first is via
a hardware scheme using the RLINK/RLCLK and TLINK/ TLCLK pins. The first method is discussed in
Section 11.1. The second involves using the internal RAF/RNAF and TAF/TNAF registers and is
discussed in Section 11.2 The third method which is covered in Section 11.3 involves an expanded
version of the second method and is one of the features added to the DS2154 from the original DS2153
definition.
11.1 HARDWARE SCHEME
On the receive side, all of the received data is reported at the RLINK pin. Via RCR2, the user can control
the RLCLK pin to pulse during any combination of Sa bits. This allows the user to create a clock that can
be used to capture the needed Sa bits. If RSYNC is programmed to output a frame boundary, it will
identify the Si bits. See Section 13 for detailed timing.
On the transmit side, the individual Sa bits can be either sourced from the internal TNAF register (see
Section 11.2 for details) or from the external TLINK pin. Via TCR2, the DS2154 can be programmed to
source any combination of the additional bits from the TLINK pin. If the user wishes to pass the Sa bits
through the DS2154 without them being altered, then the device should be set up to source all five Sa bits
via the TLINK pin and the TLINK pin should be tied to the TSER pin. Si bits can be inserted through the
TSER pin via the clearing of the TCR1.3 bit. Please see the timing diagrams and the transmit data flow
diagram in Section 13 for examples.
11.2 INTERNAL REGISTER SCHEME BASED ON DOUBLE-FRAME
On the receive side, the RAF and RNAF registers will always report the data as it received in the
Additional and International bit locations. The RAF and RNAF registers are updated with the setting of
the Receive Align Frame bit in Status Register 2 (SR2.6). The host can use the SR2.6 bit to know when to
read the RAF and RNAF registers. It has 250 us to retrieve the data before it is lost.
On the transmit side, data is sampled from the TAF and TNAF registers with the setting of the Transmit
Align Frame bit in Status Register 2 (SR2.3). The host can use the SR2.3 bit to know when to update the
TAF and TNAF registers. It has 250 us to update the data or else the old data will be retransmitted. Data
in the Si bit position will be overwritten if either the DS2154 is programmed: (1) to source the Si bits
from the TSER pin, (2) in the CRC4 mode, or (3) have automatic E-bit insertion enabled. Data in the Sa
bit position will be overwritten if any of the TCR2.3 to TCR2.7 bits are set to 1 (please see Section 11.1
for details). Please see the register descriptions for TCR1 and TCR2 and the Transmit Data Flow diagram
in Section 13 for more details.
57 of 87
DS2154
RAF: RECEIVE ALIGN FRAME REGISTER (Address=2F Hex)
(MSB)
(LSB)
Si
0
0
1
1
0
1
1
SYMBOL
POSITION NAME AND DESCRIPTION
Si
0
0
1
1
0
1
1
RAF.7
RAF.6
RAF.5
RAF.4
RAF.3
RAF.2
RAF.1
RAF.0
International Bit.
Frame Alignment Signal Bit.
Frame Alignment Signal Bit.
Frame Alignment Signal Bit.
Frame Alignment Signal Bit.
Frame Alignment Signal Bit.
Frame Alignment Signal Bit.
Frame Alignment Signal Bit.
RNAF: RECEIVE NON-ALIGN FRAME REGISTER (Address=1F Hex)
(MSB)
(LSB)
Si
1
A
Sa4
Sa5
Sa6
Sa7
Sa8
SYMBOL
POSITION NAME AND DESCRIPTION
Si
1
RNAF.7
RNAF.6
RNAF.5
RNAF.4
RNAF.3
RNAF.2
RNAF.1
RNAF.0
International Bit.
Frame Non-Alignment Signal Bit.
Remote Alarm.
A
Sa4
Sa5
Sa6
Sa7
Sa8
Additional Bit 4.
Additional Bit 5.
Additional Bit 6.
Additional Bit 7.
Additional Bit 8.
58 of 87
DS2154
TAF: TRANSMIT ALIGN FRAME REGISTER (Address=20 Hex)
(MSB)
(LSB)
Si
0
0
1
1
0
1
1
[Must be programmed with the 7-bit FAS word; the DS2154 does not automatically set these bits]
SYMBOL
POSITION NAME AND DESCRIPTION
Si
0
0
1
1
0
1
1
TAF.7
TAF.6
TAF.5
TAF.4
TAF.3
TAF.2
TAF.1
TAF.0
International Bit.
Frame Alignment Signal Bit.
Frame Alignment Signal Bit.
Frame Alignment Signal Bit.
Frame Alignment Signal Bit.
Frame Alignment Signal Bit.
Frame Alignment Signal Bit.
Frame Alignment Signal Bit.
TNAF: TRANSMIT NON-ALIGN FRAME REGISTER (Address=21 Hex)
(MSB)
(LSB)
Si
1
A
Sa4
Sa5
Sa6
Sa7
Sa8
[Bit 2 must be programmed to 1; the DS2154 does not automatically set this bit]
SYMBOL
POSITION NAME AND DESCRIPTION
Si
1
TNAF.7
TNAF.6
TNAF.5
TNAF.4
TNAF.3
TNAF.2
TNAF.1
TNAF.0
International Bit.
Frame Non-Alignment Signal Bit.
A
Remote Alarm (used to transmit the alarm).
Additional Bit 4.
Sa4
Sa5
Sa6
Sa7
Sa8
Additional Bit 5.
Additional Bit 6.
Additional Bit 7.
Additional Bit 8.
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DS2154
11.3 INTERNAL REGISTER SCHEME BASED ON CRC4 MULTIFRAME
On the receive side, there is a set of eight registers (RSiAF, RSiNAF, RRA, RSa4 to RSa8) that report the
Si and Sa bits as they are received. These registers are updated with the setting of the Receive CRC4
Multiframe bit in Status Register 2 (SR2.1). The host can use the SR2.1 bit to know when to read these
registers. The user has 2 ms to retrieve the data before it is lost. The MSB of each register is the first
received. Please see the register descriptions below and the Transmit Data Flow diagram in Section 13 for
more details.
On the transmit side, there is also a set of eight registers (TSiAF, TSiNAF, TRA, TSa4 to TSa8) that can
be programmed to insert both Si and Sa data via the Transmit Sa Bit Control Register (TSaCR). Data is
sampled from these registers with the setting of the Transmit Multiframe bit in Status Register 2 (SR2.5).
The host can use the SR2.5 bit to know when to update these registers. It has 2 ms to update the data or
else the old data will be retransmitted. The MSB of each register is the first bit transmitted. Please see the
register descriptions below and the Transmit Data Flow diagram in Section 13 for more details.
REGISTER
NAME
ADDRESS
(HEX)
FUNCTION
The 8 Si bits in the align frame
RSiAF
RSiNAF
RRA
58
59
5A
5B
5C
5D
5E
5F
50
51
52
53
54
55
56
57
The 8 Si bits in the non-align frame
The 8 reportings of the receive remote alarm (RA)
RSa4
The 8 Sa4 reported in each CRC4 multiframe
The 8 Sa5 reported in each CRC4 multiframe
The 8 Sa6 reported in each CRC4 multiframe
The 8 Sa7 reported in each CRC4 multiframe
The eight Sa8 reported in each CRC4 multiframe
The 8 Si bits to be inserted into the align frame
The 8 Si bits to be inserted into the non-align frame
The 8 settings of remote alarm (RA)
RSa5
RSa6
RSa7
RSa8
TSiAF
TSiNAF
TRA
TSa4
The 8 Sa4 settings in each CRC4 multiframe
The 8 Sa5 settings in each CRC4 multiframe
The 8 Sa6 settings in each CRC4 multiframe
The 8 Sa7 settings in each CRC4 multiframe
The 8 Sa8 settings in each CRC4 multiframe
TSa5
TSa6
TSa7
TSa8
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DS2154
TSaCR: TRANSMIT Sa BIT CONTROL REGISTER (Address=1C Hex)
(MSB)
(LSB)
SiAF
SiNAF
RA
Sa4
Sa5
Sa6
Sa7
Sa8
SYMBOL POSITION NAME AND DESCRIPTION
SiAF
SiNAF
RA
TSaCR.7
TSaCR.6
TSaCR.5
TSaCR.4
TSaCR.3
TSaCR.2
TSaCR.1
TSaCR.0
International Bit in Align Frame Insertion Control Bit.
0=do not insert data from the TSiAF register into the transmit data
stream
1=insert data from the TSiAF register into the transmit data stream
International Bit in Non-Align Frame Insertion Control Bit.
0=do not insert data from the TSiNAF register into the transmit data
stream
1=insert data from the TSiNAF register into the transmit data stream
Remote Alarm Insertion Control Bit.
0=do not insert data from the TRA register into the transmit data
stream
1=insert data from the TRA register into the transmit data stream
Sa4
Additional Bit 4 Insertion Control Bit.
0=do not insert data from the TSa4 register into the transmit data
stream
1=insert data from the TSa4 register into the transmit data stream
Sa5
Additional Bit 5 Insertion Control Bit.
0=do not insert data from the TSa5 register into the transmit data
stream
1=insert data from the TSa5 register into the transmit data stream
Sa6
Additional Bit 6 Insertion Control Bit.
0=do not insert data from the TSa6 register into the transmit data
stream
1=insert data from the TSa6 register into the transmit data stream
Sa7
Additional Bit 7 Insertion Control Bit.
0=do not insert data from the TSa7 register into the transmit data
stream
1=insert data from the TSa7 register into the transmit data stream
Sa8
Additional Bit 8 Insertion Control Bit.
0=do not insert data from the TSa8 register into the transmit data
stream
1=insert data from the TSa8 register into the transmit data stream
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DS2154
12.0 LINE INTERFACE FUNCTIONS
The line interface function in the DS2154 contains three sections: (1) the receiver which handles clock
and data recovery; (2) the transmitter which waveshapes and drives the E1 line; and (3) the jitter
attenuator. Each of these three sections is controlled by the Line Interface Control Register (LICR) which
is described below.
LICR: LINE INTERFACE CONTROL REGISTER (Address=18 Hex)
(MSB)
(LSB)
L2
L1
L0
EGL
JAS
JABDS
DJA
TPD
LICR
SYMBOL
POSITION NAME AND DESCRIPTION
L2
LICR.7
LICR.6
LICR.5
LICR.4
Line Build Out Bit 2. Transmit waveshape setting; see Table
12-2.
L1
L0
Line Build Out Bit 1. Transmit waveshape setting; see Table
12-2.
Line Build Out Bit 0. Transmit waveshape setting; see Table
12-2.
EGL
Receive Equalizer Gain Limit.
0=-12 dB
1=-43 dB
JAS
JABDS
DJA
LICR.3
LICR.2
LICR.1
LICR.0
Jitter Attenuator Select.
0=place the jitter attenuator on the receive side
1=place the jitter attenuator on the transmit side
Jitter Attenuator Buffer Depth Select
0=128-bits
1=32-bits (use for delay sensitive applications)
Disable Jitter Attenuator.
0=jitter attenuator enabled
1=jitter attenuator disabled
TPD
Transmit Power Down.
0=normal transmitter operation
1=powers down the transmitter and 3-states the TTIP and
TRING pins
12.1 RECEIVE CLOCK AND DATA RECOVERY
The DS2154 contains a digital clock recovery system. See the DS2154 Block Diagram in Section 1 and
Figure 12-1 for more details. The DS2154 couples to the receive E1 shielded twisted pair or COAX via a
1:1 transformer. See Table 12-3 for transformer details. The 2.048 MHz clock attached at the MCLK pin
is internally multiplied by 16 via an internal PLL and fed to the clock recovery system. The clock
recovery system uses the clock from the PLL circuit to form a 16 times oversampler which is used to
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DS2154
recover the clock and data. This oversampling technique offers outstanding jitter tolerance (see Figure 12-
2).
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DS2154
Normally, the clock that is output at the RCLKO pin is the recovered clock from the E1 AMI/HDB3
waveform presented at the RTIP and RRING inputs. When no AMI signal is present at RTIP and RRING,
a Receive Carrier Loss (RCL) condition will occur and the RCLKO will be sourced from the clock
applied at the MCLK pin. If the jitter attenuator is either placed in the transmit path or is disabled, the
RCLKO output can exhibit slightly shorter high cycles of the clock. This is due to the highly oversampled
digital clock recovery circuitry. If the jitter attenuator is placed in the receive path (as is the case in most
applications), the jitter attenuator restores the RCLK to being close to 50% duty cycle. Please see the
Receive AC Timing Characteristics in Section 14 for more details.
12.2 TRANSMIT WAVESHAPING AND LINE DRIVING
The DS2154 uses a set of laser-trimmed delay lines along with a precision Digital-to-Analog Converter
(DAC) to create the waveforms that are transmitted onto the E1 line. The waveforms created by the
DS2154 meet the ITU G.703 specifications. See Figure 12-3. The user will select which waveform is to
be generated by properly programming the L2/L1/L0 bits in the Line Interface Control Register (LICR).
The DS2154 can be set up in a number of various configurations depending on the application. See Table
12-2 and Figure 12-1.
LINE BUILD OUT SELECT IN LICR Table 12-2
LLL
210
RETURN
LOSS
RT (SEE
FIGURE 12-1)
APPLICATION
75 ohms normal (See Note 1)
120 ohms normal
TRANSFORMER
1:1.15 step-up
1:1.15 step-up
1:1.15 step-up
1:1.15 step-up
1:1.15 step-up
1:1.36 step-up
1:1.36 step-up
000
001
010
011
100
110
100
NM
NM
0 ohms
0 ohms
75 ohms w/ protection resistors
120 ohms w/ protection resistors
75 ohms w/ high return loss
75 ohms w/ high return loss
120 ohms w/ high return loss
NM
8.2 ohms
8.2 ohms
27 ohms
18 ohms
27 ohms
NM
21dB
21dB
21dB
NOTE:
1. This LBO is not recommended for use in the A2 revision of the DS2154.
Due to the nature of the design of the transmitter in the DS2154, very little jitter (less then 0.005 UIpp
broadband from 10 Hz to 100 kHz) is added to the jitter present on TCLK. Also, the waveforms that they
create are independent of the duty cycle of TCLK. The transmitter in the DS2154 couples to the E1
transmit shielded twisted pair or COAX via a 1:1.15 or 1:1.36 step up transformer as shown in Figure 12-
1. In order for the devices to create the proper waveforms, this transformer used must meet the
specifications listed in Table 12-3 The line driver in the DS2154 contains a current limiter that will
prevent more than 50 mA (rms) from being sourced in a 1 ohm load.
TRANSFORMER SPECIFICATIONS Table 12-3
SPECIFICATION
RECOMMENDED VALUE
1:1 (receive) and 1:1.15 or 1:1.36 (transmit) ± 5%
600 uH minimum
Turns Ratio
Primary Inductance
Leakage Inductance
Intertwining Capacitance
DC Resistance
1.0 uH maximum
40 pF maximum
1.2 ohms maximum
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DS2154
12.3 JITTER ATTENUATOR
The DS2154 contains an onboard jitter attenuator that can be set to a depth of either 32 or 128 bits via the
JABDS bit in the Line Interface Control Register (LICR). The 128-bit mode is used in applications
where large excursions of wander are expected. The 32-bit mode is used in delay sensitive applications.
The characteristics of the attenuation are shown in Figure 12-4. The jitter attenuator can be placed in
either the receive path or the transmit path by appropriately setting or clearing the JAS bit in the LICR.
Also, the jitter attenuator can be disabled (in effect, removed) by setting the DJA bit in the LICR. In order
for the jitter attenuator to operate properly, a 2.048 MHz clock (±50 ppm) must be applied at the MCLK
pin or a crystal with similar characteristics must be applied across the MCLK and XTALD pins. If a
crystal is applied across the MCLK and XTALD pins, then capacitors should be placed from each leg of
the crystal to ground as shown in Figure 12-1. Onboard circuitry adjusts either the recovered clock from
the clock/data recovery block or the clock applied at the TCLKI pin to create a smooth jitter-free clock
which is used to clock data out of the jitter attenuator FIFO. It is acceptable to provide a gapped/bursty
clock at the TCLKI pin if the jitter attenuator is placed on the transmit side. If the incoming jitter exceeds
either 120 UIpp (buffer depth is 128 bits) or 28 UIpp (buffer depth is 32 bits), then the DS2154 will
divide the internal nominal 32.768 MHz clock by either 15 or 17 instead of the normal 16 to keep the
buffer from overflowing. When the device divides by either 15 or 17, it also sets the Jitter Attenuator
Limit Trip (JALT) bit in the Receive Information Register (RIR.5).
DS2154 EXTERNAL ANALOG CONNECTIONS Figure 12-1
NOTES:
1. All resistor values are ±1%.
2. The Rt resistors are used to increase the transmitter return loss or to protect the device from over–
voltage.
3. The Rr resistors are used to terminate the receive E1 line.
4. For 75-ohm termination, Rr=37.5 ohms; for 120-ohm termination Rr=60 ohm.
5. See the separate Application Note for details on how to construct a protected interface.
6. Either a crystal can be applied across the MCLK and XTALD pins or a TTL level clock can be
applied to just MCLK.
7. C1 and C2 should be 5 pF lower than two times the nominal loading capacitance of the crystal to
adjust for the input capacitance of the DS2154.
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DS2154
DS2154 JITTER TOLERANCE Figure 12-2
DS2154 TRANSMIT WAVEFORM TEMPLATE Figure 12-3
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DS2154
DS2154 JITTER ATTENUATION Figure 12-4
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DS2154
13.0 TIMING DIAGRAMS/SYNC FLOWCHART/TRANSMIT DATA FLOW DIAGRAM
RECEIVE SIDE TIMING Figure 13-1
NOTES:
1. RSYNC in the frame mode (RCR1.6=0).
2. RSYNC in the multiframe mode (RCR1.6=1).
3. RLCLK is programmed to pulse high during the Sa4 bit position.
4. RLINK will always output all 5 Sa bits as well as the rest of the receive data stream.
5. This diagram assumes the CAS MF begins with the FAS word.
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DS2154
RECEIVE SIDE BOUNDARY TIMING
(WITH ELASTIC STORE DISABLED) Figure 13-2
NOTES:
1. RCHBLK is programmed to block Channel 2.
2. RLCLK is programmed to pulse high during the Sa4 bits position.
3. Shown is a non-align frame boundary.
4. RSIG normally contains the CAS multiframe alignment nibble (0000) in Channel 1.
RECEIVE SIDE 1.544 MHz BOUNDARY TIMING
(WITH ELASTIC STORE ENABLED) Figure 13-3
NOTES:
1. Data from the E1 Channels 1, 5, 9, 13, 17, 21, 25, and 29 is dropped (Channel 2 from the E1 link is
mapped to Channel 1 of the T1 link, etc.) and the F-bit position is added (forced to 1).
2. RSYNC is in the output mode (RCR1.5=0).
3. RSYNC is in the input mode (RCR1.5=1).
4. RCHBLK is programmed to block Channel 24.
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DS2154
RECEIVE SIDE 2.048 MHz BOUNDARY TIMING
(WITH ELASTIC STORE ENABLED) Figure 13-4
NOTES:
1. RSYNC is in the output mode (RCR1.5=0).
2. RSYNC is in the input mode (RCR1.5=1).
3. RCHBLK is programmed to block Channel 1.
4. RSIG normally contains the CAS multiframe alignment nibble (0000) in Channel 1.
TRANSMIT SIDE TIMING Figure 13-5
NOTES:
1. TSYNC in the frame mode (TCR1.1=0).
2. TSYNC in the multiframe mode (TCR1.1=1).
3. TLINK is programmed to source only the Sa4 bit.
4. This diagram assumes both the CAS MF and the CRC4 begin with the align frame.
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DS2154
TRANSMIT SIDE BOUNDARY TIMING Figure 13-6
NOTES:
1. TSYNC is in the input mode (TCR1.0=0).
2. TSYNC is in the output mode (TCR1.0=1).
3. TCHBLK is programmed to block Channel 2.
4. TLINK is programmed to source the Sa4 bits.
5. The signaling data at TSIG during Channel 1 is normally overwritten in the transmit formatter with
the CAS multiframe alignment nibble (0000).
6. Shown is a non-align frame boundary.
TRANSMIT SIDE 1.544 MHz BOUNDARY TIMING
(WITH ELASTIC STORE ENABLED) Figure 13-7
NOTES:
1. TCHBLK is programmed to block Channel 23.
2. The F-bit position is ignored by the DS2154.
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DS2154
TRANSMIT SIDE 2.048 MHz (WITH ELASTIC STORE ENABLED) Figure 13-8
NOTE:
1. TCHBLK is programmed to block Channel 31.
G.802 TIMING Figure 13-9
NOTE:
1. RCHBLK or TCHBLK is programmed to pulse high during timeslots 1 to 15, 17 to 25, and during bit
1 of timeslot 26.
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DS2154
DS2154 SYNCHRONIZATION FLOWCHART Figure 13-10
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DS2154
DS2154 TRANSMIT DATA FLOW Figure 13-11
NOTES:
1. TCLK Should be tied to RCLK and TSYNC should be tied to RFSYNC for data to be properly
sourced from RSER.
2. Auto Remote Alarm if enabled will only overwrite bit 3 of timeslot 0 in the Non Align Frames if the
alarm needs to be sent.
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DS2154
14.0 A. C. AND D. C. CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground ......................................................................................................
...........................................................................................................................................................
-1.0V to +7.0V
Operating Temperature for DS2154L ..........................................................................................................
...........................................................................................................................................................
0°C to 70°C
Operating Temperature for DS2154LN .......................................................................................................
...........................................................................................................................................................
-40°C to +85°C
Storage Temperature ....................................................................................................................................
...........................................................................................................................................................
...........................................................................................................................................................
................................................................................................................................ -55°C to +125°C
Soldering Temperature .................................................................................................................................
...........................................................................................................................................................
...........................................................................................................................................................
260°C for 10 seconds
* This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operation sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC
(0°C to 70°C for DS2154L;
OPERATING CONDITIONS
-40°C to +85°C for DS2154LN)
PARAMETER
SYMBOL MIN
TYP
MAX
VDD+0.3
+0.8
UNITS NOTES
Logic 1
VIH
VIL
2.0
-0.3
4.75
V
V
Logic 0
Supply
VDD
5.25
V
1
CAPACITANCE
PARAMETER
(tA =25°C)
UNITS NOTES
SYMBOL MIN
TYP
MAX
Input Capacitance
Output Capacitance
CIN
5
7
pF
pF
COUT
(0°C to 70°C; VDD=5V ±=5% for DS2154L;
DC CHARACTERISTICS
PARAMETER
-40°C to +85°C; VDD=5V ±=5% for DS2154LN)
SYMBOL MIN
TYP
MAX
UNITS NOTES
Supply Current @ 5V
Input Leakage
IDD
75
mA
µA
µA
mA
2
3
4
IIL
ILO
IOH
-1.0
-1.0
+1.0
1.0
Output Leakage
Output Current (2.4V)
75 of 87
DS2154
Output Current (0.4V)
IOL
+4.0
mA
NOTES:
1. Applies to RVDD, TVDD, and DVDD.
2. TCLK=RCLK=TSYSCLK=RSYSCLK=2.048 MHz; outputs open circuited.
3. 0.0V < VIN < VDD.
4. Applied to INT when 3-stated.
76 of 87
DS2154
AC CHARACTERISTICS -
MULTIPLEXED PARALLEL
PORT (MUX=1)
(0°C to 70°C; VDD=5V ±=5% for DS2154L;
-40°C to +85°C; VDD=5V ±=5% for DS2154LN)
PARAMETER
SYMBOL MIN
TYP
MAX
UNITS NOTES
Cycle Time
tCYC
PWEL
PWEH
tR, tF
tRWH
tRWS
200
100
100
ns
ns
ns
ns
ns
ns
ns
Pulse Width, DS low or RD high
Pulse Width, DS high or RD low
Input Rise/Fall times
20
10
50
20
R/ W Hold Times
R/ W Set Up time before DS high
tCS
CS Set Up time before DS, WR , or RD
active
tCH
tDHR
tDHW
tASL
tAHL
tASD
0
ns
ns
ns
ns
ns
ns
CS Hold Time
Read Data Hold time
10
0
50
Write Data Hold time
Muxed Address valid to AS or ALE fall
Muxed Address Hold time
15
10
20
Delay time DS, WR or RD to AS or
ALE rise
Pulse Width AS or ALE high
PWASH
tASED
30
10
ns
ns
Delay time, AS or ALE to DS, WR or
RD
Output Data Delay time from DS or RD
tDDR
tDSW
20
50
80
ns
ns
Data Set Up time
See Figures 14-1 to 14-3 for details.
77 of 87
DS2154
(0°C to 70°C; VDD=5V ±=5% for DS2154L;
-40°C to +85°C; VDD=5V ±=5% for DS2154LN)
AC CHARACTERISTICS -
RECEIVE SIDE
PARAMETER
SYMBOL MIN
TYP
488
244
244
244
244
488
MAX
UNITS NOTES
RCLKO Period
tLP
ns
RCLKO Pulse Width
tLH
tLL
tLH
tCL
tCP
tCH
tCL
tSP
200
200
150
150
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
1
2
2
RCLKO Pulse Width
RCLKI Period
RCLKI Pulse Width
75
75
RSYSCLK Period
122
122
50
648
488
3
4
tSP
RSYSCLK Pulse Width
tSH
tSL
tSU
tPW
tSU
50
RSYNC Set Up to RSYSCLK Falling
RSYNC Pulse Width
20
tSH-5
50
RPOSI/RNEGI Set Up to RCLKI
Falling
20
RPOSI/RNEGI Hold From RCLKI
Falling
tHD
20
ns
RSYSCLK/RCLKI Rise and Fall Times
tR, tF
tDD
25
50
ns
ns
Delay RCLKO to RPOSO, RNEGO
Valid
Delay RCLK to RSER, RDATA, RSIG,
RLINK Valid
tD1
tD2
50
50
ns
ns
Delay RCLK to RCHCLK, RSYNC,
RCHBLK, RFSYNC, RLCLK
Delay RSYSCLK to RSER, RSIG Valid
tD3
tD4
50
50
ns
ns
Delay RSYSCLK to RCHCLK,
RCHBLK, RMSYNC, RSYNC
See Figures 14-4 to 14-6 for details.
NOTES:
1. Jitter attenuator enabled in the receive path.
2. Jitter attenuator disabled or enabled in the transmit path.
3. RSYSCLK=1.544 MHz.
4. RSYSCLK=2.048 MHz.
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DS2154
INTEL BUS READ AC TIMING (BTS=0/MUX=1) Figure 14-1
INTEL BUS WRITE AC TIMING (BTS=0/MUX=1) Figure 14-2
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DS2154
MOTOROLA BUS AC TIMING (BTS=1/MUX=1) Figure 14-3
RECEIVE SIDE AC TIMING Figure 14-4
NOTES:
1. RSYNC is in the output mode (RCR1.5=0).
2. RLCLK will only pulse high during Sa bit locations as defined in RCR2; no relationship between
RLCLK and RSYNC or RFSYNC is implied.
80 of 87
DS2154
(0°C to 70°C; VDD=5V ±=5% for DS2154L;
-40°C to +85°C; VDD=5V ±=5% for DS2154LN)
AC CHARACTERISTICS -
TRANSMIT SIDE
PARAMETER
SYMBOL MIN
TYP
MAX
UNITS NOTES
TCLK Period
tCP
488
ns
ns
ns
ns
ns
TCLK Pulse Width
tCH
tCL
tLP
tLH
tLL
tSP
tSP
tSH
tSL
tSU
75
75
TCLKI Period
488
TCLKI Pulse Width
75
75
TSYSCLK Period
122
122
50
648
448
ns
ns
ns
ns
ns
1
2
TSYSCLK Pulse Width
50
TSYNC or TSSYNC Set Up toTCLK or
TSYSCLK falling
20
tCH-5 or
tSH-5
TSYNC or TSSYNC Pulse Width
tPW
tSU
50
20
ns
ns
TSER, TSIG, TDATA, TLINK, TPOSI,
TNEGI Set Up to TCLK, TSYSCLK,
TCLKI Falling
TSER, TSIG, TDATA, TLINK, TPOSI,
TNEGI Hold from TCLK, TSYSCLK,
TCLKI Falling
tHD
20
ns
TCLK, TCLKI, or TSYSCLK Rise and
Fall Times
tR, tF
tDD
25
50
ns
ns
Delay TCLKO to TPOSO, TNEGO
Valid
Delay TCLK to TESO Valid
tD1
tD2
50
50
ns
ns
Delay TCLK to TCHBLK, TCHBLK,
TSYNC, TLCLK
Delay TSYSCLK to TCHCLK,
TCHBLK
tD3
75
ns
See Figures 14-7 to 14-9 for details.
NOTES:
1. TSYSCLK=1.544 MHz.
2. TSYSCLK=2.048 MHz.
81 of 87
DS2154
RECEIVE SYSTEM SIDE AC TIMING Figure 14-5
NOTES:
1. RSYNC is in the output mode (RCR1.5=0).
2. RSYNC is in the input mode (RCR1.5=1).
RECEIVE LINE INTERFACE AC TIMING Figure 14-6
82 of 87
DS2154
TRANSMIT SIDE AC TIMING Figure 14-7
NOTES:
1. TSYNC is in the output mode (TCR1.0=1).
2. TSYNC is in the input mode (TCR1.0=0).
3. TSER is sampled on the falling edge of TCLK when the transmit side elastic store is disabled.
4. TCHCLK and TCHBLK are synchronous with TCLK when the transmit side elastic store is disabled.
5. TLINK is only sampled during Sa bit locations as defined in TCR2; no relationship between
TLCLK/TLINK and TSYNC is implied.
83 of 87
DS2154
TRANSMIT SYSTEM SIDE AC TIMING Figure 14-8
NOTES:
1. TSER is only sampled on the falling edge of TSYSCLK when the transmit side elastic store is
enabled.
2. TCHCLK and TCHBLK are synchronous with TSYSCLK when the transmit side elastic store is
enabled.
TRANSMIT LINE INTERFACE SIDE AC TIMING Figure 14-9
84 of 87
DS2154
AC CHARACTERISTICS -
NON-MULTIPLEXED PARALLEL
PORT (MUX=0)
(0°C to 70°C; VDD=5V ±=5% for DS2154T;
-40°C to +85°C; VDD=5V ±=5% for DS2154TN)
PARAMETER
SYMBOL MIN
TYP
MAX
UNITS NOTES
t1
t2
t3
t4
t5
t6
t7
t8
t9
0
0
ns
Set Up Time for A0 to A7 Valid to CS
Active
ns
ns
ns
ns
ns
ns
ns
ns
Set Up Time for CS Active to either
RD , WR , or DS Active
75
20
Delay Time from either RD or DS
Active to Data Valid
0
Hold Time from either RD , WR , or DS
Inactive to CS Inactive
5
Hold Time from CS Inactive to Data
Bus 3-state
75
10
10
10
Wait Time from either WR or DS
Active to Latch Data
Data Set Up Time to either WR or DS
Inactive
Data Hold Time from either WR or DS
Inactive
Address Hold from either WR or DS
Inactive
See Figures 14-10 to 14-13 for details.
INTEL BUS READ AC TIMING (BTS=0/MUX=0) Figure 14-10
85 of 87
DS2154
INTEL BUS WRITE AC TIMING (BTS=0/MUX=0) Figure 14-11
MOTOROLA BUS READ AC TIMING (BTS=1/MUX=0) Figure 14-12
MOTOROLA BUS WRITE AC TIMING (BTS=1/MUX=0) Figure 14-13
86 of 87
DS2154
DS2154 100-PIN LQFP
PKG
DIM
A
100-PIN
DETAIL A
MIN
MAX
1.60
-
-
A1
A2
B
0.05
1.35
0.17
0.09
15.80
1.45
0.27
0.20
16.20
C
D
D1
E
14.00 BSC
15.80
16.20
E1
e
14.00 BSC
0.50 BSC
0.45 0.75
L
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