DS3647A [ETC]
;
| 型号： | DS3647A |
| 厂家： | 
ETC |
| 描述： |
|
| 文件： | 总8页 (文件大小：152K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
February 1986
DS3647A Quad TRI-STATE MOS Memory I/O Register
É
General Description
The DS3647A is a 4-bit I/O buffer register intended for use
in MOS memory systems. This circuit employs a fall-through
latch for data storage. This method of latching captures the
data in parallel with the output, thus eliminating the delays
encountered in other designs. This circuit uses Schottky-
clamped transistor logic for minimum propagation delay and
employs PNP input transistors so that input currents are
low, allowing a large fan-out for this circuit which is needed
in a memory system.
The DS3647A features TRI-STATE outputs. The ‘‘B’’ port
outputs are designed for use in bus organized data trans-
b
mission systems and can sink 80 mA and source 5.2 mA.
Data going from port ‘‘A’’ to port ‘‘B’’ and from ‘‘B’’ to port
‘‘A’’ is inverted in the DS3647A.
Features
Y
PNP inputs minimize loading
Y
Fall-through latch design
Two pins per bit are provided, and data transfer is bi-direc-
tional so that the register can handle both input and output
data. The direction of data flow is controlled through the
input enables. The latch control, when taken low, will cause
the register to hold the data present at that time and display
it at the outputs. Data can be latched into the register inde-
pendent of the output disables or EXPANSION input. Either
or both of the outputs may be taken to the high-impedance
state with the output disables. The EXPANSION pin dis-
ables both outputs to facilitate multiplexing with other I/O
registers on the same data lines.
Y
Propagation delay of only 15 ns
Y
TRI-STATE outputs
Y
EXPANSION control
Y
Bi-directional data flow
Y
TTL compatible
Y
Transmission line driver output
Logic and Connection Diagrams
Dual-In-Line Package
TL/F/8354–2
Top View
Order Number DS3647AD or DS3647AN
See NS Package Number D16C or N16A
TL/F/8354–1
TRI-STATEÉ is a registered trademark of National Semiconductor Corp.
C
1995 National Semiconductor Corporation
TL/F/8354
RRD-B30M105/Printed in U. S. A.
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Operating Conditions
Min
Max
Units
Supply Voltage (V
)
CC
4.5
5.5
V
Temperature (T )
A
a
Supply Voltage
7V
DS3647A
0
70
C
§
b
a
1.5V to 7V
Input Voltage
b
a
65 to 150 C
Storage Temperature Range
§
§
Maximum Power Dissipation* at 25 C
§
Molded Package
1476 mW
Lead Temperature (Soldering, 10 seconds)
300 C
§
*Derate molded package 10.0 mW/ C above 25 C.
§
§
Electrical Characteristics (Notes 2 and 3)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
V
V
Logic ‘‘1’’ Input Voltage
Logic ‘‘0’’ Input Voltage
Logic ‘‘1’’ Input Current
2.0
V
IN(1)
IN(0)
IN(1)
0.8
40
V
I
Latch, Disable Inputs
Expansion
0.1
0.2
0.2
0.4
mA
mA
mA
mA
mA
mA
mA
mA
V
80
e
e
e
e
V
V
5.5V, V
5.5V, V
5.5V
0.5V
CC
IN
A Ports, B Ports
Enable Inputs
100
200
b
b
b
b
I
Logic ‘‘0’’ Input Current
Input Clamp Voltage
Latch, Disable Inputs
Expansion
25
50
50
250
500
500
1.25
IN(0)
b
b
CC
IN
A Ports, B Ports
Enable, Inputs
b
b
b
0.1
0.6
e
e
eb
b
V
V
V
V
4.5V, I
4.5V, I
18 mA
1.2
CLAMP
CC
IN
Logic ‘‘0’’ Output Voltage
A Ports
e
20 mA
0.4
0.5
V
OL(A)
CC
OL
e
e
Logic ‘‘0’’ Output Voltage
B Ports
I
I
30 mA
50 mA
0.3
0.4
3.4
3.4
3.3
3.3
0.4
0.5
V
V
V
V
V
V
OL
e
V
V
V
V
4.5V
OL(B)
OH(A)
OH(B)
OS(A)
CC
OL
e
Logic ‘‘1’’ Output Voltage
A Ports
V
V
V
V
5V
3.0
2.5
2.9
2.4
CC
eb
eb
I
I
1 mA
OH
OH
e
e
e
4.5V
5V
CC
CC
CC
Logic ‘‘1’’ Output Voltage
B Ports
5.2 mA, (Note 4)
4.5V
Output Short-Circuit Current
A Port
e
e
e
e
b
b
b
I
V
V
4.5V to 5.5V, V
4.5V to 5.5V, V
0V, (Note 4)
0V, (Note 4)
50
70
80
120
180
mA
mA
CC
CC
OUT
Output Short-Circuit Current
B Port
b
b
b
I
I
120
OS(B)
CC
OUT
e
e
Exp 3V, A Ports 0V,
B Ports Open, All Other Pins 0V DS3647A
Power Supply Current
e
100
140
mA
mA
e
Enable A, Latch 3V, A Ports
0V, B Ports Open, All Other
e
DS3647A
70
105
e
Pins 0V
Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’
they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device
operation.
a
Note 2: Unless otherwise specified min/max limits apply across the 0 C to 70 C range. All typicals are given for V
e
e
5V and T 25 C.
A
§
§
§
CC
Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted.
Note 4: Only one output at a time should be shorted.
2
e
e
25 C)
Switching Characteristics (V
5V, T
§
CC
A
Symbol
Parameter
Conditions
Min
Typ
Max
Units
DATA TRANSFER B PORT TO A PORT
e
e
(Figures 1 and 4)
CL 50 pF, R
280X,
L
t
t
Propagation Delay to a Logic ‘‘0’’
Propagation Delay to a Logic ‘‘1’’
7.5
6.0
15
12
ns
ns
pd0
e
e
50 pF, R
L
C
L
280X,
pd1
(Figures 1 and 4)
A PORT CONTROL FROM OUTPUT DISABLE A INPUT
Delay to High Impedance from
t
LZ
t
HZ
t
ZL
t
ZH
(Figures 1 and 5)
(Figures 1 and 6)
(Figures 1 and 7)
(Figures 1 and 8)
13
14
10
25
20
20
15
35
ns
ns
ns
ns
Logic ‘‘0’’
Delay to High Impedance from
Logic ‘‘1’’
Delay to Logic ‘‘0’’ from High
Impedance
Delay to Logic ‘‘1’’ from High
Impedance
DATA TRANSFER A PORT TO B PORT, DS3647A
e
(Figures 2 and 4)
e
L
C
L
50 pF, R
100 X,
100 X,
t
Propagation Delay to a Logic ‘‘0’’
Propagation Delay to a Logic ‘‘1’’
6.5
8.0
12
15
ns
ns
pd0
pd1
e
e
50 pF, R
L
C
L
t
(Figures 2 and 4)
B PORT CONTROL FROM OUTPUT DISABLE B INPUT, DS3647A
Delay to High Impedance from
t
LZ
t
HZ
t
ZL
t
ZH
(Figures 2 and 5)
(Figures 2 and 6)
(Figures 2 and 7)
(Figures 2 and 8)
15
14
10
25
25
20
16
35
ns
ns
ns
ns
Logic ‘‘0’’
Delay to High Impedance from
Logic ‘‘1’’
Delay to Logic ‘‘0’’ from High
Impedance
Delay to Logic ‘‘1’’ from High
Impedance
LATCH SET-UP AND HOLD TIMES, ALL DEVICES
Set-Up Time of Data Input Before
t
5
0
5
ns
ns
SET-UP
HOLD
Latch Goes Low
Hold Time of Data Input After
Latch Goes Low
t
10
Product Description
B Port To A Port
Function
A Port To B Port
Function
Device Number
A Port Outputs
B Port Outputs
DS3647A
Inverting
Inverting
TRI-STATE
TRI-STATE
3
Truth Table
Input
Output
A Ports
A1-A4
B Ports
B1-B4
Enables
Disables
Latch
Expansion
Comments
A
1
0
1
B
0
1
0
A
B
0
0
0
1
1
0
0
0
0
0
0
0
Hi-Z
B
A
Data in on A, output to B
Data in on B, output to A
Hi-Z
A
Hi-Z
Data stored which is present
when latch goes low
0
1
0
x
1
0
1
x
0
x
x
x
0
0
1
x
0
1
0
x
0
0
0
1
B
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Data stored which is present
when latch goes low
Hi-Z
Hi-Z
Hi-Z
Both A and B in Hi-Z state,
Data in on A, may be latched
Both A and B in Hi-Z state,
Data in on B, may be latched
Both A and B in Hi-Z state
AC Test Circuits
TL/F/8354–3
TL/F/8354–4
FIGURE 1. A Port Load
FIGURE 2. B Port Load
TRI-STATE Disabled
Note 1: C includes probe and jig capacitance.
L
Operating Waveforms
Using TRI-STATE
TL/F/8354–6
TL/F/8354–5
*When the Input Enable makes a negative transition, the output will be indeterminate for a short duration. The negative transition of the Input Enable normally
occurs during a don’t-care timing state at the output.
4
Switching Time Waveforms
t
and t
pd1
pd0
TL/F/8354–7
s
e
e
e
e
50 X
OUT
Input Characteristics: f
1 MHz, t
t
F
5 ns (10% to 90% points), duty cycle
50%, Z
R
FIGURE 4
t
t
HZ
LZ
TL/F/8354–10
TL/F/8354–8
FIGURE 6
FIGURE 5
t
ZH
t
ZL
TL/F/8354–11
TL/F/8354–9
FIGURE 8
FIGURE 7
Schematic Diagram
TL/F/8354–12
Note. Data pins A1–A4 and B1–B4 consist of
an input and an output tied together.
5
Typical Application
The diagram below shows how the DS3647A can be used as a register capable of multiplexing data lines.
TL/F/8354–13
6
Physical Dimensions inches (millimeters)
Hermetic Dual-In-Line Package (D)
Order Number DS3647AD
NS Package D16C
7
Physical Dimensions inches (millimeters) (Continued)
Molded Dual-In-Line Package (N)
Order Number DS3647AN
NS Package N16A
LIFE SUPPORT POLICY
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DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
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systems which, (a) are intended for surgical implant
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failure to perform, when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
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