DS80C320ENG [ETC]
(434.89 k) ;
ETC 
DS80C320/DS80C323
DS80C320/DS80C323
High–Speed/Low–Power Micro
FEATURES
PIN ASSIGNMENT
• 80C32–Compatible
1
2
3
4
5
6
40
39
38
37
36
35
P1.0/T2
P1.1/T2EX
P1.2/RXD1
P1.3/TXD1
P1.4/INT2
P1.5/INT3
VCC
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
EA
–
–
–
–
–
8051 Pin and instruction set compatible
Four 8–bit I/O ports
Three 16–bit timer/counters
256 bytes scratchpad RAM
Addresses 64KB ROM and 64KB RAM
7
8
34
33
P1.6/INT4
P1.7/INT5
9
32
31
30
29
28
27
26
25
24
23
22
21
RST
P3.0/RXD0
P3.1/TXD0
P3.2/INT0
P3.3/INT1
• High–speed architecture
10
11
12
13
14
15
16
17
18
19
20
DALLAS
DS80C320
10580C323
–
–
–
–
–
–
–
4 clocks/machine cycle (8032=12)
ALE
PSEN
DC to 33 MHz (DS80C320)
DC to 18 MHz (DS80C323)
Single–cycle instruction in 121 ns
Uses less power for equivalent work
Dual data pointer
A15 (P2.7)
A14 (P2.6)
A13 (P2.5)
A12 (P2.4)
A11 (P2.3)
A10 (P2.2)
A9 (P2.1)
A8 (P2.0)
P3.4/T0
P3.5/T1
P3.6/WR
P3.7/RD
XTAL2
XTAL1
GND
Optional variable length MOVX to access fast/
slow RAM/peripherals
40–PIN DIP
1
• High integration controller includes:
–
–
–
Power–fail reset
6
40
Programmable Watchdog timer
Early–warning power–fail interrupt
7
39
• Two full–duplex hardware serial ports
DALLAS
DS80C320
10580C323
• 13 total interrupt sources with six external
• Available in 40–pin DIP, 44–pin PLCC and TQFP
17
29
DESCRIPTION
The DS80C320/DS80C323 is a fast 80C31/80C32–
compatible microcontroller. Wasted clock and memory
cycles have been removed using a redesigned proces-
sor core. As a result, every 8051 instruction is executed
between 1.5 and 3 times faster than the original for the
same crystal speed. Typical applications will see a
speed improvement of 2.5 times using the same code
and same crystal. The DS80C320/DS80C323 offers a
maximum crystal rate of 33 MHz, resulting in apparent
execution speeds of 82.5 MHz (approximately 2.5X).
18
28
23
44–PIN PLCC
33
34
44
22
12
DALLAS
DS80C320
1
11
44–PIN TQFP
ECopyright 1995 by Dallas Semiconductor Corporation.
All Rights Reserved. For important information regarding
patents and other intellectual property rights, please refer to
Dallas Semiconductor data books.
110196 1/38
DS80C320/DS80C323
The DS80C320/DS80C323 is pin compatible with all
three packages of the standard 80C32 and offers the
same timer/counters, serial port, and I/O ports. In short,
the device is extremely familiar to 8051 users but pro-
vides the speed of a 16–bit processor.
speed block data memory moves. It can also adjust the
speed of off–chip data memory access to between two
and nine machine cycles for flexibility in selecting
memory and peripherals.
The DS80C320 operating voltage ranges from 4.25V to
5.5V, making it ideal as a high–performance upgrade to
existing 5V systems. For applications in which power
consumption is critical, the DS80C323 offers the same
feature set as the DS80C320, but with 2.7V to 5.5V
operation.
The DS80C320 provides several extras in addition to
greater speed. These include a second full hardware
serial port, seven additional interrupts, programmable
watchdog timer, power–fail interrupt and reset. The
device also provides dual data pointers (DPTRs) to
ORDERING INFORMATION
PART NUMBER
DS80C320–MCG
DS80C320–QCG
DS80C320–ECG
DS80C320–MNG
DS80C320–QNG
DS80C320–ENG
DS80C320–MCL
DS80C320–QCL
DS80C320–ECL
DS80C320–MNL
DS80C320–QNL
DS80C320–ENL
PACKAGE
40–pin plastic DIP
44–pin PLCC
MAX CLOCK SPEED
25 MHz
TEMPERATURE RANGE
0°C to +70°C
25 MHz
0°C to +70°C
44–pin TQFP
25 MHz
0°C to +70°C
40–pin plastic DIP
44–pin PLCC
25 MHz
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
0°C to +70°C
25 MHz
44–pin TQFP
25 MHz
40–pin plastic DIP
44–pin PLCC
33 MHz
33 MHz
0°C to +70°C
44–pin TQFP
33 MHz
0°C to +70°C
40–pin plastic DIP
44–pin PLCC
33 MHz
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
33 MHz
44–pin TQFP
33 MHz
DS80C323–MCD 40–pin plastic DIP
DS80C323–QCD 44–pin PLCC
DS80C323–ECD 44–pin TQFP
18 MHz
18 MHz
18 MHz
0°C to 70°C
0°C to 70°C
0°C to 70°C
110196 2/38
DS80C320/DS80C323
DS80C320 BLOCK DIAGRAM Figure 1
ACCUMULATOR
ALU REG. 1
PSW
B REGISTER
ALU REG. 2
STACK POINTER
ALU
DPTR1
PC ADDR. REG.
BUFFER
INTERRUPT
LOGIC
ADDRESS BUS
256 BYTES
SFR 8 RAM
PC INCREMENT
PROG. COUNTER
DPTR0
INTERRUPT REG.
INSTRUCTION
DECODE
POWER CONTROL REG.
WATCHDOG REG.
CLOCKS AND
MEMORY CONTROL
RESET
V
POWER MONITOR
CC
CONTROL
OSCILLATOR
WATCHDOG TIMER
110196 3/38
DS80C320/DS80C323
PIN DESCRIPTION Table 1
SIGNAL
NAME
DIP
40
20
9
PLCC
44
TQFP
38
DESCRIPTION
V
CC
V
CC
– +5V.
22, 23
10
16, 17
4
GND
RST
GND – Digital circuit ground.
RST – Input. The RST input pin contains a schmitt voltage input to
recognize external active high Reset inputs. The pin also employs an
internal pull–down resistor to allow for a combination of wired OR
external Reset sources. An RC is not required for power–up, as the
device provides this function internally.
18
19
20
21
14
15
XTAL2
XTAL1
XTAL1, XTAL2 – The crystal oscillator pins XTAL1 and XTAL2 pro-
vide support for parallel resonant, AT cut crystals. XTAL1 acts also as
an input in the event that an external clock source is used in place of
a crystal. XTAL2 serves as the output of the crystal amplifier.
29
32
26
PSEN
PSEN – Output. The Program Store Enable output. This signal is
commonly connected to external ROM memory as a chip enable.
PSEN will provide an active low pulse width of 2.25 XTAL1 cycles
with a period of four XTAL1 cycles. PSEN is driven high when data
memory (RAM) is being accessed through the bus and during a reset
condition.
30
33
27
ALE
ALE– Output. TheAddressLatchEnableoutputfunctionsasaclock
to latch the external address LSB from the multiplexed address/data
bus. This signal is commonly connected to the latch enable of an
external 373 family transparent latch. ALE has a pulse width of 1.5
XTAL1 cycles and a period of four XTAL1 cycles. ALE is forced high
when the device is in a Reset condition.
39
38
37
36
35
34
33
32
43
42
41
40
39
38
37
36
37
36
35
34
33
32
31
30
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD0–7(Port 0) – I/O. Port0isthemultiplexedaddress/databus. Dur-
ing the time when ALE is high, the LSB of a memory address is pres-
ented. When ALE falls, the port transitions to a bidirectional data bus.
This bus is used to read external ROM and read/write external RAM
memory or peripherals. The Port 0 has no true port latch and can not
be written directly by software. The reset condition of Port 0 is high.
No pull–up resistors are needed.
1–8
2–9
40–44
1–3
P1.0–P1.7
Port1–I/O. Port1functionsasbothan8–bitbidirectionalI/Oportand
an alternate functional interface for Timer 2 I/O, new External Inter-
rupts, and new Serial Port 1. The reset condition of Port 1 is with all
bits at a logic 1. In this state, a weak pull–up holds the port high. This
condition also serves as an input mode, since any external circuit that
writes to the port will overcome the weak pull–up. When software
writes a 0 to any port pin, the device will activate a strong pull–down
that remains on until either a 1 is written or a reset occurs. Writing a
1 after the port has been at 0 will cause a strong transition driver to
turn on, followed by a weaker sustaining pull–up. Once the momen-
tary strong driver turns off, the port once again becomes the output
high (and input) state. The alternate modes of Port 1 are outlined as
follows:
Port
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
Alternate Function
T2
External I/O for Timer/Counter 2
Timer/Counter 2 Capture/Reload Trigger
Serial Port 1 Input
1
2
3
4
5
6
7
8
2
3
4
5
6
7
8
9
40
41
42
43
44
1
T2EX
RXD1
TXD1
INT2
INT3
INT4
INT5
Serial Port 1 Output
External Interrupt 2 (Positive Edge Detect)
External Interrupt 3 (Negative Edge Detect)
External Interrupt 4 (Positive Edge Detect)
External Interrupt 5 (Negative Edge Detect)
2
3
110196 4/38
DS80C320/DS80C323
SIGNAL
NAME
DIP
PLCC
TQFP
DESCRIPTION
21
22
23
24
25
26
27
28
24
25
26
27
28
29
30
31
18
19
20
21
22
23
24
25
A8 (P2.0)
A9 (P2.1)
A15–A8 (Port 2) – Output. Port 2 serves as the MSB for external
addressing. P2.7 is A15 and P2.0 is A8. The device will automatically
place the MSB of an address on P2 for external ROM and RAM
access. Although Port 2 can be accessed like an ordinary I/O port, the
value stored on the Port 2 latch will never be seen on the pins (due
to memory access). Therefore writing to Port 2, in software is only
useful for the instructions MOVX A, @Ri or MOVX @Ri, A. These
instructions use the Port 2 internal latch to supply the external
address MSB. In this case, the Port 2 latch value will be supplied as
the address information.
A10 (P2.2)
A11 (P2.3)
A12 (P2.4)
A13 (P2.5)
A14 (P2.6)
A15 (P2.7)
10–
17
11,
13–19
5, 7–13
P3.0–P3.7
Port3–I/O. Port3functionsasbothan8–bitbidirectionalI/Oportand
an alternate functional interface for External Interrupts, Serial Port 0,
Timer 0 & 1 Inputs, RD and WR strobes. The reset condition of Port
3 is with all bits at a logic 1. In this state, a weak pull–up holds the port
high. This condition also serves as an input mode, since any external
circuit that writes to the port will overcome the weak pull–up. When
software writes a 0 to any port pin, the device will activate a strong
pull–down that remains on until either a 1 is written or a reset occurs.
Writing a 1 after the port has been at 0 will cause a strong transition
driver to turn on, followed by a weaker sustaining pull–up. Once the
momentary strong driver turns off, the port once again becomes both
the output high and input state. The alternate modes of Port 3 are out-
lined below:
Port
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
Alternate Mode
RXD0
TXD0
INT0
INT1
T0
Serial Port 0 Input
Serial Port 0 Output
External Interrupt 0
External Interrupt 1
Timer 0 External Input
Timer 1 External Input
10
11
12
13
14
15
16
17
11
13
14
15
16
17
18
19
5
7
8
9
10
11
12
13
T1
WR
RD
External Data Memory Write Strobe
External Data Memory Read Strobe
31
35
29
EA
NC
EA – Input. This pin must be connected to ground for proper opera-
tion.
–
12
34
6
28
NC – Reserved. These pins should not be connected. They are
reserved for use with future devices in this family.
–
1
39
NC – Reserved. These pins are reserved for additional ground pins
on future products.
The DS80C320/DS80C323 runs the standard 8051
80C32 COMPATIBILITY
The DS80C320/DS80C323 is a CMOS 80C32 compat-
ible microcontroller designed for high performance. In
most cases it will drop into an existing 80C32 design to
significantly improve the operation. Every effort has
beenmadetokeepthedevicefamiliarto8032users, yet
it has many new features. In general, software written
for existing 80C32 based systems will work on the
DS80C320/DS80C323. The exception is critical timing
since the High–Speed Microcontroller performs its
instructionsmuch faster than the original. It may be nec-
essary to use memories with faster access times if the
same crystal frequency is used.
instruction set and is pin compatible with an 80C32 in
any of three standard packages. It also provides the
same timer/counter resources, full–duplex serial port,
256 bytes of scratchpad RAM and I/O ports as the stan-
dard 80C32. Timers will default to a 12 clock per cycle
operation to keep timing compatible with original 8051
systems. However, they can be programmed to run at
the new 4 clocks per cycle if desired.
New hardware features are accessed using Special
Function Registers that do not overlap with standard
80C32 locations. A summary of these SFRs is provided
below.
110196 5/38
DS80C320/DS80C323
The DS80C320/DS80C323 addresses memory in an
identical fashion to the standard 80C32. Electrical tim-
ing will appear different due to the high speed nature of
the product. However, the signals are essentially the
same. Detailed timing diagrams are provided below in
the electrical specifications.
This data sheet assumes the user is familiar with the
basic features of the standard 80C32. In addition to
these standard features, the DS80C320/DS80C323
includes many new functions. This data sheet provides
onlyasummaryandoverview. Detaileddescriptionsare
available in the High–Speed Microcontroller User’s
Guide.
COMPARATIVE TIMING OF THE DS80C320/DS80C323 AND 80C32 Figure 2
DS80C320/DS80C323 TIMING
SINGLE BYTE SINGLE CYCLE
INSTRUCTION
ALE
PSEN
AD7–AD0
PORT 2
XTAL1
ALE
PSEN
AD7–AD0
PORT 2
SINGLE BYTE SINGLE CYCLE
INSTRUCTION
STANDARD 80C32 TIMING
110196 6/38
DS80C320/DS80C323
below. However, counter/timers default to run at the
older 12 clocks per increment. Therefore, while soft-
wareruns at higher speed, timer–based events need no
modification to operate as before. Timers can be set to
run at 4 clocks per increment cycle to take advantage of
higher speed operation.
HIGH–SPEED OPERATION
The DS80C320/DS80C323 is built around a high speed
80C32 compatible core. Higher speed comes not just
from increasing the clock frequency, but from a newer,
more efficient design.
In this updated core, dummy memory cycles have been
eliminated. In a conventional 80C32, machine cycles
are generated by dividing the clock frequency by 12. In
the DS80C320/DS80C323, the same machine cycle is
performed in 4 clocks. Thus the fastest instruction, one
machine cycle, is executed three times faster for the
same crystal frequency. Note that these are identical
instructions. A comparison of the timing differences is
shown in Figure 2. The majority of instructions will see
the full 3 to 1 speed improvement. Some instructions
will get between 1.5 and 2.4 X improvement. Note that
all instructions are faster than the original 80C51.
Table 2 below shows a summary of the instruction set
including the speed.
The relative time of two instructions might be different in
the new architecture than it was previously. For exam-
ple, in the original architecture, the “MOVX A, @DPTR”
instruction and the “MOV direct, direct” instruction used
two machine cycles or 24 oscillator cycles. Therefore,
they required the same amount of time. In the
DS80C320/DS80C323, the MOVX instruction can be
done in two machine cycles or eight oscillator cycles but
the“MOVdirect, direct”usesthreemachinecyclesor12
oscillatorcycles. While both are faster than their original
counterparts, they now have different execution times
from each other. This is because in most cases, the
DS80C320/DS80C323 uses one cycle for each byte.
The user concerned with precise program timing should
examinethetimingofeachinstructionforfamiliaritywith
the changes. Note that a machine cycle now requires
just four clocks, and provides one ALE pulse per cycle.
Many instructions require only one cycle, but some
require five. In the original architecture, all were one or
two cycles except for MUL and DIV.
The numerical average of all opcodes is approximately
a 2.5 to 1 speed improvement. Individual programs will
be affected differently, depending on the actual instruc-
tions used. Speed sensitive applications would make
the most use of instructions that are three times faster.
However, the sheer number of 3 to 1 improved opcodes
makes dramatic speed improvements likely for any
code. When these architecture improvements are com-
bined with 0.8 µm CMOS, the result is a single cycle
instruction execution in 160 ns. The Dual Data Pointer
feature also allows the user to eliminate wasted instruc-
tions when moving blocks of memory.
INSTRUCTION SET SUMMARY Table 2
Legends:
A
Rn
direct
@Ri
–
–
–
–
Accumulator
Register R7–R0
Internal Register address
InternalRegisterpointed–tobyR0orR1
(except MOVX)
INSTRUCTION SET SUMMARY
All instructions in the DS80C320/DS80C323 perform
the same functions as their 80C32 counterparts. Their
affect on bits, flags, and other status functions is identi-
cal. However, the timing of each instruction is different.
This applies both in absolute and relative number of
clocks.
rel
bit
#data
#data 16
addr 16
addr 11
–
–
–
–
–
–
2’s complement offset byte
direct bit–address
8–bit constant
16–bit constant
16–bit destination address
11–bit destination address
For absolute timing of real–time events, the timing of
software loops will need to be calculated using the table
110196 7/38
DS80C320/DS80C323
OSCILLATOR
CYCLES
OSCILLATOR
CYCLES
INSTRUCTION
BYTE
INSTRUCTION
BYTE
Arithmetic Instructions:
ADD A, Rn
ADD A, direct
ADD A, @Ri
ADD A, #data
ADDC A, Rn
ADDC A, direct
ADDC A, @Ri
ADDC A, #data
SUBB A, Rn
1
2
1
2
1
2
1
2
1
2
1
2
4
8
4
8
4
8
4
8
4
8
4
8
INC A
INC Rn
1
1
2
1
1
1
1
2
1
1
1
1
4
4
8
4
12
4
4
8
4
INC direct
INC @Ri
INC DPTR
DEC A
DEC Rn
DEC direct
DEC @Ri
MUL AB
DIV AB
SUBB A, direct
SUBB A, @Ri
SUBB A, #data
20
20
4
DA A
Logical Instructions:
ANL A, Rn
ANL A, direct
ANL A, @Ri
ANL A, #data
ANL direct, A
ANL direct, #data
ORL A, Rn
ORL A, direct
ORL A, @Ri
1
2
1
2
2
3
1
2
1
2
2
3
4
8
4
8
8
12
4
8
4
8
XRL A, Rn
XRL A, direct
XRL A, @Ri
XRL A, #data
XRL direct, A
XRL direct, #data
CLR A
CPL A
RL A
RLC A
RR A
1
2
1
2
2
3
1
1
1
1
1
1
1
4
8
4
8
8
12
4
4
4
4
ORL A, #data
ORL direct, A
ORL direct, #data
8
12
4
4
4
RRC A
SWAP A
Data Transfer
Instructions:
MOV A, Rn
MOV A, direct
MOV A, @Ri
MOV A, #data
MOV Rn, A
MOV Rn, direct
MOV Rn, #data
MOV direct, A
MOV direct, Rn
MOV direct1, direct2
MOV direct, @Ri
MOV direct, #data
MOV @Ri, A
1
2
1
2
1
2
2
2
2
3
2
3
1
2
2
3
4
8
4
8
4
8
8
8
8
12
8
12
4
8
8
MOVC A, @A+DPTR
MOVC A, @A+PC
MOVX A, @Ri
MOVX A, @DPTR
MOVX @Ri, A
MOVX @DPTR, A
PUSH direct
POP direct
XCH A, Rn
XCH A, direct
XCH A, @Ri
1
1
1
1
1
1
2
2
1
2
1
1
12
12
8–36 *
8–36 *
8–36 *
8–36 *
8
8
4
8
4
4
XCHD A, @Ri
MOV @Ri, direct
MOV @Ri, #data
MOV DPTR, #data 16
12
*User Selectable
110196 8/38
DS80C320/DS80C323
Bit Manipulation
Instructions:
CLR C
1
2
1
2
1
2
4
8
4
8
4
8
ANL C, bit
ANL C, bit
ORL C, bit
ORL C, bit
MOV C, bit
MOV bit, C
2
2
2
2
2
2
8
8
8
8
8
8
CLR bit
SETB C
SETB bit
CPL C
CPL bit
Program Branching
Instructions:
ACALL addr 11
LCALL addr 16
RET
2
3
1
1
2
3
2
1
2
2
2
3
12
16
16
16
12
16
12
12
12
12
12
16
CJNE A, direct, rel
CJNE A, #data, rel
CJNE Rn, #data, rel
CJNE Ri, #data, rel
NOP
JC rel
JNC rel
JB bit, rel
JNB bit, rel
3
3
3
3
1
2
2
3
3
3
16
16
16
16
4
12
12
16
16
16
RETI
AJMP addr 11
LJMP addr 16
SJMP rel
JMP @A+DPTR
JZ rel
JNZ rel
DJNZ Rn, rel
DJNZ direct, rel
JBC bit, rel
The table above shows the speed for each class of
instruction. Note that many of the instructions have mul-
tiple opcodes. There are 255 opcodes for 111 instruc-
tions. Of the 255 opcodes, 159 are three times faster
than the original 80C32. While a system that empha-
sizes those instructions will see the most improvement,
the large total number that receive a 3 to 1 improvement
assure a dramatic speed increase for any system. The
speed improvement summary is provided below.
MEMORY ACCESS
The DS80C320/DS80C323 contains no on–chip ROM
and 256 bytes of scratchpad RAM. Off–chip memory is
accessed using the multiplexed address/data bus on
P0 and the MSB address on P2. A typical memory con-
nection is shown in Figure 3. Timing diagrams are pro-
vided in the Electrical Specifications. Program memory
(ROM) is accessed at a fixed rate determined by the
crystal frequency and the actual instructions. As men-
tioned above, an instruction cycle requires 4 clocks.
Data memory (RAM) is accessed according to a vari-
able speed MOVX instruction as described below.
SPEED ADVANTAGE SUMMARY
#Opcodes
Speed Improvement
159
51
43
2
3.0 x
1.5 x
2.0 x
2.4 x
255
Average: 2.5
110196 9/38
DS80C320/DS80C323
TYPICAL MEMORY CONNECTION Figure 3
PSEN
ALE
OE
27C256
32K x 8
EPROM
LSB ADDRESS
(8)
(8)
74F373
LATCH
PORT 1
AD0–AD7
DATA BUS
(8)
CE
(7)
DS80C320/
DS80C323
PORT 3
(8)
2K x 8
SRAM
P2.0–P2.7
MSB ADDRESS
(3)
CE
RD (P3.7)
WR (P3.6)
OE
WE
be performed at full speed. This is a convenience to
existing designs that may not have fast RAM in place.
When maximum speed is desired, the software should
select a Stretch value of zero. When using very slow
RAM or peripherals, a larger stretch value can be
selected. Note that this affects data memory only and
the only way to slow program memory (ROM) access is
to use a slower crystal.
STRETCH MEMORY CYCLE
The DS80C320/DS80C323 allows the application soft-
ware to adjust the speed of data memory access. The
microcontrolleriscapableofperformingtheMOVXinas
little as two instruction cycles. However, this value can
be stretched as needed so that both fast memory and
slow memory or peripherals can be accessed with no
glue logic. Even in high–speed systems, it may not be
necessary or desirable to perform data memory access
at full speed. In addition, there are a variety of memory
mapped peripherals such as LCD displays or UARTs
that are not fast.
Using a Stretch value between one and seven causes
the microcontroller to stretch the read/write strobe and
all related timing. This results in a wider read/write
strobe allowing more time for memory/peripherals to
respond. The timing of the variable speed MOVX is
shown in the Electrical Specifications. Note that full
speed access is not the reset default case. Table 3
below shows the resulting strobe widths for each
Stretch value. The memory stretch is implemented
using the Clock Control Special Function Register at
SFR location 8Eh. The stretch value is selected using
bits CKCON.2–0. In the table, these bits are referred to
as M2 through M0. The first stretch (default) allows the
use of common 120 ns or 150 ns RAMs withoutdramati-
cally lengthening the memory access.
The Stretch MOVX is controlled by the Clock Control
Register at SFR location 8Eh as described below. This
allows the user to select a stretch value between zero
and seven. A Stretch of zero will result in a two machine
cycle MOVX. A Stretch of seven will result in a MOVX of
nine machine cycles. Software can dynamically change
this value depending on the particular memory or
peripheral.
On reset, the Stretch value will default to a one resulting
in a three cycle MOVX. Therefore, RAM access will not
110196 10/38
DS80C320/DS80C323
DATA MEMORY CYCLE STRETCH VALUES Table 3
CKCON.2–0
MEMORY
CYCLES
RD or WR STROBE
WIDTH IN CLOCKS
STROBE WIDTH
TIME @ 25 MHz
MD2
MD1
MD0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2
2
4
8
12
16
20
24
28
80 ns
3 (default)
160 ns
320 ns
480 ns
640 ns
800 ns
960 ns
1120 ns
4
5
6
7
8
9
thesoftwaresimplyswitchesbetweenDPTRand1. The
relevant register locations are as follows.
DUAL DATA POINTER
Data memory block moves can be accelerated using
the Dual Data Pointer (DPTR). The standard 8032
DPTR is a 16–bit value that is used to address off–chip
dataRAM or peripherals. In the DS80C320/DS80C323,
the standard data pointer is called DPTR 0 and is
located at SFR addresses 82h and 83h. These are the
standard locations. No modification of standard code is
needed to use DPTR. The new DPTR is located at SFR
84h and 85h and is called DPTR1. The DPTR Select bit
(DPS) chooses the active pointer and is located at the
LSB of the SFR location 86h. No other bits in register
86h have any effect and are set to 0. The user switches
between data pointers by toggling the LSB of register
86h. The increment (INC) instruction is the fastest way
to accomplish this. All DPTR–related instructions use
the currently selected DPTR for any activity. Therefore
only one instruction is required to switch from a source
to a destination address. Using the Dual–Data Pointer
saves code from needing to save source and destina-
tion addresses when doing a block move. Once loaded,
DPL
82h
83h
84h
85h
86h
Low byte original DPTR
High byte original DPTR
Low byte new DPTR
High byte new DPTR
DPTR Select (LSB)
DPH
DPL1
DPH1
DPS
Sample code listed below illustrates the saving from
using the dual DPTR. The example program was origi-
nal code written for an 8051 and requires a total of 1869
machine cycles on the DS80C320/DS80C323. This
takes 299 µs to execute at 25 MHz. The new code using
the Dual DPTR requires only 1097 machine cycles tak-
ing 175.5 µs. The Dual DPTR saves 772 machine
cycles or 123.5 µs for a 64 byte block move. Since each
pass through the loop saves 12 machine cycles when
compared to the single DPTR approach, larger blocks
gain more efficiency using this feature.
64 BYTE BLOCK MOVE WITHOUT DUAL DATA POINTER
; SH and SL are high and low byte source address.
; DH and DL are high and low byte of destination address.
# CYCLES
MOV
MOV
MOV
MOV
MOV
MOV
R5, #64d
DPTR, #SHSL
R1, #SL
R2, #SH
R3, #DL
; NUMBER OF BYTES TO MOVE
; LOAD SOURCE ADDRESS
; SAVE LOW BYTE OF SOURCE
; SAVE HIGH BYTE OF SOURCE
; SAVE LOW BYTE OF DESTINATION
; SAVE HIGH BYTE OF DESTINATION
2
3
2
2
2
2
R4, #DH
MOVE:
; THIS LOOP IS PERFORMED THE NUMBER OF TIMES LOADED INTO R5, IN THIS EXAMPLE 64
MOVX
MOV
MOV
A, @DPTR
R1, DPL
R2, DPH
; READ SOURCE DATA BYTE
; SAVE NEW SOURCE POINTER
;
2
2
2
110196 11/38
DS80C320/DS80C323
MOV
MOV
MOVX
INC
MOV
MOV
MOV
MOV
INC
DJNZ
DPL, R3
; LOAD NEW DESTINATION
;
; WRITE DATA TO DESTINATION
; NEXT DESTINATION ADDRESS
; SAVE NEW DESTINATION POINTER
;
; GET NEW SOURCE POINTER
;
; NEXT SOURCE ADDRESS
; FINISHED WITH TABLE?
2
2
2
3
2
2
2
2
3
3
DPH, R4
@DPTR, A
DPTR
R3, DPL
R4, DPH
DPL, R1
DPH, R2
DPTR
R5, MOVE
64 BYTE BLOCK MOVE WITH DUAL DATA POINTER
; SH and SL are high and low byte source address.
; DH and DL are high and low byte of destination address.
; DPS is the data pointer select. Reset condition is DPS=0, DPTR0 is selected.
# CYCLES
EQU
DPS, #86h
; TELL ASSEMBLER ABOUT DPS
MOV
MOV
INC
MOV
R5, #64
DPTR, #DHDL
DPS
; NUMBER OF BYTES TO MOVE
; LOAD DESTINATION ADDRESS
; CHANGE ACTIVE DPTR
2
3
2
2
DPTR, #SHSL
; LOAD SOURCE ADDRESS
MOVE:
; THIS LOOP IS PERFORMED THE NUMBER OF TIMES LOADED INTO R5, IN THIS EXAMPLE 64
MOVX
INC
MOVX
INC
INC
INC
A, @DPTR
DPS
@DPTR, A
DPTR
DPS
DPTR
; READ SOURCE DATA BYTE
2
2
2
3
2
3
3
; CHANGE DPTR TO DESTINATION
; WRITE DATA TO DESTINATION
; NEXT DESTINATION ADDRESS
; CHANGE DATA POINTER TO SOURCE
; NEXT SOURCE ADDRESS
DJNZ
R5, MOVE
; FINISHED WITH TABLE?
The second serial port operates in a comparable man-
ner with the first. Both can operate simultaneously but,
can be at different baud rates.
PERIPHERAL OVERVIEW
Peripherals in the DS80C320/DS80C323 are accessed
using Special Function Registers (SFRs). The device
provides several of the most commonly needed periph-
eralfunctionsinmicrocomputer–basedsystems. These
functions are new to the 80C32 family and include a
second serial port, Power–fail Reset, Power–fail Inter-
rupt, and a programmable Watchdog Timer. These are
described below, and more details are available in the
High–Speed Microcontroller User’s Guide.
The second serial port has similar control registers
(SCON1 at C0h, SBUF1 at C1h) to the original. One dif-
ference is that for timer based baud rates, the original
serial port can use Timer 1 or Timer 2 to generate baud
rates. This is selected via SFR bits. The new serial port
can only use Timer 1.
TIMER RATE CONTROL
SERIAL PORTS
One important difference exists between the
DS80C320/DS80C323 and 80C32 regarding timers.
The original 80C32 used a 12 clock per cycle scheme
for timers and consequently for some serial baud rates
(depending on the mode). The DS80C320/DS80C323
architecture normally runs using 4 clocks per cycle.
However, in the area of timers, it will default to a 12 clock
The DS80C320/DS80C323 provides a serial port
(UART)thatisidenticaltothe80C32.Manyapplications
require serial communication with multiple devices.
Thereforeasecondhardwareserialportisprovidedthat
is a full duplicate of the standard one. It optionally uses
pins P1.2 (RXD1) and P1.3 (TXD1). This port has dupli-
cate control functions included in new SFR locations.
110196 12/38
DS80C320/DS80C323
per cycle scheme on a reset. This allows existing code
with real–time dependencies such as baud rates to
operate properly. If an application needs higher speed
timersorserialbaudrates, thetimerscanbesettorunat
the 4 clock rate.
Power–fail Interrupt (PFI). When enabled by the
application software, this interrupt always has the high-
est priority. On detecting that the V
has dropped
CC
below V
and that the PFI is enabled, the processor
PFW
will vector to ROM address 0033h. The PFI enable is
located in the Watchdog Control SFR (WDCON – D8h).
SettingWDCON.5toalogiconewillenablethePFI. The
application software can also read a flag at WDCON.4.
This bit is set when a PFI condition has occurred. The
flag is independent of the interrupt enable and software
must manually clear it.
The Clock Control register (CKCON – 8Eh) determines
these timer speeds. When the relevant CKCON bit is a
logic 1, the device uses 4 clocks per cycle to generate
timer speeds. When the control bit is set to a zero, the
deviceuses12clocksfortimerspeeds. Theresetcondi-
tion is a 0. CKCON.5 selects the speed of Timer 2.
CKCON.4 selects Timer 1 and CKCON.3 selects Timer
zero. Note that unless a user desires very fast timing, it
is unnecessary to alter these bits. Note that the timer
controls are independent.
WATCHDOG TIMER
For applications that can not afford to run out–of–con-
trol, the DS80C320/DS80C323 incorporates a pro-
grammable Watchdog Timer circuit. It resets the micro-
controller if software fails to reset the Watchdog before
the selected time interval has elapsed. The user selects
one of four time–out values. After enabling the Watch-
dog, software must reset the timer prior to expiration of
theinterval, or the CPU will be reset. Both the Watchdog
Enable and the Watchdog Reset bits are protected by a
“Timed Access” circuit. This prevents accidentally
clearing the Watchdog. Time–out values are precise
since they are related to the crystal frequency as shown
below in Table 4. For reference, the time periods at 25
MHz are also shown.
POWER FAIL RESET
The DS80C320/DS80C323 incorporates a precision
band–gap voltage reference to determine when V is
CC
out–of–tolerance. While powering up, internal circuits
will hold the device in a reset state until V rises above
CC
the V
reset threshold. Once V is above this level,
CC
RST
the oscillator will begin running. An internal reset circuit
will then count 65536 clocks to allow time for power and
the oscillator to stabilize. The microcontroller will then
exit the reset condition. No external components are
needed to generate a power on reset. During power–
downorduringaseverepowerglitch, asV fallsbelow
The Watchdog Timer also provides a useful option for
systems that may not require a reset. If enabled, then
512 clocks before giving a reset, the Watchdog will give
an interrupt. The interrupt can also serve as a conve-
nient time–base generator, or be used to wake–up the
processor from Idle mode. The Watchdog function is
controlled in the Clock Control (CKCON – 8Eh), Watch-
dog Control (WDCON – D8h), and Extended Interrupt
Enable(EIE – E8h) SFRs. CKCON.7andCKCON.6are
called WD1 and WD0 respectively and are used to
select the Watchdog time–out period as shown in
Table 4.
CC
V , the microcontroller will also generate its own
RST
reset. It will hold the reset condition as long as power
remains below the threshold. This reset will occur auto-
matically, needing no action from the user or from the
software. Refer to the Electrical Specifications for the
exact value of V
.
RST
POWER FAIL INTERRUPT
The same reference that generates a precision reset
threshold can also generate an optional early warning
WATCHDOG TIME–OUT VALUES Table 4
INTERRUPT
TIME–OUT
17
TIME
(@25 MHz)
RESET
TIME–OUT
17
TIME
(@25 MHz)
WD1
WD0
0
0
1
1
0
1
0
1
2
2
2
2
clocks
clocks
clocks
clocks
5.243 ms
41.94 ms
335.54 ms
2684.35 ms
2
2
2
2
+ 512 clocks
5.263 ms
41.96 ms
335.56 ms
2684.38 ms
20
23
26
20
23
26
+ 512 clocks
+ 512 clocks
+ 512 clocks
110196 13/38
DS80C320/DS80C323
As shown above, the Watchdog Timer uses the crystal
frequency as a time base. A user selects one of four
counter values to determine the time–out. These clock
tected by Timed Access discussed below. RWT
(WDCON.0) is the bit that software uses to restart the
Watchdog Timer. Setting this bit restarts the timer for
another full interval. Application software must set this
bit prior to the time–out. As mentioned previously, WD1
and0 (CKCON .7 and 6) select the time–out. Finally, the
Watchdog Interrupt is enabled using EWDI (EIE.4). The
Special Function Register map is shown below.
17
20
counter lengths are
2
= 131,072 clocks; 2
=
23
26
1,048,576; 2 = 8,388,608 clocks; or 2 = 67,108,864
clocks. The times shown in Table 4 above are with a
25 MHz crystal frequency. Note that once the counter
chain has reached a conclusion, the optional interrupt is
generated. Regardless of whether the user enables this
interrupt, there are then 512 clocks left until a reset
occurs. There are five control bits in special function
registers that affect the Watchdog Timer and two status
flags that report to the user.
INTERRUPTS
The DS80C320/DS80C323 provides 13 sources of
interrupt with three priority levels. The Power–fail Inter-
rupt (PFI), if enabled, always has the highest priority.
There are two remaining user selectable priorities: high
and low. If two interrupts that have the same priority
occur simultaneously, the natural precedence given
below determines which is a acted upon. Except for the
PFI, all interrupts that are new to the 8051 family have a
lower natural priority than the originals.
WDIF (WDCON.3) is the interrupt flag that is set when
there are 512 clocks remaining until a reset occurs.
WTRF (WDCON.2) is the flag that is set when a Watch-
dog reset has occurred. This allows the application soft-
ware to determine the source of a reset.
EWT (WDCON.1) is the enable for the WatchdogTimer.
Software sets this bit to enable the timer. The bit is pro-
INTERRUPT PRIORITY Table 5
NAME
DESCRIPTION
VECTOR
NATURAL PRIORITY
OLD/NEW
PFI
INT0
TF0
INT1
TF1
SCON0
TF2
SCON1
INT2
INT3
INT4
INT5
WDTI
Power Fail Interrupt
External Interrupt 0
Timer 0
External Interrupt 1
Timer 1
33h
03h
0Bh
13h
1Bh
23h
2Bh
3Bh
43h
4Bh
53h
5Bh
63h
1
2
3
4
5
6
7
8
9
10
11
12
13
NEW
OLD
OLD
OLD
OLD
OLD
OLD
NEW
NEW
NEW
NEW
NEW
NEW
TI0 or RI0 from serial port 0
Timer 2
TI1 or RI1 from serial port 1
External Interrupt 2
External Interrupt 3
External Interrupt 4
External Interrupt 5
Watchdog Time–out Interrupt
cally reduced. Since clocks are running, the Idle power
consumptionis related to crystal frequency. It should be
approximately 1/2 of the operational power. The CPU
can exit the Idle state with any interrupt or a reset.
POWER MANAGEMENT
The DS80C320/DS80C323 provides the standard Idle
and power–down (Stop) that are available on the stan-
dard 80C32. However the device has enhancements
that make these modes more useful, and allow more
power saving.
Thepower–downorStopmodeisinvokedbysettingthe
PCON.1 bit. Stop mode is a lower power state than Idle
The Idle mode is invoked by setting the LSB of the
Power Control register (PCON – 87h). Idle will leave
internal clocks, serial port and timer running. No
memory access will be performed so power is dramati-
since it turns off all internal clocking. The I of a stan-
CC
dardStop mode is approximately 1 µA but is specified in
the Electrical Specifications. The CPU will exit Stop
mode from an external interrupt or a reset condition.
110196 14/38
DS80C320/DS80C323
Note that internally generated interrupts (timer, serial
port, watchdog) are not useful since they require clock-
ing activity.
this bit has no control of the reference during full power
or Idle modes.
The second feature allows an additional power saving
option. This is the ability to start instantly when exiting
Stop mode. It is accomplished using an internal ring
oscillator that can be used when exiting Stop mode in
response to an interrupt. The benefit of the ring oscilla-
tor is as follows.
IDLE MODE ENHANCEMENTS
A simple enhancement to Idle mode makes it substan-
tially more useful. The innovation involves not the Idle
mode itself, but the watchdog timer. As mentioned
above, the Watchdog Timer provides an optional inter-
rupt capability. This interrupt can provide a periodic
interval timer to bring the DS80C320/DS80C323 out of
Idle mode. This can be useful even if the Watchdog is
notnormallyused. ByenablingtheWatchdogTimerand
its interrupt prior to invoking Idle, a user can periodically
comeoutofIdleperformanoperation, thenreturntoIdle
untilthe next operation. This will lower the overall power
consumption. When using the Watchdog Interrupt to
cancel the Idle state, make sure to restart the Watchdog
Timer or it will cause a reset.
Using Stop mode turns off the crystal oscillator and all
internal clocks to save power. This requires that the
oscillator be restarted when exiting Stop mode. Actual
start–up time is crystal dependent, but is normally at
least 4 ms. A common recommendation is 10 ms. In an
applicationthatwillwake–up, performashortoperation,
then return to sleep, the crystal start–up can be longer
than the real transaction. However, the ring oscillator
will start instantly. The user can perform a simple opera-
tion and return to sleep before the crystal has even sta-
bilized. If the ring is used to start and the processor
remains running, hardware will automatically switch to
the crystal once a power–on reset interval (65536
clocks)hasexpired. Thisvalueisusedtoguaranteesta-
bility even though power is not being cycled.
STOP MODE ENHANCEMENTS
The DS80C320/DS80C323 provides two enhance-
ments to the Stop mode. As documented above, the
device provides a band–gap reference to determine
Power–fail Interrupt and Reset thresholds. The default
state is that the band–gap reference is off when Stop
mode is invoked. This allows the extremely low power
statementioned above. A user can optionally choose to
have the band–gap enabled during Stop mode. This
means that PFI and power–fail reset will be activated
and are valid means for leaving Stop mode.
If the user returns to Stop mode prior to switching of
crystal, then all clocks will be turned off again. The ring
oscillator runs at approximately 4 MHz but will not be a
precision value. No real–time precision operations
(including serial communication) should be conducted
during this ring period. Figure 7 shows how the opera-
tion would compare when using the ring, and when
starting up normally. The default state is to come out of
Stop mode without using the ring oscillator.
In Stop mode with the band–gap on, I will be approxi-
CC
mately50µAcomparedwith1µAwiththeband–gapoff.
If a user does not require a Power–fail Reset or Interrupt
while in Stop mode, the band–gap can remain turned
off. Note that only the most power sensitive applications
shouldturnofftheband–gap,asthisresultsinanuncon-
trolled power down condition.
ThisfunctioniscontrolledusingtheRGSL– RingSelect
bit at EXIF.1 (EXIF – 91h). When EXIF.1 is set, the ring
oscillator will be used to come out of Stop mode quickly.
As mentioned above, the processor will automatically
switch from the ring (if enabled) to the crystal after a
delay of 65536 crystal clocks. For a 3.57 MHz crystal,
this is approximately 18 ms. The processor sets a flag
calledRGMD–RingModetotellsoftwarethattheringis
being used. This bit at EXIF.2 will be a logic 1 when the
ring is in use. No serial communication or precision tim-
ing should be attempted while this bit is set, since the
operating frequency is not precise.
The control of the band–gap reference is located in the
Extended Interrupt Flag register (EXIF – 91h). Setting
BGS (EXIF.0) to an one will leave the band–gap refer-
ence enabled during Stop mode. The default or reset
condition is with the bit at a logic 0. This results in the
band–gap being turned off during Stop mode. Note that
110196 15/38
DS80C320/DS80C323
RING OSCILLATOR START–UP Figure 4
STOP MODE WITHOUT RING STARTUP
4–10 ms
uC OPERATING
uC OPERATING
CRYSTAL
OSCILLATION
uC ENTERS
STOP MODE
INTERRUPT;
CLOCK STARTS
CLOCK
STABLE
uC ENTERS
STOP MODE
POWER
STOP MODE WITH RING STARTUP
uC OPERATING
CRYSTAL
OSCILLATION
uC OPERATING
RING
OSCILLATION
uC ENTERS
STOP MODE
INTERRUPT;
RING STARTS
uC ENTERS
STOP MODE
POWER SAVED
POWER
Diagram assumes that the operation following Stop requires less than 18 ms complete.
EXIF.0
BGS Band–gap Select
POR Power–on Reset flag
EWT Enable Watchdog
RWT Reset Watchdog
TIMED ACCESS PROTECTION
Selected SFR bits are critical to operation, making it
desirable to protect against an accidental write opera-
tion. The Timed Access procedure prevents an errant
cpufromaccidentallyalteringabitthatwouldcausediffi-
culty. The Timed Access procedure requires that the
write of a protected bit be preceded by the following
instructions :
WDCON.6
WDCON.1
WDCON.0
WDCON.3
WDIF Watchdog Interrupt Flag
SPECIAL FUNCTION REGISTERS
Most special features of the DS80C320/DS80C323 or
80C32arecontrolledbybitsinspecialfunctionregisters
(SFRs). This allows the device to add many features but
use the same instruction set. When writing software to
use a new feature, the SFR must be defined to an
assembler or compiler using an equate statement. This
is the only change needed to access the new function.
The DS80C320/DS80C323 duplicates the SFRs that
are contained in the standard 80C32. Table 6 shows the
registeraddresses and bit locations. Many are standard
80C32 registers. The High–Speed Microcontroller
User’s Guide describes all SFRs.
MOV
MOV
0C7h, #0AAh
0C7h, #55h
BywritinganAAhfollowedbya55htotheTimedAccess
register (location C7h), the hardware opens a two cycle
window that allows software to modify one of the pro-
tectedbits. Iftheinstructionthatseekstomodifythepro-
tected bit is not immediately proceeded by these
instructions, the write will not take effect. The protected
bits are:
110196 16/38
DS80C320/DS80C323
SPECIAL FUNCTION REGISTER LOCATIONS Table 6
REGISTER
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
ADDRESS
81h
SP
DPL
82h
DPH
83h
DPL1
DPH1
DPS
84h
85h
0
0
0
–
0
–
0
0
0
SEL
IDLE
IT0
86h
PCON
TCON
TMOD
TL0
SMOD_0
TF1
SMOD0
TR1
GF1
IE1
GF0
IT1
C/T
STOP
IE0
87h
TF0
M1
TR0
M0
88h
GATE
C/T
GATE
M1
M0
89h
8Ah
8Bh
8Ch
8Dh
8Eh
90h
TL1
TH0
TH1
CKCON
P1
WD1
P1.7
WD0
P1.6
T2M
P1.5
T1M
P1.4
T0M
P1.3
–
MD2
P1.2
MD1
P1.1
MD0
P1.0
BGS
RI_0
EXIF
IE5
IE4
IE3
IE2
RGMD
RB8_0
RGSL
TI_0
91h
SCON0
SBUF0
P2
SM0/FE_0
SM1_0
SM2_0
REN_0
TB8_0
98h
99h
P2.0
EA
P2.6
ES1
P2.5
ET2
P2.4
ES0
P2.3
ET1
P2.2
EX1
P2.1
ET0
P2.0
EX0
A0h
A8h
A9h
AAh
B0h
B8h
B9h
BAh
C0h
C1h
C5h
C7h
C8h
C9h
CAh
CBh
CCh
CDh
D0h
D8h
E0h
E8h
F0h
F8h
IE
SADDR0
SADDR1
P3
P3.7
–
P3.6
PS1
P3.5
PT2
P3.4
PS0
P3.3
PT1
P3.2
PX1
P3.1
PT0
P3.0
PX0
IP
SADEN0
SADEN1
SCON1
SBUF1
STATUS
TA
SM0/FE_0
SM1_0
SM2_0
REN_0
TB8_0
RB8_0
TI_0
RI_0
PIP
HIP
LIP
1
1
1
1
1
T2CON
T2MOD
RCAP2L
RCAP2H
TL2
TF2
–
EXF2
–
RCLK
–
TCLK
–
EXEN2
–
TR2
–
C/T2
CP/RL2
DCEN
T2OE
TH2
PSW
CY
AC
F0
RS1
RS0
OV
FL
P
WDCON
ACC
SMOD_1
POR
EPFI
PFI
WDIF
WTRF
EWT
RWT
EIE
–
–
–
–
–
–
EWDI
PWDI
EX5
PX5
EX4
PX4
EX3
PX3
EX2
PX2
B
EIP
110196 17/38
DS80C320/DS80C323
ELECTRICAL SPECIFICATIONS
VCC=+5V ± 10%; tA=0°C to 70°C
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground
Operating Temperature
–1.0V to +7.0V
–40°C to +85°C
–55°C to +125°C
Storage Temperature
Soldering Temperature
260°C for 10 seconds
* This is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods of time may affect reliability.
DC ELECTRICAL CHARACTERISTICS
(0°C to 70°C; VCC=4.0V to 5.5V)
PARAMETER
SYMBOL
MIN
4.5
TYP
5.0
MAX
5.5
UNITS
NOTES
Operating Supply Voltage
Power Fail Warning
V
CC
V
V
1
1
1
2
V
PFW
4.25
4.0
4.38
4.1
4.55
4.25
45
Minimum Operating Voltage
V
RST
V
Supply Current Active Mode
@ 25 MHz
I
30
mA
CC
Supply Current Idle Mode
@ 25 MHz
I
15
35
20
.01
50
25
mA
mA
mA
µA
3
2
IDLE
Supply Current Active Mode
@ 33 MHz
I
CC
Supply Current Idle Mode
@ 33 MHz
I
3
IDLE
Supply Current Stop Mode,
Band–gap Reference Disabled
I
1
4
STOP
Supply Current Stop Mode,
I
80
µA
4, 10
SPBG
Band–gap Reference Enabled
Input Low Level
V
–0.3
2.0
+0.8
V
V
1
1
IL
Input High Level (Except XTAL1
and RST)
V
IH1
V
V
+0.3
CC
Input High Level XTAL1 and RST
V
IH2
3.5
+0.3
V
V
1
1
CC
Output Low Voltage Ports 1, 3,
V
V
0.45
OL1
@I =1.6 mA
OL
Output Low Voltage Ports 0, 2,
0.45
V
V
1, 5
1, 6
1, 7
1, 5
OL2
OH1
OH2
OH3
ALE, PSEN @I =3.2 mA
OL
Output High Voltage Ports 1, 3,
ALE, PSEN, @I =–50 µA
V
V
V
2.4
2.4
2.4
OH
Output High Voltage Ports 1, 3,
V
@I =–1.5 mA
OH
Output High Voltage Ports 0, 2,
V
ALE, PSEN I =–8 mA
OH
Input Low Current Ports 1, 3,
@0.45V
I
–55
µA
µA
IL
Transition Current from 1 to 0
Ports 1, 3, @2V
I
TL
–650
8
9
Input Leakage Port 0, Bus Mode
RST Pull–down Resistance
I
–300
50
+300
170
µA
L
R
KΩ
RST
110196 18/38
DS80C320/DS80C323
NOTES FOR DC ELECTRICAL CHARACTERISTICS:
All parameters apply to both commercial and industrial temperature operation unless otherwise noted.
1. All voltages are referenced to ground.
2. Active current is measured with a 25 MHz clock source driving XTAL1, V =RST=5.5V, all other pins discon-
CC
nected.
3. Idle mode current is measured with a 25 MHz clock source driving XTAL1, V =5.5V, RST at ground, all
CC
other pins disconnected.
4. Stop mode current measured with XTAL1 and RST grounded, V =5.5V, all other pins disconnected.
CC
5. When addressing external memory.
6. RST=V . This condition mimics operation of pins in I/O mode.
CC
7. During a 0 to 1 transition, a one–shot drives the ports hard for two clock cycles. This measurement reflects
port in transition mode.
8. Ports 1, 2, and 3 source transition current when being pulled down externally. It reaches its maximum at
approximately 2V.
9. 0.45<V <V . Not a high impedance input. This port is a weak address holding latch because Port 0 is
IN
CC
dedicated as an address bus on the DS80C320. Peak current occurs near the input transition point of the
latch, approximately 2V.
10.Over the industrial temperature range, this specification has a maximum value of 200 µA.
TYPICAL ICC VERSUS FREQUENCY Figure 5
I
CC
@ 5V
mA
35
30
25
20
15
11
@ 3V
5
3
2
0
2
4
6
8
10 12
16
18 20
24
25
30
33 MHz XTAL
FREQUENCY
110196 19/38
DS80C320/DS80C323
AC ELECTRICAL CHARACTERISTICS
(0°C to 70°C; VCC=4.0V to 5.5V)
VARIABLE
CLOCK
MIN
VARIABLE
CLOCK
MAX
25 MHz
MIN
25 MHz
MAX
PARAMETER
SYMBOL
UNITS
MHz
ns
Oscillator Frequency
ALE Pulse Width
1/t
0
50
9
25
0
25
CLCL
LHLL
AVLL
t
t
1.5t
0.5t
–10
–11
CLCL
Port 0 Address Valid to ALE Low
Address Hold After ALE Low
ns
CLCL
t
t
5
note 5
73
0.25t –5
CLCL
note 5
ns
LLAX1
LLAX2
Address Hold After ALE Low for
MOVX WR
13
0.5t
–7
ns
CLCL
ALE Low to Valid Instruction In
ALE Low to PSEN Low
t
2.5t –27
CLCL
ns
ns
ns
ns
ns
ns
ns
ns
ns
LLIV
t
3
0.25t –7
CLCL
LLPL
PSEN Pulse Width
t
83
2.25t –7
CLCL
PLPH
PSEN Low to Valid Instr. In
Input Instruction Hold After PSEN
Input Instruction Float After PSEN
Port 0 Address to Valid Instr. In
Port 2 Address to Valid Instr. In
PSEN Low to Address Float
t
69
2.25t –21
CLCL
PLIV
PXIX
t
0
0
t
35
93
t
–5
PXIZ
CLCL
t
3t –27
CLCL
AVIV1
AVIV2
t
107
3.5t –33
CLCL
t
note 5
note 5
PLAZ
NOTES FOR AC ELECTRICAL CHARACTERISTICS:
All parameters apply to both commercial and industrial temperature range operation unless otherwise noted.
1. All signals rated over operating temperature at 25 MHz.
2. All signals characterized with load capacitance of 80 pF except Port 0, ALE, PSEN, RD and WR at 100 pF.
Note that loading should be approximately equal for valid timing.
3. Interfacing to memory devices with float times (turn off times) over 35 ns may cause contention. This will not
damage the parts, but will cause an increase in operating current.
4. Specifications assume a 50% duty cycle for the oscillator. Port 2 timing will change with the duty cycle varia-
tions.
5. Address is held in a weak latch until over driven by external memory.
110196 20/38
DS80C320/DS80C323
MOVX CHARACTERISTICS
(0°C to 70°C; VCC=4.0 to 5.5V)
VARIABLE CLOCK VARIABLE CLOCK
MIN MAX
PARAMETER
SYMBOL
UNITS
STRETCH
RD Pulse Width
t
2t
–11
–11
ns
t
t
=0
>0
RLRH
CLCL
MCS
MCS
t
MCS
WR Pulse Width
t
2t
–11
–11
ns
ns
t
t
=0
>0
WLWH
CLCL
MCS
MCS
t
MCS
RD Low to Valid Data In
t
2t
–25
–25
t
t
=0
>0
RLDV
CLCL
MCS
MCS
t
MCS
Data Hold After Read
Data Float After Read
t
0
ns
ns
RHDX
t
t
2t
–5
t
t
=0
>0
RHDZ
CLCL
MCS
MCS
–5
CLCL
ALE Low to Valid Data In
t
2.5t
–26
ns
ns
ns
ns
ns
ns
ns
ns
t
t
=0
>0
LLDV
CLCL
MCS
MCS
1.5t
–28+t
CLCL
MCS
Port 0 Address to Valid
Data In
t
t
3t
CLCL
–24
t
t
=0
>0
AVDV1
AVDV2
MCS
MCS
2t
–31+t
CLCL
MCS
Port 2 Address to Valid
Data In
3.5t
–32
t
t
=0
>0
CLCL
MCS
MCS
2.5t
–34+t
CLCL
MCS
ALE Low to RD or WR
Low
t
0.5t
1.5t
–5
–5
0.5t
1.5t
+6
+8
t
t
=0
>0
LLWL
CLCL
CLCL
CLCL
CLCL
MCS
MCS
Port 0 Address Valid to RD
or WR Low
t
t
t
2t
–9
–10
t
t
=0
>0
AVWL1
CLCL
CLCL
MCS
MCS
Port 2 Address Valid to RD
or WR Low
1.5t
–9
–13
t
t
=0
>0
AVWL2
CLCL
MCS
MCS
2.5t
CLCL
Data Valid to WR
Transition
t
–9
t
t
=0
>0
QVWX
MCS
MCS
t
–10
CLCL
Data Hold After Write
t
t
–7
–5
t
t
=0
>0
WHQX
CLCL
MCS
MCS
2t
CLCL
RD Low to Address Float
t
note 5
10
ns
ns
RLAZ
RD or WR High to ALE
High
t
0
CLCL
t
t
=0
>0
WHLH
MCS
MCS
t
–5
t
+11
CLCL
NOTE: t
is a time period related to the Stretch memory cycle selection. The following table shows the value of
MCS
t
for each Stretch selection.
MCS
M2
0
M1
0
M0
0
MOVX CYCLES
2 machine cycles
3 machine cycles (default)
4 machine cycles
5 machine cycles
6 machine cycles
7 machine cycles
8 machine cycles
9 machine cycles
t
MCS
0
0
0
1
4 t
CLCL
8 t
CLCL
0
1
0
0
1
1
12 t
16 t
20 t
24 t
28 t
CLCL
CLCL
CLCL
CLCL
CLCL
1
0
0
1
0
1
1
1
0
1
1
1
110196 21/38
DS80C320/DS80C323
AC ELECTRICAL CHARACTERISTICS UP TO 33 MHz
33 MHz
(0°C to 70°C; VCC=4.0V to 5.5V)
VARIABLE
CLOCK
MIN
VARIABLE
CLOCK
MAX
33 MHz
MAX
PARAMETER
SYMBOL
UNITS
MHz
ns
MIN
Oscillator Frequency
ALE Pulse Width
1/t
0
33
0
33
CLCL
LHLL
AVLL
t
t
35
4
1.5t –10
CLCL
Port 0 Address Valid to ALE Low
Address Hold After ALE Low
.5t –11
CLCL
ns
t
t
2
note 5
49
.25t –5
CLCL
note 5
ns
LLAX1
LLAX2
Address Hold After ALE Low for
MOVX WR
8
.5t
CLCL
–7
ns
ALE Low to Valid Instruction In
ALE Low to PSEN Low
t
2.5t
–27
ns
ns
ns
ns
ns
ns
ns
ns
ns
LLIV
CLCL
t
0.5
61
.25t –7
CLCL
LLPL
PSEN Pulse Width
t
2.25t –7
CLCL
PLPH
PSEN Low to Valid Instr. In
Input Instruction Hold After PSEN
Input Instruction Float After PSEN
Port 0 Address to Valid Instr. In
Port 2 Address to Valid Instr. In
PSEN Low to Address Float
t
48
2.25t
–21
CLCL
PLIV
PXIX
t
0
0
t
25
64
t
–5
PXIZ
CLCL
t
3t
CLCL
–27
AVIV1
AVIV2
t
73
3.5t
–33
CLCL
t
note 5
note 5
PLAZ
NOTES FOR AC ELECTRICAL CHARACTERISTICS:
All parameters apply to both commercial and industrial temperature range operation unless otherwise noted.
1. All signals rated over operating temperature at 33 MHz.
2. All signals characterized with load capacitance of 80 pF except Port 0, ALE, PSEN, RD and WR at 100 pF.
Note that loading should be approximately equal for valid timing.
3. Interfacing to memory devices with float times (turn off times) over 30 ns may cause contention. This will not
damage the parts, but will cause an increase in operating current.
4. Specifications assume a 50% duty cycle for the oscillator. Port 2 timing will change with the duty cycle varia-
tions.
5. Address is held in a weak latch until over driven by external memory.
110196 22/38
DS80C320/DS80C323
MOVX CHARACTERISTICS UP TO 33 MHz
(0°C to 70°C; VCC=4.0 to 5.5V)
VARIABLE CLOCK VARIABLE CLOCK
MIN MAX
PARAMETER
SYMBOL
UNITS
STRETCH
RD Pulse Width
t
2t
–11
–11
ns
t
t
=0
>0
RLRH
CLCL
MCS
MCS
t
MCS
WR Pulse Width
t
2t
–11
–11
ns
ns
t
t
=0
>0
WLWH
CLCL
MCS
MCS
t
MCS
RD Low to Valid Data In
t
2t
–25
–25
t
t
=0
>0
RLDV
CLCL
MCS
MCS
t
MCS
Data Hold After Read
Data Float After Read
t
0
ns
ns
RHDX
t
t
2t
–5
t
t
=0
>0
RHDZ
CLCL
MCS
MCS
–5
CLCL
ALE Low to Valid Data In
t
2.5t
–26
ns
ns
ns
ns
ns
ns
ns
ns
t
t
=0
>0
LLDV
CLCL
MCS
MCS
1.5t
–28+t
CLCL
MCS
Port 0 Address to Valid
Data In
t
t
3t
CLCL
–24
t
t
=0
>0
AVDV1
AVDV2
MCS
MCS
2t
–31+t
CLCL
MCS
Port 2 Address to Valid
Data In
3.5t
–32
t
t
=0
>0
CLCL
MCS
MCS
2.5t
–34+t
CLCL
MCS
ALE Low to RD or WR
Low
t
0.5t
1.5t
–5
–5
0.5t
1.5t
+6
+8
t
t
=0
>0
LLWL
CLCL
CLCL
CLCL
CLCL
MCS
MCS
Port 0 Address Valid to RD
or WR Low
t
t
t
2t
–9
–10
t
t
=0
>0
AVWL1
CLCL
CLCL
MCS
MCS
Port 2 Address Valid to RD
or WR Low
1.5t
–9
–13
t
t
=0
>0
AVWL2
CLCL
MCS
MCS
2.5t
CLCL
Data Valid to WR
Transition
t
–9
t
t
=0
>0
QVWX
MCS
MCS
t
–10
CLCL
Data Hold After Write
t
t
–7
–5
t
t
=0
>0
WHQX
CLCL
MCS
MCS
2t
CLCL
RD Low to Address Float
t
note 5
10
ns
ns
RLAZ
RD or WR High to ALE
High
t
0
CLCL
t
t
=0
>0
WHLH
MCS
MCS
t
–5
t
+11
CLCL
NOTE: t
is a time period related to the Stretch memory cycle selection. The following table shows the value of
MCS
t
for each Stretch selection.
MCS
M2
0
M1
0
M0
0
MOVX CYCLES
2 machine cycles
3 machine cycles (default)
4 machine cycles
5 machine cycles
6 machine cycles
7 machine cycles
8 machine cycles
9 machine cycles
t
MCS
0
0
0
1
4 t
CLCL
8 t
CLCL
0
1
0
0
1
1
12 t
16 t
20 t
24 t
28 t
CLCL
CLCL
CLCL
CLCL
CLCL
1
0
0
1
0
1
1
1
0
1
1
1
110196 23/38
DS80C320/DS80C323
DS80C323 DC ELECTRICAL CHARACTERISTICS
(0°C to 70°C; VCC=2.7V to 5.5V)
PARAMETER
SYMBOL
MIN
2.7
2.6
2.5
TYP
3.0
2.7
2.6
10
MAX
5.5
UNITS
NOTES
Operating Supply Voltage
Power Fail Warning
V
CC
V
V
1
1
1
2
V
PFW
2.8
Minimum Operating Voltage
V
RST
2.7
V
Supply Current Active Mode,
18 MHz
I
mA
CC
Supply Current Idle Mode,
18 MHz
I
6
mA
µA
µA
3
2
IDLE
Supply Current Stop Mode,
Band–gap Reference Disabled
I
0.1
40
STOP
SPBG
Supply Current Stop Mode,
I
4, 10
Band–gap Reference Enabled
Input Low Level
V
–0.3
0.2 V
V
V
1
1
IL
CC
Input High Level (Except XTAL1
and RST)
V
IH1
0.7 V
V
CC
+0.3
CC
Input High Level XTAL1 and RST
V
0.7 V
0.25V
+
V
CC
+0.3
V
V
1
IH2
CC
Output Low Voltage, Ports 1, 3
V
V
0.4
1
OL1
OL2
OH1
OH2
OH3
@I =1.6 mA
OL
Output Low Voltage, Ports 0, 2,
0.4
V
1, 5
1, 6
1, 7
1, 5
PSEN/ALE @I =3.2 mA
OL
Output High Voltage Ports 1, 2,
V
V
V
V
DD
–
V
PSEN/ALE, @I =–15 µA
0.4V
OH
Output High Voltage Ports 1, 3
V
DD
–
V
@I =–1.5 mA
0.4V
OH
Output High Voltage Ports 0, 2,
V
DD
–
V
PSEN/ALE I =–3 mA
0.4V
OH
Input Low Current Ports 1, 3
@0.45V
I
–30
µA
µA
IL
Transition Current from 1 > 0,
Ports 1, 3, @2V
I
TL
–400
8
9
Input Leakage Port 0, Bus Mode
RST Pull–down Resistance
I
–300
50
+300
170
µA
L
R
KΩ
RST
NOTES FOR DS80C323 DC ELECTRICAL CHARACTERISTICS:
All parameters apply to both commercial and industrial temperature operation unless otherwise noted.
1. All voltages are referenced to ground. Device operating range is 2.7V – 5.5V. DC Electrical specifications are
for operation 2.7V – 3.3V.
2. Active mode current is measured with a 18 MHz clock source driving XTAL1, V =RST=3.3V, all other pins
CC
disconnected.
3. Idle mode current is measured with a 18 MHz clock source driving XTAL1, V =3.3V, all other pins discon-
CC
nected.
4. Stop mode current measured with XTAL1 and RST grounded, V =3.3V, all other pins disconnected.
CC
5. When addressing external memory.
110196 24/38
DS80C320/DS80C323
6. RST=V . This condition mimics operation of pins in I/O mode.
CC
7. During a 0 to 1 transition, an one–shot drives the ports hard for two clock cycles. This measurement reflects
port in transition mode.
8. Ports 1, 2, and 3 source transition current when being pulled down externally. It reaches its maximum at
approximately 2V.
9. V between ground and V – 0.3V. Not a high impedance input. This port is a weak address latch because
IN
CC
Port 0 is dedicated as an address bus on the DS80C323. Peak current occurs near the input transition point
of the latch, approximately 2V.
10.Over the industrial temperature range, this specification has a maximum value of 200 µA.
110196 25/38
DS80C320/DS80C323
DS80C323 ELECTRICAL CHARACTERISTICS
(0°C to 70°C; VCC=2.7V to 5.5V)
VARIABLE
CLOCK
MIN
VARIABLE
CLOCK
MAX
18 MHz
MIN
18 MHz
MAX
PARAMETER
SYMBOL
UNITS
MHz
ns
Oscillator Frequency
ALE Pulse Width
1/t
0
18
0
18
CLCL
LHLL
AVLL
t
t
73
16
8
1.5t
0.5t
–10
–11
CLCL
Port 0 Address Valid to ALE Low
Address Hold After ALE Low
ns
CLCL
t
t
note 5
112
0.25t –5
CLCL
note 5
ns
LLAX1
LLAX2
Address Hold After ALE Low for
MOVX WR
20
0.5t
–7
ns
CLCL
ALE Low to Valid Instruction In
ALE Low to PSEN Low
t
2.5t –27
CLCL
ns
ns
ns
ns
ns
ns
ns
ns
ns
LLIV
t
6
0.25t –7
CLCL
LLPL
PSEN Pulse Width
t
118
2.25t –7
CLCL
PLPH
PSEN Low to Valid Instr. In
Input Instruction Hold After PSEN
Input Instruction Float After PSEN
Port 0 Address to Valid Instr. In
Port 2 Address to Valid Instr. In
PSEN Low to Address Float
t
104
2.25t –21
CLCL
PLIV
PXIX
t
0
0
t
51
140
t
–5
PXIZ
CLCL
t
3t –27
CLCL
AVIV1
AVIV2
t
162
3.5t –33
CLCL
t
note 5
note 5
PLAZ
NOTES FOR AC ELECTRICAL CHARACTERISTICS:
All parameters apply to both commercial and industrial temperature range operation unless otherwise noted.
1. All signals rated over operating temperature at 18 MHz.
2. All signals characterized with load capacitance of 80 pF except Port 0, ALE, PSEN, RD and WR at 100 pF.
Note that loading should be approximately equal for valid timing.
3. Interfacing to memory devices with float times (turn off times) over 35 ns may cause contention. This will not
damage the parts, but will cause an increase in operating current.
4. Specifications assume a 50% duty cycle for the oscillator. Port 2 timing will change with the duty cycle varia-
tions.
5. Address is held in a weak latch until over driven by external memory.
110196 26/38
DS80C320/DS80C323
DS80C323 MOVX CHARACTERISTICS
(0°C to 70°C; VCC=2.7V to 5.5V)
VARIABLE CLOCK VARIABLE CLOCK
MIN MAX
PARAMETER
SYMBOL
UNITS
STRETCH
RD Pulse Width
t
2t
–11
–11
ns
t
t
=0
>0
RLRH
CLCL
MCS
MCS
t
MCS
WR Pulse Width
t
2t
–11
–11
ns
ns
t
t
=0
>0
WLWH
CLCL
MCS
MCS
t
MCS
RD Low to Valid Data In
t
2t
–25
–25
t
t
=0
>0
RLDV
CLCL
MCS
MCS
t
MCS
Data Hold After Read
Data Float After Read
t
0
ns
ns
RHDX
t
t
2t
–5
t
t
=0
>0
RHDZ
CLCL
MCS
MCS
–5
CLCL
ALE Low to Valid Data In
t
2.5t
–26
ns
ns
ns
ns
ns
ns
ns
ns
t
t
=0
>0
LLDV
CLCL
MCS
MCS
1.5t
–28+t
CLCL
MCS
Port 0 Address to Valid
Data In
t
t
3t
CLCL
–24
t
t
=0
>0
AVDV1
AVDV2
MCS
MCS
2t
–31+t
CLCL
MCS
Port 2 Address to Valid
Data In
3.5t
–32
t
t
=0
>0
CLCL
MCS
MCS
2.5t
–34+t
CLCL
MCS
ALE Low to RD or WR
Low
t
0.5t
1.5t
–5
–5
0.5t
1.5t
+6
+8
t
t
=0
>0
LLWL
CLCL
CLCL
CLCL
CLCL
MCS
MCS
Port 0 Address Valid to RD
or WR Low
t
t
t
2t
–9
–10
t
t
=0
>0
AVWL1
CLCL
CLCL
MCS
MCS
Port 2 Address Valid to RD
or WR Low
1.5t
–9
–13
t
t
=0
>0
AVWL2
CLCL
MCS
MCS
2.5t
CLCL
Data Valid to WR
Transition
t
–9
t
t
=0
>0
QVWX
MCS
MCS
t
–10
CLCL
Data Hold After Write
t
t
–7
–5
t
t
=0
>0
WHQX
CLCL
MCS
MCS
2t
CLCL
RD Low to Address Float
t
note 5
10
ns
ns
RLAZ
RD or WR High to ALE
High
t
0
CLCL
t
t
=0
>0
WHLH
MCS
MCS
t
–5
t
+11
CLCL
NOTE: t
is a time period related to the Stretch memory cycle selection. The following table shows the value of
MCS
t
for each Stretch selection.
MCS
M2
0
M1
0
M0
0
MOVX CYCLES
2 machine cycles
3 machine cycles (default)
4 machine cycles
5 machine cycles
6 machine cycles
7 machine cycles
8 machine cycles
9 machine cycles
t
MCS
0
0
0
1
4 t
CLCL
8 t
CLCL
0
1
0
0
1
1
12 t
16 t
20 t
24 t
28 t
CLCL
CLCL
CLCL
CLCL
CLCL
1
0
0
1
0
1
1
1
0
1
1
1
110196 27/38
DS80C320/DS80C323
EXTERNAL CLOCK CHARACTERISTICS
(0°C to 70°C; VCC=4.0 to 5.5V)
PARAMETER
SYMBOL
MIN
10
TYP
MAX
UNITS
ns
NOTES
Clock High Time
Clock Low Time
Clock Rise Time
Clock Fall Time
t
CHCX
t
10
ns
CLCX
CLCH
CHCL
t
t
5
5
ns
ns
SERIAL PORT MODE 0 TIMING CHARACTERISTICS
(0°C to 70°C; VCC=4.0 to 5.5V)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Serial Port Clock Cycle Time
SM2=0 12 clocks per cycle
SM2=1 4 clocks per cycle
t
ns
XLXL
12t
4t
CLCL
CLCL
Output Data Setup to Clock
Rising Edge
SM2=0 12 clocks per cycle
SM2=1 4 clocks per cycle
t
t
ns
ns
QVXH
10t
3t
CLCL
CLCL
Output Data Hold from Clock
Rising
XHQX
SM2=0 12 clocks per cycle
SM2=1 4 clocks per cycle
2t
t
CLCL
CLCL
Input Data Hold after Clock Rising
SM2=0 12 clocks per cycle
SM2=1 4 clocks per cycle
t
t
ns
ns
XHDX
t
t
CLCL
CLCL
Clock Rising Edge to Input Data
Valid
XHDV
SM2=0 12 clocks per cycle
SM2=1 4 clocks per cycle
11t
3t
CLCL
CLCL
EXPLANATION OF AC SYMBOLS
In an effort to remain compatible with the original 8051
family, this device specifies the same parameter as
such devices, using the same symbols. For complete-
ness, the following is an explanation of the symbols.
L
I
Logic level low
Instruction
PSEN
Output data
RD signal
Valid
WR signal
No longer a valid logic level
Tristate
P
Q
R
V
W
X
Z
t
Time
A
C
D
H
Address
Clock
Input data
Logic level high
110196 28/38
DS80C320/DS80C323
POWER CYCLE TIMING CHARACTERISTICS
(0°C to 70°C; VCC=4.0 to 5.5V)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Crystal Start–up Time
Power–on Reset Delay
t
1.8
ms
1
2
CSU
POR
t
65536
t
CLCL
NOTES FOR POWER CYCLE TIMING CHARACTERISTICS:
1. Start–up time for crystals varies with load capacitance and manufacturer. Time shown is for an 11.0592 MHz
crystal manufactured by Fox crystal.
2. Reset delay is a synchronous counter of crystal oscillations after crystal start–up. At 25 MHz, this time is
2.62 ms.
PROGRAM MEMORY READ CYCLE
t
LHLL
t
LLIV
ALE
t
AVLL
t
PLPH
t
PLIV
PSEN
t
LLPL
t
t
PXIZ
PLAZ
t
PXIX
t
LLAX1
ADDRESS
A0–A7
INSTRUCTION
IN
ADDRESS
A0–A7
AD0–AD7
t
AVIV1
t
AVIV2
ADDRESS A8–A15 OUT
ADDRESS A8–A15 OUT
PORT 2
110196 29/38
DS80C320/DS80C323
DATA MEMORY READ CYCLE
t
LLDV
ALE
t
WHLH
t
t
LLWL
LLAX1
PSEN
RD
t
RLRH
t
RLDV
t
AVLL
t
RLAZ
t
RHDZ
t
RHDX
t
AVWL1
INSTRUCTION
ADDRESS
A0–A7
ADDRESS
A0–A7
DATA IN
AD0–AD7
IN
t
AVDV1
t
AVDV2
PORT 2
ADDRESS A8–A15 OUT
t
AVWL2
DATA MEMORY WRITE CYCLE
ALE
t
WHLH
t
LLWL
PSEN
WR
t
LLAX2
t
WLWH
t
AVLL
t
WHQX
INSTRUCTION
IN
ADDRESS
A0–A7
ADDRESS
A0–A7
DATA OUT
AD0–AD7
t
QVWX
t
AVWL1
PORT 2
ADDRESS A8–A15 OUT
t
AVWL2
110196 30/38
DS80C320/DS80C323
DATA MEMORY WRITE WITH STRETCH=1
Last Cycle of
Previous
Instruction
First
Machine
Cycle
Second
Machine
Cycle
Third
Machine
Cycle
Need
Instruction
Machine Cycle
MOVX Instruction
C1
C2
C3
C4
C1
C2
C3
C4
C1
C2
C3
C4
C1
C2
C3
C4
C1
C2
C3
C4
CLK
ALE
PSEN
WR
AD0–AD7
A0–A7
MOVX
Instruction
Address
D0–D7
A0–A7
D0–D7
Next
A0–A7
D0–D7
A0–A7
D0–D7
Next Instr.
Address
MOVX
Data
Address
MOVX Data
MOVX
Instruction
Instruction
Read
PORT 2
A8–A15
A8–A15
A8–A15
A8–A15
110196 31/38
DS80C320/DS80C323
DATA MEMORY WRITE WITH STRETCH=2
Last Cycle
of Previous
Instruction
First
Machine
Cycle
Second
Machine
Cycle
Third
Machine
Cycle
Fourth
Machine
Cycle
Need
Instruction
Machine
Cycle
MOVX Instruction
C1 C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4
C1 C2 C3 C4
C1 C2 C3 C4 C1 C2 C3 C4
CLK
ALE
PSEN
WR
D0–D7
A0–A7
D0–D7 A0–A7
D0–D7
A0–A7
D0–D7
A0–A7
AD0–AD7
MOVX
Instruction
Address
Next Instr.
Address
MOVX
Data
Address
MOVX Data
MOVX
Next
Instruction
Instruction
Read
PORT 2
A8–A15
A8–A15
A8–A15
A8–A15
FOUR CYCLE DATA MEMORY WRITE
STRETCH VALUE=2
EXTERNAL CLOCK DRIVE
t
CLCL
t
CHCX
XTAL1
t
t
CLCH
CHCL
t
CLCX
110196 32/38
DS80C320/DS80C323
SERIAL PORT MODE 0 TIMING
SERIAL PORT 0 (SYNCHRONOUS MODE)
HIGH SPEED OPERATION SM2=1=>TXD CLOCK=XTAL/4
ALE
PSEN
t
QVXL
D0
t
XHQX
WRITE TO SBUF
RXD
D1
D2
D3
D4
D5
D7
D8
DATA OUT
TRANSMIT
TXD
CLOCK
t
XLXL
TI
WRITE TO SCON
TO CLEAR RI
RXD
DATA IN
D0
D1
D2
D3
D4
D5
D7
D8
TXD
CLOCK
RECEIVE
t
t
XHDX
XHDV
RI
SERIAL PORT 0 (SYNCHRONOUS MODE)
SM2=0=>TXD CLOCK=XTAL/12
ALE
PSEN
1/(XTAL FREQ/12)
D1
WRITE TO SBUF
RXD
DATA OUT
D0
D6
D7
TXD
CLOCK
TI
WRITE TO SCON TO CLEAR RI
RXD DATA IN
D0
D1
D6
D7
TXD CLOCK
RI
110196 33/38
DS80C320/DS80C323
POWER CYCLE TIMING
V
V
CC
PFW
V
V
RST
SS
INTERRUPT
SERVICE ROUTINE
t
CSU
XTAL1
t
POR
INTERNAL RESET
110196 34/38
DS80C320/DS80C323
40–PIN PDIP (600 MIL)
ALL DIMENSIONS ARE IN INCHES.
PKG
DIM
A
40–PIN
MIN
MAX
0.200
–
–
A1
A2
b
0.015
0.140
0.014
0.008
1.980
0.600
0.530
0.090
0.115
0.600
0.160
0.022
0.012
2.085
0.625
0.555
0.110
0.145
0.700
c
D
E
E1
e
L
eB
56–G5000–000
110196 35/38
DS80C320/DS80C323
44–PIN TQFP
1
PKG
DIM
A
44–PIN
MIN
–
MAX
1.20
0.15
1.05
12.20
A1
A2
D
0.05
0.95
11.80
D1
E
10.00 BSC
11.80
12.20
E1
L
10.00 BSC
0.45
0.75
e
0.80 BSC
B
0.30
0.09
0.45
0.20
C
56–G4012–001
110196 36/38
DS80C320/DS80C323
44–PIN PLCC
PKG
DIM
A
44–PIN
MIN
MAX
0.180
0.120
–
0.165
0.090
0.020
0.026
0.013
0.009
0.042
0.685
0.650
0.590
0.685
0.650
0.590
A1
A2
B
0.033
0.021
0.012
0.048
0.695
0.656
0.630
0.695
0.656
0.630
B1
c
CH1
D
D1
D2
E
E1
E2
e1
N
0.050 BSC
0.44
–
56–G4003–001
110196 37/38
DS80C320/DS80C323
DATA SHEET REVISION SUMMARY
Thefollowing represent the key differences between 05/23/96 and 05/22/96 version of the DS80C320 data sheet and
between 05/23/96 and 03/27/95 version of the DS80C323 data sheet. Please review this summary carefully.
DS80C320:
1. Add DS80C323 Characteristics.
2. Change DS80C320 V
specification from 4.5V to 4.55V (PCN E62802).
PFW
3. Update DS80C320 33 MHz AC Characteristics.
DS80C323:
1. Delete Data Sheet. Contents moved to DS80C320/DS80C323.
DATA SHEET REVISION SUMMARY
The following represent the key differences between the 031096 and the 052296 version of the DS80C320 data
sheet. Please review this summary carefully.
1. Add Data Sheet Revision Summary.
The following represent the key differences between the 041895 and the 031096 version of the DS80C320 data
sheet. Please review this summary carefully.
1. Remove Port 0, Port 2 from V
specification (PCN B60802).
OH1
2. V
test specification clarified (RST = V ).
CC
OH1
3. Add t
marking to External Memory Read Cycle figure.
AVWL2
4. Correct TQFP drawing to read 44–pin TQFP.
5. Rotate page 1 TQFP illustration to match assembly specifications.
The following represent the key differences between the 103196 and the 041896 version of the DS80C320 data
sheet. Please review this summary carefully.
1. Update DS80C320 25 MHz AC Characteristics.
110196 38/38
相关型号：
DS80C320MCG
Microcontroller, 8-Bit, MROM, 8051 CPU, 25MHz, CMOS, PDIP40, 0.600 INCH, PLASTIC, DIP-40
MAXIM
DS80C320MNG
Microcontroller, 8-Bit, MROM, 8051 CPU, 25MHz, CMOS, PDIP40, 0.600 INCH, PLASTIC, DIP-40
MAXIM
DS80C323+ECD
Microcontroller, 8-Bit, MROM, 8051 CPU, 18MHz, CMOS, PQFP44, 10 X 10 MM, 1 MM HEIGHT, ROHS COMPLIANT, TQFP-44
MAXIM
DS80C323+END
Microcontroller, 8-Bit, MROM, 8051 CPU, 18MHz, CMOS, PQFP44, 10 X 10 MM, 1 MM HEIGHT, ROHS COMPLIANT, TQFP-44
MAXIM
DS80C323+MCD
Microcontroller, 8-Bit, MROM, 8051 CPU, 18MHz, CMOS, PDIP40, 0.600 INCH, ROHS COMPLIANT, PLASTIC, DIP-40
MAXIM
DS80C323+QCD
Microcontroller, 8-Bit, MROM, 8051 CPU, 18MHz, CMOS, PQCC44, ROHS COMPLIANT, PLASTIC, LCC-44
MAXIM
©2020 ICPDF网 联系我们和版权申明