DSP1629T10K19.2IR_技术文档

Data Sheet

January 2002

DSP1629 Digital Signal Processor

■ Supported by DSP1629 software and hardware

development tools.

1 Features

■ Optimized for mobile communications applications

with a bit manipulation unit for higher coding effi-

ciency.

2 Description

■ On-chip, programmable, PLL clock synthesizer.

The DSP1629 is Agere Systems Inc.’s first digital signal

processor offering 100 MIPS operation at 3.0 V and

80 MIPS operation at 2.7 V with a reduction in power

consumption. Designed specifically for applications re-

quiring low power dissipation in mobile communica-

tions systems, the DSP1629 is a signal-coding device

that can be programmed to perform a wide variety of

fixed-point signal processing functions. The device is

based on the DSP1600 core with a bit manipulation unit

for enhanced signal coding efficiency. The DSP1629 in-

cludes a mix of peripherals specifically intended to sup-

port processing-intensive but cost-sensitive

■ 10 ns and 16.7 ns instruction cycle times at 3.0 V,

and 19.2 ns and 12.5 ns instruction cycle times at

2.7 V.

■ Mask-programmable memory map option: the

DSP1629x16 features 16 Kwords on-chip dual-port

RAM. The DSP1629x10 features 10 Kwords on-

chip dual-port RAM. Both feature 48 Kwords on-

chip ROM with a secure option.

■ Low power consumption:

— <1.9 mW/MIPS typical at 2.7 V.

■ Flexible power management modes:

applications in the area of digital wireless communica-

tions.

— Standard sleep: 0.2 mW/MIPS at 2.7 V.

— Sleep with slow internal clock: 0.7 mW at 2.7 V.

— Hardware STOP (pin halts DSP): <20 µA.

The DSP1629x16 contains 16 Kwords of internal dual-

port RAM (DPRAM), which allows simultaneous access

to two RAM locations in a single instruction cycle. The

DSP1629x10 supports the use of 10 Kwords of

DPRAM. Both devices contain 48 Kwords of internal

ROM (IROM).

■ Mask-programmable clock options: small signal

and CMOS.

■ 100-TQFP package, providing excellent second-

level reliability.

■ Sequenced accesses to X and Y external memory.

■ Object code and pin compatible with the DSP1627.

■ Single-cycle squaring.

The DSP1629 is object code compatible with the

DSP1627 while providing more memory. The DSP1629

is pin compatible with the DSP1627. Note that TRST

(JTAG test reset) replaces a VDD pin.

■ 16 x 16-bit multiplication and 36-bit accumulation in

one instruction cycle.

The DSP1629 supports 2.7 V and 3.0 V operation and

features flexible power management modes. Several

control mechanisms achieve low-power operation, in-

cluding a STOP pin for placing the DSP into a fully stat-

ic, halted state, and a programmable power control

register used to power down unused on-chip I/O units.

These power management modes allow for trade-offs

between power reduction and wake-up latency require-

ments. During system standby, power consumption is

reduced to less than 20 µA.

■ Instruction cache for high-speed, program-efficient,

zero-overhead looping.

■ Dual 25 Mbits/s serial I/O ports with multiprocessor

capability:

— 16-bit data channel, 8-bit protocol channel.

■ 8-bit parallel host interface:

— Supports 8-bit or 16-bit transfers.

— Motorola^®or Intel^®compatible.

The on-chip clock synthesizer can be driven by an ex-

ternal clock whose frequency is a fraction of the instruc-

tion rate.

■ 8-bit control I/O interface.

■ 256 memory-mapped I/O ports.

The device is packaged in a 144-pin PBGA, a 100-pin

BQFP, or a 100-pin TQFP, and is available with 10 ns

and 16.7 ns instruction cycle times at 3.0 V, and 19.2 ns

and 12.5 ns instruction cycle times at 2.7 V.

■ IEEE ^®P1149.1 test port (JTAG boundary scan).

■ Full-speed in-circuit emulation hardware develop-

ment system on-chip.

Data Sheet

January 2002

DSP1629 Digital Signal Processor

Table of Contents

Page Contents

Contents

Page

1

2

3

4

Features.............................................................. 1

10.1 DSP Clock Generation

Description.......................................................... 1

Pin Information.................................................... 3

Hardware Architecture ........................................ 8

(3.0 V Operation) .................................... 77

10.2 Reset Circuit (3.0 V Operation)............... 78

10.3 Reset Synchronization (3.0 V Operation) 79

10.4 JTAG I/O Specifications

(3.0 V Operation) .................................... 80

10.5 Interrupt (3.0 V Operation)...................... 81

10.6 Bit Input/Output (BIO)

(3.0 V Operation) .................................... 82

10.7 External Memory Interface

(3.0 V Operation) .................................... 83

10.8 PHIF Specifications (3.0 V Operation).... 87

10.9 Serial I/O Specifications

4.1

4.2

4.3

4.4

4.5

4.6

4.7

4.8

4.9

DSP1629 Architectural Overview ............. 8

DSP1600 Core Architectural Overview .. 11

Interrupts and Trap................................. 12

Memory Maps and Wait-States .............. 17

External Memory Interface (EMI)............ 20

Bit Manipulation Unit (BMU) ................... 21

Serial I/O Units (SIOs)............................ 21

Parallel Host Interface (PHIF)................. 23

Bit Input/Output Unit (BIO)...................... 24

4.10 Timer ...................................................... 25

4.11 JTAG Test Port....................................... 25

4.12 Clock Synthesis...................................... 27

4.13 Power Management ............................... 30

Software Architecture ....................................... 37

(3.0 V Operation) .................................... 93

10.10 Multiprocessor Communication

(3.0 V Operation) .................................... 98

11 Timing Characteristics for 2.7 V Operation ....... 99

11.1 DSP Clock Generation

5

6

5.1

5.2

5.3

Instruction Set......................................... 37

Register Settings .................................... 46

Instruction Set Formats .......................... 56

(2.7 V Operation) .................................. 100

11.2 Reset Circuit (2.7 V Operation)............. 101

11.3 Reset Synchronization

(2.7 V Operation) .................................. 102

11.4 JTAG I/O Specifications

(2.7 V Operation) .................................. 103

11.5 Interrupt (2.7 V Operation).................... 104

11.6 Bit Input/Output (BIO)

Signal Descriptions ........................................... 62

6.1

6.2

6.3

6.4

System Interface..................................... 62

External Memory Interface ..................... 64

Serial Interface #1 .................................. 65

Parallel Host Interface or Serial

Interface #2 and Control I/O Interface .... 66

Control I/O Interface ............................... 66

JTAG Test Interface ............................... 67

(2.7 V Operation) .................................. 105

11.7 External Memory Interface

(2.7 V Operation) .................................. 106

11.8 PHIF Specifications (2.7 V Operation).. 110

11.9 Serial I/O Specifications

6.5

6.6

7

8

Mask-Programmable Options ........................... 68

7.1

7.2

7.3

Input Clock Options ................................ 68

Memory Map Options ............................. 68

ROM Security Options............................ 68

(2.7 V Operation) .................................. 116

11.10 Multiprocessor Communication

Device Characteristics...................................... 69

(2.7 V Operation) .................................. 121

12 Outline Diagrams ............................................ 122

12.1 100-Pin BQFP (Bumpered Quad

Flat Pack).............................................. 122

12.2 100-Pin TQFP (Thin Quad Flat Pack)... 123

12.3 144-Pin PBGA (Plastic Ball Grid Array) 124

8.1

8.2

8.3

8.4

Absolute Maximum Ratings.................... 69

Handling Precautions ............................. 69

Recommended Operating Conditions .... 69

Package Thermal Considerations .......... 70

9

Electrical Characteristics and Requirements .... 71

9.1 Power Dissipation................................... 74

10 Timing Characteristics for 3.0 V Operation....... 76

2

Agere Systems Inc.

Data Sheet

January 2002

DSP1629 Digital Signal Processor

3 Pin Information

V^SS

14

DD

V

88

87

SADD1

DB4

DB3

DB2

DB1

DB0

IO

15

16

17

DOEN1

86

85

PIN #1

IDENTIFIER

ZONE

OCK2/PCSN

DO2/PSTAT

SYNC2/PBSEL

ILD2/PIDS

OLD2/PODS

IBF2/PIBF

OBE2/POBE

ICK2/PB0

18

19

20

21

22

23

84

83

82

81

80

79

78

77

ERAMHI

V

DD

ERAMLO

EROM

24

25

26

27

DI2/PB1

RWN

V^SS

76

75

74

73

72

71

70

69

DSP1629

DOEN2/PB2

SADD2/PB3

TRST

EXM

AB15

AB14

28

29

30

V

DD

IOBIT0/PB4

IOBIT1/PB5

IOBIT2/PB6

IOBIT3/PB7

VEC3/IOBIT4

VEC2/IOBIT5

VEC1/IOBIT6

VEC0/IOBIT7

V^SS

31

32

AB13

AB12

AB11

AB10

AB9

33

34

35

68

67

66

AB8

36

37

AB7

65

64

V^SS

38

5-4218 (F).c

Figure 1. DSP1629 BQFP Pin Diagram

Agere Systems Inc.

3

Data Sheet

January 2002

DSP1629 Digital Signal Processor

3 Pin Information (continued)

1

V^SS

DB4

V^DD

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

2

SADD1

3

DB3

DOEN1

4

DB2

OCK2/PCSN

DO2/PSTAT

SYNC2/PBSEL

ILD2/PIDS

OLD2/PODS

IBF2/PIBF

OBE2/POBE

ICK2/PB0

DI2/PB1

5

DB1

6

DB0

7

IO

8

ERAMHI

V^DD

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

ERAMLO

EROM

RWN

V^SS

DSP1629

EXM

AB15

AB14

V^DD

DOEN2/PB2

SADD2/PB3

TRST

IOBIT0/PB4

IOBIT1/PB5

IOBIT2/PB6

IOBIT3/PB7

VEC3/IOBIT4

VEC2/IOBIT5

VEC1/IOBIT6

VEC0/IOBIT7

V^SS

AB13

AB12

AB11

AB10

AB9

AB8

AB7

V^SS

5-4219 (F).c

Figure 2. DSP1629 TQFP Pin Diagram

4

Agere Systems Inc.

Data Sheet

January 2002

DSP1629 Digital Signal Processor

3 Pin Information (continued)

1

2

3

4

5

6

7

8

9

10

11

12

A

B

C

D

E

F

G

H

J

K

L

M

V^SS

V^DD

V^DDA

V^SSA

SPARE PACKAGE BALLS

SHOULD BE TIED TO

SOFT GND OR SIG GND

5-5224 (C)

Note: Solder balls viewed through package.

Figure 3. 144-Pin Plastic Ball Grid Array (Top View)

Agere Systems Inc.

5

Data Sheet

January 2002

DSP1629 Digital Signal Processor

3 Pin Information (continued)

Functional descriptions of pins 1—100 are found in Section 6, Signal Descriptions. The functionality of CKI and CKI2

pins are mask-programmable (see Section 7, Mask-Programmable Options). Input levels on all I and I/O type pins

are designed to remain at full CMOS levels when not driven by the DSP.

Table 1. Pin Descriptions

PBGA Pin

BQFP Pin

TQFP Pin

Symbol

Type

Name/Function

B6, A6, B5, A5, 1, 2, 3, 4, 5, 7, 88, 89, 90, 91,

B4, A4, B3, A3, 8, 9, 10, 11, 92, 94, 95, 96,

B2, A2, A1, B1, 12, 15, 16, 17, 97, 98, 99, 2,

DB[15:0]

I/O* External Memory Data Bus 15—0.

C2, C1, C3, D1

18, 19

20

21

3, 4, 5, 6

D2

E1

7

8

IO

ERAMHI

O^†Data Address 0x4000 to 0x40FF I/O Enable.

O^†

Data Address 0x8000 to 0xFFFF External RAM

Enable.

O^†

E2

23

10

ERAMLO

Data Address 0x4100 to 0x7FFF External RAM

Enable.

O^†

I

F1

F2

G1

24

25

27

11

12

14

EROM

RWN

Program Address External ROM Enable.

Read/Write Not.

EXM

External ROM Enable.

G2, H1, H2, J1, 28, 29, 31, 32, 15, 16, 18, 19,

J2, K1, K2, L1, 33, 34, 35, 36, 20, 21, 22, 23,

L2, M1, K3, M2, 37, 40, 41, 42, 24, 27, 28, 29,

L3, M3, L4, M4 43, 44, 45, 46 30, 31, 32, 33

AB[15:0]

O* External Memory Address Bus 15—0.

L5

M5

L6

M6

L7

47

48

50

51

52

53

54

56

57

58

59

34

35

37

38

39

40

41

43

44

45

46

INT1

INT0

IACK

STOP

TRAP

RSTB

CKO

TCK

I

Vectored Interrupt 1.

Vectored Interrupt 0.

O* Interrupt Acknowledge.

STOP Input Clock.

I/O* Nonmaskable Program Trap/Breakpoint Indication.

I

M7

L8

I

O^†

I

I^‡

O^§

I^‡

Reset Bar.

Processor Clock Output.

JTAG Test Clock.

JTAG Test Mode Select.

JTAG Test Data Output.

JTAG Test Data Input.

Mask-Programmable Input Clock Option

M8

L9

TMS

TDO

TDI

M9

L10

CMOS

CKI

V^SSA

Small Signal

VAC

L11

M11

K10

L12

K11

K12

J11

61

62

65

66

67

68

69

70

71

72

73

48

49

52

53

54

55

56

57

58

59

60

CKI**

CKI2**

I

VCM

VEC0/IOBIT7 I/O* Vectored Interrupt Indication 0/Status/Control Bit 7.

VEC1/IOBIT6 I/O* Vectored Interrupt Indication 1/Status/Control Bit 6.

VEC2/IOBIT5 I/O* Vectored Interrupt Indication 2/Status/Control Bit 5.

VEC3/IOBIT4 I/O* Vectored Interrupt Indication 3/Status/Control Bit 4.

IOBIT3/PB7 I/O* Status/Control Bit 3/PHIF Data Bus Bit 7.

IOBIT2/PB6 I/O* Status/Control Bit 2/PHIF Data Bus Bit 6.

IOBIT1/PB5 I/O* Status/Control Bit 1/PHIF Data Bus Bit 5.

IOBIT0/PB4 I/O* Status/Control Bit 0/PHIF Data Bus Bit 4.

J12

H11

H12

G11

I^‡

TRST

JTAG Test Reset.

*

3-states when RSTB = 0, or by JTAG control.

†

‡

§

3-states when RSTB = 0 and INT0 = 1. Output = 1 when RSTB = 0 and INT0 = 0, except CKO, which is free-running.

Pull-up devices on input.

3-states by JTAG control.

** See Section 7, Mask-Programmable Options.

†† For SIO multiprocessor applications, add 5 kΩ external pull-up resistors to SADD1 and/or SADD2 for proper initialization.

6

Agere Systems Inc.

Data Sheet

January 2002

DSP1629 Digital Signal Processor

3 Pin Information (continued)

Functional descriptions of pins 1—100 are found in Section 6, Signal Descriptions.

Table 1. Pin Descriptions (continued)

PBGA Pin

G12

BQFP Pin TQFP Pin

Symbol

SADD2/PB3^††

Type

Name/Function

74

75

77

78

79

61

62

64

65

66

I/O* SIO2 Multiprocessor Address/PHIF Data Bus Bit 3.

F11

F12

E11

E12

DOEN2/PB2 I/O* SIO2 Data Output Enable/PHIF Data Bus Bit 2.

DI2/PB1

ICK2/PB0

I/O* SIO2 Data Input/PHIF Data Bus Bit 1.

I/O* SIO2 Input Clock/PHIF Data Bus Bit 0.

O* SIO2 Output Buffer Empty/PHIF Output Buffer

Empty.

OBE2/POBE

D11

D12

C11

C12

80

81

82

83

67

68

69

70

IBF2/PIBF

O* SIO2 Input Buffer Full/PHIF Input Buffer Full.

OLD2/PODS I/O* SIO2 Output Load/PHIF Output Data Strobe.

ILD2/PIDS I/O* SIO2 Input Load/PHIF Input Data Strobe.

SYNC2/PBSEL I/O* SIO2 Multiprocessor Synchronization/PHIF Byte

Select.

C10

B12

B11

A12

A11

B10

A10

B9

A9

B8

A8

B7

84

85

86

87

90

91

92

93

94

95

96

98

99

71

72

73

74

77

78

79

80

81

82

83

85

86

DO2/PSTAT I/O* SIO2 Data Output/PHIF Status Register Select.

OCK2/PCSN I/O* SIO2 Output Clock/PHIF Chip Select Not.

DOEN1

SADD1^††

SYNC1

DO1

I/O* SIO1 Data Output Enable.

I/O* SIO1 Multiprocessor Address.

I/O* SIO1 Multiprocessor Synchronization.

O* SIO1 Data Output.

OLD1

OCK1

ICK1

I/O* SIO1 Output Load.

I/O* SIO1 Output Clock.

I/O* SIO1 Input Clock.

ILD1

I/O* SIO1 Input Load.

DI1

I

SIO1 Data Input.

IBF1

O* SIO1 Input Buffer Full.

A7

OBE1

V^SS

O* SIO1 Output Buffer Empty.

D4, D5, D6, D7, 6, 14, 26, 93, 1, 13,

D8, E4, E5, E6, 38, 49, 64, 25, 36, 51,

E7, E8, E9, F4, 76, 89, 97 63, 76, 84

F5, F6, F7, F8,

P

Ground.

F9, G4, G5, G6,

G7, G8, G9, H4,

H5, H6, H7, H8,

H9, J4, J5, J6, J7,

J8, J9

C4, C5, C6, C7, 13, 22, 30, 100, 9, 17,

C8, D3, D9, D10, 39, 55, 88, 26, 42, 75,

V^DD

P

Power Supply.

E3, E10, F3, F10,

G3, G10, H3,

H10, J3, J10, K4,

K5, K6, K7, K8,

K9

100

87

M10

M12

C9

60

63

—

47

50

—

V^DDA

V^SSA

—

P

—

Analog Power Supply.

Analog Ground.

No Die Connect—Unused.

*

3-states when RSTB = 0, or by JTAG control.

†

‡

§

3-states when RSTB = 0 and INT0 = 1. Output = 1 when RSTB = 0 and INT0 = 0, except CKO, which is free-running.

Pull-up devices on input.

3-states by JTAG control.

** See Section 7, Mask-Programmable Options.

†† For SIO multiprocessor applications, add 5 kΩ external pull-up resistors to SADD1 and/or SADD2 for proper initialization.

Agere Systems Inc.

7

Data Sheet

DSP1629 Digital Signal Processor

4 Hardware Architecture

January 2002

space) and data memory (Y memory space). The

DSP1600 core automatically controls the EMUX. In-

structions can transparently reference external memory

from either set of internal buses. A sequencer allows a

single instruction to access both the X and the Y exter-

nal memory spaces.

The DSP1629 device is a 16-bit, fixed-point program-

mable digital signal processor (DSP). The DSP1629

consists of a DSP1600 core together with on-chip mem-

ory and peripherals. Added architectural features give

the DSP1629 high program efficiency for signal coding

applications.

Clock Synthesis

The DSP powers up with a 1X input clock (CKI/CKI2) as

the source for the processor clock. An on-chip clock

synthesizer (PLL) can also be used to generate the sys-

tem clock for the DSP, which will run at a frequency mul-

tiple of the input clock. The clock synthesizer is

deselected and powered down on reset. For low-power

operation, an internally generated slow clock can be

used to drive the DSP. If both the clock synthesizer and

the internally generated slow clock are selected, the

slow clock will drive the DSP; however, the synthesizer

will continue to run.

4.1 DSP1629 Architectural Overview

Figure 4, DSP1629 Block Diagram, shows a block dia-

gram of the DSP1629. The following modules make up

the DSP1629.

DSP1600 Core

The DSP1600 core is the heart of the DSP1629 chip.

The core contains data and address arithmetic units,

and control for on-chip memory and peripherals. The

core provides support for external memory wait-states

and on-chip, dual-port RAM, and features vectored in-

terrupts and a trap mechanism.

The clock synthesizer and other programmable clock

sources are discussed in Section 4.12, Clock Synthesis.

The use of these programmable clock sources for pow-

er management is discussed in Section 4.13, Power

Management.

Dual-Port RAM (DPRAM)

The DSP1629x16 contains 16 banks of zero wait-state

memory and the DSP1629x10 contains 10 banks of

zero wait-state memory. Each bank consists of 1K

16-bit words and has separate address and data ports

to the instruction/coefficient and data memory spaces.

A program can reference memory from either space.

The DSP1600 core automatically performs the required

multiplexing. If references to both ports of a single bank

are made simultaneously, the DSP1600 core automati-

cally inserts a wait-state and performs the data port ac-

cess first, followed by the instruction/coefficient port

access.

Bit Manipulation Unit (BMU)

The BMU extends the DSP1600 core instruction set to

provide more efficient bit operations on accumulators.

The BMU contains logic for barrel shifting, normaliza-

tion, and bit field insertion/extraction. The unit also con-

tains a set of 36-bit alternate accumulators. The data in

the alternate accumulators can be shuffled with the data

in the main accumulators. Flags returned by the BMU

mesh seamlessly with the DSP1600 conditional instruc-

tions.

Bit Input/Output (BIO)

A program can be downloaded from slow, off-chip mem-

ory into DPRAM, and then executed without wait-states.

DPRAM is also useful for improving convolution perfor-

mance in cases where the coefficients are adaptive.

Since DPRAM can be downloaded through the JTAG

port, full-speed remote in-circuit emulation is possible.

DPRAM can also be used for downloading self-test

code via the JTAG port.

The BIO provides convenient and efficient monitoring

and control of eight individually configurable pins. When

configured as outputs, the pins can be individually set,

cleared, or toggled. When configured as inputs, individ-

ual pins or combinations of pins can be tested for pat-

terns. Flags returned by the BIO mesh seamlessly with

conditional instructions.

Read-Only Memory (ROM)

Serial Input/Output Units (SIO and SIO2)

The DSP1629 contains 48K 16-bit words of zero wait-

state, mask-programmable ROM for program and fixed

coefficients.

SIO and SIO2 offer asynchronous, full-duplex, double-

buffered channels that operate at up to 25 Mbits/s (for a

20 ns instruction cycle in a nonmultiprocessor configu-

ration), and easily interface with other Agere Systems’

fixed-point DSPs in a multiple-processor environment.

Commercially available codecs and time-division multi-

plex (TDM) channels can be interfaced to the serial I/O

ports with few, if any, additional components. SIO2 is

identical to SIO.

External Memory Multiplexer (EMUX)

The EMUX is used to connect the DSP1629 to external

memory and I/O devices. It supports read/write opera-

tions from/to instruction/coefficient memory (X memory

8

Agere Systems Inc.

Data Sheet

January 2002

DSP1629 Digital Signal Processor

4 Hardware Architecture (continued)

An 8-bit serial protocol channel may be transmitted in addition to the address of the called processor in multiproces-

sor mode. This feature is useful for transmitting high-level framing information or for error detection and correction.

SIO2 and BIO are pin-multiplexed with the PHIF.

DB[15:0] AB[15:0]

RWN

EXM

I/O

EROM ERAMHI

ERAMLO

JTAG

*

BOUNDARY SCAN

EXTERNAL MEMORY INTERFACE & EMUX

ioc

TDO

TDI

jtag

*

JCON

TCK

TMS

*

ID

DUAL-PORT

RAM

ROM

48K x 16

16K/10K x 16^†

*

BYPASS

HDS

TRST

*

BREAKPOINT

CKI

CKI2

CKO

RSTB

STOP

TRAP

INT[1:0]

IACK

YAB YDB XDB XAB

DSP1600 CORE

IDB

BMU

aa0

*

TRACE

aa1

ar0

ar1

ar2

ar3

TIMER

timerc

timer0

SIO

DI1

VEC[3:0] OR IOBIT[7:4]

DO2 OR PSTAT

OLD2 OR PODS

OCK2 OR PCSN

OBE2 OR POBE

SYNC2 OR PBSEL

ICK2 OR PB0

PHIF

phifc

ICK1

sdx(OUT)

ILD1

srta

tdms

IBF1

*

PSTAT

powerc

DO1

pllc

SIO2

M

U

X

pdx0(IN)

OCK1

OLD1

OBE1

SYNC1

SADD1

DOEN1

sdx2(OUT)

pdx0(OUT)

sdx(IN)

ILD2 OR PIDS

BIO

sbit

srta2

tdms2

DI2 OR PB1

sioc

IBF2 OR PIBF

cbit

DOEN2 OR PB2

SADD2 OR PB3

IO BIT[3:0] OR PB[7:4]

sdx2(IN)

sioc2

saddx

saddx2

5-4142 (F).f

*

These registers are accessible through the pins only.

†

16K x 16 for the DSP1629x16, 10K x 16 for the DSP1629x10.

Figure 4. DSP1629 Block Diagram

Agere Systems Inc.

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Data Sheet

January 2002

DSP1629 Digital Signal Processor

4 Hardware Architecture (continued)

Table 2. DSP1629 Block Diagram Legend

Symbol

Name

aa<0—1>

ar<0—3>

BIO

Alternate Accumulators.

Auxiliary BMU Registers.

Bit Input/Output Unit.

BMU

Bit Manipulation Unit.

BREAKPOINT

BYPASS

cbit

Four Instruction Breakpoint Registers.

JTAG Bypass Register.

Control Register for BIO.

Dual-Port RAM

EMUX

HDS

Internal RAM (16 Kwords for DSP1629x16, 10 Kwords for DSP1629x10).

External Memory Multiplexer.

Hardware Development System.

JTAG Device Identification Register.

Internal Data Bus.

ID

IDB

ioc

I/O Configuration Register.

JCON

jtag

JTAG Configuration Registers.

16-bit Serial/Parallel Register.

pdx0(in)

pdx0(out)

PHIF

Parallel Data Transmit Input Register 0.

Parallel Data Transmit Output Register 0.

Parallel Host Interface.

phifc

pllc

Parallel Host Interface Control Register.

Phase-Locked Loop Control Register.

Power Control Register.

Parallel Host Interface Status Register.

Multiprocessor Protocol Register.

Multiprocessor Protocol Register for SIO2.

Status Register for BIO.

powerc

PSTAT

saddx

saddx2

sbit

sdx(in)

sdx2(in)

sdx(out)

sdx2(out)

SIO

Serial Data Transmit Input Register.

Serial Data Transmit Input Register for SIO2.

Serial Data Transmit Output Register.

Serial Data Transmit Output Register for SIO2.

Serial Input/Output Unit.

SIO2

Serial Input/Output Unit #2.

sioc

Serial I/O Control Register.

sioc2

srta

srta2

tdms

tdms2

TIMER

timer0

timerc

TRACE

XAB

Serial I/O Control Register for SIO2.

Serial Receive/Transmit Address Register.

Serial Receive/Transmit Address Register for SIO2.

Serial I/O Time-division Multiplex Signal Control Register.

Serial I/O Time-division Multiplex Signal Control Register for SIO2.

Programmable Timer.

Timer Running Count Register.

Timer Control Register.

Program Discontinuity Trace Buffer.

Program Memory Address Bus.

XDB

Program Memory Data Bus.

YAB

Data Memory Address Bus.

YDB

Data Memory Data Bus.

10

Agere Systems Inc.

Data Sheet

January 2002

DSP1629 Digital Signal Processor

breakpoint will cause all the other processors to be

trapped (see Section 4.3, Interrupts and Trap).

4 Hardware Architecture (continued)

Parallel Host Interface (PHIF)

Pin Multiplexing

The PHIF is a passive, 8-bit parallel port which can in-

terface to an 8-bit bus containing other Agere Systems’

DSPs, microprocessors, or peripheral I/O devices. The

PHIF port supports either Motorola or Intel protocols, as

well as 8-bit or 16-bit transfers, configured in software.

The port data rate depends upon the instruction cycle

rate. A 25 ns instruction cycle allows the PHIF to sup-

port data rates up to 11.85 Mbytes/s, assuming the ex-

ternal host device can transfer 1 byte of data in 25 ns.

In order to allow flexible device interfacing while main-

taining a low package pin count, the DSP1629 multi-

plexes 16 package pins between BIO, PHIF, VEC[3:0],

and SIO2.

Upon reset, the vectored interrupt indication signals,

VEC[3:0], are connected to the package pins while

IOBIT[4:7] are disconnected. Setting bit 12, EBIOH, of

the ioc register connects IOBIT[4:7] to the package pins

and disconnects VEC[3:0].

The PHIF is accessed in two basic modes: 8-bit or

16-bit mode. In 8-bit mode, only the low byte is access-

ed. In 16-bit mode, the host determines an access of the

high or low byte. Software-programmable features al-

low for a glueless host interface to microprocessors

(see Section 4.8, Parallel Host Interface (PHIF)).

Upon reset, the parallel host interface (PHIF) is con-

nected to the package pins while the second serial port

(SIO2) and IOBIT[3:0] are disconnected. Setting bit 10,

ESIO2, of the ioc register connects the SIO2 and

IOBIT[3:0] and disconnects the PHIF.

Timer

Power Management

The timer can be used to provide an interrupt at the ex-

piration of a programmed interval. The interrupt may be

single or repetitive. More than nine orders of magnitude

of interval selection are provided. The timer may be

stopped and restarted at any time.

Many applications require programmable sleep modes

for power management. There are three different con-

trol mechanisms for achieving low-power operation: the

powerc control register, the STOP pin, and the AWAIT

bit in the alf register. The AWAIT bit in the alf register al-

lows the processor to go into a power-saving standby

mode until an interrupt occurs. The powerc register con-

figures various power-saving modes by controlling inter-

nal clocks and peripheral I/O units. The STOP pin

controls the internal processor clock. The various power

management options may be chosen based on power

consumption and/or wake-up latency requirements.

Hardware Development System (HDS) Module

The on-chip HDS performs instruction breakpointing

and branch tracing at full speed without additional off-

chip hardware. Using the JTAG port, the breakpointing

is set up and the trace history is read back. The port

works in conjunction with the HDS code in the on-chip

ROM and the hardware and software in a remote com-

puter. The HDS code must be linked to the user's appli-

cation code and reside in the first 4 Kwords of ROM.

The on-chip HDS cannot be used with the secure ROM

masking option (see Section 7.3, ROM Security Op-

tions).

4.2 DSP1600 Core Architectural Overview

Figure 5, DSP1600 Core Block Diagram, shows a block

diagram of the DSP1600 core.

System Cache and Control Section (SYS)

Four hardware breakpoints can be set on instruction ad-

dresses. A counter can be preset with the number of

breakpoints to receive before trapping the core. Break-

points can be set in interrupt service routines. Alternate-

ly, the counter can be preset with the number of cache

instructions to execute before trapping the core.

This section of the core contains a 15-word cache mem-

ory and controls the instruction sequencing. It handles

vectored interrupts and traps, and also provides decod-

ing for registers outside of the DSP1600 core. SYS

stretches the processor cycle if wait-states are required

(wait-states are programmable for external memory ac-

cesses). SYS sequences downloading via JTAG of self-

test programs to on-chip, dual-port RAM.

Every time the program branches instead of executing

the next sequential instruction, the addresses of the in-

structions executed before and after the branch are

caught in circular memory. The memory contains the

last four pairs of program discontinuities for hardware

tracing.

The cache loop iteration count can be specified at run

time under program control as well as at assembly time.

In systems with multiple processors, the processors

may be configured so that any processor reaching a

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Data Sheet

January 2002

DSP1629 Digital Signal Processor

The YAAU allows direct (or indexed) addressing of data

memory. In direct addressing, the 16-bit base register

(ybase) supplies the 11 most significant bits of the ad-

dress. The direct data instruction supplies the remaining

5 bits to form an address to Y memory space and also

specifies one of 16 registers for the source or destina-

tion.

4 Hardware Architecture (continued)

Data Arithmetic Unit (DAU)

The data arithmetic unit (DAU) contains a 16 x 16-bit

parallel multiplier that generates a full 32-bit product in

one instruction cycle. The product can be accumulated

with one of two 36-bit accumulators. The accumulator

data can be directly loaded from, or stored to, memory

in two 16-bit words with optional saturation on overflow.

The arithmetic logic unit (ALU) supports a full set of

arithmetic and logical operations on either 16-bit or

32-bit data. A standard set of flags can be tested for

conditional ALU operations, branches, and subroutine

calls. This procedure allows the processor to perform as

a powerful 16-bit or 32-bit microprocessor for logical

and control applications. The available instruction set is

fully compatible with the DSP1627 instruction set. See

Section 5.1, Instruction Set, for more information on the

instruction set.

X-Space Address Arithmetic Unit (XAAU)

The XAAU supports high-speed, register-indirect, in-

struction/coefficient memory addressing with postmodi-

fication of the register. The 16-bit pt register is used for

addressing coefficients. The signed register i holds a

user-defined postincrement. A fixed postincrement of

+1 is also available. Register PC is the program

counter. Registers pr and pi hold the return address for

subroutine calls and interrupts, respectively.

The XAAU decodes the 16-bit instruction/coefficient ad-

dress and produces enable signals for the appropriate

X memory segment. The addressable X segments are

48 Kwords of internal ROM, up to 16 Kwords of DPRAM

for the DSP1629x16 or up to 10 Kwords of DPRAM for

the DSP1629x10, and external ROM.

The user also has access to two additional DAU regis-

ters. The psw register contains status information from

the DAU (see Table 26, Processor Status Word (psw)

Register). The arithmetic control register, auc, is used to

configure some of the features of the DAU (see Table

27, Arithmetic Unit Control (auc) Register), including

single-cycle squaring. The auc register alignment field

supports an arithmetic shift left by one and left or right

by two. The auc register is cleared by reset.

The locations of these memory segments depend upon

the memory map selected (see Table 5, Instruction/Co-

efficient Memory Maps). A security mode can be select-

ed by mask option. This prevents unauthorized access

to the contents of on-chip ROM (see Section 7, Mask-

Programmable Options).

The counters c0 to c2 are signed, 8 bits wide, and may

be used to count events such as the number of times

the program has executed a sequence of code. They

are controlled by the conditional instructions and pro-

vide a convenient method of program looping.

4.3 Interrupts and Trap

The DSP1629 supports prioritized, vectored interrupts

and a trap. The device has eight internal hardware

sources of program interrupt and two external interrupt

pins. Additionally, there is a trap pin and a trap signal

from the hardware development system (HDS). A soft-

ware interrupt is available through the icall instruction.

The icall instruction is reserved for use by the HDS.

Each of these sources of interrupt and trap has a unique

vector address and priority assigned to it.

Y-Space Address Arithmetic Unit (YAAU)

The YAAU supports high-speed, register-indirect, com-

pound, and direct addressing of data (Y) memory. Four

general-purpose, 16-bit registers, r0 to r3, are available

in the YAAU. These registers can be used to supply the

read or write addresses for Y-space data. The YAAU

also decodes the 16-bit data memory address and out-

puts individual memory enables for the data access.

The YAAU can address the six 1 Kword banks of on-

chip DPRAM or three external data memory segments.

Up to 48 Kwords of off-chip RAM are addressable, with

16K addresses reserved for internal RAM.

The software interrupt and the traps are always enabled

and do not have a corresponding bit in the ins register.

Other vectored interrupts are enabled in the inc register

(see Table 29, Interrupt Control (inc) Register) and

monitored in the ins register (see Table 30, Interrupt

Status (ins) Register). When the DSP1629 goes into an

interrupt or trap service routine, the IACK pin is assert-

ed. In addition, pins VEC[3:0] encode which interrupt/

trap is being serviced. Table 4, Interrupt Vector Table,

details the encoding used for VEC[3:0].

Two 16-bit registers, rb and re, allow zero-overhead

modulo addressing of data for efficient filter implemen-

tations. Two 16-bit signed registers, j and k, are used to

hold user-defined postmodification increments. Fixed

increments of +1, –1, and +2 are also available. Four

compound-addressing modes are provided to make

read/write operations more efficient.

12

Agere Systems Inc.

Data Sheet

January 2002

DSP1629 Digital Signal Processor

4 Hardware Architecture (continued)

XDB

XAAU

i (16)

1

SYS

MUX

ADDER

XAB

CACHE

CONTROL

pr (16)

pi (16)

cloop (7)

pc (16)

pt (16)

alf (16)

ins (16)

inc (16)

mwait (16)

IDB

BRIDGE

YDB

YAAU

–1, 0, 1, 2

DAU

yh (16)

x (16)

yl (16)

j (16)

k (16)

16 x 16 MPY

p (32)

32

MUX

SHIFT (–2, 0, 1, 2)

ADDER

YAB

MUX

rb (16)

36

c0 (8)

re (16)

MUX

c1 (8)

c2 (8)

ALU/SHIFT

CMP

auc (16)

r0 (16)

r1 (16)

r2 (16)

r3 (16)

a0 (36)

a1 (36)

psw (16)

16

ybase (16)

EXTRACT/SAT

5-1741 (F).b

Figure 5. DSP1600 Core Block Diagram

Agere Systems Inc.

13

Data Sheet

January 2002

DSP1629 Digital Signal Processor

4 Hardware Architecture (continued)

Table 3. DSP1600 Core Block Diagram Legend

Symbol

Name

16 x 16 MPY

16-bit x 16-bit Multiplier.

a0—a1

alf

Accumulators 0 and 1 (16-bit halves specified as a0, a0l, a1, and a1l).*

AWAIT, LOWPR, Flags.

ALU/SHIFT

auc

c0—c2

cloop

CMP

DAU

i

Arithmetic Logic Unit/Shifter.

Arithmetic Unit Control.

Counters 0—2.

Cache Loop Count.

Comparator.

Digital Arithmetic Unit.

Increment Register for the X Address Space.

Internal Data Bus.

IDB

inc

Interrupt Control.

ins

Interrupt Status.

j

Increment Register for the Y Address Space.

Multiplexer.

k

MUX

mwait

p

External Memory Wait-states Register.

Product Register (16-bit halves specified as p, pl).

Program Counter.

PC

pi

Program Interrupt Return Register.

Program Return Register.

pr

psw

pt

Processor Status Word.

X Address Space Pointer.

r0—r3

rb

Y Address Space Pointers.

Modulo Addressing Register (begin address).

Modulo Addressing Register (end address).

System Cache and Control Section.

Multiplier Input Register.

re

SYS

x

XAAU

XAB

XDB

YAAU

YAB

YDB

ybase

y

X-Space Address Arithmetic Unit.

X-Space Address Bus.

X-Space Data Bus.

Y-Space Address Arithmetic Unit.

Y-Space Address Bus.

Y-Space Data Bus.

Direct Addressing Base Register.

DAU Register (16-bit halves specified as y, yl).

*

F3 ALU instructions with immediates require specifying the high half of the accumulators as a0h and a1h.

14

Agere Systems Inc.

Data Sheet

January 2002

DSP1629 Digital Signal Processor

Signaling Interrupt Service Status

4 Hardware Architecture (continued)

Five pins of DSP1629 are devoted to signaling interrupt

service status. The IACK pin goes high while any inter-

rupt or user trap is being serviced, and goes low when

the ireturn instruction from the service routine is issued.

Four pins, VEC[3:0], carry a code indicating which of the

interrupts or trap is being serviced. Table 4, Interrupt

Vector Table, contains the encodings used by each in-

terrupt.

Interruptibility

Vectored interrupts are serviced only after the execution

of an interruptible instruction. If more than one vectored

interrupt is asserted at the same time, the interrupts are

serviced sequentially according to their assigned priori-

ties. See Table 4, Interrupt Vector Table, for the priori-

ties assigned to the vectored interrupts. Interrupt

service routines, branch and conditional branch instruc-

tions, cache loops, and instructions that only decrement

one of the RAM pointers, r0 to r3 (e.g., *r3− −), are not

interruptible.

Traps due to HDS breakpoints have no effect on either

the IACK or VEC[3:0] pins. Instead, they show the inter-

rupt state or interrupt source of the DSP when the trap

occurred.

A trap is similar to an interrupt, but it gains control of the

processor by branching to the trap service routine even

when the current instruction is noninterruptible. It may

not be possible to return to normal instruction execution

from the trap service routine since the machine state

cannot always be saved. In particular, program execu-

tion cannot be continued from a trapped cache loop or

interrupt service routine. While in a trap service routine,

another trap is ignored.

Clearing Interrupts

The PHIF interrupts (PIBF and POBE) are cleared by

reading or writing the parallel host interface data trans-

mit registers pdx0[in] and pdx0[out], respectively. The

SIO and SIO2 interrupts (IBF, IBF2, OBE, and OBE2)

are cleared one instruction cycle AFTER reading or writ-

ing the serial data registers, (sdx[in], sdx2[in], sdx[out],

or sdx2[out]). To account for this added latency, the

user must ensure that a single instruction (NOP or any

other valid DSP16XX instruction) follows the sdx regis-

ter read or write instruction prior to exiting an interrupt

service routine (via an ireturn or goto pi instruction) or

before checking the ins register for the SIO flag status.

Adding this instruction ensures that interrupts are not

reported incorrectly following an ireturn or that stale

flags are not read from the ins register. The JTAG inter-

rupt (JINT) is cleared by reading the jtag register.

When set to 1, the status bits in the ins register indicate

that an interrupt has occurred. The processor must

reach an interruptible state (completion of an interrupt-

ible instruction) before an enabled vectored interrupt will

be acted on. An interrupt will not be serviced if it is not

enabled. Polled interrupt service can be implemented

by disabling the interrupt in the inc register and then

polling the ins register for the expected event.

Vectored Interrupts

Three of the vectored interrupts are cleared by writing to

the ins register. Writing a 1 to the INT0, INT1, or TIME

bits in the ins will cause the corresponding interrupt sta-

tus bit to be cleared to a logic 0. The status bit for these

vectored interrupts is also cleared when the ireturn in-

struction is executed, leaving set any other vectored in-

terrupts that are pending.

Table 29, Interrupt Control (inc) Register, and Table 30,

Interrupt Status (ins) Register, show the inc and ins reg-

isters, respectively. A logic 1 written to any bit of inc en-

ables (or unmasks) the associated interrupt. If the bit is

cleared to a logic 0, the interrupt is masked. Note that

neither the software interrupt nor traps can be masked.

The occurrence of an interrupt that is not masked will

cause the program execution to transfer to the memory

location pointed to by that interrupt's vector address, as-

suming no other interrupt is being serviced (see Table

4, Interrupt Vector Table). The occurrence of an inter-

rupt that is masked causes no automatic processor ac-

tion, but will set the corresponding status bit in the ins

register. If a masked interrupt occurs, it is latched in the

ins register, but the interrupt is not taken. When un-

latched, this latched interrupt will initiate automatic pro-

cessor interrupt action. See the DSP1611/17/18/27/28/

29 Digital Signal Processor Information Manual for a

more detailed description of the interrupts.

Traps

The TRAP pin of the DSP1629 is a bidirectional signal.

At reset, it is configured as an input to the processor.

Asserting the TRAP pin will force a user trap. The trap

mechanism is used for two purposes. It can be used by

an application to rapidly gain control of the processor for

asynchronous time-critical event handling (typically for

catastrophic error recovery). It is also used by the HDS

for breakpointing and gaining control of the processor.

Separate vectors are provided for the user trap (0x46)

and the HDS trap (0x3). Traps are not maskable.

Agere Systems Inc.

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Data Sheet

January 2002

DSP1629 Digital Signal Processor

4 Hardware Architecture (continued)

Table 4. Interrupt Vector Table

Source

No Interrupt

Software Interrupt

INT0

Vector

—

Priority

VEC[3:0]

0x0

0x1

0x2

0x8

0x9

0xc

Issued by

—

0x2

1

icall

0x1

2

JINT

0x42

0x4

3

jtag in

INT1

4

TIME

0x10

0x14

0x18

0x1c

0x20

0x24

0x2c

0x30

0x34

0x38

0x3

7

timer

IBF2

8

0xd

0xe

0x0

0x1

0x2

0x3

0x4

0x5

0x6

SIO2 in

OBE2

9

SIO2 out

Reserved

IBF

10

—

11

—

12

—

SIO in

14

OBE

15

SIO out

PIBF

16

PHIF in

POBE

17

18

PHIF out

breakpoint, jtag, or pin

*

—

TRAP from HDS

TRAP from User

0x46

19 = highest

0x7

* Traps due to HDS breakpoints have no effect on VEC[3:0] pins.

A trap has four cycles of latency. At most, two instruc-

tions will execute from the time the trap is received at

the pin to when it gains control. An instruction that is ex-

ecuting when a trap occurs is allowed to complete be-

fore the trap service routine is entered. (Note that the

instruction could be lengthened by wait-states.) During

normal program execution, the pi register contains ei-

ther the address of the next instruction (two-cycle in-

struction executing), or the address following the next

instruction (one-cycle instruction executing). In an inter-

rupt service routine, pi contains the interrupt return ad-

dress. When a trap occurs during an interrupt service

routine, the value of the pi register may be overwritten.

Specifically, it is not possible to return to an interrupt

service routine from a user trap (0x46) service routine.

Continuing program execution when a trap occurs dur-

ing a cache loop is also not possible.

gether. During HDS operations, one DSP is selected by

the host software to be the master. The master proces-

sor's TRAP pin is configured to be an output.

The TRAP pins of the slave processors are configured

as inputs. When the master processor reaches a break-

point, the master's TRAP pin is asserted. The slave pro-

cessors will respond to their TRAP input by beginning to

execute the HDS code.

AWAIT Interrupt (Standby or Sleep Mode)

Setting the AWAIT bit (bit 15) of the alf register (alf =

0x8000) causes the processor to go into a power-saving

standby or sleep mode. Only the minimum circuitry on

the chip required to process an incoming interrupt re-

mains active. After the AWAIT bit is set, one additional

instruction will be executed before the standby power-

saving mode is entered. A PHIF or SIO word transfer

will complete if already in progress. The AWAIT bit is re-

set when the first interrupt occurs. The chip then wakes

up and continues executing.

The HDS trap causes circuitry to force the program

memory map to MAP1 (with on-chip ROM starting at ad-

dress 0x0) when the trap is taken. The previous memo-

ry map is restored when the trap service routine exits by

issuing an ireturn. The map is forced to MAP1 because

the HDS code, if present, resides in the on-chip ROM.

Two nop instructions should be programmed after the

AWAIT bit is set. The first nop (one cycle) will be exe-

cuted before sleeping; the second will be executed after

the interrupt signal awakens the DSP and before the in-

terrupt service routine is executed.

Using the Agere Systems development tools, the TRAP

pin may be configured to be an output, or an input vec-

toring to address 0x3. In a multiprocessor environment,

the TRAP pins of all the DSPs present can be tied to-

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Agere Systems Inc.

Data Sheet

January 2002

DSP1629 Digital Signal Processor

an HDS trap, the memory map is forced to MAP1. The

user's map selection is restored when the trap service

routine has completed execution.

4 Hardware Architecture (continued)

The AWAIT bit should be set from within the cache if the

code which is executing resides in external ROM where

more than one wait-state has been programmed. This

ensures that an interrupt will not disturb the device from

completely entering the sleep state.

MAP1

MAP1 has the IROM starting at 0x0 and 1 Kword banks

of DPRAM starting at 0xC000. MAP1 is used if

DSP1629 has EXM low at reset and the LOWPR pa-

rameter is programmed to zero. It is also used during an

HDS trap.

For additional power savings, set ioc = 0x0180 and tim-

erc = 0x0040, in addition to setting alf = 0x8000. This

will hold the CKO pin low and shut down the timer and

prescaler (see Table 38, ioc Register, and Table 31,

timerc Register).

MAP2

For a description of the control mechanisms for putting

the DSP into low-power modes, see Section 4.13, Pow-

er Management.

MAP2 differs from MAP1 in that the lowest 48 Kwords

reference external ROM (EROM). MAP2 is used if EXM

is high at reset, the LOWPR parameter is programmed

to zero, and an HDS trap is not in progress.

4.4 Memory Maps and Wait-States

MAP3

The DSP1600 core implements a modified Harvard ar-

chitecture that has separate on-chip 16-bit address and

data buses for the instruction/coefficient (X) and data

(Y) memory spaces. Table 5, Instruction/Coefficient

Memory Maps, shows the instruction/coefficient memo-

ry space maps for both the DSP1629x16 and

DSP1629x10.

MAP3 has the 1 Kword banks of DPRAM, starting at

address 0x0. In MAP3, the 48 Kwords of IROM start at

0x4000. MAP3 is used if EXM is low at reset, the LOW-

PR bit is programmed to 1, and an HDS trap is not in

progress. Note that this map is not available if the se-

cure mask-programmable option has been ordered.

The DSP1629 provides a multiplexed external bus

which accesses external RAM (ERAM) and ROM

(EROM). Programmable wait-states are provided for

external memory accesses. The instruction/coefficient

memory map is configurable to provide application flex-

ibility. Table 6, Data Memory Maps, shows the data

memory space, which has one map.

MAP4

MAP4 differs from MAP3 in that addresses above

0x4000 reference external ROM (EROM). This map is

used if the LOWPR bit is programmed to 1, an HDS trap

is not in progress, and, either EXM is high during reset,

or the secure mask-programmable option has been or-

dered.

Instruction/Coefficient Memory Map Selection

Whenever the chip is reset using the RSTB pin, the de-

fault memory map will be MAP1 or MAP2, depending

upon the state of the EXM pin at reset. A reset through

the HDS will not reinitialize the alf register, so the previ-

ous memory map is retained.

In determining which memory map to use, the proces-

sor evaluates the state of two parameters. The first is

the LOWPR bit (bit 14) of the alf register. The LOWPR

bit of the alf register is initialized to 0 automatically at re-

set. LOWPR controls the starting address in memory

assigned to 1K banks of dual-port RAM. If LOWPR is

low, internal dual-port RAM begins at address 0xC000.

If LOWPR is high, internal dual-port RAM begins at ad-

dress 0x0. LOWPR also moves IROM from 0x0 in

MAP1 to 0x4000 in MAP3, and EROM from 0x0 in

MAP2 to 0x4000 in MAP4.

Boot from External ROM

After RSTB goes from low to high, the DSP1629 comes

out of reset and fetches an instruction from address

zero of the instruction/coefficient space. The physical

location of address zero is determined by the memory

map in effect. If EXM is high at the rising edge of RSTB,

MAP2 is selected. MAP2 has EROM at location zero;

thus, program execution begins from external memory.

If EXM is high and INT1 is low when RSTB rises, the

mwait register defaults to 15 wait-states for all external

memory segments. If INT1 is high, the mwait register

defaults to 0 wait-states.

The second parameter is the value of the EXM pin at re-

set (pin 27 or pin 14, depending upon the package

type). EXM determines whether the internal 48 Kwords

ROM (IROM) will be addressable in the memory map.

The Agere Systems development system tools, togeth-

er with the on-chip HDS circuitry and the JTAG port, can

independently set the memory map. Specifically, during

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17

Data Sheet

January 2002

DSP1629 Digital Signal Processor

4 Hardware Architecture (continued)

Table 5. Instruction/Coefficient Memory Maps

DSP1629x16

X Address

AB[0:15]

MAP 1*

EXM = 0

LOWPR = 0^†

IROM

MAP 2

EXM = 1

LOWPR = 0

MAP 3^‡

EXM = 0

LOWPR = 1

MAP 4

EXM = 1

LOWPR = 1

0

4K

6K

0x0000

0x1000

0x1800

0x3000

0x4000

0x5000

0x6000

0x7000

0x8000

0x9000

0xA000

0xB000

0xC000

0xD000

0xD800

0xE000

0xFFFF

EROM

(48K)

DPRAM

(16K)

DPRAM

(16K)

(48K)

12K

16K

20K

24K

28K

32K

36K

40K

44K

48K

52K

54K

56K

60K—64K

IROM

(48K)

EROM

(48K)

DPRAM

(16K)

DPRAM

(16K)

DSP1629x10

X Address

AB[0:15]

MAP 1*

EXM = 0

MAP 2

EXM = 1

MAP 3^‡

EXM = 0

MAP 4

EXM = 1

LOWPR = 0^†

LOWPR = 0

LOWPR = 1

0

4K

6K

0x0000

0x1000

0x1800

0x2800

0x3000

0x4000

0x5000

0x6000

0x7000

0x8000

0x9000

0xA000

0xB000

0xC000

0xD000

0xD800

0xE000

0xE800

0xFFFF

IROM

(48K)

EROM

(48K)

DPRAM

(10K)

DPRAM

(10K)

10K

12K

16K

20K

24K

28K

32K

36K

40K

44K

48K

52K

54K

56K

58K

60K—64K

Reserved

(6K)

Reserved

(6K)

IROM

(48K)

EROM

(48K)

DPRAM

(10K)

DPRAM

(10K)

Reserved

(6K)

Reserved

(6K)

* MAP1 is set automatically during an HDS trap. The user-selected map is restored at the end of the HDS trap service routine.

† LOWPR is an alf register bit. The Agere Systems development system tools can independently set the memory map.

‡ MAP3 is not available if the secure mask-programmable option is selected.

18

Agere Systems Inc.

Data Sheet

January 2002

DSP1629 Digital Signal Processor

1629x10 Data Memory Map (Not to Scale)

4 Hardware Architecture (continued)

Decimal

Address

Address in

r0, r1, r2, r3

Segment

Table 6. Data Memory Maps

0

0x0000

DPRAM[1:10]

1629x16 Data Memory Map (Not to Scale)

Decimal

Address

Address in

r0, r1, r2, r3

Segment

0

0x0000

DPRAM[1:16]

10K

0x2800

Reserved

(6 K)

16K

0x4000

0x4100

IO

16,640

ERAMLO

16K

0x4000

0x4100

IO

32K

0x8000

0xFFFF

ERAMHI

16,640

ERAMLO

64K – 1

32K

0x8000

ERAMHI

Wait-States

The number of wait-states (from 0 to 15) used when ac-

cessing each of the four external memory segments

(ERAMLO, IO, ERAMHI, and EROM) is programmable

in the mwait register (see Table 36, mwait Register).

When the program references memory in one of the

four external segments, the internal multiplexer is auto-

matically switched to the appropriate set of internal bus-

es, and the associated external enable of ERAMLO, IO,

ERAMHI, or EROM is issued. The external memory cy-

cle is automatically stretched by the number of wait-

states configured in the appropriate field of the mwait

register.

64K – 1

0xFFFF

On the data memory side (see Table 6, Data Memory

Maps), the 1K banks of dual-port RAM are located start-

ing at address 0. Addresses from 0x4000 to 0x40FF ref-

erence a 256-word memory-mapped I/O segment (IO).

Addresses from 0x4100 to 0x7FFF reference the low

external data RAM segment (ERAMLO). Addresses

above 0x8000 reference high external data RAM (ER-

AMHI).

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Data Sheet

January 2002

DSP1629 Digital Signal Processor

cess first, and then the external Y access, transparently

to the programmer. Wait-states are maintained as pro-

grammed in the mwait register. For example, let two in-

structions be executed: the first reads a coefficient from

EROM and writes data to ERAM; the second reads a

coefficient from EROM and reads data from ERAM. The

sequencer carries out the following steps at the external

memory interface: read EROM, write ERAM, read ER-

OM, and read ERAM. Each step is done in sequential

one-instruction cycle steps, assuming zero wait-states

are programmed. Note that the number of instruction

cycles taken by the two instructions is four. Also, in this

case, the write hold time is zero.

4 Hardware Architecture (continued)

4.5 External Memory Interface (EMI)

The external memory interface supports read/write op-

erations from instruction/coefficient memory, data

memory, and memory-mapped I/O devices. The

DSP1629 provides a 16-bit external address bus,

AB[15:0], and a 16-bit external data bus, DB[15:0].

These buses are multiplexed between the internal bus-

es for the instruction/coefficient memory and the data

memory. Four external memory segment enables,

ERAMLO, IO, ERAMHI, and EROM, select the external

memory segment to be addressed.

The DSP1629 allows writing into external instruction/

coefficient memory. By setting bit 11, WEROM, of the

ioc register (see Table 38, ioc Register), writing to (or

reading from) data memory or memory-mapped I/O as-

serts the EROM strobe instead of ERAMLO, IO, or ER-

AMHI. Therefore, with WEROM set, EROM appears in

both Y space (replacing ERAM) and X space, in its nor-

mal position.

If a data memory location with an address between

0x4100 and 0x7FFF is addressed, ERAMLO is asserted

low.

If one of the 256 external data memory locations, with

an address greater than or equal to 0x4000, and less

than or equal to 0x40FF, is addressed, IO is asserted

low. IO is intended for memory-mapped I/O.

Bit 14 of the ioc register (see Table 38, ioc Register),

EXTROM, may be used with WEROM to download to a

full 64K of external memory. When WEROM and EX-

TROM are both asserted, address bit 15 (AB15) is held

low, aliasing the upper 32K of external memory into the

lower 32K.

If a data memory location with an address greater than

or equal to 0x8000 is addressed, ERAMHI is asserted

low. When the external instruction/coefficient memory is

addressed, EROM is asserted low.

The flexibility provided by the programmable options of

the external memory interface (see Table 36, mwait

Register, and Table 38, ioc Register) allows the

DSP1629 to interface gluelessly with a variety of com-

mercial memory chips.

When an access to internal memory is made, the

AB[15:0] bus holds the last valid external memory ad-

dress. Asserting the RSTB pin low 3-states the AB[15:0]

bus. After reset, the AB[15:0] value is undefined.

Each of the four external memory segments, ERAMLO,

IO, ERAMHI, and EROM, has a number of wait-states

that is programmable (from 0 to 15) by writing to the

mwait register. When the program references memory

in one of the four external segments, the internal multi-

plexer is automatically switched to the appropriate set of

internal buses, and the associated external enable of

ERAMLO, IO, ERAMHI, or EROM is issued. The exter-

nal memory cycle is automatically stretched by the num-

ber of wait-states in the appropriate field of the mwait

register.

The leading edge of the memory segment enables can

be delayed by approximately one-half a CKO period by

programming the ioc register (see Table 38, ioc Regis-

ter). This is used to avoid a situation in which two devic-

es drive the data bus simultaneously.

Bits 7, 8, and 13 of the ioc register select the mode of

operation for the CKO pin (see Table 38, ioc Register).

Available options are a free-running unstretched clock,

a wait-stated sequenced clock (runs through two com-

plete cycles during a sequenced external memory ac-

cess), and a wait-stated clock based on the internal

instruction cycle. These clocks drop to the low-speed in-

ternal ring oscillator when SLOWCKI is enabled (see

Section 4.13, Power Management). The high-to-low

transitions of the wait-stated clock are synchronized to

the high-to-low transition of the free-running clock. Also,

the CKO pin provides either a continuously high level, a

continuously low level, or changes at the rate of the in-

ternal processor clock. This last option, only available

with the small-signal input clock options, enables the

DSP1629 CKI input buffer to deliver a full-rate clock to

other devices while the DSP1629 itself is in one of the

low-power modes.

When writing to external memory, the RWN pin goes

low for the external cycle. The external data bus,

DB[15:0], is driven by the DSP1629, starting halfway

through the cycle. The data driven on the external data

bus is automatically held after the cycle for one addi-

tional clock period unless an external read cycle imme-

diately follows.

The DSP1629 has one external address bus and one

external data bus for both memory spaces. Since some

instructions provide the capability of simultaneous ac-

cess to both X space and Y space, some provision must

be made to avoid collisions for external accesses. The

DSP1629 has a sequencer that does the external X ac-

20

Agere Systems Inc.

Data Sheet

January 2002

DSP1629 Digital Signal Processor

signals are wrapped around internally from the output to

the input (DO1 to DI1 and DO2 to DI2). To exercise loop-

back, the SIO clocks (ICK1, ICK2, OCK1, and OCK2)

should either all be in the active mode,

16-bit condition, or each pair should be driven from one

external source in passive mode. Similarly, pins ILD1

(ILD2) and OLD1 (OLD2) must both be in active mode or

tied together and driven from one external frame clock in

passive mode. During loopback, DO1, DO2, DI1, DI2,

ICK1, ICK2, OCK1, OCK2, ILD1, ILD2, OLD1, OLD2,

SADD1, SADD2, SYNC1, SYNC2, DOEN1, and DOEN2

are 3-stated.

4 Hardware Architecture (continued)

4.6 Bit Manipulation Unit (BMU)

The BMU interfaces directly to the main accumulators in

the DAU, providing the following features:

■ Barrel shifting—logical and arithmetic, left and right

shift

■ Normalization and extraction of exponent

■ Bit-field extraction and insertion

These features increase the efficiency of the DSP in ap-

plications such as control or data encoding and decod-

ing. For example, data packing and unpacking, in which

short data words are packed into one 16-bit word for

more efficient memory storage, is very easy.

Setting DODLY = 1 (sioc and sioc2) delays DO by one

phase of OCK so that DO changes on the falling edge of

OCK instead of the rising edge (DODLY = 0). This reduc-

es the time available for DO to drive DI and to be valid

for the rising edge of ICK, but increases the hold time on

DO by half a cycle on OCK.

In addition, the BMU provides two auxiliary accumula-

tors, aa0 and aa1. In one instruction cycle, 36-bit data

can be shuffled, or swapped, between one of the main

accumulators and one of the alternate accumulators.

The ar<0—3> registers are 16-bit registers that control

the operations of the BMU. They store a value that de-

termines the amount of shift or the width and offset fields

for bit extraction or insertion. Certain operations in the

BMU set flags in the DAU psw register and the alf regis-

ter (see Table 26, Processor Status Word (psw) Regis-

ter, and Table 35, alf Register). The ar<0—3> registers

can also be used as general-purpose registers.

Programmable Modes

Programmable modes of operation for the SIO and SIO2

are controlled by the serial I/O control registers (sioc and

sioc2). These registers, shown in Table 22, Serial I/O

Control Registers, are used to set the ports into various

configurations. Both input and output operations can be

independently configured as either active or passive.

When active, the DSP1629 generates load and clock

signals. When passive, load and clock signal pins are in-

puts.

The BMU instructions are detailed in Section 5.1, In-

struction Set. For a thorough description of the BMU,

see the DSP1611/17/18/27/28/29 Digital Signal Proces-

sor Information Manual.

Since input and output can be independently configured,

each SIO has four different modes of operation. Each of

the sioc registers is also used to select the frequency of

active clocks for that SIO. Finally, these registers are

used to configure the serial I/O data formats. The data

can be 8 bits or 16 bits long, and can also be input/output

MSB first or LSB first. Input and output data formats can

be independently configured.

4.7 Serial I/O Units (SIOs)

The serial I/O ports on the DSP1629 device provide a

serial interface to many codecs and signal processors

with little, if any, external hardware required. Each high-

speed, double-buffered port (sdx and sdx2) supports

back-to-back transmissions of data. SIO and SIO2 are

identical. The output buffer empty (OBE and OBE2) and

input buffer full (IBF and IBF2) flags facilitate the reading

and/or writing of each serial I/O port by program-driven

or interrupt-driven I/O. There are four selectable active

clock speeds.

Multiprocessor Mode

The multiprocessor mode allows up to eight devices that

support multiprocessor mode (codecs or DSP16XX de-

vices) to be connected together to provide data trans-

mission among any of the multiprocessor devices in the

system. Either of the DSP1629’s SIO ports (SIO or

SIO2) may be independently used for the multiprocessor

mode. The multiprocessor interface is a four-wire inter-

face, consisting of a data channel, an address/protocol

channel, a transmit/receive clock, and a sync signal (see

Figure 6, Multiprocessor Communication and Connec-

tions). The DI1 and DO1 pins of all the DSPs are con-

nected to transmit and receive the data channel. The

SADD1 pins of all the DSPs are connected to transmit

and receive the address/protocol channel. ICK1 and

OCK1 should be tied together and driven from one

source. The SYNC1 pins of all the DSPs are connected.

A bit-reversal mode provides compatibility with either the

most significant bit (MSB) first or least significant bit

(LSB) first serial I/O formats (see Table 22, Serial I/O

Control Registers). A multiprocessor I/O configuration is

supported. This feature allows up to eight DSP161X de-

vices to be connected together on an SIO port without

requiring external glue logic.

The serial data may be internally looped back by setting

the SIO loopback control bit, SIOLBC, of the ioc register.

SIOLBC affects both the SIO and SIO2. The data output

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Data Sheet

January 2002

DSP1629 Digital Signal Processor

In order to prevent multiple bus drivers, only one DSP

can be programmed to transmit in a particular time slot.

In addition, it is important to note that the address/pro-

tocol channel is 3-stated in any time slot that is not being

driven.

4 Hardware Architecture (continued)

In the configuration shown in Figure 6, Multiprocessor

Communication and Connections, the master DSP

(DSP0) generates active SYNC1 and OCK1 signals

while the slave DSPs use the SYNC1 and OCK1 signals

in passive mode to synchronize operations. In addition,

all DSPs must have their ILD1 and OLD1 signals in ac-

tive mode.

Therefore, to prevent spurious inputs, the address/pro-

tocol channel should be pulled up to VDD with a 5 kΩ re-

sistor, or it should be guaranteed that the bus is driven

in every time slot. (If the SYNC1 signal is externally gen-

erated, then this pull-up is required for correct initializa-

tion.)

While ILD1 and OLD1 are not required externally for

multiprocessor operation, they are used internally in the

DSP's SIO. Setting the LD field of the master's sioc reg-

ister to a logic level 1 will ensure that the active genera-

tion of SYNC1, ILD1, and OLD1 is derived from OCK1

(see Table 22, Serial I/O Control Registers). With this

configuration, all DSPs should use ICK1 (tied to OCK1)

in passive mode to avoid conflicts on the clock (CK) line

(see the DSP1611/17/18/27/28/29 Digital Signal Pro-

cessor Information Manual for more information).

Each SIO also has a fully decoded transmitting address

specified by the srta register transmit address field (bits

7—0). This is used to transmit information regarding the

destination(s) of the data. The fully decoded receive ad-

dress specified by the srta register receive address field

(bits 15—8) determines which data will be received.

The SIO protocol channel data is controlled via the sad-

dx register. When the saddx register is written, the lower

8 bits contain the 8-bit protocol field. On a read, the

high-order 8 bits read from saddx are the most recently

received protocol field sent from the transmitting DSP's

saddx output register. The low-order 8 bits are read as

0s.

Four registers (per SIO) configure the multiprocessor

mode: the time-division multiplexed slot register (tdms

or tdms2), the serial receive and transmit address reg-

ister (srta or srta2), the serial data transmit register (sdx

or sdx2), and the multiprocessor serial address/protocol

register (saddx or saddx2).

An example use of the protocol channel is to use the top

3 bits of the saddx value as an encoded source address

for the DSPs on the multiprocessor bus. This leaves the

remaining 5 bits available to convey additional control

information, such as whether the associated field is an

opcode or data, or whether it is the last word in a trans-

fer, etc. These bits can also be used to transfer parity in-

formation about the data. Alternatively, the entire field

can be used for data transmission, boosting the band-

width of the port by 50%.

Multiprocessor mode requires no external logic and

uses a TDM interface with eight 16-bit time slots per

frame. The transmission in any time slot consists of

16 bits of serial data in the data channel and 16 bits of

address and protocol information in the address/proto-

col channel. The address information consists of the

transmit address field of the srta register of the transmit-

ting device. The address information is transmitted con-

currently with the transmission of the first 8 bits of data.

The protocol information consists of the transmit proto-

col field written to the saddx register and is transmitted

concurrently with the last 8 bits of data (see Table 25,

Multiprocessor Protocol Registers). Data is received or

recognized by other DSP(s) whose receive address

matches the address in the address/protocol channel.

Each SIO port has a user-programmable receive ad-

dress and transmit address associated with it. The

transmit and receive addresses are programmed in the

srta register.

Using SIO2

The SIO2 functions the same as the SIO. Please refer

to the Pin Multiplexing section for a description of pin

multiplexing of BIO, PHIF, VEC[3:0], and SIO2.

In multiprocessor mode, each device can send data in

a unique time slot designated by the tdms register trans-

mit slot field (bits 7—0). The tdms register has a fully de-

coded transmit slot field in order to allow one DSP1629

device to transmit in more than one time slot. This pro-

cedure is useful for multiprocessor systems with less

than eight DSP1629 devices when a higher bandwidth

is necessary between certain devices in that system.

The DSP operating during time slot 0 also drives

SYNC1.

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Agere Systems Inc.

Data Sheet

January 2002

DSP1629 Digital Signal Processor

4 Hardware Architecture (continued)

DSP 0

DSP 1

DSP 7

5 kΩ

DATA CHANNEL

CLOCK

V^DD

ADDRESS/PROTOCOL CHANNEL

SYNC SIGNAL

5-4181 (F).a

Figure 6. Multiprocessor Communication and Connections

PHIF port, PCSN should be grounded. If PCSN is low

4.8 Parallel Host Interface (PHIF)

and the respective bits in the inc register are set, the as-

sertion of PIDS and PODS by an external device caus-

es the DSP1629 device to recognize an interrupt.

The DSP1629 has an 8-bit parallel host interface for

rapid transfer of data with external devices. This parallel

port is passive (data strobes provided by an external de-

vice) and supports either Motorola or Intel microcontrol-

ler protocols. The PHIF also provides for 8-bit or

16-bit data transfers. As a flexible host interface, it re-

quires little or no glue logic to interface to other devices

(e.g., microcontrollers, microprocessors, or another

DSP).

Programmability

The parallel host interface can be programmed for 8-bit

or 16-bit data transfers using bit 0, PMODE, of the phifc

register. Setting PMODE selects 16-bit transfer mode.

An input pin controlled by the host, PBSEL, determines

an access of either the high or low bytes. The assertion

level of the PBSEL input pin is configurable in software

using bit 3 of the phifc register, PBSELF. Table 7, PHIF

Function (8-bit and 16-bit Modes), summarizes the

port's functionality as controlled by the PSTAT and PB-

SEL pins and the PBSELF and PMODE fields.

The data path of the PHIF consists of a 16-bit input buff-

er, pdx0(in), and a 16-bit output buffer, pdx0(out). Two

output pins, parallel input buffer full (PIBF) and parallel

output buffer empty (POBE), indicate the state of the

buffers. In addition, there are two registers used to con-

trol and monitor the PHIF's operation: the parallel host

interface control register (phifc, see Table 28, Parallel

Host Interface Control (phifc) Register), and the PHIF

status register (PSTAT, see Table 8, pstat Register as

Seen on PB[7:0]). The PSTAT register, which reflects

the state of the PIBF and POBE flags, can only be read

by an external device when the PSTAT input pin is as-

serted. The phifc register defines the programmable op-

tions for this port.

For 16-bit transfers, if PBSELF is zero, the PIBF and

POBE flags are set after the high byte is transferred. If

PBSELF is one, the flags are set after the low byte is

transferred. In 8-bit mode, only the low byte is access-

ed, and every completion of an input or output access

sets PIBF or POBE.

Bit 1 of the phifc register, PSTROBE, configures the

port to operate either with an Intel protocol, where only

the chip select (PCSN) and either of the data strobes

(PIDS or PODS) are needed to make an access, or with

a Motorola protocol, where the chip select (PCSN), a

data strobe (PDS), and a read/write strobe (PRWN) are

needed. PIDS and PODS are negative assertion data

strobes while the assertion level of PDS is programma-

ble through bit 2, PSTRB, of the phifc register.

The function of the pins, PIDS and PODS, is program-

mable to support both the Intel and Motorola protocols.

The pin, PCSN, is an input that, when low, enables

PIDS and PODS (or PRWN and PDS, depending on the

protocol used). While PCSN is high, the DSP1629 ig-

nores any activity on PIDS and/or PODS. If a DSP1629

is intended to be continuously accessed through the

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Data Sheet

January 2002

DSP1629 Digital Signal Processor

4 Hardware Architecture (continued)

Finally, the assertion level of the output pins, PIBF and POBE, is controlled through bit 4, PFLAG. When PFLAG is

set low, PIBF and POBE output pins have positive assertion levels. By setting bit 5, PFLAGSEL, the logical OR of

PIBF and POBE flags (positive assertion) is seen at the output pin PIBF. By setting bit 7 in phifc, PSOBEF, the po-

larity of the POBE flag in the status register, PSTAT, can be changed. PSOBEF has no effect on the POBE pin.

Pin Multiplexing

Please refer to the Pin Multiplexing section for a description of BIO, PHIF, VEC[3:0], and SIO2 pins.

Table 7. PHIF Function (8-bit and 16-bit Modes)

PMODE Field

PSTAT Pin

PBSEL Pin

PBSELF Field = 0

pdx0 low byte

reserved

PSTAT

reserved

pdx0 low byte

pdx0 high byte

PSTAT

PBSELF Field = 1

reserved

0 (8-bit)

0

1

0

1

0

1

0

1

0

1

0

1

0

pdx0 low byte

reserved

PSTAT

1 (16-bit)

pdx0 high byte

pdx0 low byte

reserved

1

reserved

PSTAT

Table 8. pstat Register as Seen on PB[7:0]

Bit

7

6

5

4

3

2

1

0

Field

RSVD

PIBF

POBE

allf (all false), somet (some true), and somef (some

false). These flags can be used for conditional branch or

special instructions. The state of these flags can be

saved and restored by reading and writing bits 0 to 3 of

the alf register (see Table 35, alf Register).

4.9 Bit Input/Output Unit (BIO)

The BIO controls the directions of eight bidirectional

control I/O pins, IOBIT[7:0]. If a pin is configured as an

output, it can be individually set, cleared, or toggled. If a

pin is configured as an input, it can be read and/or test-

ed.

Table 9. BIO Operations

MODE/

MASK[n]

DATA/

PAT[n]

Action

The lower half of the sbit register (see Table 33, sbit

Register) contains current values (VALUE[7:0]) of the

eight bidirectional pins IOBIT[7:0]. The upper half of the

sbit register (DIREC[7:0]) controls the direction of each

of the pins. A logic 1 configures the corresponding pin as

an output; a logic 0 configures it as an input. The upper

half of the sbit register is cleared upon reset.

DIREC[n]^*

1 (Output)

0 (Input)

0

1

0

1

0

1

0

1

0

1

0

1

Clear

Set

No Change

Toggle

No Test

The cbit register (see Table 34, cbit Register) contains

two 8-bit fields: MODE/MASK[7:0] and DATA/PAT[7:0].

The values of DATA/PAT[7:0] are cleared upon reset.

The meaning of a bit in either field depends on whether

it has been configured as an input or an output in sbit. If

a pin has been configured to be an output, the meanings

are MODE and DATA. For an input, the meanings are

MASK and PAT (pattern). Table 9, BIO Operations,

shows the functionality of the MODE/MASK and DATA/

PAT bits based on the direction selected for the associ-

ated IOBIT pin.

Test for Zero

Test for One

* 0 ≤ n ≤ 7.

If a BIO pin is switched from being configured as an out-

put to being configured as an input and then back to be-

ing configured as an output, the pin retains the previous

output value.

Pin Multiplexing

Those bits that have been configured as inputs can be

individually tested for 1 or 0. For those inputs that are

being tested, there are four flags produced: allt (all true),

Please refer to the Pin Multiplexing section for a descrip-

tion of BIO, PHIF, VEC[3:0], and SIO2 pins.

24

Agere Systems Inc.

Data Sheet

January 2002

DSP1629 Digital Signal Processor

The PRESCALE field of the timerc register selects one

of 16 possible clock rates for the timer input clock (see

Table 31, timerc Register).

4 Hardware Architecture (continued)

4.10 Timer

Setting the DISABLE bit of the timerc register to a logic

1 shuts down the timer and the prescaler for power sav-

ings. Setting the TIMERDIS, bit 4, in the powerc register

has the same effect of shutting down the timer. The

DISABLE bit and the TIMERDIS bit are cleared by writ-

ing a 0 to their respective registers to restore the normal

operating mode.

The interrupt timer is composed of the timerc (control)

register, the timer0 register, the prescaler, and the

counter itself. The timer control register (see Table 31,

timerc Register) sets up the operational state of the tim-

er and prescaler. The timer0 register is used to hold the

counter reload value (or period register) and to set the

initial value of the counter. The prescaler slows the

clock to the timer by a number of binary divisors to allow

for a wide range of interrupt delay periods.

4.11 JTAG Test Port

The counter is a 16-bit down counter that can be loaded

with an arbitrary number from software. It counts down

to 0 at the clock rate provided by the prescaler. Upon

reaching 0 count, a vectored interrupt to program ad-

dress 0x10 is issued to the DSP1629, providing the in-

terrupt is enabled (bit 8 of inc and ins registers). The

counter will then either wait in an inactive state for an-

other command from software, or will automatically re-

peat the last interrupting period, depending upon the

state of the RELOAD bit in the timerc register.

The DSP1629 uses a JTAG/IEEE 1149.1 standard five-

wire test port (TDI, TDO, TCK, TMS, TRST) for self-test

and hardware emulation. An instruction register, a

boundary-scan register, a bypass register, and a device

identification register have been implemented. The de-

vice identification register coding for the DSP1629 is

shown in Table 37, DSP1629 32-Bit JTAG ID Register.

The instruction register (IR) is 4 bits long. The instruc-

tion for accessing the device ID is 0xE (1110). The be-

havior of the instruction register is summarized in Table

10, JTAG Instruction Register. Cell 0 is the LSB (closest

to TDO).

When RELOAD is 0, the counter counts down from its

initial value to 0, interrupts the DSP1629, and then

stops, remaining inactive until another value is written to

the timer0 register. Writing to the timer0 register causes

both the counter and the period register to be written

with the specified 16-bit number. When RELOAD is 1,

the counter counts down from its initial value to 0, inter-

rupts the DSP1629, automatically reloads the specified

initial value from the period register into the counter,

and repeats indefinitely. This provides for either a single

timed interrupt event or a regular interrupt clock of arbi-

trary period.

Table 10. JTAG Instruction Register

IR Cell #:

3

Y

N

2

Y

N

1

N

Y

0

N

Y

N

Parallel Input?

Always Logic 1?

Always Logic 0?

The first line shows the cells in the IR that capture from

a parallel input in the capture-IR controller state. The

second line shows the cells that always load a logic 1 in

the capture-IR controller state. The third line shows the

cells that always load a logic 0 in the capture-IR control-

ler state. Cell 3 (MSB of IR) is tied to status signal PINT,

and cell 2 is tied to status signal JINT. The state of these

signals can therefore be captured during capture-IR and

shifted out during SHIFT-IR controller states.

The timer can be stopped and started by software, and

can be reloaded with a new period at any time. Its count

value, at the time of the read, can also be read by soft-

ware. Due to pipeline stages, stopping and starting the

timer may result in one inaccurate count or prescaled

period. When the DSP1629 is reset, the bottom 6 bits of

the timerc register and the timer0 register and counter

are initialized to 0. This sets the prescaler to CKO/2*,

turns off the reload feature, disables timer counting, and

initializes the timer to its inactive state. The act of reset-

ting the chip does not cause a timer interrupt. Note that

the period register is not initialized on reset.

Boundary-Scan Register

All of the chip's inputs and outputs are incorporated in a

JTAG scan path shown in Table 11, JTAG Boundary-

Scan Register. The types of boundary-scan cells are as

follows:

The T0EN bit of the timerc register enables the clock to

the timer. When T0EN is a 1, the timer counts down to-

wards 0. When T0EN is a 0, the timer holds its current

count.

■ I = input cell

■ O = 3-state output cell

■ B = bidirectional (I/O) cell

■ OE = 3-state control cell

■ DC = bidirectional control cell

*

Frequency of CKO/2 is equivalent to either CKI/2 for the PLL by-

passed or related to CKI by the PLL multiplying factors. See Sec-

tion 4.12, Clock Synthesis.

Agere Systems Inc.

25

Data Sheet

January 2002

DSP1629 Digital Signal Processor

4 Hardware Architecture (continued)

Note that the direction of shifting is from TDI to cell 104 to cell 103 . . . to cell 0 of TDO.

Table 11. JTAG Boundary-Scan Register

Cell

0

Type

Signal Name/Function

Cell

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

101

102

103

104

—

Type

Signal Name/Function

OCK2/PCSN^*

OE Controls cells 1, 27—31

B

1

O

I

CKO

DC Controls cell 71

DO2/PSTAT*

DC Controls cell 73

SYNC2/PBSEL*

DC Controls cell 75

ILD2/PIDS*

DC Controls cell 77

2

RSTB

B

3

DC Controls cell 4

4

B

I

TRAP

STOP^†

IACK

B

5

6

O

I

B

7

INT0

8

OE Controls cells 6, 10—25, 49, 50, 78, 79

B

O

OLD2/PODS*

IBF2/PIBF*

9

I

INT1

10—25

26

27

28—31

32—36

37

38—48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

O

I

AB[0:15]

OBE2/POBE*

EXM

DC Controls cell 81

ICK2/PB0*

DC Controls cell 83

DI2/PB1*

DC Controls cell 85

DOEN2/PB2*

DC Controls cell 87

SADD2/PB3*

DC Controls cell 89

IOBIT0/PB4*

DC Controls cell 91

IOBIT1/PB5*

DC Controls cell 93

IOBIT2/PB6*

DC Controls cell 95

IOBIT3/PB7*

DC Controls cell 97

VEC3/IOBIT4*

DC Controls cell 99

VEC2/IOBIT5*

DC Controls cell 101

VEC1/IOBIT6*

DC Controls cell 103

O

B

RWN

B

EROM, ERAMLO, ERAMHI, IO

DB[0:4]

B

DC Controls cells 32—36, 38—48

B

O

I

DB[5:15]

OBE1

IBF1

B

DI1

DC Controls cell 53

ILD1

DC Controls cell 55

ICK1

DC Controls cell 57

OCK1

DC Controls cell 59

OLD1

OE Controls cell 61

DO1

DC Controls cell 63

SYNC1

DC Controls cell 65

SADD1

DC Controls cell 67

DOEN1

DC Controls cell 69

B

O

B

I

VEC0/IOBIT7*

CKI^‡

B

—

* Please refer to the Pin Multiplexing section for a description of pin multiplexing of BIO, PHIF, VEC[3:0], and SIO2.

† Note that shifting a zero into this cell in the mode to scan a zero into the chip will disable the processor clocks just as the STOP pin will.

‡ When the JTAG SAMPLE instruction is used, this cell will have a logic one regardless of the state of the pin.

26

Agere Systems Inc.

Data Sheet

January 2002

DSP1629 Digital Signal Processor

4 Hardware Architecture (continued)

4.12 Clock Synthesis

SLOWCKI

powerc

f^{SLOW CLOCK}

f^CKI

INTERNAL

PROCESSOR

CLOCK

RING

OSCILLATOR

CKI INPUT CLOCK

M

U

X

f^CKI

VCO CLOCK

f^VCO

f

INTERNAL CLOCK

÷ 2

LOCK

PLLSEL

pllc

(FLAG TO INDICATE LOCK

CONDITION OF PLL)

PHASE

DETECTOR

CHARGE

PUMP

VCO

÷ N

PLLEN

LOOP

FILTER

Nbits[2:0]

÷ M

Mbits[4:0]

LF[3:0]

PLL/SYNTHESIZER

5-4520 (F)

Figure 7. Clock Source Block Diagram

PLL Control Signals

The DSP1629 provides an on-chip, programmable

clock synthesizer. Figure 7, Clock Source Block Dia-

gram, is the clock source diagram. The 1X CKI input

clock, the output of the synthesizer, or a slow internal

ring oscillator can be used as the source for the internal

DSP clock. The clock synthesizer is based on a phase-

locked loop (PLL), and the terms clock synthesizer and

PLL are used interchangeably.

The input to the PLL comes from one of the three mask-

programmable clock options: CMOS or small-signal.

The PLL cannot operate without an external input clock.

To use the PLL, the PLL must first be allowed to stabi-

lize and lock to the programmed frequency. After the

PLL has locked, the LOCK flag is set and the lock detect

circuitry is disabled. The synthesizer can then be used

as the clock source. Setting the PLLSEL bit in the pllc

register will switch sources from fCKI to fVCO/2 without

glitching. It is important to note that the setting of the pllc

register must be maintained. Otherwise, the PLL will

seek the new set point. Every time the pllc register is

written, the LOCK flag is reset.

On powerup, CKI is used as the clock source for the

DSP. This clock is used to generate the internal proces-

sor clocks and CKO, where fCKI = fCKO. Setting the ap-

propriate bits in the pllc control register (described in

Table 32, Phase-Locked Loop Control (pllc) Register)

will enable the clock synthesizer to become the clock

source. The powerc register, which is discussed in Sec-

tion 4.13, Power Management, can override the selec-

tion to stop clocks or force the use of the slow clock for

low-power operation.

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Data Sheet

January 2002

DSP1629 Digital Signal Processor

Two other bits in the pllc register control the PLL. Clear-

ing the PLLEN bit powers down the PLL; setting this bit

powers up the PLL. Clearing the PLLSEL bit deselects

the PLL so that the DSP is clocked by a 1X version of

the CKI input; setting the PLLSEL bit selects the PLL-

generated clock for the source of the DSP internal pro-

cessor clock. The pllc register is cleared on reset and

powerup. Therefore, the DSP comes out of reset with

the PLL deselected and powered down. M and N should

be changed only while the PLL is deselected. The val-

ues of M and N should not be changed when powering

down or deselecting the PLL.

4 Hardware Architecture (continued)

The frequency of the PLL output clock, fVCO, is deter-

mined by the values loaded into the 3-bit N divider and

the 5-bit M divider. When the PLL is selected and

locked, the frequency of the internal processor clock is

related to the frequency of CKI by the following equa-

tions:

fVCO = fCKI * M/N

f^{INTERNAL CLOCK}= f^CKO= f^VCO÷ 2

The frequency of the VCO, fVCO, must fall within the

range listed in Table 63, PLL Electrical Specifications,

VCO Frequency Ranges. Also note that fVCO must be at

least twice fCKI.

As previously mentioned, the PLL also provides a user

flag, LOCK, to indicate when the loop has locked. When

this flag is not asserted, the PLL output is unstable. The

DSP should not be switched to the PLL-based clock

without first checking that the lock flag is set. The lock

flag is cleared by writing to the pllc register. When the

PLL is deselected, it is necessary to wait for the PLL to

relock before the DSP can be switched to the PLL-

based clock. Before the input clock is stopped, the PLL

should be powered down. Otherwise, the LOCK flag will

not be reset and there may be no way to determine if the

PLL is stable, once the input clock is applied again.

The coding of the Mbits and Nbits is described as fol-

lows:

Mbits = M − 2

if (N = 1)

Nbits = 0x7

else

Nbits = N − 2

The lock-in time depends on the frequency of operation

and the values programmed for M and N (see Table 64,

PLL Electrical Specifications and pllc Register Set-

tings).

where N ranges from 1 to 8 and M ranges from 2 to 20.

The loop filter bits LF[3:0] should be programmed ac-

cording to Table 64, PLL Electrical Specifications and

pllc Register Settings.

28

Agere Systems Inc.

Data Sheet

January 2002

DSP1629 Digital Signal Processor

4 Hardware Architecture (continued)

PLL Programming Examples

The following section of code illustrates how the PLL would be initialized on powerup, assuming the following oper-

ating conditions:

■ CKI input frequency = 10 MHz

■ Internal clock and CKO frequency = 50 MHz

■ VCO frequency = 100 MHz

■ Input divide down count N = 2 (Set Nbits[2:0] = 000 to get N = 2, as described in Table 32, Phase-Locked Loop

Control (pllc) Register.)

■ Feedback down count M = 20 (Set Mbits[4:0] = 10010 to get M = 18 + 2 = 20, as described in Table 32, Phase-

Locked Loop Control (pllc) Register.)

The device would come out of reset with the PLL disabled and deselected.

pllinit: pllc = 0x2912 /* Running CKI input clock at 10 MHz, set up counters in PLL */

pllc = 0xA912 /* Power on PLL, but PLL remains deselected */

call pllwait

/* Loop to check for LOCK flag assertion */

pllc = 0xE912 /* Select high-speed, PLL clock */

goto start

pllwait: if lock return

goto pllwait

/* User's code, now running at 50 MHz */

Programming examples which illustrate how to use the PLL with the various power management modes are listed

in Section 4.13, Power Management.

Latency

The switch between the CKI-based clock and the PLL-based clock is synchronous. This method results in the actual

switch taking place several cycles after the PLLSEL bit is changed. During this time, actual code can be executed,

but it will be at the previous clock rate. Table 12, Latency Times for Switching Between CKI and PLL-Based Clocks,

shows the latency times for switching between CKI-based and PLL-based clocks. In the example given, the delay

to switch to the PLL source is 1—4 CKO cycles, and to switch back is 11—31 CKO cycles.

Table 12. Latency Times for Switching Between CKI and PLL-Based Clocks

Minimum Latency (Cycles)

Maximum Latency (Cycles)

N + 2

Switch to PLL-Based Clock

Switch from PLL-Based Clock

1

M/N + 1

M + M/N + 1

Frequency Accuracy and Jitter

When using the PLL to multiply the input clock frequency up to the instruction clock rate, it is important to realize

that although the average frequency of the internal clock and CKO will have about the same relative accuracy as

the input clock, noise sources within the DSP will produce jitter on the PLL clock so that each individual clock period

will have some error associated with it. The PLL is guaranteed only to have sufficiently low jitter to operate the DSP,

and thus, this clock should not be used as an input to jitter-sensitive devices in the system.

VDDA and VSSA Connections

The PLL has its own power and ground pins, VDDA and VSSA. Additional filtering should be provided for VDDA in the

form of a ferrite bead connected from VDDA to VDD and two decoupling capacitors (4.7 µF tantalum in parallel with

a 0.01 µF ceramic) from VDDA to VSS. VSSA can be connected directly to the main ground plane. This recommen-

dation is subject to change and may need to be modified for specific applications, depending on the characteristics

of the supply noise.

Note: For devices with the CMOS clock input option, the CKI2 pin should be connected to VSSA.

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Data Sheet

January 2002

DSP1629 Digital Signal Processor

SIO1DIS: This is a powerdown signal to the SIO1 I/O

unit. It disables the clock input to the unit, thus eliminat-

ing any sleep power associated with the SIO1. Since

the gating of the clocks may result in incomplete trans-

actions, it is recommended that this option be used in

applications where the SIO1 is not used or when reset

may be used to reenable the SIO1 unit. Otherwise, the

first transaction after reenabling the unit may be corrupt-

ed.

4 Hardware Architecture (continued)

4.13 Power Management

There are three different control mechanisms for putting

the DSP1629 into low-power modes: the powerc control

register, the STOP pin, and the AWAIT bit in the alf reg-

ister. The PLL can also be disabled with the PLLEN bit

of the pllc register for more power saving.

SIO2DIS: This bit powers down the SIO2 in the same

way SIO1DIS powers down the SIO1.

Powerc Control Register Bits

The powerc register has 10 bits that power down vari-

ous portions of the chip and select the clock source:

PHIFDIS: This is a powerdown signal to the parallel

host interface. It disables the clock input to the unit, thus

eliminating any sleep power associated with the PHIF.

Since the gating of the clocks may result in incomplete

transactions, it is recommended that this option be used

in applications where the PHIF is not used, or when re-

set may be used to reenable the PHIF. Otherwise, the

first transaction after reenabling the unit may be corrupt-

ed.

XTLOFF: Assertion of the XTLOFF bit powers down the

small-signal input circuit, disabling the internal proces-

sor clock. Since the small-signal input circuit takes

many cycles to stabilize, care must be taken with the

turn-on sequence, as described later.

SLOWCKI: Assertion of the SLOWCKI bit selects the

ring oscillator as the clock source for the internal pro-

cessor clock instead of CKI or the PLL. When CKI or the

PLL is selected, the ring oscillator is powered down.

Switching of the clocks is synchronized so that no par-

tial or short clock pulses occur. Two nops should follow

the instruction that sets or clears SLOWCKI.

TIMERDIS: This is a timer disable signal which disables

the clock input to the timer unit. Its function is identical

to the DISABLE field of the timerc control register. Writ-

ing a 0 to the TIMERDIS field will continue the timer op-

eration.

Figure 8, Power Management Using the powerc and the

pllc Registers, shows a functional view of the effect of

the bits of the powerc register on the clock circuitry. It

shows only the high-level operation of each bit. Not

shown are the bits that power down the peripheral units.

NOCK: Assertion of the NOCK bit synchronously turns

off the internal processor clock, regardless of whether

its source is provided by CKI, the PLL, or the ring oscil-

lator. The NOCK bit can be cleared by resetting the chip

with the RSTB pin, or asserting the INT0 or INT1 pins.

Two nops should follow the instruction that sets NOCK.

The PLL remains running, if enabled, while NOCK is

set.

STOP Pin

Assertion (active-low) of the STOP pin has the same ef-

fect as setting the NOCK bit in the powerc register. The

internal processor clock is synchronously disabled until

the STOP pin is returned high. Once the STOP pin is re-

turned high, program execution will continue from

where it left off without any loss of state. No chip reset

is required. The PLL remains running, if enabled, during

STOP assertion.

INT0EN: This bit allows the INT0 pin to asynchronously

clear the NOCK bit, thereby allowing the device to con-

tinue program execution from where it left off without

any loss of state. No chip reset is required. It is recom-

mended that, when INT0EN is to be used, the INT0

interrupt be disabled in the inc register so that an unin-

tended interrupt does not occur. After the program re-

sumes, the INT0 interrupt in the ins register should be

cleared.

The pllc Register Bits

INT1EN: This bit enables the INT1 pin to be used as the

NOCK clear, exactly like INT0EN, previously described.

The PLLEN bit of the pllc register can be used to power

down the clock synthesizer circuitry. Before shutting

down the clock synthesizer circuitry, the system clock

should be switched to either CKI using the PLLSEL bit

of pllc, or to the ring oscillator using the SLOWCKI bit of

powerc.

The following control bits power down the peripheral

I/O units of the DSP. These bits can be used to further

reduce the power consumption during standard sleep

mode.

30

Agere Systems Inc.

Data Sheet

January 2002

DSP1629 Digital Signal Processor

4 Hardware Architecture (continued)

PLLEN

XTLOFF

OFF

DEEP

SLEEP

ON

RING

OSCILLATOR

CKI2

SMALL SIGNAL

CLOCK

f^{SLOW CLOCK}

f^VCO/2

PLL

MASK-PROGRAMMABLE

CKI

OPTION

f^CKI

CMOS

INPUT

CLOCK

SYNC.

MUX

PLLSEL

SLOWCKI

STOP

HW STOP

DEEP

SLEEP

SW STOP

NOCK

SYNC.

GATE

DISABLE

CLEAR NOCK

RSTB

f^{INTERNAL CLOCK}

INT0

INTERNAL

PROCESSOR

CLOCK

INT0EN

INT1

INT1EN

5-4124 (F).h

Notes:

The functions in the shaded ovals are bits in the powerc control register. The functions in the nonshaded ovals are bits in the pllc control register.

Deep sleep is the state arrived at either by a hardware or software stop of the internal processor clock.

The switching of the multiplexers and the synchronous gate is designed so that no partial clocks or glitching will occur.

When the deep sleep state is entered with the ring oscillator selected, the internal processor clock is turned off before the ring oscillator is pow-

ered down.

PLL select is the PLLSEL bit of pllc; PLL powerdown is the PLLEN bit of pllc.

Figure 8. Power Management Using the powerc and the pllc Registers

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Data Sheet

January 2002

DSP1629 Digital Signal Processor

Two scenarios exist here:

4 Hardware Architecture (continued)

1. Immediate Turn-Off, Turn-On with RSTB: This sce-

nario applies to situations where the target device is

not required to execute any code while the small-sig-

nal input circuit is powered down, and where restart

from a reset state can be tolerated. In this case, the

processor clock derived from either the oscillator or

the small-signal input is running when XTLOFF is as-

serted. This effectively stops the internal processor

clock. When the system chooses to reenable the os-

cillator or small-signal input, a reset of the device will

be required. The reset pulse must be of sufficient du-

ration for the small-signal start-up interval to be sat-

isfied (required for the small-signal input circuit to

reach its dc operating point). A minimum reset pulse

of 20 µs will be adequate. The falling edge of the re-

set signal, RSTB, will asynchronously clear the

XTLOFF field, thus reenabling the power to the

small-signal circuitry. The target DSP will then start

execution from a reset state, following the rising

edge of RSTB.

Await Bit of the alf Register

Setting the AWAIT bit of the alf register causes the pro-

cessor to go into the standard sleep state or power-sav-

ing standby mode. Operation of the AWAIT bit is the

same as in the DSP1610, DSP1611, DSP1616,

DSP1617, and DSP1618. In this mode, the minimum

circuitry required to process an incoming interrupt re-

mains active, and the PLL remains active if enabled. An

interrupt will return the processor to the previous state,

and program execution will continue. The action result-

ing from setting the AWAIT bit and the action resulting

from setting bits in the powerc register are mostly inde-

pendent. As long as the processor is receiving a clock,

whether slow or fast, the DSP may be put into standard

sleep mode with the AWAIT bit. Once the AWAIT bit is

set, the STOP pin can be used to stop and later restart

the processor clock, returning to the standard sleep

state. If the processor clock is not running, however, the

AWAIT bit cannot be set.

2. Running from Slow Clock While XTLOFF Active: The

second scenario applies to situations where the de-

vice needs to continue execution of its target code.

In this case, the device switches to the slow ring os-

cillator clock first by enabling the SLOWCKI field.

Then, if the small-signal input is being used, power

down this circuitry by writing a 1 to the XTLOFF field.

Two nops are needed in between the two write oper-

ations to the powerc register. The target device will

then continue execution of its code at slow speed,

while the small-signal input clock is turned off.

Switching from the slow clock back to the high-speed

clock is then accomplished in three user steps. First,

XTLOFF is cleared. Then, a user-programmed rou-

tine sets the internal timer to a delay to wait for the

small-signal input oscillations to become stable.

When the timer counts down to zero, the high-speed

clock is selected by clearing the SLOWCKI field, ei-

ther in the timer's interrupt service routine or follow-

ing a timer polling loop. If PLL operation is desired,

then an additional routine is necessary to enable the

PLL and wait for it to lock.

Power Management Sequencing

There are important considerations for sequencing the

power management modes. The small-signal clock in-

put circuit has a start-up delay which must be taken into

account, and the PLL requires a delay to reach lock-in.

Also, the chip may or may not need to be reset following

a return from a low-power state.

Devices with a small-signal input clocking option may

use the XTLOFF bit in the powerc register to power

down the on-chip oscillator or small-signal circuitry,

thereby reducing the power dissipation. When reen-

abling the oscillator or the small-signal circuitry, it is im-

portant to bear in mind that a start-up interval exists,

during which time the clocks are not stable.

32

Agere Systems Inc.

Data Sheet

January 2002

DSP1629 Digital Signal Processor

4 Hardware Architecture (continued)

Power Management Examples Without the PLL

The following examples show the more significant options for reducing the power dissipation. These are valid only

if the pllc register is set to disable and deselect the PLL (PLLEN = 0, PLLSEL = 0).

Standard Sleep Mode. This is the standard sleep mode. While the processor is clocked with a high-speed clock,

CKI, the alf register's AWAIT bit is set. Peripheral units may be turned off to further reduce the sleep power.

powerc = 0X00F0

sleep:a0 = 0x8000

/* Turn off peripherals, core running with CKI */

/* Set alf register in cache loop if running from */

/* external memory with >1 wait state */

/* Stop internal processor clock, interrupt circuits */

/* active */

do 1 {

alf = a0

nop

}

nop

cont: .

/* Needed for bedtime execution. Only sleep power */

/* consumed here until.... interrupt wakes up the device */

/* User code executes here */

.

powerc = 0x0

/* Turn peripheral units back on */

Sleep with Slow Internal Clock. In this case, the ring oscillator is selected to clock the processor before the device

is put to sleep. This will reduce the power dissipation while waiting for an interrupt to continue program execution.

powerc = 0x40F0

2*nop

/* Turn off peripherals and select slow clock */

/* Wait for it to take effect */

sleep:a0 = 0x8000

/* Set alf register in cache loop if running from */

/* external memory with >1 wait state */

/* Stop internal processor clock, interrupt circuits */

/* active */

do 1 {

alf = a0

nop

}

nop

cont: .

/* Needed for bedtime execution. Reduced sleep power */

/* consumed here.... Interrupt wakes up the device */

/* User code executes here */

.

powerc = 0x00F0

2*nop

/* Select high-speed clock */

/* Wait for it to take effect */

powerc = 0x0000

/* Turn peripheral units back on */

Note that, in this case, the wake-up latency is determined by the period of the ring oscillator clock.

Sleep with Slow Internal Clock and Small-Signal Disabled. If the target device contains the small-signal clock

option, the clock input circuitry can be powered down to further reduce power. In this case, the slow clock must be

selected first.

powerc = 0x40F0

2*nop

/* Turn off peripherals and select slow clock */

/* Wait for it to take effect */

powerc = 0xC0F0

sleep:a0 = 0x8000

/* Turn off the small-signal input buffer */

/* Set alf register in cache loop if running from */

/* external memory with >1 wait state */

/* Stop internal processor clock, interrupt circuits */

/* active */

do 1 {

alf = a0

nop

}

nop

/* Needed for bedtime execution. Reduced sleep power */

/* consumed here.... Interrupt wakes up the device */

/* Clear XTLOFF, reenable small-signal */

/* Wait until small-signal is stable */

/* Select high-speed clock */

powerc = 0x40F0

call xtlwait

cont: powerc = 0x00F0

2*nop

/* Wait for it to take effect */

powerc = 0x0000

/* Turn peripheral units back on */

Note that, in this case, the wake-up latency is dominated by the small-signal start-up period.

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DSP1629 Digital Signal Processor

4 Hardware Architecture (continued)

Software Stop. In this case, all internal clocking is disabled. INT0, INT1, or RSTB may be used to reenable the

clocks.The power management must be done in correct sequence.

powerc = 0x4000

2*nop

/* SLOWCKI asserted */

/* Wait for it to take effect */

powerc = 0xD000

inc = NOINT0

/* XTLOFF asserted if applicable and INT0EN asserted */

/* Disable the INT0 interrupt */

sopor:powerc = 0xF000

/* NOCK asserted, all clocks stop */

/* Minimum switching power consumed here */

/* Some nops will be needed */

3*nop

/* INT0 pin clears the NOCK field, clocking resumes */

/* INT0EN cleared and XTLOFF cleared, if applicable*/

/* Wait for the small-signal to */

cont: powerc = 0x4000

call waitxtl

/* stabilize, if applicable*/

powerc = 0x0

2*nop

/* Clear SLOWCKI field, back to high speed */

/* Wait for it to take effect */

ins = 0x0010

/* Clear the INT0 status bit */

In this case also, the wake-up latency is dominated by the small-signal start-up period.

The previous examples do not provide an exhaustive list of options available to the user. Many different clocking

possibilities exist for which the target device may be programmed, depending on:

■ The clock source to the processor.

■ Whether the user chooses to power down the peripheral units.

■ The operational state of the small-signal clock input, powered or unpowered.

■ Whether the internal processor clock is disabled through hardware or software.

■ The combination of power management modes the user chooses.

■ Whether or not the PLL is enabled.

An example subroutine for xtlwait follows:

xtlwait:

timer0 = 0x2710

timerc = 0x0010

inc = 0x0000

a0 = ins

/* Load a count of 10,000 into the timer */

/* Start the timer with a PRESCALE of two */

/* Disable the interrupts

/* Poll the ins register

*/

loop1:

a0 = a0 & 0x0100 /* Check bit 8 (TIME) of the ins register */

if eq goto loop1 /* Loop if the bit is not set

*/

ins = 0x0100

return

/* Clear the TIME interrupt bit

/* Return to the main program

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Data Sheet

January 2002

DSP1629 Digital Signal Processor

4 Hardware Architecture (continued)

Power Management Examples with the PLL

The following examples show the more significant options for reducing power dissipation if operation with the PLL

clock synthesizer is desired.

Standard Sleep Mode, PLL Running. This mode would be entered in the same manner as without the PLL. While

the input to the clock synthesizer, CKI, remains running, the alf register's AWAIT bit is set. The PLL will continue to

run and dissipate power. Peripheral units may be turned off to further reduce the sleep power.

powerc = 0x00F0

sleep:a0 = 0x8000

/* Turn off peripherals, core running with PLL */

/* Set alf register in cache loop if running from */

/* external memory with >1 wait state */

/* Stop internal processor clock, interrupt circuits */

/* active */

do 1 {

alf = a0

nop

}

nop

/* Needed for bedtime execution. Only sleep power plus PLL */

/* power consumed here.... Interrupt wakes up the device */

/* User code executes here */

cont: . . .

powerc = 0x0

/* Turn peripheral units back on */

Sleep with Slow Internal Clock, PLL Running. In this case, the ring oscillator is selected to clock the processor

before the device is put to sleep. This will reduce power dissipation while waiting for an interrupt to continue program

execution.

powerc = 0x40F0

2*nop

sleep:a0 = 0x8000

/* Turn off peripherals and select slow clock */

/* Wait for slow clock to take effect */

/* Set alf register in cache loop if running from */

/* external memory with >1 wait state */

/* Stop internal processor clock, interrupt circuits */

/* active */

do 1 {

alf = a0

nop

}

nop

/* Needed for bedtime execution. Reduced sleep power, PLL */

/* power, and ring oscillator power consumed here... */

/* Interrupt wakes up the device */

cont: . . .

/* User code executes here */

powerc = 0x00F0

2*nop

/* Select high-speed PLL based clock */

/* Wait for it to take effect */

powerc = 0x0000

/* Turn peripheral units back on */

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Data Sheet

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DSP1629 Digital Signal Processor

4 Hardware Architecture (continued)

Sleep with Slow Internal Clock and Small-Signal Disabled, PLL Disabled. If the target device contains the small-

signal clock option, the clock input circuitry can be powered down to further reduce power. In this case, the slow

clock must be selected first, and then the PLL must be disabled, since the PLL cannot run without the clock input

circuitry being active.

powerc = 0x40F0

2*nop

pllc = 0x29F2

powerc = 0xC0F0

/* Turn off peripherals and select slow clock */

/* Wait for slow clock to take effect */

/* Disable PLL (assume N = 1,M = 20, LF = 1001) */

/* Disable small-signal input buffer */

/* Set alf register in cache loop if running from */

/* external memory with >1 wait state */

/* Stop internal processor clock, interrupt circuits */

/* active */

sleep:a0 = 0x8000

do 1 {

alf = a0

nop

}

nop

/* Needed for bedtime execution. Reduced sleep power

/* consumed here.... Interrupt wakes up device */

/* Clear XTLOFF, leave PLL disabled */

/* Wait until small-signal is stable */

/* Enable PLL, continue to run off slow clock */

/* Loop to check for LOCK flag assertion */

/* Select high-speed PLL based clock */

/* Wait for it to take effect */

powerc = 0x40F0

call xtlwait

pllc = 0xE9F2

call pllwait

cont: powerc = 0x00F0

2*nop

powerc = 0x0000

/* Turn peripherals back on */

Software Stop, PLL Disabled. In this case, all internal clocking is disabled. INT0, INT1, or RSTB may be used to

reenable the clocks. The power management must be done in the correct sequence, with the PLL being disabled

before shutting down the clock input buffer.

powerc = 0x4000

2*nop

pllc = 0x29F2

powerc = 0xD000

/* SLOWCKI asserted */

/* Wait for slow clock to take effect */

/* Disable PLL (assume N = 1, M = 20, LF = 1001) */

/* XTLOFF asserted, if applicable and INT0EN

/* asserted */

sopor:powerc = 0xF000

3*nop

/* NOCK asserted, all clocks stop */

/* Minimum switching power consumed here */

/* Some nops will be needed */

/* INT0 pin clears NOCK field, clocking resumes */

/* INTOEN cleared and XTLOFF cleared, if applicable */

/* Wait until small-signal is stable */

/* if applicable */

cont: powerc = 0x4000

call xtlwait

pllc = 0xE9F2

call pllwait

powerc = 0x0

2*nop

/* Enable PLL, continue to run off slow clock */

/* Loop to check for LOCK flag assertion */

/* Select high-speed PLL based clock */

/* Wait for it to take effect */

ins = 0x0010

/ * Clear the INT0 status bit */

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Data Sheet

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DSP1629 Digital Signal Processor

Multiply/ALU Instructions

5 Software Architecture

Note that the function statements and transfer state-

ments in Table 13, Multiply/ALU Instructions, are cho-

sen independently. Any function statement (F1) can be

combined with any transfer statement to form a valid

multiply/ALU instruction. If either statement is not re-

quired, a single statement from either column also con-

stitutes a valid instruction. The number of cycles to

execute the instruction is a function of the transfer col-

umn. (An instruction with no transfer statement exe-

cutes in one instruction cycle.) Whenever PC, pt, or rM

is used in the instruction and points to external memory,

the programmed number of wait-states must be added

to the instruction cycle count. All multiply/ALU instruc-

tions require one word of program memory. The no-op-

eration (nop) instruction is a special-case encoding of a

multiply/ALU instruction and executes in one cycle. The

assembly-language representation of a nop is either

nop or a single semicolon.

5.1 Instruction Set

The DSP1629 processor has seven types of instruc-

tions: multiply/ALU, special function, control, F3 ALU,

BMU, cache, and data move. The multiply/ALU instruc-

tions are the primary instructions used to implement sig-

nal processing algorithms. Statements from this group

can be combined to generate multiply/accumulate, log-

ical, and other ALU functions and to transfer data be-

tween memory and registers in the data arithmetic unit.

The special function instructions can be conditionally

executed based on flags from the previous ALU or BMU

operation, the condition of one of the counters, or the

value of a pseudorandom bit in the DSP1629 device.

Special function instructions perform shift, round, and

complement functions. The F3 ALU instructions enrich

the operations available on accumulators. The BMU in-

structions provide high-performance bit manipulation.

The control instructions implement the goto and call

commands. Control instructions can also be executed

conditionally. Cache instructions are used to implement

low-overhead loops, conserve program memory, and

decrease the execution time of certain multiply/ALU in-

structions. Data move instructions are used to transfer

data between memory and registers or between accu-

mulators and registers. See the DSP1611/17/18/27/28/

29 Digital Signal Processor Information Manual for a de-

tailed description of the instruction set.

A single-cycle squaring function is provided in

DSP1629. By setting the X = Y = bit in the auc register,

any instruction that loads the high half of the y register

also loads the x register with the same value. A subse-

quent instruction to multiply the x register and y register

results in the square of the value being placed in the p

register. The instruction a0 = p p = x*y y = *r0++ with

the X = Y = bit set to one will read the value pointed to

by r0, load it to both x and y, multiply the previously

fetched value of x and y, and transfer the previous prod-

uct to a0. A table of values pointed to by r0 can thus be

squared in a pipeline with one instruction cycle per each

value. Multiply/ALU instructions that use x = X transfer

statements (such as a0 = p p = x*y y = *r0++ x = *pt++)

are not recommended for squaring because pt will be

incremented even though x is not loaded from the value

pointed to by pt. Also, the same conflict wait occurs from

reading the same bank of internal memory or reading

from external memory apply, since the X space fetch

occurs (even though its value is not used).

The following operators are used in describing the in-

struction set:

■ *

16 x 16-bit –> 32-bit multiplication or register-

indirect addressing when used as a prefix to an

address register or denotes direct addressing

when used as a prefix to an immediate

■ +

36-bit addition^†

■ –

36-bit subtraction^†

Arithmetic right shift

■ >>

■ >>> Logical right shift

■ << Arithmetic left shift

■ <<< Logical left shift

■ |

36-bit bitwise OR^†

■ &

36-bit bitwise AND^†

■ ^

■ :

36-bit bitwise EXCLUSIVE OR^†

Compound address swapping, accumulator

shuffling

■ ~

One's complement

†

These are 36-bit operations. One operand is 36-bit data in an ac-

cumulator; the other operand may be 16 bits, 32 bits, or 36 bits.

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DSP1629 Digital Signal Processor

5 Software Architecture (continued)

Table 13. Multiply/ALU Instructions

Function Statement

Transfer Statement^†

Cycles (Out/In Cache)^‡

p = x y

y = Y

x = X

2/1

1/1

*

aD = p

p = x y

y = aT

*

aD = aS + p

aD = aS – p

p = x y

y[l] = Y

*

p = x y

aT[l] = Y

*

aD = p

x = Y

Y

1/1

2/2

aD = aS + p

aD = aS – p

aD = y

Y = y[l]

Y = aT[l]

aD = aS + y

aD = aS – y

aD = aS & y

aD = aS | y

aD = aS ^ y

aS – y

Z:y

x = X

Z:y[l]

Z:aT[l]

aS & y

† The l in [ ] is an optional argument that specifies the low 16 bits of aT or y.

‡ Add cycles for:

1. When an external memory access is made in X or Y space and wait-states are programmed, add the number of wait-states.

2. If an X-space access and a Y-space access are made to the same bank of DPRAM in one instruction, add one cycle.

Note: For transfer statements when loading the upper half of an accumulator, the lower half is cleared if the corre-

sponding CLR bit in the auc register is zero. auc is cleared by reset.

Table 14. Replacement Table for Multiply/ALU Instructions

Replace

aD, aS, aT

X

Value

a0, a1

Meaning

One of two DAU accumulators.

*pt++, *pt++i

X memory space location pointed to by pt. pt is postmodified by +1 and

i, respectively.

Y

Z

*rM, *rM++, *rM--, rM++j

RAM location pointed to by rM (M = 0, 1, 2, 3). rM is postmodified by

0, +1, –1, or j, respectively.

*rMzp, *rMpz, *rMm2, *rMjk Read/write compound addressing. rM (M = 0, 1, 2, 3) is used twice.

First, postmodified by 0, +1, –1, or j, respectively; and, second, post-

modified by +1, 0, +2, or k, respectively.

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Data Sheet

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DSP1629 Digital Signal Processor

5 Software Architecture (continued)

Special Function Instructions

All forms of the special function require one word of program memory and execute in one instruction cycle. (If PC

points to external memory, add programmed wait-states.)

aD = aS >> 1

aD = aS >> 4

aD = aS >> 8

aD = aS >> 16

}

Arithmetic right shift (sign preserved) of 36-bit accumulators

aD = aS

Load destination accumulator from source accumulator

2's complement

aD = –aS

aD = ~aS*

1's complement

aD = rnd(aS) Round upper 20 bits of accumulator

aDh = aSh + 1 Increment upper half of accumulator (lower half cleared)

aD = aS + 1

aD = y

Increment accumulator

Load accumulator with 32-bit y register value with sign extend

Load accumulator with 32-bit p register value with sign extend

aD = p

aD = aS << 1

}

aD = aS << 4

aD = aS << 8

aD = aS << 16

Arithmetic left shift (sign not preserved) of the lower 32 bits of accumulators

(upper 4 bits are sign-bit-extended from bit 31 at the completion of the shift)

The above special functions can be conditionally executed, as in:

if CON instruction

and with an event counter:

ifc CON instruction

which means:

if CON is true then

c1 = c1 + 1

instruction

c2 = c1

else

c1 = c1 + 1

The above special function statements can be executed unconditionally by writing them directly, e.g., a0 = a1.

Table 15. Replacement Table for Special Function Instructions

Replace

aD

Value

a0, a1

Meaning

One of two DAU accumulators.

aS

CON

mi, pl, eq, ne, gt, le, lvs, lvc, mvs, mvc, c0ge,

See Table 17, DSP1629 Conditional Mne-

c0lt, c1ge, c1lt, heads, tails, true, false, allt, allf, monics, for definitions of mnemonics.

somet, somef, oddp, evenp, mns1, nmns1, npint,

njint, lock

*

This function is not available for the DSP16A.

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DSP1629 Digital Signal Processor

5 Software Architecture (continued)

Control Instructions

All control instructions executed unconditionally execute in two cycles, except icall, which takes three cycles. Control

instructions executed conditionally execute in three instruction cycles. (If PC, pt, or pr point to external memory, add

programmed wait-states.) Control instructions executed unconditionally require one word of program memory, while

control instructions executed conditionally require two words. Control instructions cannot be executed from the

cache.

goto JA^†

goto pt

call JA^†

call pt

icall^‡

return

ireturn

(goto pr)

(goto pi)

†

‡

The goto JA and call JA instructions should not be placed in the last or next-to-last instruction before the boundary of a 4 Kwords page. If

the goto or call is placed there, the program counter will have incremented to the next page and the jump will be to the next page, rather than

to the desired current page.

The icall instruction is reserved for development system use.

The above control instructions, with the exception of ireturn and icall, can be conditionally executed. For example:

if le goto 0x0345

Table 16. Replacement Table for Control Instructions

Replace

Value

Meaning

CON

mi, pl, eq, ne, gt, le, nlvs, lvc, mvs, mvc, c0ge, c0lt, See Table 17, DSP1629 Conditional Mne-

c1ge, c1lt, heads, tails, true, false, allt, allf, somet,

somef, oddp, evenp, mns1, nmns1, npint, njint, lock

monics, for definitions of mnemonics.

JA

12-bit value

Least significant 12 bits of absolute address

within the same 4 Kwords memory section.

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Data Sheet

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DSP1629 Digital Signal Processor

5 Software Architecture (continued)

Conditional Mnemonics (Flags)

Table 17, DSP1629 Conditional Mnemonics, lists mnemonics used in conditional execution of special function and

control instructions.

Table 17. DSP1629 Conditional Mnemonics

Test

pl

Meaning

Result is nonnegative (sign bit is bit 35) (≥0).

Result is equal to 0 (=0).

Test

mi

Meaning

Result is negative (<0).

eq

ne

Result is not equal to 0 (≠0).

Result is less than or equal to 0 (≤0).

Logical overflow clear.

gt

Result is greater than 0 (>0).

Logical overflow set.^*

Mathematical overflow set.^†

le

lvs

mvs

lvc

mvc

c0lt

c1lt

tails

false

Mathematical overflow clear.

Counter 0 less than 0.

c0ge Counter 0 greater than or equal to 0.

c1ge Counter 1 greater than or equal to 0.

heads Pseudorandom sequence bit set.

Counter 1 less than 0.

Pseudorandom sequence bit clear.

true

The condition is always satisfied in an if in-

struction.

The condition is never satisfied in an if instruc-

tion.

allt

All true, all BIO input bits tested compared

successfully.

allf

All false, no BIO input bits tested compared

successfully.

somet Some true, some BIO input bits tested com-

pared successfully.

somef Some false, some BIO input bits tested did not

compare successfully.

oddp Odd parity, from BMU operation.

mns1 Minus 1, result of BMU operation.

evenp Even parity, from BMU operation.

nmns1 Not minus 1, result of BMU operation.

npint Not PINT, used by hardware development

system.

njint

Not JINT, used by hardware development

system.

lock

The PLL has achieved lock and is stable.

—

* Result is not representable in the 36-bit accumulators (36-bit overflow).

† Bits 35—31 are not the same (32-bit overflow).

Notes:

Testing the state of the counters (c0 or c1) automatically increments the counter by one.

The heads or tails condition is determined by a randomly set or cleared bit, respectively. The bit is randomly set with a probability of 0.5. A random

rounding function can be implemented with either heads or tails. The random bit is generated by a ten-stage pseudorandom sequence generator

(PSG) that is updated after either a heads or tails test. The pseudorandom sequence may be reset by writing any value to the pi register, except

during an interrupt service routine (ISR). While in an ISR, writing to the pi register updates the register and does not reset the PSG. If not in an

ISR, writing to the pi register resets the PSG. (The pi register is updated, but will be written with the contents of the PC on the next instruction.)

Interrupts must be disabled when writing to the pi register. If an interrupt is taken after the pi write, but before pi is updated with the PC value,

the ireturn instruction will not return to the correct location. If the RAND bit in the auc register is set, however, writing the pi register never resets

the PSG.

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Data Sheet

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DSP1629 Digital Signal Processor

5 Software Architecture (continued)

F3 ALU Instructions

These instructions are implemented in the DSP1600 core. They allow accumulator two-operand operations with ei-

ther another accumulator, the p register, or a 16-bit immediate operand (IM16). The result is placed in a destination

accumulator that can be independently specified. All operations are done with the full 36 bits. For the accumulator

with accumulator operations, both inputs are 36 bits. For the accumulator with p register operations, the p register

is sign-extended into bits 35—32 before the operation. For the accumulator high with immediate operations, the im-

mediate is sign-extended into bits 35—32 and the lower bits 15—0 are filled with zeros, except for the AND opera-

tion, because they are filled with ones. These conventions allow the user to do operations with 32-bit immediates by

programming two consecutive 16-bit immediate operations. The F3 ALU instructions are shown in Table 18, F3 ALU

Instructions.

Table 18. F3 ALU Instructions

F3 ALU Instructions*

Not Cacheable (Two-Cycle)^†

Cacheable (One-Cycle)

aD = aS + aT

aD = aS – aT

aD = aS & aT

aD = aS | aT

aD = aS ^ aT

aS – aT

aD = aSh + IM16

aD = aSh – IM16

aD = aSh & IM16

aD = aSh | IM16

aD = aSh ^ IM16

aSh – IM16

aS & aT

aSh & IM16

aD = aS + p

aD = aS – p

aD = aS & p

aD = aS | p

aD = aS ^ p

aS – p

aD = aSl + IM16

aD = aSl – IM16

aD = aSl & IM16

aD = aSl | IM16

aD = aSl ^ IM16

aSl – IM16

aS & p

aSl & IM16

*

If PC points to external memory, add programmed wait-states.

†

The h and l are required notation in these instructions.

Note: The F3 ALU instructions that do not have a destination accumulator are used to set flags for conditional operations, i.e., bit test operations.

F4 BMU Instructions

The bit manipulation unit in the DSP1629 provides a set of efficient bit manipulation operations on accumulators. It

contains four auxiliary registers, ar<0—3> (arM, M = 0, 1, 2, 3), two alternate accumulators (aa0—aa1), which can

be shuffled with the working set, and four flags (oddp, evenp, mns1, and nmns1). The flags are testable by condi-

tional instructions and can be read and written via bits 4—7 of the alf register. The BMU also sets the LMI, LEQ,

LLV, and LMV flags in the psw register.

LMI = 1 if negative (i.e., bit 35 = 1)

LEQ = 1 if zero (i.e., bits 35—0 are 0)

LLV = 1 if (a) 36-bit overflow, or if (b) illegal shift on field width/offset condition

LMV = 1 if bits 31—35 are not the same (32-bit overflow)

The BMU instructions and cycle times follow. (If PC points to external memory, add programmed wait-states.) All

BMU instructions require 1 word of program memory unless otherwise noted. Please refer to the DSP1611/17/18/

27/28/29 Digital Signal Processor Information Manual for further discussion of the BMU instructions.

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DSP1629 Digital Signal Processor

5 Software Architecture (continued)

■ Barrel Shifter:

aD = aS >> IM16

aD = aS >> arM

aD = aS >> aS

Arithmetic right shift by immediate (36-bit, sign filled in); 2-cycle, 2-word.

Arithmetic right shift by arM (36-bit, sign filled in); 1-cycle.

Arithmetic right shift by aS (36-bit, sign filled in); 2-cycle.

aD = aS >>> IM16

aD = aS >>> arM

aD = aS >>> aS

Logical right shift by immediate (32-bit shift, 0s filled in); 2-cycle, 2-word.

Logical right shift by arM (32-bit shift, 0s filled in); 1-cycle.

Logical right shift by aS (32-bit shift, 0s filled in); 2-cycle.

aD = aS << IM16

aD = aS << arM

aD = aS << aS

Arithmetic left shift^†by immediate (36-bit shift, 0s filled in); 2-cycle, 2-word.

Arithmetic left shift^†by arM (36-bit shift, 0s filled in); 1-cycle.

Arithmetic left shift^†by aS (36-bit shift, 0s filled in); 2-cycle.

aD = aS <<< IM16

aD = aS <<< arM

aD = aS <<< aS

Logical left shift by immediate (36-bit shift, 0s filled in); 2-cycle, 2-word.

Logical left shift by arM (36-bit shift, 0s filled in); 1-cycle.

Logical left shift by aS (36-bit shift, 0s filled in); 2-cycle.

†

Not the same as the special function arithmetic left shift. Here, the guard bits in the destination accumulator are shifted into, not sign-extended.

■ Normalization and Exponent Computation:

aD = exp(aS)

Detect the number of redundant sign bits in accumulator; 1-cycle.

aD = norm(aS, arM)

Normalize aS with respect to bit 31, with exponent in arM; 1-cycle.

■ Bit Field Extraction and Insertion:

aD = extracts(aS, IM16) Extraction with sign extension, field specified as immediate; 2-cycle, 2-word.

aD = extracts(aS, arM) Extraction with sign extension, field specified in arM; 1-cycle.

aD = extractz(aS, IM16) Extraction with zero extension, field specified as immediate; 2-cycle, 2-word.

aD = extractz(aS, arM) Extraction with zero extension, field specified in arM; 1-cycle.

aD = insert(aS, IM16) Bit field insertion, field specified as immediate; 2-cycle, 2-word.

aD = insert(aS, arM)

Bit field insertion, field specified in arM; 2-cycle.

Note: The bit field to be inserted or extracted is specified as follows. The width (in bits) of the field is the upper byte

of the operand (immediate or arM), and the offset from the LSB is in the lower byte.

■ Alternate Accumulator Set:

aD = aS:aa0

Shuffle accumulators with alternate accumulator 0 (aa0); 1-cycle.

aD = aS:aa1

Shuffle accumulators with alternate accumulator 1 (aa1); 1-cycle.

Note: The alternate accumulator gets what was in aS. aD gets what was in the alternate accumulator.

Table 19. Replacement Table for F3 ALU Instructions and F4 BMU Instructions

Replace

aD, aT, aS

IM16

Value

Meaning

One of the two accumulators.

a0 or a1

immediate

ar<0—3>

16-bit data, sign-, zero-, or one-extended as appropriate.

One of the auxiliary BMU registers.

arM

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Data Sheet

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DSP1629 Digital Signal Processor

5 Software Architecture (continued)

Cache Instructions

Cache instructions require one word of program memory. The do instruction executes in one instruction cycle, and

the redo instruction executes in two instruction cycles. (If PC points to external memory, add programmed wait-

states.) Control instructions and long immediate values cannot be stored inside the cache. The instruction formats

are as follows:

■ do K {

■ instr1

■ instr2

■ .

■ instrN

■ }

■ redo K

Table 20. Replacement Table for Cache Instructions

Replace

Instruction

Encoding

Meaning

cloop^†

K

Number of times the instructions are to be executed taken from bits 0—6 of the cloop

register.

1 to 127

1 to 15

Number of times the instructions to be executed are encoded in the instruction.

1 to 15 instructions can be included.

N

† The assembly-language statement, do cloop (or redo cloop), is used to specify that the number of iterations is to be taken from the cloop

register. K is encoded as 0 in the instruction encoding to select cloop.

When the cache is used to execute a block of instructions, the cycle timings of the instructions are as follows:

1. In the first pass, the instructions are fetched from program memory and the cycle times are the normal out-of-

cache values, except for the last instruction in the block of N instructions. This instruction executes in two cycles.

2. During pass two through pass K – 1, each instruction is fetched from cache and the in-cache timings apply.

3. During the last (Kth) pass, the block of instructions is fetched from cache and the in-cache timings apply, except

that the timing of the last instruction is the same as if it were out-of-cache.

4. If any of the instructions access external memory, programmed wait-states must be added to the cycle counts.

The redo instruction treats the instructions currently in the cache memory as another loop to be executed K times.

Using the redo instruction, instructions are reexecuted from the cache without reloading the cache.

The number of iterations, K, for a do or redo can be set at run time by first moving the number of iterations into the

cloop register (7 bits unsigned), and then issuing the do cloop or redo cloop. At the completion of the loop, the

value of cloop is decremented to 0; hence, cloop needs to be written before each do cloop or redo cloop.

44

Agere Systems Inc.

Data Sheet

January 2002

DSP1629 Digital Signal Processor

5 Software Architecture (continued)

Data Move Instructions

Data move instructions normally execute in two instruction cycles. (If PC or rM point to external memory, any pro-

grammed wait-states must be added. In addition, if PC and rM point to the same bank of DPRAM, then one cycle

must be added.) Immediate data move instructions require two words of program memory; all other data move in-

structions require only one word. The only exception to these statements is a special case immediate load (short

immediate) instruction. If a YAAU register is loaded with a 9-bit short immediate value, the instruction requires only

one word of memory and executes in one instruction cycle. All data move instructions, except those doing long im-

mediate loads, can be executed from within the cache. The data move instructions are as follows:

■ R = IM16

■ aT[l] = R

■ SR = IM9

■ Y = R

■ R = Y

■ Z:R

■ R = aS[l]

■ DR = *(OFFSET)

■ (OFFSET) = DR

Table 21. Replacement Table for Data Move Instructions

Replace

Value

Meaning

R

Any of the registers in Table 51,

R Field

—

DR

r<0—3>, a0[l], a1[l], y[l], p, pl, x, Subset of registers accessible with direct addressing.

pt, pr, psw

aS, aT

a0, a1

rM, rM++, rM--, rM++j

High half of accumulator.

Y

Z

Same as in multiply/ALU instructions.

*

rMzp, rMpz, rMm2, rMjk

*

IM16

IM9

16-bit value

9-bit value

Long immediate data.

Short immediate data for YAAU registers.

OFFSET

5-bit value from instruction

11-bit value in base register

Value in bits [15:5] of ybase register form the 11 most significant

bits of the base address. The 5-bit offset is concatenated to this to

form a 16-bit address.

SR

r<0—3>, rb, re, j, k

Subset of registers for short immediate.

Notes:

sioc, sioc2, tdms, tdms2, srta, and srta2 registers are not readable.

When signed registers less than 16 bits wide (c0, c1, c2) are read, their contents are sign-extended to 16 bits. When unsigned registers less than

16 bits wide are read, their contents are zero-extended to 16 bits.

Loading an accumulator with a data move instruction does not affect the flags.

Agere Systems Inc.

45

Data Sheet

January 2002

DSP1629 Digital Signal Processor

5 Software Architecture (continued)

5.2 Register Settings

Table 22, Serial I/O Control Registers, through Table 38, ioc Register, describe the programmable registers of the

DSP1629 device. Table 40, Register Settings After Reset, describes the register settings after reset.

Note that the following abbreviations are used in the tables:

■ x = don't care

■ R = read only

■ W = read/write

The reserved (RSVD) bits in the tables should always be written with zeros to make the program compatible with

future chip versions.

Table 22. Serial I/O Control Registers

sioc

Bit

10

9

8

7

6

5

4

3

2

1

0

Field DODLY

LD

CLK

MSB

OLD

ILD

OCK

ICK

OLEN ILEN

Field

DODLY

Value

Description

DO changes on the rising edge of OCK.

DO changes on the falling edge of OCK. This delay in driving DO increases the hold

0

1

time on DO by half a cycle of OCK.

In active mode, ILD1 and/or OLD1 = ICK1/16, active SYNC1 = ICK1/[128/256*].

In active mode, ILD1 and/or OLD1 = OCK1/16, active SYNC1 = OCK1/[128/256*].

Active clock = CKI/2 (1X).

Active clock = CKI/6 (1X).

Active clock = CKI/8 (1X).

Active clock = CKI/10 (1X).

LSB first.

MSB first.

OLD1 is an input (passive mode).

OLD1 is an output (active mode).

ILD1 is an input (passive mode).

ILD1 is an output (active mode).

OCK1 is an input (passive mode).

OCK1 is an output (active mode).

ICK1 is an input (passive mode).

ICK1 is an output (active mode).

16-bit output.

LD

0

1

CLK

00

01

10

11

0

1

0

1

0

1

0

1

0

1

0

1

0

MSB

OLD

ILD

OCK

ICK

OLEN

ILEN

8-bit output.

16-bit input.

1

8-bit input.

sioc2^†

Bit

10

9

8

7

6

5

4

3

2

1

0

Field DODLY2

LD2

CLK2

MSB2

OLD2

ILD2

OCK2

ICK2 OLEN2 ILEN2

* See tdms register, SYNC field.

† The bit definitions of the sioc2 register are identical to the sioc register bit definitions.

46

Agere Systems Inc.

Data Sheet

January 2002

DSP1629 Digital Signal Processor

5 Software Architecture (continued)

Table 23. Time-Division Multiplex Slot Registers

tdms

Bit

9

8

7

6

5

4

3

2

1

0

Field

SYNCSP

MODE

TRANSMIT SLOT

SYNC

Field

Value

Description

0^†

SYNCSP*

SYNC1 = ICK1/128 if LD = 0*.

SYNC1 = OCK1/128 if LD = 1*.

SYNC1 = ICK1/256 if LD = 0*.

SYNC1 = OCK1/256 if LD = 1*.

1

MODE

0

Multiprocessor mode off; DOEN1 is an input (passive mode).

Multiprocessor mode on; DOEN1 is an output (active mode).

Transmit slot 7.

1

TRANSMIT SLOT

1xxxxxx

x1xxxxx

xx1xxxx

xxx1xxx

xxxx1xx

xxxxx1x

xxxxxx1

1

Transmit slot 6.

Transmit slot 5.

Transmit slot 4.

Transmit slot 3.

Transmit slot 2.

Transmit slot 1.

SYNC

Transmit slot 0, SYNC1 is an output (active mode).

SYNC1 is an input (passive mode).

0

tdms2^‡

Bit

9

8

7

6

5

4

3

2

1

0

Field

*

MODE2

TRANSMIT SLOT2

SYNC2

SYNCSP2

* See sioc register, LD field.

† Select this mode when in multiprocessor mode.

‡ The tdms2 register bit definitions are identical to the tdms register bit definitions.

Agere Systems Inc.

47

Data Sheet

January 2002

DSP1629 Digital Signal Processor

5 Software Architecture (continued)

Table 24. Serial Receive/Transmit Address Registers

srta

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Field

RECEIVE ADDRESS

TRANSMIT ADDRESS

Field

Value

Description

RECEIVE ADDRESS

1xxxxxxx

x1xxxxxx

xx1xxxxx

xxx1xxxx

xxxx1xxx

xxxxx1xx

xxxxxx1x

xxxxxxx1

Receive address 7.

Receive address 6.

Receive address 5.

Receive address 4.

Receive address 3.

Receive address 2.

Receive address 1.

Receive address 0.

Transmit address 7.

Transmit address 6.

Transmit address 5.

Transmit address 4.

Transmit address 3.

Transmit address 2.

Transmit address 1.

Transmit address 0.

TRANSMIT ADDRESS

1xxxxxxx

x1xxxxxx

xx1xxxxx

xxx1xxxx

xxxx1xxx

xxxxx1xx

xxxxxx1x

xxxxxxx1

srta2^*

Bit

Field

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

RECEIVE ADDRESS2

TRANSMIT ADDRESS2

* The srta2 field definitions are identical to the srta register field definitions.

Table 25. Multiprocessor Protocol Registers

saddx

Bit Field

Write

15—8

7—0

X

Write Protocol Field [7:0]

0

Read

Read Protocol Field [7:0]

saddx2^†

Bit Field

Write

15—8

7—0

X

Write Protocol2 Field [7:0]

0

Read

Read Protocol2 Field [7:0]

† The saddx2 field definitions are identical to the saddx register field definitions.

48

Agere Systems Inc.

Data Sheet

January 2002

DSP1629 Digital Signal Processor

5 Software Architecture (continued)

Table 26. Processor Status Word (psw) Register

Bit

15

14

13

12

11

X

10

X

9

8

7

6

5

4

3

2

1

0

Field

DAU FLAGS

a1[V]

a1[35:32]

a0[V]

a0[35:32]

Field

DAU FLAGS^*

Value

Wxxx

xWxx

xxWx

xxxW

W

Description

LMI—logical minus when set (bit 35 = 1).

LEQ—logical equal when set (bit [35:0] = 0).

LLV—logical overflow when set.

LMV—mathematical overflow when set.

Accumulator 1 (a1) overflow when set.

Accumulator 1 (a1) bit 35.

a1[V]

a1[35:32]

Wxxx

xWxx

xxWx

xxxW

W

Accumulator 1 (a1) bit 34.

Accumulator 1 (a1) bit 33.

Accumulator 1 (a1) bit 32.

a0[V]

Accumulator 0 (a0) overflow when set.

Accumulator 0 (a0) bit 35.

a0[35:32]

Wxxx

xWxx

xxWx

xxxW

Accumulator 0 (a0) bit 34.

Accumulator 0 (a0) bit 33.

Accumulator 0 (a0) bit 32.

* The DAU flags can be set by either BMU or DAU operations.

Table 27. Arithmetic Unit Control (auc) Register^†

Bit

8

7

6

5

4

3

2

1

0

Field

RAND

X=Y=

CLR

SAT

ALIGN

Field

Value

Description

RAND

X=Y=

CLR

0

Pseudorandom sequence generator (PSG) reset by writing the pi

register only outside an interrupt service routine.

PSG never reset by writing the pi register.

1

0

1

Normal operation.

All instructions which load the high half of the y register also load

the x register, allowing single-cycle squaring with p = x * y.

1xx

x1x

xx1

1x

Clearing yl is disabled (enabled when 0).

Clearing a1l is disabled (enabled when 0).

Clearing a0l is disabled (enabled when 0).

a1 saturation on overflow is disabled (enabled when 0).

a0 saturation on overflow is disabled (enabled when 0).

a0, a1 ← p.

SAT

x1

ALIGN

00

01

a0, a1 ← p/4.

10

a0, a1 ← p x 4 (and zeros written to the two LSBs).

a0, a1 ← p x 2 (and zero written to the LSB).

11

† The auc is 9 bits [8:0]. The upper 7 bits [15:9] are always zero when read and should always be written with zeros to make the program

compatible with future chip versions. The auc register is cleared at reset.

Agere Systems Inc.

49

Data Sheet

January 2002

DSP1629 Digital Signal Processor

5 Software Architecture (continued)

Table 28. Parallel Host Interface Control (phifc) Register

Bit

15—7

RSVD

6

5

4

3

2

1

0

Field

PSOBEF

PFLAGSEL

PFLAG

PBSELF

PSTRB

PSTROBE

PMODE

Field

Value

Description

PMODE

PSTROBE

PSTRB

0

1

8-bit data transfers.

16-bit data transfers.

0

1

Intel protocol: PIDS and PODS data strobes.

Motorola protocol: PRWN and PDS data strobes.

0

1

When PSTROBE = 1, PODS pin (PDS) active-low.

When PSTROBE = 1, PODS pin (PDS) active-high.

PBSELF

0

1

In either mode, PBSEL pin = 0 → pdx0 low byte. See Table 7, PHIF Func-

tion (8-bit and 16-bit Modes).

If PMODE = 0, PBSEL pin = 1 → pdx0 low byte.

If PMODE = 1, PBSEL pin = 0 → pdx0 high byte.

PFLAG

0

1

PIBF and POBE pins active-high.

PIBF and POBE pins active-low.

PFLAGSEL

0

1

Normal.

PIBF flag ORed with POBE flag and output on PIBF pin; POBE pin un-

changed (output buffer empty).

PSOBEF

0

1

Normal.

POBE flag as read through PSTAT register is active-low.

Table 29. Interrupt Control (inc) Register

Bit

15

14—11

RSVD

10

9

8

7—6

5—4

3

2

1

0

Field

JINT*

OBE2

IBF2

TIME RSVD INT[1:0]

PIBF

POBE

OBE

IBF

*

JINT is a JTAG interrupt and is controlled by the HDS. It may be made unmaskable by the Agere Systems development system tools.

Encoding: a 0 disables an interrupt; a 1 enables an interrupt.

Table 30. Interrupt Status (ins) Register

Bit

15

14—11

RSVD

10

9

8

7—6

5—4

3

2

1

0

Field

JINT

OBE2

IBF2

TIME RSVD

INT[1:0]

PIBF

POBE

OBE

IBF

Encoding: a 0 indicates no interrupt. A 1 indicates an interrupt has been recognized and is pending or being ser-

viced. If a 1 is written to bits 4, 5, or 8 of ins, the corresponding interrupt is cleared.

50

Agere Systems Inc.

Data Sheet

January 2002

DSP1629 Digital Signal Processor

5 Software Architecture (continued)

Table 31. timerc Register

Bit

15—7

RSVD

6

5

4

3—0

Field

DISABLE

RELOAD

T0EN

PRESCALE

Field

Value

Description

DISABLE

RELOAD

T0EN

0

1

Timer enabled.

Timer and prescaler disabled. The period register and timer0 are not reset.

0

1

Timer stops after counting down to 0.

Timer automatically reloads and repeats indefinitely.

0

1

Timer holds current count.

Timer counts down to 0.

PRESCALE

—

See the PRESCALE Field table.

PRESCALE Field

PRESCALE

Frequency of

PRESCALE

Frequency of

Timer Interrupts

0000

0001

0010

0011

0100

0101

0110

0111

CKO/2

CKO/4

1000

1001

1010

1011

1100

1101

1110

1111

CKO/512

CKO/1024

CKO/2048

CKO/4096

CKO/8192

CKO/16384

CKO/32768

CKO/65536

CKO/8

CKO/16

CKO/32

CKO/64

CKO/128

CKO/256

Table 32. Phase-Locked Loop Control (pllc) Register

Bit

15

14

13

12

RSVD

11—8

7—5

Nbits[2:0]

4—0

Field

PLLEN

PLLSEL

ICP

LF[3:0]

Mbits[4:0]

Field

Value

Description

PLLEN

PLLSEL

ICP

0

1

PLL powered down.

PLL powered up.

0

1

DSP internal clock taken directly from CKI.

DSP internal clock taken from PLL.

—

Charge pump current selection (see Table 64, PLL Electrical Specifications and pllc Reg-

ister Settings for proper value).

RSVD

0

—

LF[3:0]

—

Loop filter setting (see Table 64, PLL Electrical Specifications and pllc Register Settings

for proper value).

Nbits[2:0]

Mbits[4:0]

—

Encodes N, 1 ≤ N ≤ 8, where N = Nbits[2:0] + 2, unless Nbits[2:0] = 111, then N = 1.

Encodes M, 2 ≤ M ≤ 20, where M = Mbits[4:0] + 2, f^{INTERNAL CLOCK}= f^CKIx (M/(2N)).

Agere Systems Inc.

51

Data Sheet

January 2002

DSP1629 Digital Signal Processor

5 Software Architecture (continued)

Table 33. sbit Register

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Field

DIREC[7:0]

VALUE[7:0]

Field

DIREC

Value

Description

1xxxxxxx

x1xxxxxx

xx1xxxxx

xxx1xxxx

xxxx1xxx

xxxxx1xx

xxxxxx1x

xxxxxxx1

Rxxxxxxx

xRxxxxxx

xxRxxxxx

xxxRxxxx

xxxxRxxx

xxxxxRxx

xxxxxxRx

xxxxxxxR

IOBIT7 is an output (input when 0).

IOBIT6 is an output (input when 0).

IOBIT5 is an output (input when 0).

IOBIT4 is an output (input when 0).

IOBIT3 is an output (input when 0).

IOBIT2 is an output (input when 0).

IOBIT1 is an output (input when 0).

IOBIT0 is an output (input when 0).

Reads the current value of IOBIT7.

Reads the current value of IOBIT6.

Reads the current value of IOBIT5.

Reads the current value of IOBIT4.

Reads the current value of IOBIT3.

Reads the current value of IOBIT2.

Reads the current value of IOBIT1.

Reads the current value of IOBIT0.

VALUE

Table 34. cbit Register

Bit

15

14

13

12

11

MODE/MASK[3:0]

MODE/MASK[n]

10

9

8

7

6

5

4

3

2

1

0

Field

MODE/MASK[7:4]

DATA/PAT[7:4]

DATA/PAT[3:0]

DIREC[n]^*

DATA/PAT[n]

Action

1 (Output)

0 (Input)

0

1

0

1

0

1

0

1

0

1

0

1

Clear

Set

No Change

Toggle

No Test

0 (Input)

No Test

0 (Input)

Test for Zero

Test for One

0 (Input)

* 0 ≤ n ≤ 7.

52

Agere Systems Inc.

Data Sheet

January 2002

DSP1629 Digital Signal Processor

5 Software Architecture (continued)

Table 35. alf Register

Bit

15

14

13—0

Field

AWAIT

LOWPR

FLAGS

Field

Value

Action

AWAIT

LOWPR

FLAGS

1

0

Power-saving standby mode or standard sleep enabled.

Normal operation.

1

0

The internal DPRAM is addressed beginning at 0x0000 in X space.

The internal DPRAM is addressed beginning at 0xc000 in X space.

—

See the following table.

Bit

Flag

Reserved

nmns1

mns1

evenp

oddp

Use

13—8

—

7

6

5

4

3

2

1

0

NOT-MINUS-ONE from BMU

MINUS-ONE from BMU

EVEN PARITY from BMU

ODD PARITY from BMU

SOME FALSE from BIO

SOME TRUE from BIO

ALL FALSE from BIO

ALL TRUE from BIO

somef

somet

allf

allt

Table 36. mwait Register

Bit

15—12

11—8

ERAMHI[3:0]

7—4

3—0

Field

EROM[3:0]

IO[3:0]

ERAMLO[3:0]

If the EXM pin is high and the INT1 is low upon reset, the mwait register is initialized to all 1s (15 wait-states for all

external memory). Otherwise, the mwait register is initialized to all 0s (0 wait-states) upon reset.

Table 37. DSP1629 32-Bit JTAG ID Register

Bit

31

30

29—28

CLOCK

27—19

18—12

11—0

0x03B

Field

RSVD

SECURE

ROMCODE

PART ID

Field

Value

Mask-Programmable Features

RSVD

0

—

SECURE

0

1

Nonsecure ROM option.

Secure ROM option.

CLOCK

01

11

Small-signal input clock option.

CMOS level input clock option.

ROMCODE

—

Users ROMCODE ID:

The ROMCODE ID is the 9-bit binary value of the following expression:

(20 x value for first letter) + (value of second letter), where the values of the let-

ters are in the following table. For example, ROMCODE GK is (20 x 6) + (9) = 129

or 0 1000 0001.

PART ID

0x29

DSP1629.

ROMCODE Letter

Value

A

0

B

C

2

D

3

E

4

F

5

G

6

H

7

J

K

9

L

M

N

P

R

S

T

U

W

Y

1

8

10 11 12 13 14 15 16 17 18 19

Agere Systems Inc.

53

Data Sheet

January 2002

DSP1629 Digital Signal Processor

5 Software Architecture (continued)

Table 38. ioc Register^*

Bit

15

14

13

12

11

10

9

8—7

6—4

3—0

Field

RSVD EXTROM CKO2 EBIOH WEROM ESIO2 SIOLBC CKO[1:0]

RSVD DENB[3:0]

* The field definitions for the ioc register are different from the DSP1610.

ioc Fields

ioc Field

Description

EXTROM

CKO2

If 1, sets AB15 low during external memory accesses when WEROM = 1.

CKO configuration (see the following table).

EBIOH

If 1, enables the high half of BIO, IOBIT[4:7], and disables VEC[3:0] from pins.

If 1, allows writing into external program (X) memory.

If 1, enables SIO2 and low half of BIO, and disables PHIF from pins.

If 1, DO1 and DO2 looped back to DI1 and DI2.

CKO configuration (see the following table).

If 1, delay EROM.

WEROM

ESIO2

SIOLBC

CKO[1:0]

DENB3

DENB2

DENB1

DENB0

If 1, delay ERAMHI.

If 1, delay IO.

If 1, delay ERAMLO.

CKO2

CKO1

CKO0

CKO Output

PLL

CKI x M/(2N)

Description

—

Free-running clock.^*,

—

0

—

0

—

0

1X

†

‡

CKI

Wait-stated clock.^{* †}

0

1

CKI/(1 + W) CKI x (M/(2N))/[1 + W]

, ,

0

1

0

1

0

1

0

1

0

1

0

1

0

Held high.

Held low.

CKI

Output of CKI buffer.

**

‡

†

*

CKI/(1 + W) CKI x (M/(2N))/[1 + W]

Sequenced, wait-stated clock. , , ,

Reserved.

* The phase of CKI is synchronized by the rising edge of RSTB.

† When SLOWCKI is enabled in the powerc register, these options reflect the low-speed internal ring oscillator.

‡ The wait-stated clock reflects the internal instruction cycle and may be stretched based on the mwait register setting (see Table 36, mwait

Register). During sequenced external memory accesses, it completes one cycle.

**The sequenced wait-stated clock completes two cycles during a sequenced external memory access and may be stretched based on the mwait

register setting (see Table 36, mwait Register).

54

Agere Systems Inc.

Data Sheet

January 2002

DSP1629 Digital Signal Processor

5 Software Architecture (continued)

Table 39. powerc Register

The powerc register configures various power management modes.

Bit

15

14

13

12

11

10

9—8

7

6

5

4

3—0

Field XTLOFF SLOWCKI NOCK INT0EN RSVD INT1EN RSVD SIO1DIS SIO2DIS PHIFDIS TIMERDIS RSVD

Note: The reserved (RSVD) bits should always be written with zeros to make the program compatible with future chip versions.

powerc fields

Field

XTLOFF

SLOWCKI

NOCK

INT0EN

INT1EN

SIO1DIS

SIO2DIS

PHIFDIS

TIMERDIS

Description

1 = powerdown small-signal clock input.

1 = select ring oscillator clock (internal slow clock).

1 = disable internal processor clock.

1 = INT0 clears NOCK field.

1 = INT1 clears NOCK field.

1 = disable SIO1.

1 = disable SIO2.

1 = disable PHIF.

1 = disable timer.

A •indicates that this bit is unknown on powerup reset and unaffected on subsequent reset. An S indicates that this

bit shadows the PC. P indicates the value on an input pin, i.e., the bit in the register reflects the value on the corre-

sponding input pin.

Table 40. Register Settings After Reset

Register

Bits 15—0

••••••••••••••••

Register

ybase

inc

Bits 15—0

••••••••••••••••

0000000000000000

0000010000000110

••••••••••••••••

r0

r1

r2

r3

j

••••••••••••••••

ins

sdx2

saddx

cloop

mwait

saddx2

sioc2

cbit

••••••••••••••••

k

rb

••••••••••••••••

000000000•••••••

0000000000000000^†

••••••••••••••••

••••••0000000000

••••••••••••••••

0000000000000000

re

pt

pr

0000000000000000

••••••••••••••••

pi

i

p

SSSSSSSSSSSSSSSS

••••••••••••••••

sbit

ioc

jtag

00000000PPPPPPPP

0000000000000000

••••••••••••••••

pl

••••••••••••••••

a0

••••••••••••••••

x

••••••••••••••••

a0l

••••••••••••••••

y

••••••••••••••••

a1

••••••••••••••••

yl

••••••••••••••••

a1l

••••••••••••••••

auc

psw

c0

c1

c2

sioc

srta

sdx

tdms

phifc

pdx0

0000000000000000

••••00••••••••••

timerc

timer0

tdms2

srta2

powerc

pllc

••••••••00000000

0000000000000000

••••••0000000000

••••••••••••••••

0000000000000000

••••••••••••••••

00000000••••••••

••••••••••••••••

•••••••••••••••

••••••••••••••••

••••••0000000000

••••••••••••••••

ar0

ar1

ar2

ar3

••••••••••••••••

••••••0000000000

0000000000000000

alf

† If EXM is high and INT1 is low when RSTB goes high, mwait will contain all ones instead of all zeros.

Agere Systems Inc.

55

Data Sheet

January 2002

DSP1629 Digital Signal Processor

5 Software Architecture (continued)

5.3 Instruction Set Formats

This section defines the hardware-level encoding of the DSP1629 device instructions.

Multiply/ALU Instructions

Format 1: Multiply/ALU Read/Write Group

Field

Bit

T

D

S

9

F1

X

4

Y

15

14

13

12

11

10

8

7

6

5

3

2

1

0

Format 1a: Multiply/ALU Read/Write Group

Field

Bit

T

aT

10

S

9

X

4

Y

15

14

13

12

11

Format 2: Multiply/ALU Read/Write Group

Field

Bit

T

D

S

9

X

4

15

14

13

12

11

10

Format 2a: Multiply/ALU Read/Write Group

Field

Bit

T

aT

10

S

9

X

4

15

14

13

12

11

Special Function Instructions

Format 3: F2 ALU Special Functions

Field

Bit

T

D

S

9

F2

F3

CON

2

15

14

13

12

11

10

8

7

6

5

4

3

1

0

Format 3a: F3 ALU Operations

Field

T

D

S

SRC2

aT

2

0

1

0

Immediate Operand (IM16)

10

Bit

15

14

13

12

11

9

8

7

6

4

3

Format 3b: BMU Operations

Field

T

D

S

F4[3—1]

Immediate Operand (IM16)

10

0

5

F4[0]

4

AR

Bit

15

14

13

12

11

9

8

7

6

3

2

1

0

56

Agere Systems Inc.

Data Sheet

January 2002

DSP1629 Digital Signal Processor

5 Software Architecture (continued)

Control Instructions

Format 4: Branch Direct Group

Field

Bit

T

JA

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Format 5: Branch Indirect Group

Field

Bit

T

B

Reserved

4

0

15

14

13

12

9

1

Format 6: Conditional Branch Qualifier/Software Interrupt (icall)

Note that a branch instruction immediately follows except for a software interrupt (icall).

Field

Bit

T

SI

Reserved

CON

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Data Move Instructions

Format 7: Data Move Group

Field

Bit

T

aT

10

R

Y/Z

15

14

13

12 11

9

8

7

6

5

4

3

Format 8: Data Move (immediate operand—2 words)

Field

T

D

R

Reserved

Immediate Operand (IM16)

Bit

15

14

13

12

11

10

9

8

7

6

4

3

2

1

0

Format 9: Short Immediate Group

Field

Bit

T

I

Short Immediate Operand (IM9)

15

14

13

12

10

9

8

6

5

4

3

2

Format 9a: Direct Addressing

Field

Bit

T

R/W

10

DR

1

5

OFFSET

2

15

14

13

12

9

8

Cache Instructions

Format 10: Do/Redo

Field

T

N

K

3

Bit

15

14

13

12

11

10

7

6

5

4

2

1

0

Agere Systems Inc.

57

Data Sheet

January 2002

DSP1629 Digital Signal Processor

Table 43. aT Field

5 Software Architecture (continued)

Specifies transfer accumulator.

Field Descriptions

aT

Register

Table 41. T Field

0

1

Accumulator 1

Accumulator 0

Specifies the type of instruction.

T

Operation

goto JA

Short imm j, k, rb, re

Short imm r0, r1, r2, r3

Y = a1[l]

Format

Table 44. S Field

0000x

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

1000x

10010

10011

10100

10101

10110

10111

11000

11001

4

9

1

2a

1

1a

7

8

7

10

7

4

3

Specifies a source accumulator.

S

0

1

Register

F1

Accumulator 0

Accumulator 1

Z:aT[l]

Y

aT[l] = Y

Table 45. F1 Field

Bit 0 = 0, aT = R

Bit 0 = 1, aTl = R

Bit 10 = 0, R = a0

Bit 10 = 1, R = a0l

R = IM16

Bit 10 = 0, R = a1

Bit 10 = 1, R = a1l

Y = R

Specifies the multiply/ALU function.

F1

Operation

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

aD = pp = x * y

aD = aS + pp = x * y

p = x * y

aD = aS – pp = x * y

aD = p

Z:R

do, redo

R = Y

call JA

ifc CON

if CON

Y = y[l]

Z:y[l]

aD = aS + p

nop

aD = aS – p

aD = aS | y

aD = aS ^ y

aS & y

F2

F1

3

1

2

1

5

3a

1

aS – y

aD = y

x = Y

y[l] = Y

Bit 0 = 0, branch indirect

Bit 0 = 1, F3 ALU

y = a0 x = X

aD = aS + y

aD = aS & y

aD = aS – y

F1

11010 Conditional branch qualifier

6

Table 46. X Field

11011

11100

11101

11110

11111

y = a1 x = X

Y = a0[l]

Z:y x = X

F1

1

2

3b

9a

1

Specifies the addressing of ROM data in two-operand

multiply/ALU instructions. Specifies the high or low half

of an accumulator, or the y register in one-operand mul-

tiply/ALU instructions.

Bit 5 = 0, F4 ALU (BMU)

Bit 5 = 1, direct addressing

y = Y x = X F1

X

Operation

Two-Operand Multiply/ALU

pt++

Table 42. D Field

0

1

*

Specifies a destination accumulator.

pt++i

*

D

0

1

Register

Accumulator 0

Accumulator 1

One-Operand Multiply/ALU

0

1

aTl, yl

aTh, yh

58

Agere Systems Inc.

Data Sheet

January 2002

DSP1629 Digital Signal Processor

Table 49. F2 Field

Specifies the special function to be performed.

5 Software Architecture (continued)

Table 47. Y Field

F2

Operation

aD = aS >> 1

aD = aS << 1

aD = aS >> 4

aD = aS << 4

aD = aS >> 8

aD = aS << 8

aD = aS >> 16

aD = aS << 16

aD = p

Specifies the form of register indirect addressing with

postmodification.

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

Y

Operation

r0

0000

*

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

r0++

*

r0--

*

r0++j

*

r1

*

r1++

*

aDh = aSh + 1

aD = ~aS

r1--

*

r1++j

r2

aD = rnd(aS)

aD = y

*

r2++

*

aD = aS + 1

aD = aS

r2--

*

aD = – aS

r2++j

r3

*

Table 50. CON Field

r3++

*

Specifies the condition for special functions and condi-

tional control instructions.

r3--

*

r3++j

CON

Condition

mi

CON

01110

01111

10000

10001

10010

10011

10100

10101

10110

10111

11000

11001

11010

11011

11100

—

Condition

true

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

Table 48. Z Field

pl

false

gt

Specifies the form of register indirect compound ad-

dressing with postmodification.

eq

ne

le

Z

Operation

lvs

allt

0000

r0zp

lvc

allf

*

mvs

mvc

heads

tails

c0ge

c0lt

somet

somef

oddp

evenp

mns1

nmns1

npint

njint

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

r0pz

r0m2

*

r0jk

*

r1zp

r1pz

*

r1m2

*

c1ge

c1lt

r1jk

*

r2zp

*

lock

Other

codes

Reserved

—

r2pz

*

r2m2

*

r2jk

*

r3zp

*

r3pz

*

r3m2

*

r3jk

*

Agere Systems Inc.

59

Data Sheet

January 2002

DSP1629 Digital Signal Processor

Table 53. DR Field

5 Software Architecture (continued)

DR Value

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

Register

Table 51. R Field

r0

r1

r2

r3

a0

a0l

a1

a1l

y

Specifies the register for data move instructions.

R

Register

R

Register

inc

000000

000001

000010

000011

000100

000101

000110

000111

001000

001001

001010

001011

001100

001101

001110

001111

010000

010001

010010

010011

010100

010101

010110

010111

011000

011001

011010

011011

011100

011101

011110

011111

r0

100000

100001

100010

100011

100100

100101

100110

100111

101000

101001

101010

101011

101100

101101

101110

101111

110000

110001

110010

110011

110100

110101

110110

110111

111000

111001

111010

111011

111100

111101

111110

111111

r1

ins

r2

sdx2

r3

saddx

cloop

mwait

saddx2

sioc2

cbit

j

k

rb

yl

re

p

pt

pl

pr

sbit

x

pi

i

ioc

pt

jtag

pr

psw

p

Reserved

a0

pl

Table 54. I Field

pllc

Specifies a register for short immediate data move in-

structions.

Reserved

x

y

a0l

I

Register

r0/j

yl

a1

00

01

10

11

auc

psw

c0

a1l

r1/k

timerc

timer0

tdms2

srta2

powerc

Reserved

ar0

r2/rb

r3/re

c1

Table 55. SI Field

c2

Specifies when the conditional branch qualifier instruc-

tion should be interpreted as a software interrupt in-

struction.

sioc

srta

sdx

tdms

phifc

pdx0

Reserved

ybase

ar1

SI

0

Operation

ar2

Not a software interrupt

Software interrupt

ar3

1

Reserved

alf

Table 52. B Field

Specifies the type of branch instruction (except software

interrupt).

B

Operation

return

000

001

010

011

1xx

ireturn

goto pt

call pt

Reserved

60

Agere Systems Inc.

Data Sheet

January 2002

DSP1629 Digital Signal Processor

5 Software Architecture (continued)

Table 58. BMU Encodings

F4

AR

Operation

aD = aS >> arM

N Field

0000

0001

0000

0001

1000

1001

1000

1001

1100

1101

1100

1101

0000

0001

1110

0010

1110

0010

1110

1010

0111

00xx

10xx

0000

1000

0000

1000

1100

11xx

0000

00xx

0100

01xx

1000

10xx

0000

0001

Number of instructions to be loaded into the cache. Zero

implies redo operation.

aD = aS << arM

aD = aS >>> arM

aD = aS <<< arM

aD = aS >> aS

K Field

aD = aS << aS

Number of times the N instructions in cache are to be

executed. Zero specifies use of value in cloop register.

aD = aS >>> aS

aD = aS <<< aS

JA Field

aD = aS >> IM16

aD = aS << IM16

aD = aS >>> IM16

aD = aS <<< IM16

aD = exp(aS)

12-bit jump address.

R/W Field

A zero specifies a write, *(O) = DR.

A one specifies a read, DR = *(O).

aD = norm(aS, arM)

aD = extracts(aS, IM16)

aD = extracts(aS, arM)

aD = extractz(aS, IM16)

aD = extractz(aS, arM)

aD = insert(aS, IM16)

aD = insert(aS, arM)

aD = aS:aa0

Table 56. F3 Field

Specifies the operation in an F3 ALU instruction.

F3

Operation

1000

1001

1010

1011

1101

1110

1111

aD = aS[h, l]

aS[h, l]

|

{aT, IM16, p}

^

aD = aS:aa1

&

–

+

&

–

Note: xx encodes the auxiliary register to be used; 00 (ar0), 01(ar1),

10 (ar2), or 11(ar3).

aS[h, l]

aD = aS[h, l]

Table 57. SRC2 Field

Specifies operands in an F3 ALU instruction.

SRC2

00

Operands

aSl, IM16

aSh, IM16

aS, aT

10

01

11

aS, p

Agere Systems Inc.

61

Data Sheet

January 2002

DSP1629 Digital Signal Processor

6 Signal Descriptions

16

RSTB

CKO

CKI2

CKI

AB[15:0]

16

SYSTEM

INTERFACE

OR

DB[15:0]

RWN

CONTROL I/O

INTERFACE

EXTERNAL

EXM

STOP

MEMORY

2

4

INT[1:0]

INTERFACE

EROM

ERAMHI

IO

VEC[3:0] OR IOBIT[4:7]

IACK

TRAP

ERAMLO

DSEL

PSTAT OR DO2

PODS OR OLD2

PCSN OR OCK2

POBE OR OBE2

PBSEL OR SYNC2

PB0 OR ICK2

PARALLEL HOST

INTERFACE

DSP1629

DO1

OR

SERIAL INTERFACE #2

AND CONTROL I/O

INTERFACE

OLD1

OCK1

OBE1

DI1

PIDS OR ILD2

PB1 OR DI2

SERIAL

INTERFACE #1

PIBF OR IBF2

ILD1

PB2 OR DOEN2

ICK1

PB3 OR SADD2

IBF1

SYNC1

SADD1

DOEN1

4

PB[7:4] OR IOBIT[3:O]

JTAG TEST

INTERFACE

TRST

TDI

TDO

TCK

TMS

5-4006 (F).i

Figure 9. DSP1629 Pinout by Interface

Figure 9, DSP1629 Pinout by Interface, shows the pi-

nout for the DSP1629. The signals can be separated

into five interfaces, as shown. These interfaces and the

signals that comprise them are described in Section 6.1,

System Interface.

and PODS status bits set), alf (upper 2 bits, AWAIT and

LOWPR), ioc, rb, and re registers are cleared. The

mwait register is initialized to all 0s (zero wait-states)

unless the EXM pin is high and the INT1 pin is low. In

that case, the mwait register is initialized to all 1s

(15 wait-states).

Reset clears IACK, VEC[3:0]/IOBIT[4:7], IBF, and IBF2.

The DAU condition flags are not affected by reset.

IOBIT[7:0] are initialized as inputs. If any of the IOBIT

pins are switched to outputs (by writing sbit), their initial

value will be logic zero (see Table 40, Register Settings

After Reset).

6.1 System Interface

The system interface consists of the clock, interrupt,

and reset signals for the processor.

RSTB

Upon negation of the signal, the processor begins exe-

cution at location 0x0000 in the active memory map

(see Section 4.4, Memory Maps and Wait-States).

Reset: Negative assertion. A high-to-low transition

causes the processor to enter the reset state. The auc,

powerc, sioc, sioc2, phifc, pdx0, tdms, tdms2, timerc,

timer0, sbit (upper byte), inc, ins (except OBE, OBE2,

62

Agere Systems Inc.

Data Sheet

January 2002

DSP1629 Digital Signal Processor

PLL is programmed.

6 Signal Descriptions (continued)

■ A logic 0.

■ A logic 1.

CKI

Input Clock: A mask-programmable option selects one

of three possible input buffers for the CKI pin (see Sec-

tion 7, Mask-Programmable Options, and Table 1, Pin

Descriptions). The internal CKI from the output of the

selected input buffer can then drive the internal proces-

sor clock directly (1X) or drive the on-chip PLL (see Sec-

tion 4.13, Power Management). The PLL allows the CKI

input clock to be at a lower frequency than the internal

processor clock.

INT[1:0]

Processor Interrupts 0 and 1: Positive assertion.

Hardware interrupt inputs to the DSP1629. Each is en-

abled via the inc register. When enabled and asserted,

each cause the processor to vector to the memory loca-

tion described in Table 4, Interrupt Vector Table. INT1

is used in conjunction with EXM to select the desired re-

set initialization of the mwait register (see Table 36,

mwait Register). When both INT0 and RSTB are assert-

ed, all output and bidirectional pins (except TDO, which

3-states by JTAG control) are put in a 3-state condition.

CKI2

Input Clock 2: Used with mask-programmable input

clock options which require an external small signal dif-

ferential across CKI and CKI2 (see Table 1, Pin De-

scriptions). When the CMOS option is selected, this pin

should be tied to VSSA.

VEC[3:0]

Interrupt Output Vector: These four pins indicate

which interrupt is currently being serviced by the device.

Table 4, Interrupt Vector Table, shows the code associ-

ated with each interrupt condition. VEC[3:0] are multi-

plexed with IOBIT[4:7].

STOP

Stop Input Clock: Negative assertion. A high-to-low

transition synchronously stops all of the internal proces-

sor clocks, leaving the processor in a defined state. Re-

turning the pin high will synchronously restart the

processor clocks to continue program execution from

where it left off, without any loss of state. This hardware

feature has the same effect as setting the NOCK bit in

the powerc register (see Table 39, powerc Register).

IACK

Interrupt Acknowledge: Positive assertion. IACK

signals when an interrupt is being serviced by the

DSP1629. IACK remains asserted while in an interrupt

service routine, and is cleared when the ireturn instruc-

tion is executed.

CKO

TRAP

Clock Out: Buffered output clock with options program-

mable via the ioc register (see Table 38, ioc Register).

The selectable CKO options (see Table 38, ioc Register

and Table 29, Interrupt Control (inc) Register) are as fol-

lows:

Trap Signal: Positive assertion. When asserted, the

processor is put into the trap condition, which normally

causes a branch to the location 0x0046. The hardware

development system (HDS) can configure the trap pin

to cause an HDS trap, which causes a branch to loca-

tion 0x0003. Although normally an input, the pin can be

configured as an output by the HDS. As an output, the

pin can be used to signal an HDS breakpoint in a multi-

ple processor environment.

■ A free-running output clock at the frequency of the in-

ternal processor clock; runs at the internal ring oscil-

lator frequency when SLOWCKI is enabled.

■ A wait-stated clock based on the internal instruction

cycle; runs at the internal ring oscillator frequency

when SLOWCKI is enabled.

■ A sequenced, wait-stated clock based on the EMI se-

quencer cycle; runs at the internal ring oscillator fre-

quency when SLOWCKI is enabled.

■ A free-running output clock that runs at the CKI rate,

independent of the powerc register setting. This op-

tion is only available with the small-signal clock op-

tions. When the PLL is selected, the CKO frequency

equals the input CKI frequency, regardless of how the

Agere Systems Inc.

63

Data Sheet

January 2002

DSP1629 Digital Signal Processor

EROM

6 Signal Descriptions (continued)

External ROM Enable Signal: Negative assertion.

When asserted, the signal indicates an access to exter-

nal program memory (see Table 5, Instruction/Coeffi-

cient Memory Maps). This signal's leading edge can be

delayed via the ioc register (see Table 38, ioc Register).

6.2 External Memory Interface

The external memory interface is used to interface the

DSP1629 to external memory and I/O devices. It sup-

ports read/write operations from/to program and data

memory spaces. The interface supports four external

memory segments. Each external memory segment

can have an independent number of software-program-

mable wait-states. One hardware address is decoded,

and an enable line is provided, to allow glueless I/O in-

terfacing.

ERAMHI

External RAM High Enable Signal: Negative asser-

tion. When asserted, the signal indicates an access to

external data memory addresses 0x8000 through

0xFFFF (see Table 6, Data Memory Maps). This sig-

nal's leading edge can be delayed via the ioc register

(see Table 38, ioc Register).

AB[15:0]

External Memory Address Bus: Output only. This

16-bit bus supplies the address for read or write opera-

tions to the external memory or I/O. During external

memory accesses, AB[15:0] retain the value of the last

valid external access.

ERAMLO

External RAM Low Enable Signal: Negative asser-

tion. When asserted, the signal indicates an access to

external data memory addresses 0x4100 through

0x7FFF (see Table 6, Data Memory Maps). This sig-

nal's leading edge can be delayed via the ioc register

(see Table 38, ioc Register).

DB[15:0]

External Memory Data Bus: This 16-bit bidirectional

data bus is used for read or write operations to the ex-

ternal memory or I/O.

I/O

External I/O Enable Signal: Negative assertion. When

asserted, the signal indicates an access to external data

memory addresses 0x4000 through 0x40FF (see

Table 6, Data Memory Maps). This memory segment is

intended for memory-mapped I/O. This signal's leading

edge can be delayed via the ioc register (see Table 38,

ioc Register).

RWN

Read/Write Not: When a logic 1, the pin indicates that

the memory access is a read operation. When a logic 0,

the memory access is a write operation.

EXM

External Memory Select: Input only. This signal is

latched into the device on the rising edge of RSTB. The

value of EXM latched in determines whether the internal

ROM is addressable in the instruction/coefficient mem-

ory map. If EXM is low, internal ROM is addressable. If

EXM is high, only external ROM is addressable in the

instruction/coefficient memory map (see Table 5, In-

struction/Coefficient Memory Maps). EXM chooses be-

tween MAP1 or MAP2 and between MAP3 or MAP4.

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Data Sheet

January 2002

DSP1629 Digital Signal Processor

OCK1

6 Signal Descriptions (continued)

Output Clock: The clock for serial output data. In active

mode, OCK1 is an output; in passive mode, OCK1 is an

input, according to the sioc register OCK field (see Ta-

ble 22, Serial I/O Control Registers). Input typically has

0.7 V hysteresis.

6.3 Serial Interface #1

The serial interface pins implement a full-featured syn-

chronous/asynchronous serial I/O channel. In addition,

several pins offer a glueless TDM interface for multipro-

cessing communication applications (see Figure 6, Mul-

tiprocessor Communication and Connections).

OLD1

Output Load: The clock for loading the output shift reg-

ister, osr, from the output buffer sdx[out]. A falling edge

of OLD1 indicates the beginning of a serial output word.

In active mode, OLD1 is an output; in passive, OLD1 is

an input, according to the sioc register OLD field (see

Table 22, Serial I/O Control Registers). Input typically

has 0.7 V hysteresis.

DI1

Data Input: Serial data is latched on the rising edge of

ICK1, either LSB or MSB first, according to the sioc reg-

ister MSB field (see Table 22, Serial I/O Control Regis-

ters).

ICK1

OBE1

Input Clock: The clock for serial input data. In active

mode, ICK1 is an output; in passive mode, ICK1 is an

input, according to the sioc register ICK field (see Table

22, Serial I/O Control Registers). Input typically has

0.7 V hysteresis.

Output Buffer Empty: Positive assertion. OBE1 is as-

serted when the output buffer, sdx[out], is emptied

(moved to the output shift register for transmission). It is

cleared with a write to the buffer, as in sdx = a0. OBE1

is also set by asserting RSTB.

ILD1

SADD1

Input Load: The clock for loading the input buffer,

sdx[in], from the input shift register isr. A falling edge of

ILD1 indicates the beginning of a serial input word. In

active mode, ILD1 is an output; in passive mode, ILD1

is an input, according to the sioc register ILD field (see

Table 22, Serial I/O Control Registers). Input typically

has 0.7 V hysteresis.

Serial Address: Negative assertion. A 16-bit serial bit

stream typically used for addressing during multiproces-

sor communication between multiple DSP16xx devices.

In multiprocessor mode, SADD1 is an output when the

tdms time slot dictates a serial transmission; otherwise,

it is an input. Both the source and destination DSP can

be identified in the transmission. SADD1 is always an

output when not in multiprocessor mode and can be

used as a second 16-bit serial output. See the

IBF1

DSP1611/17/18/27/28/29 Digital Signal Processor In-

formation Manual for additional information. SADD1 is

3-stated when DOEN1 is high. When used on a bus,

SADD1 should be pulled high through a 5 kΩ resistor.

Input Buffer Full: Positive assertion. IBF1 is asserted

when the input buffer, sdx[in], is filled. IBF1 is negated

by a read of the buffer, as in a0 = sdx. IBF1 is also ne-

gated by asserting RSTB.

SYNC1

DO1

Multiprocessor Synchronization: Typically used in

the multiprocessor mode, a falling edge of SYNC1 indi-

cates the first word (time slot 0) of a TDM I/O stream

and causes the resynchronization of the active ILD1

and OLD1 generators. SYNC1 is an output when the

tdms register SYNC field is set (i.e., selects the master

DSP and uses time slot 0 for transmit). As an input,

SYNC1 must be tied low unless part of a TDM interface.

When used as an output, SYNC1 = [ILD1/OLD1]/8 or

16, depending on the setting of the SYNCSP field of the

tdms register. When configured as described above,

SYNC1 can be used to generate a slow clock for SIO

operations. Input typically has 0.7 V hysteresis.

Data Output: The serial data output from the output

shift register (osr), either LSB or MSB first (according to

the sioc register MSB field). DO1 changes on the rising

edges of OCK1. DO1 is 3-stated when DOEN1 is high.

DOEN1

Data Output Enable: Negative assertion. An input

when not in the multiprocessor mode. DO1 and SADD1

are enabled only if DOEN1 is low. DOEN1 is bidirection-

al when in the multiprocessor mode (tdms register

MODE field set). In the multiprocessor mode, DOEN1

indicates a valid time slot for a serial output.

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Data Sheet

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DSP1629 Digital Signal Processor

PIDS/PRWN indicates an external read operation by the

external device.

6 Signal Descriptions (continued)

6.4 Parallel Host Interface or Serial Interface

#2 and Control I/O Interface

PODS

Parallel Output Data Strobe: An input pin, software

configurable to support both Intel and Motorola proto-

cols.

This interface pin multiplexes a parallel host interface

with a second serial I/O interface and a 4-bit I/O inter-

face. The interface selection is made by writing the

ESIO2 bit in the ioc register (see Table 38, ioc Register

and Section 4.1, DSP1629 Architectural Overview). The

functions and signals for the second SIO correspond ex-

actly with those in SIO #1. Therefore, the following pin

descriptions discuss only PHIF and BIO pin functional-

ity.

In Intel mode: negative assertion. When PODS is pulled

low by an external device, the DSP1629 places the con-

tents of the parallel output register, pdx0, onto the PB

bus.

In Motorola mode: software-configurable assertion lev-

el. The external device uses PODS/PDS as its data

strobe for both read and write operations.

PB[7:0]

Parallel I/O Data Bus: This 8-bit bidirectional bus is

PIBF

used to input data to, or output data from, the PHIF.

Parallel Input Buffer Full: An output pin with positive

assertion; configurable in software. This flag is cleared

after reset, indicating an empty input buffer pdx0[in].

Note that PB[3:0] are pin multiplexed with SIO2 func-

tionality, and PB[7:4] are pin multiplexed with BIO unit

pins IOBIT[3:0] (see Section 4.1, DSP1629 Architectur-

al Overview).

PIBF is set immediately after the rising edge of PIDS or

PCSN, indicating that data has been latched into the

pdx0[in] register. When the DSP1629 reads the con-

tents of this register, emptying the buffer, the flag is

cleared.

PCSN

Peripheral Chip Select Not: Negative assertion. PCSN

is an input. While PCSN is low, the data strobes PIDS

and PODS are enabled. While PCSN is high, the

DSP1629 ignores any activity on PIDS and PODS.

Configured in software, PIBF may become the logical

OR of the PIBF and POBE flags.

POBE

PBSEL

Parallel Output Buffer Empty: An output pin with pos-

itive assertion; configurable in software. This flag is set

after reset, indicating an empty output buffer pdx0[out].

Peripheral Byte Select: An input pin, configurable in

software. Selects the high or low byte of pdx0 available

for host accesses.

POBE is set immediately after the rising edge of PODS

or PCSN, indicating that the data in pdx0[out] has been

driven onto the PB bus. When the DSP1629 writes to

pdx0[out], filling the buffer, this flag is cleared.

PSTAT

Peripheral Status Select: PSTAT is an input. When a

logic 0, the PHIF will output the pdx0[out] register on the

PB bus. When a logic 1, the PHIF will output the con-

tents of the PSTAT register on PB[7:0].

6.5 Control I/O Interface

This interface is used for status and control operations

provided by the bit I/O unit of the DSP1629. It is pin mul-

tiplexed with the PHIF and VEC[3:0] pins (see Section

4.1, DSP1629 Architectural Overview). Setting the

ESIO2 and EBIOH bits in the ioc register provides a full

8-bit BIO interface at the associated pins.

PIDS

Parallel Input Data Strobe: An input pin, software con-

figurable to support both Intel and Motorola protocols.

In Intel mode: negative assertion. PIDS is pulled low by

an external device to indicate that data is available on

the PB bus. The DSP latches data on the PB bus on the

rising edge (low-to-high transition) of PIDS or PCSN,

whichever comes first.

IOBIT[7:0]

I/O Bits [7:0]: Each of these bits can be independently

configured as either an input or an output. As outputs,

they can be independently set, toggled, or cleared. As

inputs, they can be tested independently or in combina-

tions for various data patterns.

In Motorola mode: PIDS/PRWN functions as a read/

write strobe. The external device sets PIDS/PRWN to a

logic 0 to indicate that data is available on the PB bus

(write operation by the external device). A logic 1 on

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Data Sheet

January 2002

DSP1629 Digital Signal Processor

TDO

6 Signal Descriptions (continued)

Test Data Output: JTAG serial output signal. Serial-

scanned data and status bits are output on this pin.

6.6 JTAG Test Interface

The JTAG test interface has features that allow pro-

grams and data to be downloaded into the DSP via four

pins. This provides extensive test and diagnostic capa-

bility. In addition, internal circuitry allows the device to

be controlled through the JTAG port to provide on-chip

in-circuit emulation. Agere Systems provides hardware

and software tools to interface to the on-chip HDS via

the JTAG port.

TMS

Test Mode Select: JTAG mode control signal that,

when combined with TCK, controls the scan operations.

This pin has an internal pull-up resistor.

TCK

Note: The DSP1629 provides all JTAG/IEEE 1149.1

standard test capabilities, including boundary

scan. See the DSP1611/17/18/27/28/29 Digital

Signal Processor Information Manual for addi-

tional information on the JTAG test interface.

Test Clock: JTAG serial shift clock. This signal clocks

all data into the port through TDI, and out of the port

through TDO, and controls the port by latching the TMS

signal inside the state-machine controller.

TRST

TDI

Test Reset: Negative assertion. JTAG test reset. When

asserted low, asynchronously resets JTAG TAP con-

troller. In an application environment, this pin must be

asserted prior to or concurrent with RSTB. This pin has

an internal pull-up resistor.

Test Data Input: JTAG serial input signal. All serial-

scanned data and instructions are input on this pin. This

pin has an internal pull-up resistor.

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Data Sheet

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DSP1629 Digital Signal Processor

7 Mask-Programmable Options

The DSP1629 contains a ROM that is mask-programmable. The selection of several programmable features is

made when a custom ROM is encoded. These features select the input clock options, the instruction/coefficient

memory map option, and the hardware emulation or ROM security option, as summarized in Table 59, DSP1629

ROM Options.

Table 59. DSP1629 ROM Options

Features

Options

Comments

Input Clock

CMOS Level

Small Signal

2.7 V and 3 V.

Memory Map

ROM Security

DSP1629x16

DSP1629x10

16 Kwords DPRAM.

10 Kwords DPRAM.

Specify and link 1629hds.v# ^*,

allows emulation.

Nonsecure

Secure

†

Specify and link crc16.v# ,

no emulation capability.

* 1629hds.v# (# indicates the current version number) is the relocatable HDS object code. It uses approximately 140 words

and must reside in the first 4 Kwords of ROM.

† crc16.v# is the cyclic redundancy check object code. It uses approximately 75 words and must reside in the first 4 Kwords

of ROM. See the DSP1600 Support Tools Manual for detailed information.

7.1 Input Clock Options

For all input options, the input clock CKI can run at some fraction of the internal clock frequency by setting the PLL

multiplication factors appropriately (see Section 4.12, Clock Synthesis). When the PLL is bypassed, the input clock

CKI frequency is the internal clock frequency.

7.2 Memory Map Options

The DSP1629 offers a DSP1629x16 or a DSP1629x10, where the difference is in the memory maps. The

DSP1629x16 contains 16 Kwords of internal RAM (DPRAM). The DSP1629x10 supports the use of only 10 Kwords

of DPRAM. See Section 4.4, Memory Maps and Wait-States, for further description.

7.3 ROM Security Options

The DSP1600 hardware development system (HDS) provides on-chip in-circuit emulation and requires that the re-

locatable HDS code be linked to the application code. This code's object file is called 1629hds.v#, where # is a

unique version identifier. Refer to the DSP1629-ST software tools release for more specific information. If on-chip,

in-circuit emulation is desired, a nonsecure ROM must be chosen. If ROM security is desired with the DSP1629, the

HDS cannot be used. To provide testing of the internal ROM contents on a secure ROM device, a cyclic redundancy

check (CRC) program is called by and linked with the user's source code. The CRC code resides in the first

4 Kwords of ROM.

See the DSP1600 Support Tools Manual for more detailed information.

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Data Sheet

January 2002

DSP1629 Digital Signal Processor

8 Device Characteristics

8.1 Absolute Maximum Ratings

Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are abso-

lute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess

of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended

periods can adversely affect device reliability.

External leads can be bonded and soldered safely at temperatures of up to 300 °C. (TBD for 144-pin PBGA.)

Voltage Range on VDD with Respect to Ground Using Devices Designed

for 3 V Operation ..............................................................................................................................–0.5 V to +4.6 V

Voltage Range on Any Pin ............................................................................................. VSS – 0.5 V to VDD + 0.5 V

Power Dissipation................................................................................................................................................ 1 W

Ambient Temperature Range ......................................................................................................... –40 °C to +85 °C

Storage Temperature Range.................................................................................................................... –65 °C to +150 °C

8.2 Handling Precautions

All MOS devices must be handled with certain precautions to avoid damage due to the accumulation of static

charge. Although input protection circuitry has been incorporated into the devices to minimize the effect of this static

buildup, proper precautions should be taken to avoid exposure to electrostatic discharge during handling and mount-

ing. Agere Systems employs a human-body model for ESD-susceptibility testing. Since the failure voltage of elec-

tronic devices is dependent on the current, voltage, and hence, the resistance and capacitance, it is important that

standard values be employed to establish a reference by which to compare test data. Values of 100 pF and 1500 Ω

are the most common and are the values used in the Agere Systems human-body model test circuit. The breakdown

voltage for the DSP1629 is greater than 2000 V.

8.3 Recommended Operating Conditions

Table 60. Recommended Operating Conditions

Maximum

Instruction

Rate (MIPS)

Device

Speed

Input Clock

Package

Supply Voltage

VDD (V)

Ambient

Temperature TA (°C)

Min

Max

Min

Max

52

19.2 ns

12.5 ns

16.7 ns

10 ns

CMOS, Small-signal

PBGA

BQFP

or TQFP

2.7

3.3

–40

85

80

PBGA

BQFP

or TQFP

2.7

3.0

3.3

3.6

–40

85

60

PBGA

BQFP

or TQFP

100

PBGA

BQFP

or TQFP

The ratio of the instruction cycle rate to the input clock frequency is 1:1 without the PLL (referred to as 1X operation),

and M/(2N) with the PLL selected (see Section 4.12, Clock Synthesis). Device speeds greater than 50 MIPS do not

support 1X

operation; use the PLL.

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Data Sheet

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DSP1629 Digital Signal Processor

8 Device Characteristics (continued)

8.4 Package Thermal Considerations

The recommended operating temperature specified in Section 8.3, Recommended Operating Conditions, is based

on the maximum power, package type, and maximum junction temperature. The following equations describe the

relationship between these parameters. If the applications' maximum power is less than the worst-case value, this

relationship determines a higher maximum ambient temperature or the maximum temperature measured at top

dead center of the package.

TA = TJ – P x ΘJA

TTDC = TJ – P x ΘJ-TDC

where TA is the still-air ambient temperature and TTDC is the temperature measured by a thermocouple at the top

dead center of the package.

Maximum Junction Temperature (TJ) in 100-Pin BQFP..................................................................................100 °C

100-pin BQFP Maximum Thermal Resistance in Still-Air-Ambient (ΘJA) ..................................................... 55 °C/W

100-pin BQFP Maximum Thermal Resistance, Junction to Top Dead Center (ΘJ-TDC)............................... 12 °C/W

Maximum Junction Temperature (TJ) in 100-Pin TQFP ..................................................................................100 °C

100-pin TQFP Maximum Thermal Resistance in Still-Air-Ambient (ΘJA) ..................................................... 30 °C/W

100-pin TQFP Maximum Thermal Resistance, Junction to Top Dead Center (ΘJ-TDC)................................. 6 °C/W

Maximum Junction Temperature (TJ) in 144-Pin PBGA..................................................................................100 °C

144-pin PBGA Maximum Thermal Resistance in Still-Air-Ambient (ΘJA)..........................TBD (estimated 30 °C/W)

144-pin PBGA Maximum Thermal Resistance, Junction to Top Dead Center (ΘJ-TDC)..................................... TBD

WARNING: Due to package thermal constraints, proper precautions in the user's application should be tak-

en to avoid exceeding the maximum junction temperature of 100 °C. Otherwise, the device will

be affected adversely.

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Data Sheet

January 2002

DSP1629 Digital Signal Processor

9 Electrical Characteristics and Requirements

The following electrical characteristics are preliminary and are subject to change. Electrical characteristics refer to the

behavior of the device under specified conditions. Electrical requirements refer to conditions imposed on the user for

proper operation of the device. The parameters in Table 61, Electrical Characteristics and Requirements, are valid for

the conditions described in Section 8.3, Recommended Operating Conditions.

Table 61. Electrical Characteristics and Requirements

Parameter

Symbol

Min

Max

Unit

Input Voltage:

Low

High

VIL

VIH

–0.3

0.7 * VDD

0.3 * VDD

VDD + 0.3

V

Input Current (except TMS, TDI):

Low (VIL = 0 V, VDD = 5.25 V)

High (VIH = 5.25 V, VDD = 5.25 V)

Input Current (TMS, TDI):

Low (VIL = 0 V, VDD = 5.25 V)

High (VIH = 5.25 V, VDD = 5.25 V)

Output Low Voltage:

IIL

IIH

–5

—

5

µA

IIL

IIH

–100

—

5

µA

Low (IOL = 2.0 mA)

Low (IOL = 50 µA)

VOL

—

0.4

0.2

V

Output High Voltage:

High (IOH = –2.0 mA)

High (IOH = –50 µA)

VOH

VDD – 0.7

VDD – 0.2

—

V

Output 3-State Current:

Low (VDD = 5.25 V, VIL = 0 V)

High (VDD = 5.25 V, VIH = 5.25 V)

Input Capacitance

IOZL

IOZH

CI

–10

—

10

5

µA

pF

Table 62. Electrical Requirements for Mask-Programmable Input Clock Options

Parameter

Symbol

Min

Max

Unit

CKI CMOS Level Input Voltage:

Low

High

VIL

VIH

–0.3

0.7 * VDD

0.3 * VDD

VDD + 0.3

V

Small-signal Peak-to-peak Voltage

Vpp

0.6

—

V

†

(on CKI)

‡

DCyc

Vin

45

55

%

V

Small-signal Input Duty Cycle

Small-signal Input Voltage Range

(pins: CKI, CKI2)

0.2 * VDD

0.6 * VDD

Small-signal Buffer Frequency Range

fss

—

35

MHz

†

‡

The small-signal buffer must be used in single-ended mode where an ac waveform (sine or square) is applied to CKI and a dc voltage approx-

imately equal to the average value of CKI is applied to CKI2, as shown in the following figure. The maximum allowable ripple on CKI2 is 100 mV.

Duty cycle for a sine wave is defined as the percentage of time during each clock cycle that the voltage on CKI exceeds the voltage on CKI2.

CKI

CKI2

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Data Sheet

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DSP1629 Digital Signal Processor

9 Electrical Characteristics and Requirements (continued)

Table 63. PLL Electrical Specifications, VCO Frequency Ranges

Parameter

Symbol

Min

Max

Unit

VCO Frequency Range (VDD = 3 V ± 10%)^*

VCO Frequency Range (VDD = 3.0 V – 3.6 V)

Input Jitter at CKI

fVCO

50

160

MHz

fVCO

50

—

200

MHz

—

ps-rms

*

The M and N counter values in the pllc register must be set so that the VCO will operate in the appropriate range (see Table 63, PLL Electrical

Specifications, VCO Frequency Ranges). Choose the lowest value of N and then the appropriate value of M for f^{INTERNAL CLOCK}= f^CKIx (M/

(2N)) = f^VCO/2.

Table 64. PLL Electrical Specifications and pllc Register Settings

Typical Lock-in Time (µs)^*

M

VDD

pllc13 (ICP)

pllc12

Reserved

pllc[11:8]

(LF[3:0])

23—24

21—22

19—20

16—18

12—15

8—11

2.7 V – 3.6 V

1

0

1011

1010

1001

1000

0111

0110

0100

30

2—7

*

Lock-in time represents the time following assertion of the PLLEN bit of the pllc register during which the PLL output clock is unstable. The

DSP must operate from the 1X CKI input clock or from the slow ring oscillator while the PLL is locking. Completion of the lock-in interval is

indicated by assertion of the LOCK flag.

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Data Sheet

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DSP1629 Digital Signal Processor

9 Electrical Characteristics and Requirements (continued)

V^DD

V^DD– 0.1

DEVICE

UNDER

TEST

V^DD– 0.2

V^OH

I^OH

V^DD– 0.3

V^DD– 0.4

0

5

10

15

20

25

30

35

40

45

50

I^OH(mA)

5-4007 (F).a

Figure 10. Plot of VOH vs. IOH Under Typical Operating Conditions

0.4

0.3

DEVICE

UNDER

TEST

0.2

V^OL

I^OL

0.1

0

5

10

15

20

25

30

35

40

45

50

I^OL(mA)

5-4008 (F).b

Figure 11. Plot of VOL vs. IOL Under Typical Operating Conditions

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Data Sheet

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DSP1629 Digital Signal Processor

9 Electrical Characteristics and Requirements (continued)

9.1 Power Dissipation

Power dissipation is highly dependent on DSP program activity and the frequency of operation. The typical power

dissipation listed is for a selected application. The following electrical characteristics are preliminary and are subject

to change.

Table 65. Power Dissipation and Wake-Up Latency

Typical Power Dissipation (mW)

I/O Units ON I/O Units OFF

powerc[7:4] = 0x0 powerc[7:4] = 0xf During Wake State) During Wake State)

Wake-Up Latency

Operating Mode

(PLL Not Used (PLL Used

(Unused inputs at VDD or VSS)

VDD=

3 V

Normal Operation ioc = 0x0180

PLL Disabled

CKI and CKO = 40 MHz:

CMOS

93.7

96.3

91.2

93.7

—

Small Signal

CKI and CKO = 0 MHz:

CMOS

0.17

2.75

0.17

2.75

—

Small Signal

Normal Operationioc = 0x0180

PLL Enabled pllc = 0xFC0E

CKI = 10 MHz CKO = 40 MHz

CMOS

96.7

99.3

94.2

96.7

—

Small Signal

Power Management Modes CKO = 40 MHz

Standard Sleep, External Interrupt

alf[15] = 1, ioc = 0x0180

PLL Disabled During Sleep

3T* + tL^†

14.0

16.3

9.3

3T*

CMOS

12.0

Small Signal

Standard Sleep, External Interrupt

alf[15] = 1, ioc = 0x0180

PLL Enabled During Sleep

CMOS

16.5

18.9

11.2

14.0

—

3T*

Small Signal

Sleep with Slow Internal Clock

Small Signal Enabled

powerc[15:14] = 01,

alf[15] = 1, ioc = 0x0180

PLL Disabled During Sleep

5.0 µs + tL^†

0.7

3.7

0.5

3.5

5.0 µs

CMOS

Small Signal

Sleep with Slow Internal Clock

Small Signal Enabled

powerc[15:14] = 01,

alf[15] = 1, ioc = 0x0180

PLL Enabled During Sleep

CMOS

3.3

6.1

2.9

5.5

—

5.0 µs

Small Signal

*

T = CKI clock cycle for 1X input clock option or T = CKI clock cycle divided by M/(2N) for PLL clock option (see Section 4.12, Clock Synthesis).

† tL = PLL lock time (see Table 64, PLL Electrical Specifications and pllc Register Settings).

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Data Sheet

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DSP1629 Digital Signal Processor

9 Electrical Characteristics and Requirements (continued)

Table 65. Power Dissipation and Wake-Up Latency (continued)

Typical Power Dissipation (mW)

I/O Units ON I/O Units OFF

powerc[7:4] = 0x0 powerc[7:4] = 0xf During Wake State) During Wake State)

Wake-Up Latency

Operating Mode

(PLL Not Used (PLL Used

(Unused inputs at VDD or VSS)

VDD=

3 V

Sleep with Slow Internal Clock

Small Signal Disabled

powerc[15:14] = 11,

alf[15] = 1, ioc = 0x0180

PLL Disabled During Sleep

20 µs + tL^†

3T* + tL^†

0.40

0.060

0.30

0.060

20 µs

3T*

Small Signal

Software Stop

powerc[15:12] = 0011

PLL Disabled During STOP

CMOS

Software Stop

powerc[15:12] = 1111

PLL Disabled During STOP

20 µs + tL^†

20 µs

Small Signal

Hardware Stop (STOP = VSS)

powerc[15:12] = 0000

PLL Disabled During STOP

CMOS

0.060

1.20

0.060

1.20

3T*

—

Small Signal

Hardware Stop (STOP = VSS)

powerc[15:12] = 0000

PLL Enabled During STOP

CMOS

2.5

3.6

2.5

3.6

3T*

Small Signal

*

T = CKI clock cycle for 1X input clock option or T = CKI clock cycle divided by M/(2N) for PLL clock option (see Section 4.12, Clock Synthesis).

† tL = PLL lock time (see Table 64, PLL Electrical Specifications and pllc Register Settings).

The power dissipation listed is for internal power dissipation only. Total power dissipation can be calculated on the

basis of the application by adding C x VDD/2 x f for each output, where C is the additional load capacitance and f is

the output frequency.

Power dissipation due to the input buffers is highly dependent on the input voltage level. At full CMOS levels, es-

sentially no dc current is drawn. However, for levels between the power supply rails, especially at or near the thresh-

old of VDD/2, high currents can flow. Although input and I/O buffers may be left untied (since the input voltage levels

of the input and I/O buffers are designed to remain at full CMOS levels when not driven by the DSP), it is still rec-

ommended that unused input and I/O pins be tied to VSS or VDD through a 10 kΩ resistor to avoid application am-

biguities. Further, if I/O pins are tied high or low, they should be pulled fully to VSS or VDD.

WARNING: The device needs to be clocked for at least six CKI cycles during reset after powerup. Other-

wise, high currents may flow.

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Data Sheet

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DSP1629 Digital Signal Processor

10 Timing Characteristics for 3.0 V Operation

The following timing characteristics and requirements are preliminary information and are subject to change. Timing

characteristics refer to the behavior of the device under specified conditions. Timing requirements refer to conditions

imposed on the user for proper operation of the device. All timing data is valid for the following conditions:

TA = –40 °C to +85 °C (See Section 8.3, Recommended Operating Conditions.)

VDD = 3.0 V to 3.6 V, VSS = 0 V (See Section 8.3, Recommended Operating Conditions.)

Capacitance load on outputs (CL) = 50 pF, except for CKO, where CL = 20 pF.

Output characteristics can be derated as a function of load capacitance (CL).

All outputs: 0.03 ns/pF ≤ dt/dCL ≤ 0.07 ns/pF for 10 ≤ CL ≤ 100 pF at VIH for rising edge and at VIL for falling edge.

For example, if the actual load capacitance is 30 pF instead of 50 pF, the derating for a rising edge is (30 – 50) pF

x 0.06 ns/pF = 1.2 ns less than the specified rise time or delay that includes a rise time.

Test conditions for inputs:

■ Rise and fall times of 4 ns or less

■ Timing reference levels for delays = VIH, VIL

Test conditions for outputs (unless noted otherwise):

■ CLOAD = 50 pF; except for CKO, where CLOAD = 20 pF

■ Timing reference levels for delays = VIH, VIL

■ 3-state delays measured to the high-impedance state of the output driver

For the timing diagrams, see Table 62, Electrical Requirements for Mask-Programmable Input Clock Options, for

input clock requirements.

Unless otherwise noted, CKO in the timing diagrams is the free-running CKO.

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Data Sheet

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DSP1629 Digital Signal Processor

10 Timing Characteristics for 3.0 V Operation (continued)

10.1 DSP Clock Generation (3.0 V Operation)

t1

t3

t2

1X CKI*

t4

t5

†

CKO

t6, t6a

‡

CKO

EXTERNAL MEMORY CYCLE

§

W = 1

5-4009 (F).a

*

See Table 62, Electrical Requirements for Mask-Programmable Input Clock Options, for input clock electrical requirements.

†

‡

§

Free-running clock.

Wait-stated clock (see Table 38, ioc Register).

W = number of wait-states.

Figure 12. I/O Clock Timing Diagram (3.0 V Operation)

Table 66. Timing Requirements for Input Clock (3.0 V Operation)

Abbreviated Reference

Parameter

Clock In Period (high to high)

Clock In Low Time (low to high)

Clock In High Time (high to low)

Min

20^†

10

Max

Unit

ns

‡

t1

t2

t3

—

ns

10

ns

†

‡

Device speeds greater than 50 MIPS do not support 1X operation. Use the PLL.

Device is fully static, t1 is tested at 100 ns for 1X input clock option, and memory hold time is tested at 0.1 s.

Table 67. Timing Characteristics for Input Clock and Output Clock (3.0 V Operation)

Abbreviated Reference

Parameter

Clock Out High Delay

Min

—

Max

Unit

ns

t4

t5

10

—

Clock Out Low Delay (high to low)

Clock Out Period (low to low)

—

T^†

ns

t6

ns

t6a

Clock Out Period with SLOWCKI Bit Set in powerc

Register (low to low)

0.74

3.8

µs

†

T = internal clock period, set by CKI or by CKI and the PLL parameters.

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Data Sheet

January 2002

DSP1629 Digital Signal Processor

10 Timing Characteristics for 3.0 V Operation (continued)

10.2 Reset Circuit (3.0 V Operation)

The DSP1629 has two external reset pins: RSTB and TRST. At initial powerup, or if the supply voltage falls below

VDD MIN* and a device reset is required, both TRST and RSTB must be asserted to initialize the device. Figure 13,

Powerup Reset and Chip Reset Timing Diagram (3.0 V Operation), shows two separate events:

■ Chip reset at initial powerup.

■ Chip reset following a drop in power supply.

Note: The TRST pin must be asserted even if the JTAG controller is not used by the application.

*

See Table 60, Recommended Operating Conditions.

V

DD MIN

t146

VDD MIN

VDD

RAMP

0.4 V

t153

t146

0.4 V

t9

t8

V

IH

RSTB,

TRST

IL

t10

t11

t10

OUTPUT VOH

PINS *

V

OL

†

CKI

5-4010 (F).a

*

When both INT0 and RSTB are asserted, all output and bidirectional pins (except TDO, which 3-states by JTAG control) are put in a 3-state

condition. With RSTB asserted and INT0 not asserted, EROM, ERAMHI, ERAMLO, IO, and RWN outputs remain high, and CKO remains a

free-running clock.

†

See Table 62, Electrical Requirements for Mask-Programmable Input Clock Options, for input clock electrical requirements.

Figure 13. Powerup Reset and Chip Reset Timing Diagram (3.0 V Operation)

Table 68. Timing Requirements for Powerup Reset and Chip Reset (3.0 V Operation)

Abbreviated Reference

Parameter

RSTB and TRST Reset Pulse (low to high)

VDD Ramp

Min

6T

Max

—

Unit

ns

t8

t9

—

10

ms

t146

VDD MIN to RSTB Low:

CMOS

2T

20

—

ns

µs

Small-signal

t153

RSTB (low to high)

—

54

ns

Table 69. Timing Characteristics for Powerup Reset and Chip Reset (3.0 V Operation)

Abbreviated Reference

Parameter

Min

—

Max

100

Unit

ns

t10

t11

RSTB Disable Time (low to 3-state)

RSTB Enable Time (high to valid)

—

ns

Note: The device needs to be clocked for at least six CKI cycles during reset after powerup. Otherwise, high cur-

rents may flow.

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Data Sheet

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DSP1629 Digital Signal Processor

10 Timing Characteristics for 3.0 V Operation (continued)

10.3 Reset Synchronization (3.0 V Operation)

t5 + 2 x t6

V^IH

V^IL

*

CKI

t126

V^IH

V^IL

RSTB

CKO

V^IH

V^IL

V^IH

V^IL

CKO

5-4011 (F).a

*

See Table 62, Electrical Requirements for Mask-Programmable Input Clock Options, for input clock electrical requirements.

Notes:

CKO¹and CKO²are two possible CKO states before reset. CKO is free-running.

If the rising edge of RSTB (low to high) is captured instead by the falling edge of CKO (high to low), CKO and CKI will be in-phase at t5 + 2 x t6.

Figure 14. Reset Synchronization Timing (3.0 V Operation)

Table 70. Timing Requirements for Reset Synchronization Timing (3.0 V Operation)

Abbreviated Reference

Parameter

Reset Setup (high to high)

Min

Max

Unit

t126

3

T/2 – 1

ns

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Data Sheet

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DSP1629 Digital Signal Processor

10 Timing Characteristics for 3.0 V Operation (continued)

10.4 JTAG I/O Specifications (3.0 V Operation)

t12

t155

t13

t14

V^IH

V^IL

TCK

TMS

TDI

t15

t156

t16

t18

V^IH

V^IL

t17

V^IH

V^IL

t19

t20

V^OH

V^OL

TDO

5-4017 (F)

Figure 15. JTAG Timing Diagram (3.0 V Operation)

Table 71. Timing Requirements for JTAG Input/Output (3.0 V Operation)

Abbreviated Reference

Parameter

TCK Period (high to high)

Min

50

Max

Unit

ns

t12

t13

—

TCK High Time (high to low)

22.5

0.6

7.5

2

ns

t14

TCK Low Time (low to high)

ns

t155

t156

t15

TCK Rise Transition Time (low to high)

TCK Fall Transition Time (high to low)

TMS Setup Time (valid to high)

TMS Hold Time (high to invalid)

TDI Setup Time (valid to high)

TDI Hold Time (high to invalid)

V/ns

ns

t16

ns

t17

7.5

2

ns

t18

ns

Table 72. Timing Characteristics for JTAG Input/Output (3.0 V Operation)

Abbreviated Reference

Parameter

TDO Delay (low to valid)

TDO Hold (low to invalid)

Min

—

0

Max

19

Unit

ns

t19

t20

—

ns

80

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Data Sheet

January 2002

DSP1629 Digital Signal Processor

10 Timing Characteristics for 3.0 V Operation (continued)

10.5 Interrupt (3.0 V Operation)

V

OH

OL

*

CKO

V

t21

V

IH

IL

INT[1:0]

V

t22

t23

t25

t26

V

OH

OL

†

IACK

V

t24

V

OH

OL

VEC[3:0]

V

5-4018 (F)

*

†

CKO is free-running.

IACK assertion is guaranteed to be enclosed by VEC[3:0] assertion.

Figure 16. Interrupt Timing Diagram (3.0 V Operation)

Table 73. Timing Requirements for Interrupt (3.0 V Operation)

Abbreviated Reference

Parameter

Min

19

Max

—

Unit

t21

t22

Interrupt Setup (high to low)

INT Assertion Time (high to low)

ns

2T

—

Note: Interrupt is asserted during an interruptible instruction and no other pending interrupts.

Table 74. Timing Characteristics for Interrupt (3.0 V Operation)

Abbreviated Reference

Parameter

Min

—

Max

T/2 + 10

12.5

Unit

ns

t23

t24

t25

t26

IACK Assertion Time (low to high)

VEC Assertion Time (low to high)

IACK Invalid Time (low to low)

VEC Invalid Time (low to low)

—

ns

—

10

ns

—

12.5

ns

Note: Interrupt is asserted during an interruptible instruction and no other pending interrupts.

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Data Sheet

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DSP1629 Digital Signal Processor

10 Timing Characteristics for 3.0 V Operation (continued)

10.6 Bit Input/Output (BIO) (3.0 V Operation)

t144

V^OH

CKO

V^OL

t29

IOBIT

(OUTPUT)

V^OH

V^OL

VALID OUTPUT

t28

t27

V^IH

V^IL

IOBIT

(INPUT)

DATA INPUT

5-4019 (F).a

Figure 17. Write Outputs Followed by Read Inputs (cbit = Immediate; a1 = sbit) (3.0 V Operation)

Table 75. Timing Requirements for BIO Input Read (3.0 V Operation)

Abbreviated Reference

Parameter

Min

15

0

Max

—

Unit

ns

t27

t28

IOBIT Input Setup Time (valid to high)

IOBIT Input Hold Time (high to invalid)

—

ns

Table 76. Timing Characteristics for BIO Output (3.0 V Operation)

Abbreviated Reference

Parameter

Min

—

1

Max

9

Unit

ns

t29

IOBIT Output Valid Time (low to valid)

IOBIT Output Hold Time (low to invalid)

t144

—

ns

t144

V^OH–

CKO

V^OL–

t29

IOBIT

(OUTPUT)

V^OH–

V^OL–

VALID OUTPUT

t142

t141

V^IH–

V^IL–

IOBIT

(INPUT)

TEST INPUT

5-4019 (F).b

Figure 18. Write Outputs and Test Inputs (cbit = Immediate) (3.0 V Operation)

Table 77. Timing Requirements for BIO Input Test (3.0 V Operation)

Abbreviated Reference

Parameter

Min

15

0

Max

—

Unit

ns

t141

t142

IOBIT Input Setup Time (valid to low)

IOBIT Input Hold Time (low to invalid)

—

ns

82

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Data Sheet

January 2002

DSP1629 Digital Signal Processor

10 Timing Characteristics for 3.0 V Operation (continued)

10.7 External Memory Interface (3.0 V Operation)

The following timing diagrams, characteristics, and requirements do not apply to interactions with delayed external

memory enables unless so stated. See the DSP1611/17/18/27/28/29 Digital Signal Processor Information Manual

for a detailed description of the external memory interface, including other functional diagrams.

V^OH

CKO

V^OL

t33

t34

V^OH

V^OL

*

ENABLE

W = 0

5-4020 (F).b

*

W = number of wait-states.

Figure 19. Enable Transition Timing (3.0 V Operation)

Table 78. Timing Characteristics for External Memory Enables (EROM, ERAMHI, IO, ERAMLO) (3.0 V Oper-

ation)

Abbreviated Reference

Parameter

Min

0

Max

4.5

4

Unit

ns

t33

t34

CKO to ENABLE Active (low to low)

CKO to ENABLE Inactive (low to high)

–1

ns

Table 79. Timing Characteristics for Delayed External Memory Enables (ioc = 0x000F) (3.0 V Operation)

Abbreviated Reference

Parameter

Min

Max

Unit

t33

CKO to Delayed ENABLE Active (low to low)

T/2

T/2 + 7

ns

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Data Sheet

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DSP1629 Digital Signal Processor

10 Timing Characteristics for 3.0 V Operation (continued)

(MWAIT = 0 x 2222)

W* = 2

V^OH

CKO

V^OL

t127

V^OH

ENABLE

V^OL

t129

t130

V^IH

DB

AB

READ DATA

V^IL

t150

t128

V^OH

V^OL

READ ADDRESS

5-4021 (F).a

*

W = number of wait-states.

Figure 20. External Memory Data Read Timing Diagram (3.0 V Operation)

Table 80. Timing Characteristics for External Memory Access (3.0 V Operation)

Abbreviated Reference

Parameter

Enable Width (low to high)

Min

T(1 + W) – 1.5

—

Max

Unit

ns

t127

t128

—

2

Address Valid (enable low to valid)

ns

Table 81. Timing Requirements for External Memory Read (EROM, ERAMHI, IO, ERAMLO) (3.0 V Operation)

Abbreviated Reference

Parameter

Min

12

0

Max

Unit

ns

t129

t130

t150

Read Data Setup (valid to enable high)

Read Data Hold (enable high to hold)

External Memory Access Time (valid to valid)

—

ns

—

T(1 + W) – 13

ns

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Data Sheet

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DSP1629 Digital Signal Processor

10 Timing Characteristics for 3.0 V Operation (continued)

(MWAIT = 0x1002)

W* = 2

W* = 1

V^OH

CKO

V^OL

V^OH

ERAMLO

V^OL

V^OH

DB

WRITE DATA

READ

V^OL

t131

V^OH

V^OL

EROM

t132

t133

t136

t134

V^OH

V^OL

RWN

AB

t135

V^OH

V^OL

WRITE ADDRESS

READ ADDRESS

5-4022 (F).a

*

W = number of wait-states.

Figure 21. External Memory Data Write Timing Diagram (3.0 V Operation)

Table 82. Timing Characteristics for External Memory Data Write (All Enables) (3.0 V Operation)

Abbreviated Reference

Parameter

Min

Max

0

Unit

ns

t131

t132

t133

t134

t135

t136

Write Overlap (enable low to 3-state)

RWN Advance (RWN high to enable high)

RWN Delay (enable low to RWN low)

Write Data Setup (data valid to RWN high)

RWN Width (low to high)

—

0

—

ns

0

ns

T(1 + W)/2 – 3

T(1 + W) – 4

0

ns

Write Address Setup (address valid to RWN low)

ns

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Data Sheet

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DSP1629 Digital Signal Processor

10 Timing Characteristics for 3.0 V Operation (continued)

(MWAIT = 0x1002)

W* = 1

W* = 2

V^OH

CKO

V^OL

V^OH

ERAMLO

V^OL

V^OH

EROM

V^OL

t131

V^OH

DB

WRITE

READ

V^OL

t137

t138

V^OH

V^OL

RWN

t139

V^OH

V^OL

AB

WRITE ADDRESS

READ ADDRESS

5-4023 (F).a

*

W = number of wait-states.

Figure 22. Write Cycle Followed by Read Cycle (3.0 V Operation)

Table 83. Timing Characteristics for Write Cycle Followed by Read Cycle (3.0 V Operation)

Abbreviated Reference

Parameter

Min

—

0

Max

Unit

ns

t131

t137

t138

t139

Write Overlap (enable low to 3-state)

Write Data 3-state (RWN high to 3-state)

Write Data Hold (RWN high to data hold)

Write Address Hold (RWN high to address hold)

0

2

ns

—

ns

0

ns

86

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Data Sheet

January 2002

DSP1629 Digital Signal Processor

10 Timing Characteristics for 3.0 V Operation (continued)

10.8 PHIF Specifications (3.0 V Operation)

For the PHIF, read means read by the external user (output by the DSP); write is similarly defined. The 8-bit reads/writes

are identical to one-half of a 16-bit access.

16-bit READ

16-bit WRITE

V

IH–

IL–

PCSN

PODS

V

IH–

IL–

V

t41

t42

t44

V

IH–

IL–

PIDS

PBSEL

PSTAT

V

t43

t47

V

IH–

IL–

V

t45

t48

t52

t46

V

IH–

IL–

V

t51

t50

t154

t49

V

IH–

IL–

PB[7:0]

V

5-4036 (F)

Figure 23. PHIF Intel Mode Signaling (Read and Write) Timing Diagram (3.0 V Operation)

Table 84. Timing Requirements for PHIF Intel Mode Signaling (3.0 V Operation)

Abbreviated Reference

Parameter

Min

0

Max

—

Unit

t41

t42

PODS to PCSN Setup (low to low)

PCSN to PODS Hold (high to high)

PIDS to PCSN Setup (low to low)

PCSN to PIDS Hold (high to high)

PSTAT to PCSN Setup (valid to low)

PCSN to PSTAT Hold (high to invalid)

PBSEL to PCSN Setup (valid to low)

PCSN to PBSEL Hold (high to invalid)

PB Write to PCSN Setup (valid to high)

PCSN to PB Write Hold (high to invalid)

ns

0

t43

0

t44

0

t45*

t46*

t47*

t48*

t51*

t52*

4

0

6

0

10

4

*

This timing diagram for the PHIF port shows accesses using the PCSN signal to initiate and complete a transaction. The transactions can also be

initiated and completed with the PIDS and PODS signals. An output transaction (read) is initiated by PCSN or PODS going low, whichever comes

last. For example, the timing requirements referenced to PCSN going low, t45 and t49, should be referenced to PODS going low, if PODS goes low

after PCSN. An output transaction is completed by PCSN or PODS going high, whichever comes first. An input transaction is initiated by PCSN or

PIDS going low, whichever comes last. An input transaction is completed by PCSN or PIDS going high, whichever comes first. All requirements

referenced to PCSN apply to PIDS or PODS, if PIDS or PODS is the controlling signal.

Table 85. Timing Characteristics for PHIF Intel Mode Signaling (3.0 V Operation)

Abbreviated Reference

Parameter

Min

—

0

Max

12

—

Unit

ns

t49^*

t50*

t154

PCSN to PB Read (low to valid)

PCSN to PB Read Hold (high to invalid)

PCSN to PB Read 3-state (high to 3-state)

ns

—

8

ns

*

This timing diagram for the PHIF port shows accesses using the PCSN signal to initiate and complete a transaction. The transactions can also

be initiated and completed with the PIDS and PODS signals. An output transaction (read) is initiated by PCSN or PODS going low, whichever

comes last. For example, the timing requirements referenced to PCSN going low, t45 and t49, should be referenced to PODS going low, if PODS

goes low after PCSN. An output transaction is completed by PCSN or PODS going high, whichever comes first. An input transaction is initiated

by PCSN or PIDS going low, whichever comes last. An input transaction is completed by PCSN or PIDS going high, whichever comes first. All

requirements referenced to PCSN apply to PIDS or PODS, if PIDS or PODS is the controlling signal.

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Data Sheet

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DSP1629 Digital Signal Processor

10 Timing Characteristics for 3.0 V Operation (continued)

16-bit READ

16-bit WRITE

8-bit READ

8-bit WRITE

t55

V

IH

PCSN

V

IL

t56

t55

t56

V

IH

PODS

PIDS

V

IL

t56

t55

VIH

V

IL

t56

V

OH

PBSEL

POBE

PIBF

V

OL

t53

V

OH

VOL

t54

VOH

VOL

5-4037 (F).a

Figure 24. PHIF Intel Mode Signaling (Pulse Period and Flags) Timing Diagram (3.0 V Operation)

Table 86. Timing Requirements for PHIF Intel Mode Signaling (3.0 V Operation)

Abbreviated Reference

Parameter

Min

20.5

Max

—

Unit

ns

t55

t56

PCSN/PODS/PIDS Pulse Width (high to low)

PCSN/PODS/PIDS Pulse Width (low to high)

—

ns

Table 87. Timing Characteristics for PHIF Intel Mode Signaling (3.0 V Operation)

Abbreviated Reference

Parameter

PCSN/PODS to POBE^†(high to high)

Min

Max

Unit

t53^*

—

17

ns

PCSN/PIDS to PIBF^†(high to high)

t54*

—

17

ns

*

t53 should be referenced to the rising edge of PCSN or PODS, whichever comes first. t54 should be referenced to the rising edge of PCSN

or PIDS, whichever comes first.

†

POBE and PIBF may be programmed to be the opposite logic levels shown in the diagram (positive assertion levels shown). t53 and t54

apply to the inverted levels as well as those shown.

88

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Data Sheet

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DSP1629 Digital Signal Processor

10 Timing Characteristics for 3.0 V Operation (continued)

16-bit READ

16-bit WRITE

V^IH—

PCSN

V^IL—

t42

V^IH—

PDS

V^IL—

t41

t43

t44

V^IH—

PRWN

V^IL—

t43

t45

t44

V^IH—

V^IL—

PBSEL

t47

t48

t52

t46

V^IH—

V^IL—

PSTAT

PB[7:0]

t49

t50

t154

t51

V^IH—

V^IL—

5-4038 (F).a

Figure 25. PHIF Motorola Mode Signaling (Read and Write) Timing Diagram (3.0 V Operation)

Table 88. Timing Requirements for PHIF Motorola Mode Signaling (3.0 V Operation)

Abbreviated Reference

Parameter

Min

Max

Unit

PDS^†to PCSN Setup (valid to low)

t41

0

—

ns

PCSN to PDS^†Hold (high to invalid)

PRWN to PCSN Setup (valid to low)

PCSN to PRWN Hold (high to invalid)

PSTAT to PCSN Setup (valid to low)

PCSN to PSTAT Hold (high to invalid)

PBSEL to PCSN Setup (valid to low)

PCSN to PBSEL Hold (high to invalid)

PB Write to PCSN Setup (valid to high)

PCSN to PB Write Hold (high to invalid)

t42

0

—

t43

t44

4

0

4

0

6

0

10

4

—

ns

t45*

t46*

t47*

t48*

t51*

t52*

*

This timing diagram for the PHIF port shows accesses using the PCSN signal to initiate and complete a transaction. The transactions can

also be initiated and completed with the PDS signal. An input/output transaction is initiated by PCSN or PDS going low, whichever comes last.

For example, the timing requirements referenced to PCSN going low, t45 and t49, should be referenced to PDS going low, if PDS goes low

after PCSN. An input/output transaction is completed by PCSN or PDS going high, whichever comes first. All requirements referenced to

PCSN should be referenced to PDS, if PDS is the controlling signal. PRWN should never be used to initiate or complete a transaction.

PDS is programmable to be active-high or active-low. It is shown active-low in Figures 49 and 50. POBE and PIBF may be programmed to

be the opposite logic levels shown in the diagram. t53 and t54 apply to the inverted levels as well as those shown.

†

Table 89. Timing Characteristics for PHIF Motorola Mode Signaling (3.0 V Operation)

Abbreviated Reference

Parameter

PCSN to PB Read (low to valid)

PCSN to PB Read Hold (high to invalid)

PCSN to PB Read 3-state (high to 3-state)

Min

—

0

Max

12

—

Unit

ns

t49*

t50*

t154

—

8

ns

*

This timing diagram for the PHIF port shows accesses using the PCSN signal to initiate and complete a transaction. The transactions can

also be initiated and completed with the PDS signal. An input/output transaction is initiated by PCSN or PDS going low, whichever comes last.

For example, the timing requirements referenced to PCSN going low, t45 and t49, should be referenced to PDS going low, if PDS goes low

after PCSN. An input/output transaction is completed by PCSN or PDS going high, whichever comes first. All requirements referenced to

PCSN should be referenced to PDS, if PDS is the controlling signal. PRWN should never be used to initiate or complete a transaction.

Agere Systems Inc.

89

Data Sheet

January 2002

DSP1629 Digital Signal Processor

10 Timing Characteristics for 3.0 V Operation (continued)

16-bit READ

16-bit WRITE

8-bit READ

8-bit WRITE

t55

V

IH

–

PCSN

V

IL

t56

t55

t56

V

IH

–

PDS

V

IL

t56

t55

V

IH

–

PIDS

V

IL

t56

V

OH

–

PBSEL

POBE

PIBF

V

OL–

t53

VOH

–

V

OL

t54

VOH

–

V

OL

5-4039 (F).a

Figure 26. PHIF Motorola Mode Signaling (Pulse Period and Flags) Timing Diagram (3.0 V Operation)

Table 90. Timing Characteristics for PHIF Motorola Mode Signaling (3.0 V Operation)

Abbreviated Reference

Parameter

PCSN/PDS^†to POBE^†(high to high)

PCSN/PDS^†to PIBF^†(high to high)

Min

—

Max

17

Unit

ns

t53*

t54*

—

17

ns

*

An input/output transaction is initiated by PCSN or PDS going low, whichever comes last. For example, t53 and t54 should be referenced to

PDS going low, if PDS goes low after PCSN. An input/output transaction is completed by PCSN or PDS going high, whichever comes first.

All requirements referenced to PCSN should be referenced to PDS, if PDS is the controlling signal. PRWN should never be used to initiate or

complete a transaction.

†

PDS is programmable to be active-high or active-low. It is shown active-low in Figures 49 and 50. POBE and PIBF may be programmed to

be the opposite logic levels shown in the diagram. t53 and t54 apply to the inverted levels as well as those shown.

Table 91. Timing Requirements for PHIF Motorola Mode Signaling (3.0 V Operation)

Abbreviated Reference

Parameter

Min

20

Max

—

Unit

ns

t55

t56

PCSN/PDS/PRWN Pulse Width (high to low)

PCSN/PDS/PRWN Pulse Width (low to high)

20

—

ns

90

Agere Systems Inc.

Data Sheet

January 2002

DSP1629 Digital Signal Processor

10 Timing Characteristics for 3.0 V Operation (continued)

V^IH—

PCSN

V^IL—

V^IH—

V^IL—

PODS (PDS*)

V^IH—

V^IL—

PIDS (PRWN*)

t47

t48

t46

V^IH—

V^IL—

PBSEL

t45

V^IH—

V^IL—

PSTAT

t50

t154

t49

V^IH—

PB[7:0]

V^IL—

5-4040 (F).a

*

Motorola mode signal name.

Figure 27. PHIF Intel or Motorola Mode Signaling (Status Register Read) Timing Diagram (3.0 V Operation)

Table 92. Timing Requirements for Intel and Motorola Mode Signaling (Status Register Read) (3.0 V Opera-

tion)

Abbreviated Reference

Parameter

Min

4

Max

—

Unit

ns

t45^†

t46^‡

t47^†

t48^‡

PSTAT to PCSN Setup (valid to low)

PCSN to PSTAT Hold (high to invalid)

PBSEL to PCSN Setup (valid to low)

PCSN to PBSEL Hold (high to invalid)

0

—

ns

6

—

ns

0

—

ns

†

‡

t45, t47, and t49 are referenced to the falling edge of PCSN or PODS(PDS), whichever occurs last.

t46, t48, and t50 are referenced to the rising edge of PCSN or PODS(PDS), whichever occurs first.

Table 93. Timing Characteristics for Intel and Motorola Mode Signaling (Status Register Read) (3.0 V Oper-

ation)

Abbreviated Reference

Parameter

Min

—

0

Max

12

—

Unit

ns

t49^†

t50^‡

t154

PCSN to PB Read (low to valid)

PCSN to PB Read Hold (high to invalid)

PCSN to PB Read 3-state (high to 3-state)

ns

—

8

ns

†

‡

t45, t47, and t49 are referenced to the falling edge of PCSN or PODS(PDS), whichever occurs last.

t46, t48, t154, and t50 are referenced to the rising edge of PCSN or PODS(PDS), whichever occurs first.

Agere Systems Inc.

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Data Sheet

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DSP1629 Digital Signal Processor

10 Timing Characteristics for 3.0 V Operation (continued)

V^IH–

RSTB

V^IL–

t57

V^OH–

POBE

V^OL–

t58

V^OH–

PIBF

V^OL–

5-4775 (F)

Figure 28. PHIF, PIBF, and POBE Reset Timing Diagram (3.0 V Operation)

Table 94. PHIF Timing Characteristics for PHIF, PIBF, and POBE Reset (3.0 V Operation)

Abbreviated Reference

Parameter

Min

—

3

Max

Unit

ns

t57

t58

RSTB Disable to POBE/PIBF* (high to valid)

RSTB Enable to POBE/PIBF* (low to invalid)

25

ns

*

After reset, POBE and PIBF always go to the levels shown, indicating output buffer empty and input buffer empty. The DSP program, however,

may later invert the definition of the logic levels for POBE and PIBF. t57 and t58 continue to apply.

V^IH–

CKO

V^IL–

t59

V^OH–

V^OL–

†

POBE

t59

V^OH–

V^OL–

†

PIBF

5-4776 (F)

†

POBE and PIBF can be programmed to be active-high or active-low. They are shown active-high. The timing characteristic for active-low is

the same as for active-high^.

Figure 29. PHIF, PIBF, and POBE Disable Timing Diagram (3.0 V Operation)

Table 95. PHIF Timing Characteristics for POBE and PIBF Disable (3.0 V Operation)

Abbreviated Reference

Parameter

Min

Max

Unit

t59

CKO to POBE/PIBF Disable (high/low to disable)

—

20

ns

92

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Data Sheet

January 2002

DSP1629 Digital Signal Processor

10 Timing Characteristics for 3.0 V Operation (continued)

10.9 Serial I/O Specifications (3.0 V Operation)

t70

t72

t75

t71

t74

V^IH–

V^IL–

ICK

t73

t75

V^IH–

V^IL–

ILD

DI

t77

t78

V^IH–

V^IL–

B0

B1

BN – 1*

t79

B0

V^OH–

V^OL–

IBF

5-4777 (F)

*

N = 16 bits or 8 bits.

Figure 30. SIO Passive Mode Input Timing Diagram (3.0 V Operation)

Table 96. Timing Requirements for Serial Inputs (3.0 V Operation)

Abbreviated Reference

Parameter

Clock Period (high to high)^†

Clock Low Time (low to high)

Clock High Time (high to low)

Load High Setup (high to high)

Load Low Setup (low to high)

Load High Hold (high to invalid)

Data Setup (valid to high)

Min

40

18

8

Max

Unit

ns

‡

t70

t71

t72

t73

t74

t75

t77

t78

—

8

0

7

Data Hold (high to invalid)

0

†

‡

For multiprocessor mode, see note in Section 11.10, Multiprocessor Communication (2.7 V Operation).

Device is fully static; t70 is tested at 200 ns.

Table 97. Timing Characteristics for Serial Outputs (3.0 V Operation)

Abbreviated Reference

Parameter

Min

Max

35

Unit

t79

IBF Delay (high to high)

—

ns

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Data Sheet

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DSP1629 Digital Signal Processor

10 Timing Characteristics for 3.0 V Operation (continued)

V^OH–

ICK

V^OL–

t101

t76a

V^OH–

ILD

V^OL–

*

t77

t78

V^IH–

V^IL–

DI

B0

B1

BN – 1

t79

B0

V^OH–

V^OL–

IBF

5-4778 (F)

*

ILD goes high during bit 6 (of 0:15); N = 8 or 16.

Figure 31. SIO Active Mode Input Timing Diagram (3.0 V Operation)

Table 98. Timing Requirements for Serial Inputs (3.0 V Operation)

Abbreviated Reference

Parameter

Data Setup (valid to high)

Data Hold (high to invalid)

Min

7

Max

Unit

ns

t77

t78

—

0

ns

Table 99. Timing Characteristics for Serial Outputs (3.0 V Operation)

Abbreviated Reference

Parameter

ILD Delay (high to low)

ILD Hold (high to invalid)

IBF Delay (high to high)

Min

—

3

Max

35

Unit

ns

t76a

t101

t79

—

ns

—

35

ns

94

Agere Systems Inc.

Data Sheet

January 2002

DSP1629 Digital Signal Processor

10 Timing Characteristics for 3.0 V Operation (continued)

t80

t82

t85

t81

t84

V^IH–

V^IL–

OCK

t83

t85

V^IH–

V^IL–

OLD

DO*

t88

t94

t87

B0

t90

B1

t90

t93

V^OH–

V^OL–

B7

BN – 1

AS7

t89

t95

t92

AD0

t93

V^OH–

V^OL–

SADD

DOEN

OBE

AD7

AD1

V^IH–

V^IL–

t96

V^OH–

V^OL–

5-4796 (F)

*

See sioc register, MSB field, to determine if B0 is the MSB or LSB. See sioc register, ILEN field, to determine if the DO word length is 8 bits

or 16 bits.

Figure 32. SIO Passive Mode Output Timing Diagram (3.0 V Operation)

Table 100. Timing Requirements for Serial Inputs (3.0 V Operation)

Abbreviated Reference

Parameter

Min

Max

Unit

Clock Period (high to high)^†

Clock Low Time (low to high)

Clock High Time (high to low)

Load High Setup (high to high)

Load Low Setup (low to high)

Load Hold (high to invalid)

‡

t80

40

ns

—

t81

t82

t83

t84

t85

18

8

—

ns

8

0

†

‡

For multiprocessor mode, see note in Section 11.10, Multiprocessor Communication (2.7 V Operation).

Device is fully static; t80 is tested at 200 ns.

Table 101. Timing Characteristics for Serial Outputs (3.0 V Operation)

Abbreviated Reference

Parameter

Min

—

3

Max

35

—

Unit

ns

t87

t88

t89

t90

t92

t93

t94

t95

t96

Data Delay (high to valid)

Enable Data Delay (low to active)

Disable Data Delay (high to 3-state)

Data Hold (high to invalid)

Address Delay (high to valid)

Address Hold (high to invalid)

Enable Delay (low to active)

Disable Delay (high to 3-state)

OBE Delay (high to high)

—

3

35

—

35

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Data Sheet

January 2002

DSP1629 Digital Signal Processor

10 Timing Characteristics for 3.0 V Operation (continued)

V^OH–

OCK

V^OL–

t102

t86a

V^OH–

OLD

*

V^OL–

t88

t94

t87

B0

t90

B1

t90

t93

V^OH–

V^OL–

DO

B7

BN – 1

AS7

t89

t95

t92

AD0

t93

V^OH–

V^OL–

SADD

DOEN

OBE

AD7

AD1

V^IH–

V^IL–

t96

V^OH–

V^OL–

5-4797 (F)

*

OLD goes high at the end of bit 6 of 0:15.

Figure 33. SIO Active Mode Output Timing Diagram (3.0 V Operation)

Table 102. Timing Characteristics for Serial Output (3.0 V Operation)

Abbreviated Reference

Parameter

OLD Delay (high to low)

Min

—

3

Max

Unit

ns

t86a

t102

t87

t88

t89

t90

t92

t93

t94

t95

t96

35

—

35

—

35

—

35

OLD Hold (high to invalid)

Data Delay (high to valid)

—

3

Enable Data Delay (low to active)

Disable Data Delay (high to 3-state)

Data Hold (high to invalid)

Address Delay (high to valid)

Address Hold (high to invalid)

Enable Delay (low to active)

Disable Delay (high to 3-state)

OBE Delay (high to high)

—

3

—

96

Agere Systems Inc.

Data Sheet

January 2002

DSP1629 Digital Signal Processor

10 Timing Characteristics for 3.0 V Operation (continued)

V^OH–

CKO

V^OL–

t97

t99

t98

V^OH–

V^OL–

ICK

t100

V^OH–

V^OL–

OCK

V^OH–

ICK/OCK*

t76a

t101

t76b

t101

V^OH–

V^OL–

ILD

t86a

t102

t86b

t102

V^OH–

V^OL–

OLD

t104

t105

t103

t105

V^OH–

V^OL–

SYNC

5-4798 (F)

*

See sioc register, LD field.

Figure 34. Serial I/O Active Mode Clock Timing (3.0 V Operation)

Table 103. Timing Characteristics for Signal Generation (3.0 V Operation)

Abbreviated Reference

Parameter

Min

—

3

Max

18

35

—

Unit

t97

ICK Delay (high to high)

ICK Delay (high to low)

OCK Delay (high to high)

OCK Delay (high to low)

ILD Delay (high to low)

ILD Delay (high to high)

ILD Hold (high to invalid)

OLD Delay (high to low)

OLD Delay (high to high)

OLD Hold (high to invalid)

SYNC Delay (high to low)

SYNC Delay (high to high)

SYNC Hold (high to invalid)

ns

t98

t99

t100

t76a

t76b

t101

t86a

t86b

t102

t103

t104

t105

—

3

35

—

3

35

—

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Data Sheet

January 2002

DSP1629 Digital Signal Processor

10 Timing Characteristics for 3.0 V Operation (continued)

10.10 Multiprocessor Communication (3.0 V Operation)

TIME SLOT 1

TIME SLOT 2

OCK/ICK

t113

t112

t113

V^IH–

V^IL–

SYNC

*

t116

B1

t117

V^OH–

V^OL–

B15

B0

B7

B8

B15

AS7

B0

DO/D1

SADD

t114

t122

t120

t121

AD0 AD1

t115

AD7 AS0

AD0

t120

V^OH–

V^OL–

DOEN

5-4799 (F)

*

Negative edge initiates time slot 0.

Figure 35. SIO Multiprocessor Timing Diagram (3.0 V Operation)

Note: All serial I/O timing requirements and characteristics still apply, but the minimum clock period in passive

multiprocessor mode, assuming 50% duty cycle, is calculated as (t77 + t116) 2.

*

Table 104. Timing Requirements for SIO Multiprocessor Communication (3.0 V Operation)

Abbreviated Reference

Parameter

Sync Setup (high/low to high)

Sync Hold (high to high/low)

Address Setup (valid to high)

Address Hold (high to invalid)

Min

35

0

Max

—

Unit

ns

t112

t113

t114

t115

—

ns

12

0

—

ns

—

ns

Table 105. Timing Characteristics for SIO Multiprocessor Communication (3.0 V Operation)

Abbreviated Reference^†

Parameter

Min

—

Max

35

Unit

ns

t116

t117

t120

t121

t122

Data Delay (bit 0 only) (low to valid)

Data Disable Delay (high to 3-state)

DOEN Valid Delay (high to valid)

Address Delay (bit 0 only) (low to valid)

Address Disable Delay (high to 3-state)

—

30

ns

—

25

ns

—

35

ns

—

30

ns

†

With capacitance load on ICK, OCK, DO, SYNC, and SADD = 100 pF, add 4 ns to t116—t122.

98

Agere Systems Inc.

Data Sheet

January 2002

DSP1629 Digital Signal Processor

11 Timing Characteristics for 2.7 V Operation

The following timing characteristics and requirements are preliminary information and are subject to change. Timing

characteristics refer to the behavior of the device under specified conditions. Timing requirements refer to conditions

imposed on the user for proper operation of the device. All timing data is valid for the following conditions:

TA = –40 °C to +85 °C (See Section 8.3, Recommended Operating Conditions.)

VDD = 3 V ± 10%, VSS = 0 V (See Section 8.3, Recommended Operating Conditions.)

Capacitance load on outputs (CL) = 50 pF, except for CKO, where CL = 20 pF.

Output characteristics can be derated as a function of load capacitance (CL).

All outputs: 0.03 ns/pF ≤ dt/dCL ≤ 0.07 ns/pF for 10 ≤ CL ≤ 100 pF at VIH for rising edge and at VIL for falling edge.

For example, if the actual load capacitance is 30 pF instead of 50 pF, the derating for a rising edge is (30 – 50) pF

x 0.06 ns/pF = 1.2 ns less than the specified rise time or delay that includes a rise time.

Test conditions for inputs:

■ Rise and fall times of 4 ns or less

■ Timing reference levels for delays = VIH, VIL

Test conditions for outputs (unless noted otherwise):

■ CLOAD = 50 pF; except for CKO, where CLOAD = 20 pF

■ Timing reference levels for delays = VIH, VIL

■ 3-state delays measured to the high-impedance state of the output driver

For the timing diagrams, see Table 62, Electrical Requirements for Mask-Programmable Input Clock Options, for

input clock requirements.

Unless otherwise noted, CKO in the timing diagrams is the free-running CKO.

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Data Sheet

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DSP1629 Digital Signal Processor

11 Timing Characteristics for 2.7 V Operation (continued)

11.1 DSP Clock Generation (2.7 V Operation)

t1

t3

t2

1X CKI*

t4

t5

†

CKO

t6, t6a

‡

CKO

EXTERNAL MEMORY CYCLE

§

W = 1

5-4009 (F).a

*

See Table 62, Electrical Requirements for Mask-Programmable Input Clock Options, for input clock electrical requirements.

†

‡

§

Free-running clock.

Wait-stated clock (see Table 38, ioc Register).

W = number of wait-states.

Figure 36. I/O Clock Timing Diagram (2.7 V Operation)

Table 106. Timing Requirements for Input Clock (2.7 V Operation)

19.2 ns and 12.5 ns^†

Abbreviated Reference

Parameter

Min

Max

Unit

‡

t1

Clock In Period (high to high)

20

ns

—

t2

t3

Clock In Low Time (low to high)

Clock In High Time (high to low)

10

—

ns

†

‡

Device speeds greater than 50 MIPS do not support 1X operation. Use the PLL.

Device is fully static, t1 is tested at 100 ns for 1X input clock option, and memory hold time is tested at 0.1 s.

Table 107. Timing Characteristics for Input Clock and Output Clock (2.7 V Operation)

Abbreviated Reference

Parameter

19.2 ns

12.5 ns

Unit

Min

Max

14

Min

Max

10

t4

t5

Clock Out High Delay

—

T^†

—

T^†

ns

µs

Clock Out Low Delay (high to low)

Clock Out Period (low to low)

14

10

t6

—

t6a

Clock Out Period with SLOWCKI Bit Set 0.74

in powerc Register (low to low)

3.8

0.74

3.8

†

T = internal clock period, set by CKI or by CKI and the PLL parameters.

100

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Data Sheet

January 2002

DSP1629 Digital Signal Processor

11 Timing Characteristics for 2.7 V Operation (continued)

11.2 Reset Circuit (2.7 V Operation)

The DSP1629 has two external reset pins: RSTB and TRST. At initial powerup, or if the supply voltage falls below

VDD MIN* and a device reset is required, both TRST and RSTB must be asserted to initialize the device. Figure 37,

Powerup Reset and Chip Reset Timing Diagram (2.7 V Operation), shows two separate events:

■ Chip reset at initial powerup.

■ Chip reset following a drop in power supply.

Note: The TRST pin must be asserted even if the JTAG controller is not used by the application.

*

See Table 60, Recommended Operating Conditions.

V

^DDMIN

t146

VDD MIN

VDD

RAMP

0.4 V

t153

t146

0.4 V

t9

t8

V

IH

RSTB,

TRST

IL

t10

t11

t10

OUTPUT VOH

PINS*

V

OL

†

CKI

5-4010 (F).a

*

When both INT0 and RSTB are asserted, all output and bidirectional pins (except TDO, which 3-states by JTAG control) are put in a 3-state

condition. With RSTB asserted and INT0 not asserted, EROM, ERAMHI, ERAMLO, IO, and RWN outputs remain high, and CKO remains a

free-running clock.

†

See Table 62, Electrical Requirements for Mask-Programmable Input Clock Options, for input clock electrical requirements.

Figure 37. Powerup Reset and Chip Reset Timing Diagram (2.7 V Operation)

Table 108. Timing Requirements for Powerup Reset and Chip Reset (2.7 V Operation)

Abbreviated Reference

Parameter

RSTB and TRST Reset Pulse (low to high)

VDD Ramp

Min

6T

Max

—

Unit

ns

t8

t9

—

10

ms

t146

VDD MIN to RSTB Low:

CMOS

2T

20

—

ns

µs

Small-signal

t153

RSTB (low to high)

—

54

ns

Table 109. Timing Characteristics for Powerup Reset and Chip Reset (2.7 V Operation)

Abbreviated Reference

Parameter

Min

—

Max

100

Unit

ns

t10

t11

RSTB Disable Time (low to 3-state)

RSTB Enable Time (high to valid)

—

ns

Note: The device needs to be clocked for at least six CKI cycles during reset after powerup. Otherwise, high currents may flow.

Agere Systems Inc.

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Data Sheet

January 2002

DSP1629 Digital Signal Processor

11 Timing Characteristics for 2.7 V Operation (continued)

11.3 Reset Synchronization (2.7 V Operation)

t5 + 2 x t6

V^IH

V^IL

*

CKI

t126

V^IH

V^IL

RSTB

CKO

V^IH

V^IL

V^IH

V^IL

CKO

5-4011 (F).a

*

See Table 62, Electrical Requirements for Mask-Programmable Input Clock Options, for input clock electrical requirements.

Notes:

CKO¹and CKO²are two possible CKO states before reset. CKO is free-running.

If the rising edge of RSTB (low to high) is captured instead by the falling edge of CKO (high to low), CKO and CKI will be in-phase at t5 + 2 x t6.

Figure 38. Reset Synchronization Timing (2.7 V Operation)

Table 110. Timing Requirements for Reset Synchronization Timing (2.7 V Operation)

Abbreviated Reference

Parameter

Reset Setup (high to high)

Min

Max

Unit

t126

3

T/2 – 1

ns

102

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Data Sheet

January 2002

DSP1629 Digital Signal Processor

11 Timing Characteristics for 2.7 V Operation (continued)

11.4 JTAG I/O Specifications (2.7 V Operation)

t12

t155

t13

t14

V^IH

V^IL

TCK

TMS

TDI

t15

t156

t16

t18

V^IH

V^IL

t17

V^IH

V^IL

t19

t20

V^OH

V^OL

TDO

5-4017 (F)

Figure 39. JTAG Timing Diagram (2.7 V Operation)

Table 111. Timing Requirements for JTAG Input/Output (2.7 V Operation)

Abbreviated Reference

Parameter

Min

50

Max

—

Unit

t12

t13

TCK Period (high to high)

ns

TCK High Time (high to low)

22.5

0.6

7.5

2

t14

TCK Low Transition Time (low to high)

TCK Rise Transition Time (low to high)

TCK Fall Transition Time (high to low)

TMS Setup Time (valid to high)

TMS Hold Time (high to invalid)

TDI Setup Time (valid to high)

TDI Hold Time (high to invalid)

ns

t155

t156

t15

V/ns

ns

t16

ns

t17

7.5

2

ns

t18

ns

Table 112. Timing Characteristics for JTAG Input/Output (2.7 V Operation)

Abbreviated Reference

Parameter

TDO Delay (low to valid)

TDO Hold (low to invalid)

Min

—

0

Max

19

Unit

ns

t19

t20

—

ns

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Data Sheet

January 2002

DSP1629 Digital Signal Processor

11 Timing Characteristics for 2.7 V Operation (continued)

11.5 Interrupt (2.7 V Operation)

V

OH

OL

*

CKO

V

t21

V

IH

IL

INT[1:0]

V

t22

t23

t25

t26

V

OH

OL

†

IACK

V

t24

V

OH

OL

VEC[3:0]

V

5-4018 (F)

*

†

CKO is free-running.

IACK assertion is guaranteed to be enclosed by VEC[3:0] assertion.

Figure 40. Interrupt Timing Diagram (2.7 V Operation)

Table 113. Timing Requirements for Interrupt (2.7 V Operation)

Abbreviated Reference

Parameter

Min

19

Max

—

Unit

ns

t21

t22

Interrupt Setup (high to low)

INT Assertion Time (high to low)

2T

—

ns

Note: Interrupt is asserted during an interruptible instruction and no other pending interrupts.

Table 114. Timing Characteristics for Interrupt (2.7 V Operation)

Abbreviated Reference

Parameter

Min

—

Max

Unit

t23

t24

t25

t26

IACK Assertion Time (low to high)

VEC Assertion Time (low to high)

IACK Invalid Time (low to low)

VEC Invalid Time (low to low)

T/2 + 10

12.5

ns

—

10

—

12.5

Note: Interrupt is asserted during an interruptible instruction and no other pending interrupts.

104

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Data Sheet

January 2002

DSP1629 Digital Signal Processor

11 Timing Characteristics for 2.7 V Operation (continued)

11.6 Bit Input/Output (BIO) (2.7 V Operation)

t144

V^OH

CKO

V^OL

t29

IOBIT

(OUTPUT)

V^OH

V^OL

VALID OUTPUT

t28

t27

V^IH

V^IL

IOBIT

(INPUT)

DATA INPUT

5-4019 (F).a

Figure 41. Write Outputs Followed by Read Inputs (cbit = Immediate; a1 = sbit) (2.7 V Operation)

Table 115. Timing Requirements for BIO Input Read (2.7 V Operation)

Abbreviated Reference

Parameter

Min

15

0

Max

—

Unit

ns

t27

t28

IOBIT Input Setup Time (valid to high)

IOBIT Input Hold Time (high to invalid)

—

ns

Table 116. Timing Characteristics for BIO Output (2.7 V Operation)

Abbreviated Reference

Parameter

Min

—

1

Max

9

Unit

ns

t29

IOBIT Output Valid Time (low to valid)

IOBIT Output Hold Time (low to invalid)

t144

—

ns

t144

V^OH–

CKO

V^OL–

t29

IOBIT

(OUTPUT)

V^OH–

V^OL–

VALID OUTPUT

t142

t141

V^IH–

V^IL–

IOBIT

(INPUT)

TEST INPUT

5-4019 (F).b

Figure 42. Write Outputs and Test Inputs (cbit = Immediate) (2.7 V Operation)

Table 117. Timing Requirements for BIO Input Test (2.7 V Operation)

Abbreviated Reference

Parameter

Min

15

0

Max

—

Unit

ns

t141

t142

IOBIT Input Setup Time (valid to low)

IOBIT Input Hold Time (low to invalid)

—

ns

Agere Systems Inc.

105

Data Sheet

January 2002

DSP1629 Digital Signal Processor

11 Timing Characteristics for 2.7 V Operation (continued)

11.7 External Memory Interface (2.7 V Operation)

The following timing diagrams, characteristics, and requirements do not apply to interactions with delayed external

memory enables unless so stated. See the DSP1611/17/18/27/28/29 Digital Signal Processor Information Manual

for a detailed description of the external memory interface, including other functional diagrams.

V^OH

CKO

V^OL

t33

t34

V^OH

V^OL

*

ENABLE

W = 0

5-4020 (F).b

*

W = number of wait-states.

Figure 43. Enable Transition Timing (2.7 V Operation)

Table 118. Timing Characteristics for External Memory Enables (EROM, ERAMHI, IO, ERAMLO) (2.7 V Oper-

ation)

Abbreviated Reference

Parameter

Min

0

Max

5

Unit

ns

t33

t34

CKO to ENABLE Active (low to low)

CKO to ENABLE Inactive (low to high)

–1

4.5

ns

Table 119. Timing Characteristics for Delayed External Memory Enables (ioc = 0x000F) (2.7 V Operation)

Abbreviated Reference

Parameter

Min

Max

Unit

t33

CKO to Delayed ENABLE Active (low to low)

T/2

T/2 + 7

ns

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Data Sheet

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DSP1629 Digital Signal Processor

11 Timing Characteristics for 2.7 V Operation (continued)

(MWAIT = 0 x 2222)

W* = 2

V^OH

CKO

V^OL

t127

V^OH

ENABLE

V^OL

t129

t130

V^IH

DB

AB

READ DATA

V^IL

t150

t128

V^OH

V^OL

READ ADDRESS

5-4021 (F).a

*

W = number of wait-states.

Figure 44. External Memory Data Read Timing Diagram (2.7 V Operation)

Table 120. Timing Characteristics for External Memory Access (2.7 V Operation)

Abbreviated Reference

Parameter

Min

T(1 + W) – 1.5

—

Max

—

Unit

ns

t127

t128

Enable Width (low to high)

Address Valid (enable low to valid)

2.5

ns

Table 121. Timing Requirements for External Memory Read (EROM, ERAMHI, IO, ERAMLO) (2.7 V Operation)

Abbreviated

Reference

Parameter

19.2 ns

Max

12.5 ns

Max

Unit

Min

15

0

Min

13

0

t129

t130

t150

Read Data Setup (valid to enable high)

Read Data Hold (enable high to hold)

External Memory Access Time (valid to valid)

—

ns

—

T(1 + W) – 15

—

T(1 + W) – 14 ns

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Data Sheet

January 2002

DSP1629 Digital Signal Processor

11 Timing Characteristics for 2.7 V Operation (continued)

(MWAIT = 0x1002)

W* = 2

W* = 1

V^OH

CKO

V^OL

V^OH

ERAMLO

V^OL

V^OH

DB

WRITE DATA

READ

V^OL

t131

V^OH

V^OL

EROM

t132

t133

t136

t134

V^OH

V^OL

RWN

AB

t135

V^OH

V^OL

WRITE ADDRESS

READ ADDRESS

5-4022 (F).a

*

W = number of wait-states.

Figure 45. External Memory Data Write Timing Diagram (2.7 V Operation)

Table 122. Timing Characteristics for External Memory Data Write (All Enables) (2.7 V Operation)

Abbreviated

Reference

Parameter

19.2 ns

Min

12.5 ns

Min

Unit

Max

0

Max

0

t131

t132

t133

t134

t135

t136

Write Overlap (enable low to 3-state)

RWN Advance (RWN high to enable high)

RWN Delay (enable low to RWN low)

Write Data Setup (data valid to RWN high)

RWN Width (low to high)

—

ns

0

—

0

—

0

T(1 + W)/2 – 4

T(1 + W) – 5

0

T(1 + W)/2 – 3

T(1 + W) – 4

0

Write Address Setup (address valid to RWN low)

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Data Sheet

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DSP1629 Digital Signal Processor

11 Timing Characteristics for 2.7 V Operation (continued)

(MWAIT = 0x1002)

W* = 1

W* = 2

V^OH

CKO

V^OL

V^OH

ERAMLO

V^OL

V^OH

EROM

V^OL

t131

V^OH

DB

WRITE

READ

V^OL

t137

t138

V^OH

V^OL

RWN

t139

V^OH

V^OL

AB

WRITE ADDRESS

READ ADDRESS

5-4023 (F).a

*

W = number of wait-states.

Figure 46. Write Cycle Followed by Read Cycle (2.7 V Operation)

Table 123. Timing Characteristics for Write Cycle Followed by Read Cycle (2.7 V Operation)

Abbreviated Reference

Parameter

Min

—

0

Max

0

Unit

ns

t131

t137

t138

t139

Write Overlap (enable low to 3-state)

Write Data 3-state (RWN high to 3-state)

Write Data Hold (RWN high to data hold)

Write Address Hold (RWN high to address hold)

2

ns

—

ns

0

ns

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Data Sheet

January 2002

DSP1629 Digital Signal Processor

11 Timing Characteristics for 2.7 V Operation (continued)

11.8 PHIF Specifications (2.7 V Operation)

For the PHIF, read means read by the external user (output by the DSP); write is similarly defined. The 8-bit reads/

writes are identical to one-half of a 16-bit access.

16-bit READ

16-bit WRITE

VIH–

PCSN

PODS

V

IL–

VIH–

VIL–

t41

t42

t44

VIH–

PIDS

PBSEL

PSTAT

V

IL–

t43

t47

VIH–

VIL–

t45

t48

t52

t46

VIH–

VIL–

t50

t154

t51

t49

VIH–

PB[7:0]

VIL–

5-4036 (F)

Figure 47. PHIF Intel Mode Signaling (Read and Write) Timing Diagram (2.7 V Operation)

Table 124. Timing Requirements for PHIF Intel Mode Signaling (2.7 V Operation)

Abbreviated Reference

Parameter

Min

0

Max

—

Unit

ns

t41

t42

PODS to PCSN Setup (low to low)

PCSN to PODS Hold (high to high)

PIDS to PCSN Setup (low to low)

PCSN to PIDS Hold (high to high)

PSTAT to PCSN Setup (valid to low)

PCSN to PSTAT Hold (high to invalid)

PBSEL to PCSN Setup (valid to low)

PCSN to PBSEL Hold (high to invalid)

PB Write to PCSN Setup (valid to high)

PCSN to PB Write Hold (high to invalid)

0

t43

0

t44

0

t45*

t46*

t47*

t48*

t51*

t52*

4

0

6

0

10

4

*

This timing diagram for the PHIF port shows accesses using the PCSN signal to initiate and complete a transaction. The transactions can

also be initiated and completed with the PIDS and PODS signals. An output transaction (read) is initiated by PCSN or PODS going low, which-

ever comes last. For example, the timing requirements referenced to PCSN going low, t45 and t49, should be referenced to PODS going low,

if PODS goes low after PCSN. An output transaction is completed by PCSN or PODS going high, whichever comes first. An input transaction

is initiated by PCSN or PIDS going low, whichever comes last. An input transaction is completed by PCSN or PIDS going high, whichever

comes first. All requirements referenced to PCSN apply to PIDS or PODS, if PIDS or PODS is the controlling signal.

Table 125. Timing Characteristics for PHIF Intel Mode Signaling (2.7 V Operation)

Abbreviated Reference

Parameter

Min

—

0

Max

12

—

Unit

ns

t49*

t50*

t154

PCSN to PB Read (low to valid)

PCSN to PB Read Hold (high to invalid)

PCSN to PB Read 3-state (high to 3-state)

ns

—

8

ns

*

This timing diagram for the PHIF port shows accesses using the PCSN signal to initiate and complete a transaction. The transactions can

also be initiated and completed with the PIDS and PODS signals. An output transaction (read) is initiated by PCSN or PODS going low, which-

ever comes last. For example, the timing requirements referenced to PCSN going low, t45 and t49, should be referenced to PODS going low,

if PODS goes low after PCSN. An output transaction is completed by PCSN or PODS going high, whichever comes first. An input transaction

is initiated by PCSN or PIDS going low, whichever comes last. An input transaction is completed by PCSN or PIDS going high, whichever

comes first. All requirements referenced to PCSN apply to PIDS or PODS, if PIDS or PODS is the controlling signal.

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Data Sheet

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DSP1629 Digital Signal Processor

11 Timing Characteristics for 2.7 V Operation (continued)

16-bit READ

16-bit WRITE

8-bit READ

8-bit WRITE

t55

V

IH

PCSN

V

IL

t56

t55

t56

V

IH

PODS

PIDS

V

IL

t56

t55

VIH

V

IL

t56

V

OH

PBSEL

POBE

PIBF

V

OL

t53

VOH

V

OL

t54

VOH

V

OL

5-4037 (F).a

Figure 48. PHIF Intel Mode Signaling (Pulse Period and Flags) Timing Diagram (2.7 V Operation)

Table 126. Timing Requirements for PHIF Intel Mode Signaling (2.7 V Operation)

Abbreviated Reference

Parameter

Min

20.5

Max

—

Unit

ns

t55

t56

PCSN/PODS/PIDS Pulse Width (high to low)

PCSN/PODS/PIDS Pulse Width (low to high)

—

ns

Table 127. Timing Characteristics for PHIF Intel Mode Signaling (2.7 V Operation)

Abbreviated Reference

Parameter

PCSN/PODS to POBE^†(high to high)

PCSN/PIDS to PIBF^†(high to high)

Min

—

Max

17

Unit

ns

t53*

t54*

—

17

ns

*

t53 should be referenced to the rising edge of PCSN or PODS, whichever comes first. t54 should be referenced to the rising edge of

PCSN or PIDS, whichever comes first.

†

POBE and PIBF may be programmed to be the opposite logic levels shown in the diagram (positive assertion levels shown). t53 and

t54 apply to the inverted levels as well as those shown.

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Data Sheet

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DSP1629 Digital Signal Processor

11 Timing Characteristics for 2.7 V Operation (continued)

16-bit READ

16-bit WRITE

V

IH

PCSN

PDS

V

IL

t42

V

IH

V

IL

t41

t43

t44

V

IH

PRWN

PBSEL

V

IL

t44

V

IH

V

IL

t47

t48

t52

t45

t46

V

IH

PSTAT

PB[7:0]

IL

t49

t50

t154

t51

5-4038 (F).a

Figure 49. PHIF Motorola Mode Signaling (Read and Write) Timing Diagram (2.7 V Operation)

Table 128. Timing Requirements for PHIF Motorola Mode Signaling (2.7 V Operation)

Abbreviated Reference

Parameter

Min

Max

Unit

PDS^†to PCSN Setup (valid to low)

PCSN to PDS^†Hold (high to invalid)

PRWN to PCSN Setup (valid to low)

PCSN to PRWN Hold (high to invalid)

0

—

ns

t41

t42

0

4

—

ns

t43

0

t44

PSTAT to PCSN Setup (valid to low)

PCSN to PSTAT Hold (high to invalid)

PBSEL to PCSN Setup (valid to low)

PCSN to PBSEL Hold (high to invalid)

PB Write to PCSN Setup (valid to high)

PCSN to PB Write Hold (high to invalid)

4

t45*

t46*

t47*

t48*

t51*

t52*

0

6

0

10

4

*

This timing diagram for the PHIF port shows accesses using the PCSN signal to initiate and complete a transaction. The transactions can

also be initiated and completed with the PDS signal. An input/output transaction is initiated by PCSN or PDS going low, whichever comes last.

For example, the timing requirements referenced to PCSN going low, t45 and t49, should be referenced to PDS going low, if PDS goes low

after PCSN. An input/output transaction is completed by PCSN or PDS going high, whichever comes first. All requirements referenced to

PCSN should be referenced to PDS, if PDS is the controlling signal. PRWN should never be used to initiate or complete a transaction.

PDS is programmable to be active-high or active-low. It is shown active-low in Figures 49 and 50. POBE and PIBF may be programmed to

be the opposite logic levels shown in the diagram. t53 and t54 apply to the inverted levels as well as those shown.

†

Table 129. Timing Characteristics for PHIF Motorola Mode Signaling (2.7 V Operation)

Abbreviated Reference

Parameter

PCSN to PB Read (low to valid)

PCSN to PB Read Hold (high to invalid)

PCSN to PB Read 3-state (high to 3-state)

Min

—

0

Max

12

—

Unit

ns

t49*

t50*

t154

—

8

ns

*

This timing diagram for the PHIF port shows accesses using the PCSN signal to initiate and complete a transaction. The transactions can

also be initiated and completed with the PDS signal. An input/output transaction is initiated by PCSN or PDS going low, whichever comes last.

For example, the timing requirements referenced to PCSN going low, t45 and t49, should be referenced to PDS going low, if PDS goes low

after PCSN. An input/output transaction is completed by PCSN or PDS going high, whichever comes first. All requirements referenced to

PCSN should be referenced to PDS, if PDS is the controlling signal. PRWN should never be used to initiate or complete a transaction.

112

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Data Sheet

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DSP1629 Digital Signal Processor

11 Timing Characteristics for 2.7 V Operation (continued)

16-bit READ

16-bit WRITE

8-bit READ

8-bit WRITE

t55

V

IH

–

PCSN

V

IL

t56

t55

t56

V

IH

–

PDS

V

IL

t56

t55

V

IH

–

PRWN

V

IL

t56

V

OH

–

PBSEL

POBE

PIBF

V

OL–

t53

V

OH

–

V

OL

t54

V

OH

–

V

OL

5-4039 (F).a

Figure 50. PHIF Motorola Mode Signaling (Pulse Period and Flags) Timing Diagram (2.7 V Operation)

Table 130. Timing Characteristics for PHIF Motorola Mode Signaling (2.7 V Operation)

Abbreviated Reference

Parameter

PCSN/PDS^†to POBE^†(high to high)

PCSN/PDS^†to PIBF^†(high to high)

Min

—

Max

17

Unit

ns

t53*

t54*

—

17

ns

*

An input/output transaction is initiated by PCSN or PDS going low, whichever comes last. For example, t53 and t54 should be referenced

to PDS going low, if PDS goes low after PCSN. An input/output transaction is completed by PCSN or PDS going high, whichever comes first.

All requirements referenced to PCSN should be referenced to PDS, if PDS is the controlling signal. PRWN should never be used to initiate or

complete a transaction.

†

PDS is programmable to be active-high or active-low. It is shown active-low in Figures 49 and 50. POBE and PIBF may be programmed to

be the opposite logic levels shown in the diagram. t53 and t54 apply to the inverted levels as well as those shown.

Table 131. Timing Requirements for PHIF Motorola Mode Signaling (2.7 V Operation)

Abbreviated Reference

Parameter

Min

20

Max

—

Unit

ns

t55

t56

PCSN/PDS/PRWN Pulse Width (high to low)

PCSN/PDS/PRWN Pulse Width (low to high)

20

—

ns

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Data Sheet

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DSP1629 Digital Signal Processor

11 Timing Characteristics for 2.7 V Operation (continued)

V

IH

IL

—

PCSN

V

IH

IL

—

PODS (PDS*)

V

IH

IL

—

PIDS (PRWN*)

PBSEL

V

t47

t45

t48

t46

V

IH

IL

—

V

IH

IL

—

PSTAT

PB[7:0]

V

t50

t154

t49

V

OH

OL

—

V

5-4040 (F).a

*

Motorola mode signal name.

Figure 51. PHIF Intel or Motorola Mode Signaling (Status Register Read) Timing Diagram (2.7 V Operation)

Table 132. Timing Requirements for Intel and Motorola Mode Signaling (Status Register Read) (2.7 V Oper-

ation)

Abbreviated Reference

Parameter

Min

4

Max

—

Unit

ns

t45^†

t46^‡

t47^†

t48^‡

PSTAT to PCSN Setup (valid to low)

PCSN to PSTAT Hold (high to invalid)

PBSEL to PCSN Setup (valid to low)

PCSN to PBSEL Hold (high to invalid)

0

—

ns

6

—

ns

0

—

ns

†

‡

t45, t47, and t49 are referenced to the falling edge of PCSN or PODS(PDS), whichever occurs last.

t46, t48, and t50 are referenced to the rising edge of PCSN or PODS(PDS), whichever occurs first.

Table 133. Timing Characteristics for Intel and Motorola Mode Signaling (Status Register Read) (2.7 V Op-

eration)

Abbreviated Reference

Parameter

Min

—

0

Max

12

—

Unit

ns

t49^†

t50^‡

PCSN to PB Read (low to valid)

PCSN to PB Read Hold (high to invalid)

PCSN to PB Read 3-state (high to 3-state)

ns

t154

—

8

ns

†

‡

t45, t47, and t49 are referenced to the falling edge of PCSN or PODS(PDS), whichever occurs last.

t46, t48, and t50 are referenced to the rising edge of PCSN or PODS(PDS), whichever occurs first.

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Data Sheet

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DSP1629 Digital Signal Processor

11 Timing Characteristics for 2.7 V Operation (continued)

V^IH–

RSTB

V^IL–

t57

V^OH–

POBE

V^OL–

t58

V^OH–

PIBF

V^OL–

5-4775 (F)

Figure 52. PHIF, PIBF, and POBE Reset Timing Diagram (2.7 V Operation)

Table 134. PHIF Timing Characteristics for PHIF, PIBF, and POBE Reset (2.7 V Operation)

Abbreviated Reference

Parameter

Min

—

3

Max

25

Unit

t57

t58

RSTB Disable to POBE/PIBF* (high to valid)

RSTB Enable to POBE/PIBF* (low to invalid)

ns

25

*

After reset, POBE and PIBF always go to the levels shown, indicating output buffer empty and input buffer empty. The DSP program, however,

may later invert the definition of the logic levels for POBE and PIBF. t57 and t58 continue to apply.

V^IH–

CKO

V^IL–

t59

V^OH–

V^OL–

†

POBE

t59

V^OH–

V^OL–

†

PIBF

5-4776 (F)

POBE and PIBF can be programmed to be active-high or active-low. They are shown active-high. The timing characteristic for active-low is

the same as for active-high^.

†

Figure 53. PHIF, PIBF, and POBE Disable Timing Diagram (2.7 V Operation)

Table 135. PHIF Timing Characteristics for POBE and PIBF Disable (2.7 V Operation)

Abbreviated Reference

Parameter

Min

Max

Unit

t59

CKO to POBE/PIBF Disable (high/low to disable)

—

20

ns

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115

Data Sheet

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DSP1629 Digital Signal Processor

11 Timing Characteristics for 2.7 V Operation (continued)

11.9 Serial I/O Specifications (2.7 V Operation)

t70

t72

t75

t71

t74

V^IH–

V^IL–

ICK

t73

t75

V^IH–

V^IL–

ILD

DI

t77

t78

V^IH–

V^IL–

B0

B1

BN – 1*

t79

B0

V^OH–

V^OL–

IBF

5-4777 (F)

*

N = 16 bits or 8 bits.

Figure 54. SIO Passive Mode Input Timing Diagram (2.7 V Operation)

Table 136. Timing Requirements for Serial Inputs (2.7 V Operation)

Abbreviated Reference

Parameter

Clock Period (high to high)^†

Clock Low Time (low to high)

Clock High Time (high to low)

Load High Setup (high to high)

Load Low Setup (low to high)

Load High Hold (high to invalid)

Data Setup (valid to high)

Min

40

18

8

Max

Unit

ns

‡

t70

t71

t72

t73

t74

t75

t77

t78

—

8

0

7

Data Hold (high to invalid)

0

†

‡

For multiprocessor mode, see note in Section 11.10, Multiprocessor Communication (2.7 V Operation).

Device is fully static; t70 is tested at 200 ns.

Table 137. Timing Characteristics for Serial Outputs (2.7 V Operation)

Abbreviated Reference

Parameter

Min

Max

35

Unit

t79

IBF Delay (high to high)

—

ns

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Data Sheet

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DSP1629 Digital Signal Processor

11 Timing Characteristics for 2.7 V Operation (continued)

V^OH–

ICK

V^OL–

t101

t76a

V^OH–

ILD

V^OL–

*

t77

t78

V^IH–

V^IL–

DI

B0

B1

BN – 1

t79

B0

V^OH–

V^OL–

IBF

5-4778 (F)

*

ILD goes high during bit 6 (of 0:15), N = 8 or 16.

Figure 55. SIO Active Mode Input Timing Diagram (2.7 V Operation)

Table 138. Timing Requirements for Serial Inputs (2.7 V Operation)

Abbreviated Reference

Parameter

Data Setup (valid to high)

Data Hold (high to invalid)

Min

7

Max

—

Unit

t77

t78

ns

0

—

Table 139. Timing Characteristics for Serial Outputs (2.7 V Operation)

Abbreviated Reference

Parameter

ILD Delay (high to low)

Min

—

3

Max

Unit

ns

t76a

t101

t79

35

—

35

ILD Hold (high to invalid)

IBF Delay (high to high)

ns

—

ns

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Data Sheet

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DSP1629 Digital Signal Processor

11 Timing Characteristics for 2.7 V Operation (continued)

t80

t82

t85

t81

t84

V^IH–

V^IL–

OCK

t83

t85

V^IH–

V^IL–

OLD

DO*

t88

t94

t87

B0

t90

B1

t90

t93

V^OH–

V^OL–

B7

BN – 1

AS7

t89

t95

t92

AD0

t93

V^OH–

V^OL–

SADD

DOEN

OBE

AD7

AD1

V^IH–

V^IL–

t96

V^OH–

V^OL–

5-4796 (F)

*

See sioc register, MSB field, to determine if B0 is the MSB or LSB. See sioc register, ILEN field, to determine if the DO word length is 8 bits

or 16 bits.

Figure 56. SIO Passive Mode Output Timing Diagram (2.7 V Operation)

Table 140. Timing Requirements for Serial Inputs (2.7 V Operation)

Abbreviated Reference

Parameter

Clock Period (high to high)^†

Min

40

18

8

Max

Unit

ns

‡

t80

t81

t82

t83

t84

t85

—

Clock Low Time (low to high)

Clock High Time (high to low)

Load High Setup (high to high)

Load Low Setup (low to high)

Load Hold (high to invalid)

—

ns

8

ns

0

ns

†

‡

For multiprocessor mode, see note in Section 11.10, Multiprocessor Communication (2.7 V Operation).

Device is fully static; t80 is tested at 200 ns.

Table 141. Timing Characteristics for Serial Outputs (2.7 V Operation)

Abbreviated Reference

Parameter

Data Delay (high to valid)

Min

—

3

Max

35

—

Unit

ns

t87

t88

t89

t90

t92

t93

t94

t95

t96

Enable Data Delay (low to active)

Disable Data Delay (high to 3-state)

Data Hold (high to invalid)

Address Delay (high to valid)

Address Hold (high to invalid)

Enable Delay (low to active)

Disable Delay (high to 3-state)

OBE Delay (high to high)

—

3

35

—

35

118

Agere Systems Inc.

Data Sheet

January 2002

DSP1629 Digital Signal Processor

11 Timing Characteristics for 2.7 V Operation (continued)

V^OH–

OCK

V^OL–

t102

t86a

V^OH–

OLD

*

V^OL–

t88

t94

t87

B0

t90

B1

t90

t93

V^OH–

V^OL–

DO

B7

BN – 1

AS7

t89

t95

t92

AD0

t93

V^OH–

V^OL–

SADD

DOEN

OBE

AD7

AD1

V^IH–

V^IL–

t96

V^OH–

V^OL–

5-4797 (F)

*

OLD goes high at the end of bit 6 of 0:15.

Figure 57. SIO Active Mode Output Timing Diagram (2.7 V Operation)

Table 142. Timing Characteristics for Serial Output (2.7 V Operation)

Abbreviated Reference

Parameter

Min

—

3

Max

35

—

Unit

t86a

t102

t87

t88

t89

t90

t92

t93

t94

t95

t96

OLD Delay (high to low)

ns

OLD Hold (high to invalid)

Data Delay (high to valid)

—

3

35

—

Enable Data Delay (low to active)

Disable Data Delay (high to 3-state)

Data Hold (high to invalid)

Address Delay (high to valid)

Address Hold (high to invalid)

Enable Delay (low to active)

Disable Delay (high to 3-state)

OBE Delay (high to high)

—

3

35

—

35

Agere Systems Inc.

119

Data Sheet

January 2002

DSP1629 Digital Signal Processor

11 Timing Characteristics for 2.7 V Operation (continued)

V^OH–

CKO

V^OL–

t97

t99

t98

V^OH–

V^OL–

ICK

t100

V^OH–

V^OL–

OCK

V^OH–

ICK/OCK*

t76a

t101

t76b

t101

V^OH–

V^OL–

ILD

t86a

t102

t86b

t102

V^OH–

V^OL–

OLD

t104

t105

t103

t105

V^OH–

V^OL–

SYNC

5-4798 (F)

*

See sioc register, LD field.

Figure 58. Serial I/O Active Mode Clock Timing (2.7 V Operation)

Table 143. Timing Characteristics for Signal Generation (2.7 V Operation)

Abbreviated Reference

Parameter

ICK Delay (high to high)

ICK Delay (high to low)

OCK Delay (high to high)

OCK Delay (high to low)

ILD Delay (high to low)

ILD Delay (high to high)

ILD Hold (high to invalid)

OLD Delay (high to low)

OLD Delay (high to high)

OLD Hold (high to invalid)

SYNC Delay (high to low)

SYNC Delay (high to high)

SYNC Hold (high to invalid)

Min

—

3

Max

18

35

—

Unit

ns

t97

t98

t99

t100

t76a

t76b

t101

t86a

t86b

t102

t103

t104

t105

—

3

35

—

3

35

—

120

Agere Systems Inc.

Data Sheet

January 2002

DSP1629 Digital Signal Processor

11 Timing Characteristics for 2.7 V Operation (continued)

11.10 Multiprocessor Communication (2.7 V Operation)

TIME SLOT 1

TIME SLOT 2

OCK/ICK

t113

t112

t113

V^IH–

V^IL–

SYNC

*

t116

B1

t117

V^OH–

V^OL–

B15

B0

B7

B8

B15

AS7

B0

DO/D1

SADD

t114

t122

t120

t121

AD0 AD1

t115

AD7 AS0

AD0

t120

V^OH–

V^OL–

DOEN

5-4799 (F)

*

Negative edge initiates time slot 0.

Figure 59. SIO Multiprocessor Timing Diagram (2.7 V Operation)

Note: All serial I/O timing requirements and characteristics still apply, but the minimum clock period in passive

multiprocessor mode, assuming 50% duty cycle, is calculated as (t77 + t116) x 2.

Table 144. Timing Requirements for SIO Multiprocessor Communication (2.7 V Operation)

Abbreviated Reference

Parameter

Sync Setup (high/low to high)

Sync Hold (high to high/low)

Address Setup (valid to high)

Address Hold (high to invalid)

Min

35

0

Max

—

Unit

ns

t112

t113

t114

t115

—

ns

12

0

—

ns

—

ns

Table 145. Timing Characteristics for SIO Multiprocessor Communication (2.7 V Operation)

Abbreviated Reference^†

Parameter

Min

—

Max

35

Unit

ns

t116

t117

t120

t121

t122

Data Delay (bit 0 only) (low to valid)

Data Disable Delay (high to 3-state)

DOEN Valid Delay (high to valid)

Address Delay (bit 0 only) (low to valid)

Address Disable Delay (high to 3-state)

—

30

ns

—

25

ns

—

35

ns

—

30

ns

†

With capacitance load on ICK, OCK, DO, SYNC, and SADD = 100 pF, add 4 ns to t116—t122.

Agere Systems Inc.

121

Data Sheet

January 2002

DSP1629 Digital Signal Processor

12 Outline Diagrams

12.1 100-Pin BQFP (Bumpered Quad Flat Pack)

All dimensions are in millimeters.

22.860 ± 0.305

22.350 ± 0.255

19.050 ± 0.405

13

1

89

14

88

PIN #1

IDENTIFIER

ZONE

EDGE CHAMFER

22.350

± 0.255

19.050

± 0.405

22.860

± 0.305

38

64

39

63

DETAIL A

DETAIL B

4.570 MAX

3.555

± 0.255

SEATING PLANE

0.10

0.760 ± 0.255

0.635 TYP

0.255

0.175 ± 0.025

GAGE PLANE

SEATING PLANE

0.280 ± 0.075

0.91/1.17

M

0.150

DETAIL B

DETAIL A

5-1970 (F)r.10

122

Agere Systems Inc.

Data Sheet

January 2002

DSP1629 Digital Signal Processor

12 Outline Diagrams (continued)

12.2 100-Pin TQFP (Thin Quad Flat Pack)

All dimensions are in millimeters.

16.00 ± 0.20

14.00 ± 0.20

PIN #1 IDENTIFIER ZONE

100

76

1

75

14.00

± 0.20

16.00

± 0.20

25

51

26

50

DETAIL A

DETAIL B

1.40 ± 0.05

1.60 MAX

SEATING PLANE

0.08

0.05/0.15

0.50 TYP

1.00 REF

0.106/0.200

0.25

GAGE PLANE

SEATING PLANE

0.19/0.27

0.45/0.75

M

0.08

DETAIL B

DETAIL A

5-2146 (F)r.14

Agere Systems Inc.

123

Data Sheet

January 2002

DSP1629 Digital Signal Processor

12 Outline Diagrams (continued)

12.3 144-Pin PBGA (Plastic Ball Grid Array)

All dimensions are in millimeters.

13.00 ± 0.20

+ 0.70

– 0.00

11.50

PIN A1

CORNER

+ 0.70

– 0.00

11.50

13.00

± 0.20

MOLD

COMPOUND

PWB

0.80 ± 0.05

0.36 ± 0.04

1.56 + 0.19

– 0.21

SEATING PLANE

0.20

SOLDER BALL

0.40 ± 0.10

11 SPACES @ 1.00 = 11.00

M

L

K

J

0.50 ± 0.10

H

G

F

11 SPACES @

1.00 = 11.00

E

D

C

B

A

1

2

3

4

5

6

7

8

9

10 11 12

PIN A1

CORNER

5-5205 (F)

124

Agere Systems Inc.

Data Sheet

January 2002

DSP1629 Digital Signal Processor

Notes

Agere Systems Inc.

125

Motorola is a registered trademark of Motorola, Inc.

Intel is a registered trademark of Intel Corp.

IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc.

For additional information, contact your Agere Systems Account Manager or the following:

INTERNET:

E-MAIL:

http://www.agere.com

docmaster@agere.com

N. AMERICA: Agere Systems Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18109-3286

1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106)

ASIA:

Agere Systems Hong Kong Ltd., Suites 3201 & 3210-12, 32/F, Tower 2, The Gateway, Harbour City, Kowloon

Tel. (852) 3129-2000, FAX (852) 3129-2020

CHINA: (86) 21-5047-1212 (Shanghai), (86) 10-6522-5566 (Beijing), (86) 755-695-7224 (Shenzhen)

JAPAN: (81) 3-5421-1600 (Tokyo), KOREA: (82) 2-767-1850 (Seoul), SINGAPORE: (65) 778-8833, TAIWAN: (886) 2-2725-5858 (Taipei)

Tel. (44) 7000 624624, FAX (44) 1344 488 045

EUROPE:

Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application.

January 2002

DS02-060AUTO


型号：	DSP1629T10K19.2IR
厂家：	ETC
描述：	DSP\|16-BIT\|CMOS\|QFP\|100PIN\|PLASTIC
文件：	总126页 (文件大小：1786K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DSP1629T10K19.2IR [ETC]

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