DV2054S2_14 [ETC]
Li-Ion Charger Development System Control of On-Board PNP Switch-Mode Regulator;
| 型号： | DV2054S2_14 |
| 厂家： | 
ETC |
| 描述： | Li-Ion Charger Development System Control of On-Board PNP Switch-Mode Regulator |
| 文件： | 总5页 (文件大小：892K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DV2054S2
Li-Ion Charger Development System
Control of On-Board PNP Switch-Mode Regulator
Features
➤ bq2054 fast-charge control evaluation and
development, based on switching buck converter with
low-side battery-current sensing
➤ On-board configuration for fast charge of 1, 2, 3, or 4
Li-Ion cells
➤ Charge termination by selectable minimum current,
or maximum time-out
➤ Constant current (up to 1.25A) and constant voltage
(up to 16.8V) provided by on-board switch-mode
regulator
➤ J umper-configurable LED display
➤ Direct connections for battery and thermistor
➤ Maximum charge time of 5 hours
General Description
The DV2054S2 Development System provides a develop-
ment environment for the bq2054 Lithium Ion Fast-
Charge IC. The DV2054S2 incorporates a bq2054 and a
buck-type switch-mode regulator to provide fast charge
control for 1 through 4 Li-Ion cells.
Fast charge is preceded by a pre-charge qualification pe-
riod.
Connection Descriptions
Fast charge termination occurs on:
Minimum current – IMAX divided by 10, 20, or 30
Maximum time-out
J 1
DC+
DC-
Charger supply positive (24VDC max.)
Charger supply ground
The bq2054 can be reset and a new charge cycle started
by applicaton of power to the board or battery replace-
ment.
J 2
BAT+
TEM+
BAT-
Positive battery terminal
The user provides a DC power supply and batteries
and configures the board for the number of cells, the
m in im u m cu r r en t t h r esh old, a n d t h e LE D displa y
mode. The board has direct connections for the battery
and the provided thermistor.
Postive thermistor connections
Negative battery terminal and
thermistor connecton.
J P1
J P2
J P3
Display mode selection
Number of cells selection
Before using the DV2054S2 board, please review the
bq2054 data sheet.
Full and minimum current termination
select
SLUU024–APRIL 1999
Rev. B Board
1
DV2054S2
J P 2: Configures the board for the number of cells.
Fixed Configuration
JP2
Number of Cells
The DV2054S2 board has the following characteristics:
1
2
3
4
[1 2 ] 3 4 5 6 7 8
1 2 [3 4] 5 6 7 8
1 2 3 4 [5 6] 7 8
1 2 3 4 5 6 [7 8]
VCC for the fast-charge IC is regulated onboard
from the supply at connector J 1.
J 1 can accept a maximum of 25VDC.
LED indicates charge status.
Charge begins on the later application of
J P 3: Sets the minimum current termination.
–
–
The battery
JP3
[1 2] 3
1 [2 3]
1 2 3
IMIN
Supply voltage
IMAX
10
The on-board regulator supplies a fast charge current
IMAX of 1.25A. The fast-charge voltage VMAX is set at
25°C.
IMAX
20
IMAX
30
The switching frequency of the PWM control loops is
120kHz.
Setup Procedure
The regulated current is controlled by the value of the
sense resistor RSNS according to the relationship
1. Connect the thermistor to TEM+ and BAT-.
2. Attach the battery pack to BAT+ and BAT-.
3. Connect the charging supply to J 1.
0.250V
ICHG
=
RSNS
The value of RSNS (R17 in the schematic) at shipment is
0.200Ω. This resistor can be changed depending on the
application. The maximum charging current IMAX for
the DV2054S2 board is 1.25A.
The following table shows the minimum input require-
ment for a given number of cells.
Minimum Charger
Number of Cells
Supply Input
The thermistor provided is a Philips 2322–640–63103.
With this thermistor connected between TEM+ and
BAT-, the temperature fault limits are VLTF (low-tem-
perature fault) = 0°C, VHTF (high-temperature fault) =
45°C, and VTCO (charge cutoff) = 47°C.
1
2
3
4
8.5VDC
13VDC
19VDC
25VDC
Jumper-Selectable Configuration
The combined charging and system load should not ex-
ceed the IMAX limit of 1.25A.
The DV2054S2 can be configured as follows (see J umber
Configuration Diagram for location of the jumbers):
J P 1: Configures the display mode (DSEL).
JP1
Display Mode
Mode 1
[1 2 ] 3
1 [2 3]
1 2 3
Mode 2
Mode 3
2
DV2054S2
Jumper Configuration Diagram
J2
7
8
5
6
3
4
1
2
J1
BAT+
DC+
DC-
TEM+
BAT-
JP2
BAT-
3
2
1
JP3
JP1
3
2 1
BD2954JCDL.eps
DV2054S2 Board Schematic
3
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Copyright © 1999, Texas Instruments Incorporated
4
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