E1467D-B [ETC]
CLOCK CIRCUIT|CMOS|DIE ; 时钟电路| CMOS | DIE\n
| 型号： | E1467D-B |
| 厂家： | 
ETC |
| 描述： | CLOCK CIRCUIT|CMOS|DIE
|
| 文件： | 总6页 (文件大小：42K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
e1467D
32-kHz Clock CMOS IC with Digital Trimming and Alarm
FD e3a2t-ukHrzesvoltage regulated oscillator
D Output pulse formers
D 1.1 V to 2.2 V operating-voltage range
D Integrated capacitors for digital trimming
D Suitable for up to 12.5 pF quartz
D Mask options for motor period and pulse width
D Low resistance output for bipolar stepping motor
D Alarm function
D Trimming inputs insensitive to stray capacitance
D Motor-fast-test function
Pad Configuration
General Description
SC4 SC3 SC2 SC1
The e1467D is an integrated circuit in CMOS Silicon
Gate Technology for analog clocks. It consists of a
32-kHz oscillator, frequency divider, output pulse
formers, push-pull motor drivers and alarm output.
Integrated capacitors are mask-selectable to accomodate
the external quartz crystal. Additional capacitance can be
selected through pad bonding for trimming the oscillator
frequency.
*
V
1
2
13 12 11 10
9
8
OSCIN
DD
*
OSCOUT
V
SS
e 1467D
ALOUT
MOT2
7
**ALIN /
MTEST
3
4
6
5
**MOT1L
MOT1R
9611897
*) The pads for V and OSCOUT are interchangeable
DD
per mask option
**) The pads for ALIN/-MTEST and MOT1L are inter-
changeable per mask-option
Figure 4. Pad configuration
Absolute Maximum Ratings
Parameters
Symbol
Value
–0.3 to 5 V
Unit
V
V
Supply voltage
V
SS
V
IN
Input voltage range, all inputs
Output short circuit duration
Power dissipation (DIL package)
Operating ambient temperature range
Storage temperature range
(V – 0.3 V) x V x (V + 0.3 V)
SS
IN
DD
indefinite
P
tot
125 mW
–20 to +70
–40 to + 125
260
mW
°C
°C
T
amb
T
stg
Lead temperature during soldering at 2 mm
distance, 10 seconds
T
sld
°C
Absolute maximum ratings define parameter limits electrostatic discharges. However, precautions to
which, if exceeded, may permanently change or damage minimize the build-up of electrostatic charges during
the device.
handling are recommended.
All inputs and outputs in Atmel Wireless
&
This circuit is protected against supply voltage reversal
Microcontrollers’ circuits are protected against for typically 5 minutes.
Rev. A2, 15-Jan-01
1 (6)
e1467D
Functional Description
The output is configured for npn and pnp bipolar
capability. The output is an alarm tone modulated by a
low frequency. Tone frequencies, modulation
frequencies, and on/off times are selectable via the metal
mask option.
Oscillator
An oscillator inverter with feedback resistor is provided
for generation of the 32768 Hz clock frequency. Values
for the fixed capacitors at OSCIN and OSCOUT are
mask-selectable (see note 3 of operating characteristics).
Four control inputs SC1 to SC4 enable the addition of
integrated trimming capacitors to OSCIN and OSCOUT,
providing 15 tuning steps.
Alarm Input
A debounced alarm input is provided. Alarm activation is
either to V or V by a mask option.
DD
SS
Trimming Capacitors
A frequency variation of typ. 4 ppm for each tuning step
is obtained by bonding the capacitor switch pads to V
.
Test Functions
DD
As none of these pads are bonded, the IC is in an
untrimmed state. Figure 5 shows the trimming curve
characteristic.
For test purposes the ALIN/MTEST pad is open. With a
high resistance probe (R w 10 MW, C v 20 pF), a test
frequency f
of 128 Hz can be measured at the ALIN/
TEST
Note:
MTEST pad. Connecting ALIN/MTEST (for at least
32 ms) to the opposite polarity for alarm activation
For applications which utilize this integrated trimming
feature, Atmel Wireless & Microcontrollers will deter-
mine optimum values for the integrated capacitors
changes the motor period from the selected value to T
MT
(mask-selectable) while the pulse width remains
unaffected. This feature can be used for testing the
mechanical parts of the clock.
C
and C
OSCIN
OSCOUT.
Motor Drive Output
V
DD
The e1467D contains two push-pull output buffers for
driving bipolar stepping motors. During a motor pulse,
the n-channel device of one buffer and the p-channel
device of the other buffer will be activated. Both
n-channel transistor are on and conducting, between
output pulses. The outputs are protected against inductive
voltage spikes with diodes to both supply pins. The motor
output period and pulse width are mask programmable, as
listed below:
R3
V
OSCIN
DD
13
11 10
12
9
8
1
2
V
SS
OSCOUT
ALOUT
e1467D
7
ALIN/
–MT
MOT2
R1
3
4
6
5
Available motor periods (T ):
M
R2
MOT1R
125, 250, 500 ms and 2, 16 s
Available max. pulse widths (t ):
MOT1L
V
SS
M
9611896
15, 6, 23.4, 31.25, 46.9 ms
Available motor periods for motor test (T ):
MT
Figure 5. Functional test
250, 500 ms and 1 s
Note: The following constraints for combination of
motor period and pulse widths have to be
considered: T
alternatively T = 2 * t , T = 2 * t
4 * t , T
4 * t or
Test Crystal Specification
M
M
MT
M
u
u
M
M
MT
M
Oscillation frequency
Series resistance
f
= 32768 Hz
OSC
R = 30 kW
S
Static capacitance
Dynamic capacitance
C = 1.5 pF
C = 3.0 fF
1
O
Alarm Outputs
The alarm output driver consists of push-pull stage for Load capacitance
driving a speaker via an external bipolar transistor.
C optionally 10 or 12.5 pF
L
2 (6)
Rev. A2, 15-Jan-01
e1467D
Operating Characteristics
V
SS
= 0, V = 1.5 V, T
= +25°C, unless otherwise specified
DD
amb
All voltage levels are measured with reference to V . Test crystal as specified below.
SS
Parameters
Operating voltage
Test Conditions / Pins
Symbol
Min.
1.1
Typ.
1.5
Max.
2.2
Unit
V
V
DD
Operating temperature
Operating current
Motor drive output
Motor output current
Motor period
T
I
–20
+70
3
°C
mA
amb
DD
R = ∞, note 2
1
1
V
DD
= 1.2 V, R = 200 W
I
M
T
T
"4.3
mA
s
ms
1
See option list
See option list
M
Motor period during motor
test
MT
Motor pulse width
t
See option list
ms
M
Oscillator
Startup voltage
Frequency stability
Within 2 s
DV = 100 mV
V
Df/f
1.2
2.2
0.2
V
ppm
START
0.1
DD
V
DD
= 1.1 to 2.2 V
Integrated input capacitance
Integrated output capacitance
Input current SC1 to SC4
Note 3
C
See option list
See option list
pF
pF
mA
mA
OSCIN
C
OSCOUT
V
IN
V
IN
= 0.2 V
= V , note 5
I
I
1
0.05
5
0.15
25
0.5
SCINL
SCINH
DD
Alarm/output
Output current for
driving npn-transistor
n-channel
V
= 1.2 V
DD
R = 100 kW
I
I
1
–0.5
3
–1
10
mA
mA
3
ANn
ANp
p-channel
R = 1 kW, note 2, note 4
2
Output current for
driving pnp-transistor
n-channel
V
= 1.2 V
DD
R = 1 kW
I
I
0.5
–1
1
–2
mA
mA
3
APn
APp
p-channel
R = 100 kW, note 2, note 4
2
–10
Alarm options
Tone frequency
Modulation frequency
On/Off time
f
See option list
See option list
See option list
Hz
Hz
s
A
f
MOD
t
/t
ON OFF
Alarm input/motor test
Input current
Input current
ALIN = V , peak current
I
I
0.6
–0.6
23.4
3
–3
10
–10
31.2
mA
mA
ms
DD
AINH
ALIN = V , peak current
SS
AINL
Input debounce delay
t
AIN
Note 1: Typical parameters represent the statistical mean values
Note 2: See test circuit
Note 3: Values can be selected in 1 pF steps. A total capacitance (C
Note 4: npn or pnp driving transistors defined by mask options
+ C
) of 38 pF is available
OSCOUT
OSCIN
Note 5: I
is the peak current of a pulsed current with duty cycle 1:63. Average current is always smaller than
SCINH
10 nA
Rev. A2, 15-Jan-01
3 (6)
e1467D
a
V
V
DD
ALIN/
MT
SS
V
V
DD
MOT1
SS
t
M
T
MT
T
M
V
V
DD
MOT2
SS
Motor output signal during normal mode and motortest
Detail a:
1/f
TEST
9611898
Figure 6. Motor output signal during normal operation and during motor test
T < t
T > t
T < t
T > t
V4
AIN
AIN
V4
V
DD
ALIN /
MTEST
V
SS
b
V
DD
ALOUT
V
SS
t
t
OFF
ON
Signal on alarm input and alarm output during alarm activation
Detail b:
V
DD
V
SS
1/f
A
1/f
MOD
Alarm output signal
9611899
Figure 7. Alarm operation
4 (6)
Rev. A2, 15-Jan-01
e1467D
2.00006
2.00005
2.00004
2.00003
2.00002
2.00001
2.00000
1.99999
1.99998
1.99997
1.99996
1.99995
1.99994
1.99993
1.99992
1.99991
C
=
OX
1.05
1.00
0.95
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
9611900
Trimming steps
Figure 8. Typical trimming curve characteristic for TM of 2 s
C
means frequency deviation due to production process variations.
OX
Trimming inputs SC1 ... SC4 are binary weighted, i.e., SC1 ... SC4 = 0 corresponds to trimming step 0
SC1 ... SC4 = 1 corresponds to trimming step 15
LSB = SC1
Rev. A2, 15-Jan-01
5 (6)
e1467D
Ordering Information
Table 4. Option list e1267D–
Option
Motor
Alarm
Load
Cap.
Integrated Capacitance
Cycle
(T
s
Pulse
Test
(T
MT
ms
Frequency Modulation
Frequency
On/ Off
Time
s
Driver
Type
Activation
Polarity
C
C
OSCIN
*)
OSCOUT
*)
)
(t
M
)
)
M
ms
23.4
31.25
23.4
46.9
Hz
Hz
pF
10
pF
17
17
20
20
pF
12
12
16
16
–B
–D
2
2
250
250
250
250
2048
2048
2048
2048
8
0.5/ 0.5
0.5/ 0.5
0.5/ 0.5
1/ 3
NPN
NPN
NPN
NPN
V
SS
8
V
DD
10
–V2
E2
0.5
2
8
V
V
12.5
12.5
SS
8
SS
*) on-chip stray capacitance included
Option
Pad Designation
Pad 1
Pad 2
Pad 3
Pad 4
Pad 5
Pad 6
Pad 7
Pad 8
Pad 9
Pad 10
Pad 11
Pad 12
Pad 13
–B
–D
OSCIN
V
ALOUT MOT2
MOT1
MOT1
MOT1
MOT1
MOT1
MOT1
MOT1
ALIN/
MTEST
V
SS
V
SS
V
SS
V
SS
OSC-
OUT
SC4
SC4
SC4
SC4
SC3
SC2
SC2
SC2
SC2
SC1
DD
OSCIN
OSCIN
OSCIN
OSC- ALOUT MOT2
OUT
ALIN/
MTEST
V
DD
SC3
SC3
SC3
SC1
SC1
SC1
–V2
–D
V
DD
ALOUT MOT2
ALIN/
MTEST
OSC-
OUT
OSC- ALOUT MOT2
OUT
ALIN/
TEST
MOT1
V
DD
We reserve the right to make changes to improve technical design and may do so without further notice.
Parameters can vary in different applications. All operating parameters must be validated for each customer
application by the customer. Should the buyer use Atmel Wireless & Microcontrollers products for any unintended
or unauthorized application, the buyer shall indemnify Atmel Wireless & Microcontrollers against all claims,
costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death
associated with such unintended or unauthorized use.
Data sheets can also be retrieved from the Internet:
http://www.atmel–wm.com
Atmel Germany GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany
Telephone: 49 (0)7131 67 2594, Fax number: 49 (0)7131 67 2423
6 (6)
Rev. A2, 15-Jan-01
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