EDI88128C10NM [ETC]
128KX8 MONOLITHIC SRAM, SMD 5962-89598; 128Kx8单片SRAM , SMD 5962-89598型号: | EDI88128C10NM |
厂家: | ETC |
描述: | 128KX8 MONOLITHIC SRAM, SMD 5962-89598 |
文件: | 总8页 (文件大小:151K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
The EDI88128C is a high speed, high performance, Mono-
lithic CMOS Static RAM organized as 128Kx8.
n Access Times of 70, 85, 100ns
n Available with Single Chip Selects (EDI88128) or Dual
Chip Selects (EDI88130)
n 2V Data Retention (LP Versions)
n CS and OE Functions for Bus Control
n TTL Compatible Inputs and Outputs
n Fully Static, No Clocks
The device is also available as EDI88130C with an additional
chip select line (CS2) which will automatically power down
the device when proper logic levels are applied.
The second chip select line (CS2) can be used to provide
system memory security during power down in non-battery
backed up systems and simplifiy decoding schemes in memory
banking where large multiple pages of memory are required.
n Organized as 128Kx8
n Industrial, Military and Commercial Temperature Ranges
n Thru-hole and Surface Mount Packages JEDEC Pinout
•32 pin Ceramic DIP, 0.6 mils wide (Package 9)
•32 lead Ceramic SOJ (Package 140)
n Single +5V ( 10ꢀ) Supply Operation
The EDI88128C and the EDI88130C have eight bi-directional
input-output lines to provide simultaneous access to all
bits in a word. An automatic power down feature permits
the on-chip circuitry to enter a very low standby mode and
be brought back into operation at a speed equal to the
address access time.
Low power versions, EDI88128LP and EDI88130LP, offer a
2V data retention function for battery back-up opperation.
Military product is available compliant to Appendix A of
MIL-PRF-38535.
FIG. 1
32 DIP
32 SOJ
I/O0-7
A0-16
WE
DataInputs/Outputs
AddressInputs
Write Enable
CS1, CS2
OE
Chip Selects
NC
A16
A14
A12
A7
A6
A5
A4
A3
1
2
3
4
5
6
7
8
9
32 VCC
Output Enable
Power (+5V 10ꢀ)
Ground
31 A15
30 NC/CS2*
29 WE
28 A13
27 A8
26 A9
25 A11
24 OE
VCC
VSS
NC
Not Connected
A2 10
A1 11
AØ 12
I/OØ 13
I/O1 14
I/O2 15
23 A10
22 CS1
21 I/O7
20 I/O6
19 I/O5
18 I/O4
17 I/O3
VSS 16
* Pin 30 is NC for 88128 or CS2 for 88130.
March 2002 Rev. 16
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
X
X
X
H
L
H
X
X
L
X
L
X
X
X
H
H
L
Standby
Standby
High Z
High Z
High Z
High Z
Data Out
Data In
Icc2, Icc3
Icc2, Icc3
Icc1
Voltage on any pin relative to Vss
-0.5 to 7.0
V
L
Output Deselect
Output Deselect
Read
Commercial
Industrial
0to+70
-40 to +85
-55 to +125
-65 to +150
1
°C
°C
H
H
H
Icc1
L
Icc1
Military
°C
X
L
Write
Icc1
Storage Temperature, Plastic
Power Dissipation
OutputCurrent
Junction Temperature, TJ
NOTE:
Stress greater than those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions greater than those
indicated in the operational sections of this specification is not implied. Expo-
sure to absolute maximum rating conditions for extended periods may affect
reliability.
°C
W
20
mA
°C
175
Supply Voltage
Supply Voltage
VCC
4.5
0
5.0
0
5.5
V
V
V
V
VSS
VIH
VIL
0
Input High Voltage
Input Low Voltage
2.2
-0.3
—
—
Vcc +0.5
+0.8
AddressLines
CI
V
IN = Vcc or Vss, f = 1.0MHz
12
14
pF
pF
Input/OutputLines
CO
VOUT = Vcc or Vss, f = 1.0MHz
These parameters are sampled, not 100ꢀ tested.
InputLeakageCurrent
OutputLeakageCurrent
ILI
VIN =0VtoVCC
-5
-10
—
—
—
+5
+10
120
110
10
µA
µA
ILO
VI/O =0VtoVCC, CS1 ³ VIH and/orCS2 £ VIL
WE, CS1 = VIL, II/O = 0mA, Min Cycle
CS2 =VIH
(70-85ns)
(100ns)
mA
mA
mA
OperatingPowerSupplyCurrent
ICC1
ICC2
—
Standby(TTL)PowerSupplyCurrent
CS1 ³ VIH and/or CS2 £ VIL, VIN ³ VIH or £ VIL
—
CS1 ³ VCC -0.2V and/or CS2 £ Vcc +0.2V
VIN ³ Vcc -0.2V or VIN £ 0.2V
IOL = 2.1mA
C
LP
—
—
—
1
—
—
5
1
0.4
mA
mA
V
FullStandbyPowerSupplyCurrent
OutputLowVoltage
ICC3
VOL
OutputHighVoltage
VOH
IOH = -1.0mA
2.4
—
—
V
NOTE:DCtestconditions : VIL = 0.3V, VIH = Vcc -0.3V
White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520
Read Cycle Time
tAVAV
tAVQV
tRC
70
85
100
ns
ns
AddressAccessTime
ChipSelectAccessTime
tAA
70
85
100
tELQV
tSHQV
tACS
tACS
70
70
85
85
100
100
ns
ns
ChipSelecttoOutput inLowZ (1)
ChipDisabletoOutputinHighZ (1)
tELQX
tSHQX
tCLZ
tCLZ
3
3
3
3
3
3
ns
ns
tEHQZ
tSLQZ
tCHZ
tCHZ
0
0
30
30
0
0
30
30
0
0
30
30
ns
ns
OutputHoldfromAddressChange
OutputEnabletoOutputValid
tAVQX
tGLQV
tGLQX
tGHQZ
tOH
tOE
3
3
3
ns
ns
ns
ns
25
30
30
30
50
30
OutputEnabletoOutputinLowZ(1)
OutputDisabletoOutputinHighZ(1)
tOLZ
tOHZ
0
0
0
0
0
0
1. This parameter is guaranteed by design but not tested.
Input Pulse Levels
VSS to 3.0V
Figure 1
Figure 2
Input Rise and Fall Times
Input and Output Timing Levels
OutputLoad
5ns
1.5V
Vcc
Vcc
Figure 1
480Ω
480Ω
NOTE: For tEHQZ, tGHQZ and tWLQZ, CL = 5pF Figure 2)
Q
Q
30pF
5pF
255Ω
255Ω
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
Write Cycle Time
tAVAV
tWC
70
85
100
ns
Chip Select to End of Write
tELWH
tELEH
tSHWH
tSHSL
tCW
tCW
tCW
tCW
60
60
60
60
75
75
75
75
85
85
85
85
ns
ns
ns
ns
Address Setup Time
tAVWL
tAVEL
tAVSH
tAS
tAS
tAS
0
0
0
0
0
0
0
0
0
ns
ns
ns
Address Valid to End of Write
Write Pulse Width
tAVWH
tAW
60
75
85
ns
tWLWH
tWLEH
tWLSL
tWP
tWP
tWP
35
35
35
70
70
70
80
80
80
ns
ns
ns
Write Recovery Time
Data Hold Time
tWHAX
tEHAX
tSLAX
tWR
tWR
tWR
5
5
5
5
5
5
5
5
5
ns
ns
ns
tWHDX
tEHDX
tSLDX
tDH
tDH
tDH
0
0
0
0
0
0
0
0
0
ns
ns
ns
Write to Output in High Z (1)
Data to Write Time
tWLQZ
tWHZ
0
30
0
35
0
40
ns
tDVWH
tDVEH
tDVSL
tDW
tDW
tDW
35
35
35
40
40
40
40
40
40
ns
ns
ns
Output Active from End of Write (1)
tWHQX
tWLZ
5
5
5
ns
1. This parameter is guaranteed by design but not tested.
White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520
tAVAV
ADDRESS
tAVQV
CS1
tELQV
tELQX
tEHQZ
tAVAV
CS2
tSHQV
tSHQX
ADDRESS
DATA I/O
ADDRESS 1
ADDRESS 2
tSLQZ
OE
tAVQV
tAVQX
tGLQV
tGLQX
tGHQZ
DATA
1
DATA 2
DATA I/O
READ CYCLE 2 (WE HIGH)
READ CYCLE 1 (WE HIGH; OE, CS LOW)
tAVAV
ADDRESS
WE
tAVWH
tAVWL
tWHAX
tWLWH
CS
CS
1
2
tELWH
tWHQX
tWHDX
tSHWH
tDVWH
DATA IN
DATA VALID
tWLQZ
HIGH Z
DATA OUT
WRITE CYCLE 1 - LATE WRITE, WE CONTROLLED
tAVAV
tAVAV
WS32K32-XHX
ADDRESS
ADDRESS
WE
tSLAX
tEHAX
tAVSH
tAVEL
tWLSL
tWLEH
WE
tSHSL
tELEH
CS1
CS1
CS2
CS2
tDVSL
tSLDX
tDVEH
tEHDX
DATA IN
DATA IN
DATA VALID
2 CONTROLLED
DATA VALID
WRITE CYCLE 3 - EARLY WRITE, CS
WRITE CYCLE 2 - EARLY WRITE, CS
1
CONTROLLED
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
DataRetentionVoltage
VDD
VDD =2.0V
2
–
–
–
–
V
DataRetentionQuiescentCurrent
ICCDR
CS1 ³ VDD -0.2V
400
µA
ChipDisabletoDataRetentionTime(1)
OperationRecoveryTime(1)
TCDR
VIN ³VDD -0.2V
orVIN £ 0.2V
0
–
–
–
–
ns
ns
TR
TAVAV*
NOTE:
1. Parameterguaranteedbydesign, butnottested.
* Read Cycle Time
Data Retention Mode
WS32K32-XHX
4.5V
4.5V
Vcc
V
DD
tCDR
tR
CS1
CS
1 VDD -0.2V
DATA RETENTION, CS1 CONTROLLED
Data Retention Mode
WS32K32-XHX
4.5V
4.5V
Vcc
VDD
tCDR
tR
CS
2
CS2 ≤ 0.2V
DATA RETENTION, CS
2
CONTROLLED
White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520
32 PIN SIDEBRAZED CERAMIC DIP (600MILS WIDE)
1.616
1.584
0.620
0.600
0.060
0.040
Pin 1 Indicator
0.200
0.125
0.155
0.115
0.600
NOM
0.020
0.100
TYP
0.016
0.061
0.017
15 x 0.100 = 1.500
ALL Dimensions ARE in inches
32 LEAD CERAMIC SOJ
0.010
0.006
0.019
0.015
0.840
0.820
0.050
TYP
0.444
0.430
0.379
0.155
0.106
ALL Dimensions ARE in inches
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
8 130 = Dual Chip Select
C=CMOSStandardPower
LP=LowPower
C = 32 lead Sidebrazed DIP, 600 mil (Package 9)
N = 32 lead Ceramic SOJ (Package 140)
B = MIL-STD-883Compliant
M= MilitaryScreened
I = Industrial
C = Commercial
-55°Cto+125°C
-40°Cto+85°C
0°Cto+70°C
White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520
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