EDI88512LPAF36B [ETC]
512Kx8 Monolithic SRAM, SMD 5962-95600; 512Kx8单片SRAM ， SMD 5962-95600
| 型号： | EDI88512LPAF36B |
| 厂家： | 
ETC |
| 描述： | 512Kx8 Monolithic SRAM, SMD 5962-95600 |
| 文件： | 总9页 (文件大小：269K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EDI88512CA
512Kx8 Monolithic SRAM, SMD 5962-95600
FEATURES
The EDI88512CA is a 4 megabit Monolithic CMOS
Static RAM.
■ Access Times of 15, 17, 20, 25, 35, 45, 55ns
■ Data Retention Function (LPA version)
■ TTL Compatible Inputs and Outputs
■ Fully Static, No Clocks
The 32 pin DIP pinout adheres to the JEDEC evolu-
tionary standard for the four megabit device. All 32 pin
packages are pin for pin upgrades for the single chip
enable 128K x 8, the EDI88128CS. Pins 1 and 30 be-
come the higher order addresses.
The 36 pin revolutionary pinout also adheres to the
JEDEC standard for the four megabit device. The cen-
ter pin power and ground pins help to reduce noise in
high performance systems. The 36 pin pinout also
allows the user an upgrade path to the future 2Mx8.
■ Organized as 512Kx8
■ Commercial, Industrial and Military Temperature Ranges
■ 32 lead JEDEC Approved Evolutionary Pinout
•
•
•
•
•
Ceramic Sidebrazed 600 mil DIP (Package 9)
Ceramic Sidebrazed 400 mil DIP (Package 326)
Ceramic 32 pin Flatpack (Package 344)
Ceramic Thin Flatpack (Package 321)
Ceramic SOJ (Package 140)
A
Low Power version with Data Retention
(EDI88512LPA) is also available for battery backed
applications. Military product is available compliant to
Appendix A of MIL-PRF-38535.
■ 36 lead JEDEC Approved Revolutionary Pinout
•
•
•
Ceramic Flatpack (Package 316)
Ceramic SOJ (Package 327)
Ceramic LCC (Package 502)
■ Single +5V (±10%) Supply Operation
FIG. 1 PIN CONFIGURATION
PIN DESCRIPTION
I/O0-7 Data Inputs/Outputs
36 PIN
32 PIN
TOP VIEW
TOP VIEW
A0-18
WE
CS
Address Inputs
Write Enables
Chip Selects
A18
A16
A14
A12
A7
A6
A5
A4
A3
1
2
3
4
5
6
7
8
9
32 VCC
31 A15
30 A17
29 WE
28 A13
27 A8
OE
Output Enable
Power (+5V ±10%)
Ground
VCC
VSS
NC
26 A9
25 A11
24 OE
23 A10
22 CS
21 I/O7
20 I/O6
19 I/O5
18 I/O4
17 I/O3
Not Connected
A2 10
A1 11
A0 12
I/O0 13
I/O1 14
I/O2 15
BLOCK DIAGRAM
Memory Array
VSS 16
Address
Buffer
Address
Decoder
I/O
Circuits
A
-18
I/O -7
WE
CS
OE
Aug. 2002 Rev. 9
1
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
EDI88512CA
ABSOLUTE MAXIMUM RATINGS
TRUTH TABLE
Mode
Standby
Output Deselect High Z
OE
X
CS
H
L
WE
X
Output
Power
Icc2, Icc3
Icc1
Parameter
Unit
High Z
Voltage on any pin relative to Vss
Operating Temperature TA (Ambient)
Commercial
-0.5 to 7.0
V
H
H
L
X
L
H
L
Read
Write
Data Out
Data In
Icc1
0 to +70
-40 to +85
-55 to +125
-65 to +150
1.5
°C
°C
°C
°C
W
mA
°C
L
Icc1
Industrial
Military
Storage Temperature, Plastic
Power Dissipation
RECOMMENDED OPERATING CONDITIONS
Output Current
20
175
Parameter
Symbol
Min
4.5
0
2.2
-0.3
Typ
5.0
0
—
—
Max
5.5
0
3.0
+0.8
Unit
V
Junction Temperature, TJ
Supply Voltage
Supply Voltage
Input High Voltage
Input Low Voltage
VCC
VSS
VIH
VIL
V
NOTE:
V
Stress greater than those listed under "Absolute Maximum Ratings"
may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other
conditions greater than those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
V
CAPACITANCE
(TA = +25°C)
Parameter
Address Lines
Data Lines
Symbol
CI
CO
Condition
Max Unit
VIN = Vcc or Vss, f = 1.0MHz 12 pF
VOUT = Vcc or Vss, f = 1.0MHz 14 pF
These parameters are sampled, not 100% tested.
DC CHARACTERISTICS
(VCC = 5V, TA = -55°C TO +125°C)
Parameter
Symbol
Conditions
Units
Min
-10
-10
—
Max
10
Input Leakage Current
Output Leakage Current
Operating Power Supply Current
ILI
ILO
VIN = 0V to VCC
VI/O = 0V to VCC
µA
µA
mA
mA
mA
mA
mA
V
10
ICC1
WE, CS = VIL, II/O = 0mA, Min Cycle
(17ns)
250
225
60
25
20
0.4
—
(20 -55ns)
—
Standby (TTL) Power Supply Current
Full Standby Power Supply Current
ICC2
ICC3
CS O VIH, VIN ? VIL, VIN O VIH
CS O VCC -0.2V
VIN O Vcc -0.2V or VIN ? 0.2V
IOL = 8.0mA
IOH = -4.0mA
—
CA
LPA
—
—
Output Low Voltage
Output High Voltage
VOL
VOH
—
2.4
V
NOTE: DC test conditions: VIL = 0.3V, VIH = Vcc -0.3V
AC TEST CONDITIONS
Input Pulse Levels
VSS to 3.0V
5ns
Figure 1
Figure 2
Input Rise and Fall Times
Vcc
Vcc
Input and Output Timing Levels
Output Load
1.5V
Figure 1
480Ω
480Ω
NOTE: For tEHQZ, tGHQZ and tWLQZ, CL = 5pF Figure 2)
Q
Q
30pF
5pF
255Ω
255Ω
White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520
2
EDI88512CA
AC CHARACTERISTICS – READ CYCLE
(VCC = 5.0V, VSS = 0V, TA = -55°C TO +125°C)
Symbol
15ns
17ns
20ns
25ns
35ns
45ns
55ns
Parameter
JEDEC Alt.
Min Max Min Max Min Max Min Max Min Max Min Max Min Max Units
Read Cycle Time
tAVAV
tAVQV
tELQV
tELQX
tEHQZ
tAVQX
tGLQV
tGLQX
tGHQZ
tRC
tAA
tACS
tCLZ
tCHZ
tOH
tOE
tOLZ
tOHZ
15
17
20
25
35
45
55
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
Chip Enable Access Time
15
15
17
17
20
20
25
25
35
35
45
45
55
55
Chip Enable to Output in Low Z (1)
Chip Disable to Output in High Z (1)
Output Hold from Address Change
Output Enable to Output Valid
Output Enable to Output in Low Z (1)
Output Disable to Output in High Z(1)
2
0
0
3
0
0
3
0
0
3
0
0
3
0
0
3
0
0
3
0
0
7
8
7
7
8
7
8
10
8
10
12
10
15
15
15
20
25
20
20
30
20
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1. This parameter is guaranteed by design but not tested.
AC CHARACTERISTICS – WRITE CYCLE
(VCC = 5.0V, VSS = 0V, TA = -55°C TO +125°C)
Symbol
15ns
17ns
20ns
25ns
35ns
45ns
55ns
Parameter
Write Cycle Time
Chip Enable to End of Write
JEDEC Alt.
Min Max Min Max Min Max Min Max Min Max Min Max Min Max Units
tAVAV
tWC
15
17
20
25
35
45
55
ns
tELWH
tCW
13
14
15
17
25
30
50
ns
tELEH
tCW
13
14
15
17
25
30
50
ns
Address Setup Time
Address Valid to End of Write
Write Pulse Width
tAVWL
tAS
tAS
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ns
ns
tAVEL
tAVWH
tAW
13
14
15
17
25
30
50
ns
tAVEH
tAW
13
14
15
17
25
30
50
ns
tWLWH
tWP
tWP
13
13
14
14
15
15
17
17
25
25
30
30
45
45
ns
ns
tWLEH
Write Recovery Time
Data Hold Time
tWHAX
tWR
0
0
0
0
0
0
0
ns
tEHAX
tWR
0
0
0
0
0
0
0
ns
tWHDX
tDH
tDH
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ns
ns
tEHDX
Write to Output in High Z (1)
Data to Write Time
tWLQZ
tWHZ
0
8
0
8
0
8
10
25
30
0
30
ns
tDVWH
tDW
8
8
10
12
20
25
40
ns
tDVEH
tDW
8
8
10
12
20
25
30
ns
Output Active from End of Write (1)
tWHQX
tWLZ
0
0
0
0
0
0
0
ns
1. This parameter is guaranteed by design but not tested.
3
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
EDI88512CA
FIG. 2 TIMING WAVEFORM - READ CYCLE
tAVAV
ADDRESS
tAVQV
CS
tAVAV
tEHQZ
tELQV
tELQX
ADDRESS
DATA I/O
ADDRESS 1
ADDRESS 2
OE
tAVQV
tAVQX
tGLQV
tGLQX
tGHQZ
DATA
1
DATA 2
DATA OUT
READ CYCLE 1 (WE HIGH; OE, CS LOW)
READ CYCLE 2 (WE HIGH)
FIG. 3 WRITE CYCLE - WE CONTROLLED
tAVAV
ADDRESS
tAVWH
tELWH
tWHAX
CS
tAVWL
tWLWH
WE
tDVWH
tWHDX
DATA IN
DATA VALID
tWLQZ
tWHQX
HIGH Z
DATA OUT
WRITE CYCLE 1, WE CONTROLLED
FIG. 4 WRITE CYCLE - CS CONTROLLED
tAVAV
ADDRESS
WS32K32-XH
tAVEH
tELEH
tEHAX
CS
tAVEL
tWLEH
WE
tDVEH
tEHDX
DATA IN
DATA VALID
HIGH Z
DATA OUT
WRITE CYCLE 2, CS CONTROLLED
White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520
4
EDI88512CA
DATA RETENTION CHARACTERISTICS (EDI88512LPAONLY)
(TA = -55°C TO +125°C)
Characteristic
Sym
Conditions
Min
Typ
Max
Units
Low Power Version only
Data Retention Voltage
Data Retention Quiescent Current
Chip Disable to Data Retention Time
Operation Recovery Time
VDD
ICCDR
TCDR
TR
VDD = 2.0V
CS O VDD -0.2V
VIN O VDD -0.2V
or VIN ? 0.2V
2
–
–
–
–
–
–
2
–
–
V
mA
ns
0
TAVAV
ns
FIG. 5 DATA RETENTION - CS CONTROLLED
DATA RETENTION MODE
WS32K32-XHX
4.5V
4.5V
VCC
VDD
tCDR
tR
CS
CS = VDD -0.2V
DATA RETENTION, CS CONTROLLED
5
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
EDI88512CA
PACKAGE 9: 32 LEAD SIDEBRAZED CERAMIC DIP, SMD 5962-95600XXMXA
1.616
1.584
0.620
0.060
0.040
Pin 1 Indicator
0.600
0.200
0.125
0.155
0.115
0.600
NOM
0.020
0.016
0.100
TYP
0.061
0.017
15 x 0.100 = 1.500
ALL DIMENSIONS ARE IN INCHES
PACKAGE 326: 32 LEAD SIDEBRAZED CERAMIC DIP
1.616
1.584
0.420
0.400
Pin 1 Indicator
1
1
0.200
0.125
0.155
0.115
0.400
NOM
0.020
0.016
0.100
TYP
0.061
0.017
15 x 0.100 = 1.500
ALL DIMENSIONS ARE IN INCHES
PACKAGE 140: 32 LEAD CERAMIC SOJ, SMD 5962-95600XXMUA
0.010
0.006
0.019
0.015
0.840
0.820
0.050
TYP
0.444
0.430
0.379
0.155
0.106
ALL DIMENSIONS ARE IN INCHES
White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520
6
EDI88512CA
PACKAGE 316: 36 PIN CERAMIC FLATPACK, SMD 5962-95600XXMTA
0.920 – 0.010
0.007
0.003
0.370
0.250
1.00 REF
0.395
0.385
0.515
0.505
0.040
0.030
Pin 1
0.019
0.015
0.045
0.020
0.125
0.100
0.050
TYP
ALL DIMENSIONS ARE IN INCHES
PACKAGE 321: 32 PIN THINPACK™ FLATPACK, SMD 5962-95600XXMYA
0.838
MAX
0.567
0.427
0.429
0.559
0.118
MAX.
0.020
0.030
0.008
0.005
0.050
TYP
0.016 0.008
ALL DIMENSIONS ARE IN INCHES
PACKAGE 344: 32 PIN CERAMIC FLATPACK, SMD 5962-95600XXM9A
ALL DIMENSIONS ARE IN INCHES
7
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
EDI88512CA
PACKAGE 327: 36 LEAD CERAMIC SOJ, SMD 5962-95600XXMMA
0.010
0.006
0.019
0.015
0.920
0.940
0.050
TYP
0.444
0.434
0.379
0.155
0.106
ALL DIMENSIONS ARE IN INCHES
PACKAGE 502: 36 LEAD CERAMIC LCC, SMD 5962-95600XXMNA (Pending)
0.135
0.115
0.100
0.080
0.100
TYP
36
1
0.009 TYP
0.028
0.022
0.930
0.910
0.860
0.840
0.050
BSC
0.066
0.054
0.460
0.445
ALL DIMENSIONS ARE IN INCHES
White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520
8
EDI88512CA
ORDERING INFORMATION
EDI 8 8 512 CA X X X
WHITE ELECTRONIC DESIGNS
SRAM
ORGANIZATION, 512Kx8
TECHNOLOGY:
CA = CMOS Standard Power
LPA = Low Power
ACCESS TIME (ns)
PACKAGETYPE:
C = 32 lead Sidebrazed DIP, 600 mil (Package 9)
K = 36 lead Ceramic LCC (Package 502)
N = 32 lead Ceramic SOJ (Package 140)
T = 32 lead Sidebrazed DIP, 400 mil (Package 326)
B32 = 32 pin Ceramic Thinpack™ Flatpack (Package 321)
F32 = 32 pin Ceramic Flatpack (Package 344)
F36 = 36 pin Ceramic Flatpack (Package 316)
N36 = 36 lead Ceramic SOJ (Package 327)
DEVICE GRADE:
B = MIL-STD-883Compliant
M = Military Screened
I = Industrial
-55°C to +125°C
-40°C to +85°C
0°C to +70°C
C = Commercial
9
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
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