EDI8G321024CA12MNC [ETC]
x32 SRAM Module ; X32 SRAM模块\n
| 型号： | EDI8G321024CA12MNC |
| 厂家： | 
ETC |
| 描述： | x32 SRAM Module
|
| 文件： | 总6页 (文件大小：114K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EDI8F321024CA
1024Kx32 SRAM Module
1024Kx32 Static RAM
CMOS, High Speed Module
Features
The EDI8F321024CA is a high speed 32 megabit Static
RAM module organized as 1024K words by 32 bits. This
moduleisconstructedfromeight1024Kx4StaticRAMsin
SOJ packages on an epoxy laminate (FR4) board.
Four chip enables (EØ-E3) are used to independently
enablethefourbytes. Readingorwritingcanbeexecuted
on individual bytes or any combination of multiple bytes
throughproperuseofselects.
1024Kx32 bit CMOS Static
Random Access Memory
• Access Times: 12, 15ns
• Individual Byte Selects
• Fully Static, No Clocks
• TTL Compatible I/O
TheEDI8F321024CAisofferedina72leadSIMMpackage,
whichenable 32megabits ofmemorytobe placedinless
than1.3squareinchesofboardspace.
AllinputsandoutputsareTTLcompatibleandoperatefrom
asingle5Vsupply.Fullyasynchronous circuitry requires
no clocks or refreshing for operation and provides equal
access and cycle times for ease of use.
HighDensityPackage
• 72 lead SIMM, No. 176 (Angle)
• 72 lead SIMM, No. 356 (Straight)
• Common Data Inputs and Outputs
Single +5V (±10%) Supply Operation
Pins PD1-PD4,areusedtoidentifymodulememorydensity
inapplicationswherealternatemodulescanbeinterchanged.
Pin Configurations and Block Diagram
Pin Names
1
3
5
7
9
NC
NC
PD4
PD1
DQØ
DQ1 10
DQ2 12
DQ3 14
VCC 16
A7 18
A8 20
A9 22
DQ4 24
DQ5 26
DQ6 28
DQ7 30
2
4
6
8
PD3
VSS
PD2
DQ8
AØ-A19
EØ-E3
W
Address Inputs
Chip Enables
Write Enable
Output Enable
Common Data
Input/Output
Power(+5V±10%)
Ground
No Connection
11 DQ9
13 DQ10
15 DQ11
17 AØ
19 A1
21 A2
23 DQ12
25 DQ13
27 DQ14
29 DQ15
31 VSS
33 A15
35 E1
G
DQØ-DQ31
VCC
VSS
NC
W
32
AØ-A19
A14 34
EØ 36
20
W
G
37 E3
39 A17
41
43 DQ24
45 DQ25
47 DQ26
49 DQ27
51 A3
53 A4
55 A5
57 VCC
59 A6
61 DQ28
63 DQ29
65 DQ30
67 DQ31
69 A18
71 NC
E2 38
A16 40
G
VSS 42
DQ16 44
DQ17 46
DQ18 48
DQ19 50
A10 52
A11 54
A12 56
A13 58
DQ20 60
DQ21 62
DQ22 64
DQ23 66
VSS 68
A19 70
DQØ-DQ3
DQ4-DQ7
4
4
4
4
4
4
4
4
EØ
E1
E2
E3
DQ8-DQ11
DQ16-DQ19
DQ24-DQ27
DQ12-DQ15
DQ20-DQ23
DQ28-DQ31
NC 72
PD1 & PD3 = VSS
PD2 & PD4 = Open
ElectronicDesigns,Inc.
•OneResearchDrive•Westborough,MA01581USA•508-366-5151• FAX508-836-4850•
http://www.electronic-designs.com
1
EDI8F321024CA Rev. 0 7/98 ECO#10589
Absolute Maximum Ratings*
Recommended DC Operating Conditions
Parameter
Supply Voltage
Supply Voltage
Input High Voltage VIH 2.2
Input Low Voltage VIL -0.3
Sym Min Typ Max Units
Voltage on any pin relative to VSS
Operating Temperature TA (Ambient)
Commercial
Industrial
Storage Temperature, Plastic
Power Dissipation
-0.5V to 7.0V
VCC 4.5
VSS
5.0
0
5.5
0
V
V
V
V
0
0°C to +70°C
-40°C to +85°C
-55°C to +125°C
7.0 Watts
--
--
6.0
0.8
Output Current
20 mA
AC Test Conditions
*Stress greater than those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions greater than those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
Input Pulse Levels
VSS to 3.0V
5ns
1.5V
1TTL, CL = 30pF
Input Rise and Fall Times
Input and Output Timing Levels
Output Load
(note: For TEHQZ,TGHQZ and TWLQZ, CL = 5pF)
DC Electrical Characteristics
Parameter
Sym
Conditions
Min
Typ
Max Units
Operating Power Supply Current
Standby (TTL) Power Supply Current ICC2 E ³ VIH, VIN £ VIL or VIN ³ VIH
Full Standby Power Supply Current
CMOS
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage
ICC1 W, E = VIL, II/O = 0mA, Min Cycle
1600
600
90
mA
mA
mA
ICC3
E ³ VCC-0.2V
VIN ³ VCC-0.2V or VIN £ 0.2V
VIN = 0V to VCC
ILI
--
--
2.4
--
--
--
--
--
±80
±20
--
µA
µA
V
ILO
VOH
VOL
V I/O = 0V to VCC
IOH = -4.0mA
IOL = 8.0mA
0.4
V
*Typical: TA = 25°C, VCC = 5.0V
Truth Table
Capacitance
(f=1.0MHz, VIN=VCC or VSS)
E
H
L
L
W
X
H
L
G
X
L
Mode
Standby
Read
Write
Output
Deselect
Output
HIGH Z
DOUT
DIN
Power
ICC2/ICC3
ICC1
Parameter
Sym
Max
60
20
20
60
Unit
Address Lines
Data Lines
Chip Enable Line
Write Line
CI
CD/Q
CC
pF
pF
pF
pF
X
ICC1
L
H
H
HIGH Z
ICC1
CN
These parameters are sampled, not 100% tested.
EDI8F321024CA
1024Kx32 SRAM Module
2
EDI8F321024CA Rev. 0 7/98 ECO#10589
EDI8F321024CA
1024Kx32 SRAM Module
AC Characteristics Read Cycle
Symbol
JEDEC
12ns
15ns
Parameter
Read Cycle Time
Address Access Time
Chip Enable Access
Chip Enable to Output in Low Z (1)
Chip Disable to Output in High Z (1)
Output Hold from Address Change
Output Enable to Output Valid
Output Enable to Output in Low Z (1)
Output Disable to Output in High Z(1)
Alt.
Min
12
Max
Min
15
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
TAVAV
TAVQV
TELQV
TELQX
TEHQZ
TAVQX
TGLQV
TGLQX
TGHQZ
TRC
TAA
TACS
TCLZ
TCHZ
TOH
TOE
TOLZ
TOHZ
12
12
15
15
3
3
0
3
3
0
6
6
6
7
7
7
ns
Note 1: Parameter guaranteed, but not tested.
Read Cycle 1 - W High, G, E Low
TAVAV
ADDRESS 1
TAVQV
ADDRESS 2
TAVQX
A
DATA 2
Q
DATA 1
Read Cycle 2 - W High
TAVAV
A
TAVQV
E
TELQV
TEHQZ
TGHQZ
TELQX
G
TGLQV
TGLQX
Q
3
EDI8F321024CA Rev. 0 7/98 ECO#10589
AC Characteristics Write Cycle
Symbol
JEDEC
15ns
Min
15
10
10
0
17ns
Min
15
12
12
0
Parameter
Write Cycle Time
Chip Enable to End of Write
Alt.
TWC
TCW
TCW
TAS
Max
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TAVAV
TELWH
TWLEH
TAVWL
TAVEL
TAVWH
TAVEH
TWLWH
TELEH
TWHAX
TEHAX
TWHDX
TEHDX
TWLQZ
TDVWH
TDVEH
TWHQX
Address Setup Time
Address Valid to End of Write
Write Pulse Width
TAS
0
0
TAW
TAW
TWP
TWP
TWR
TWR
TDH
10
10
10
10
0
0
0
0
0
12
12
12
12
0
0
0
0
0
Write Recovery Time
Data Hold Time
TDH
Write to Output in High Z (1)
Data to Write Time
TWHZ
TDW
TDW
TWLZ
7
8
7
7
3
10
10
3
Output Active from End of Write (1)
Note 1: Parameter guaranteed, but not tested.
Write Cycle 1 - W Controlled
TAVAV
A
E
TELWH
TAVWH
TWHAX
TWLWH
W
TAVWL
TWHDX
TWHQX
TDVWH
D
Q
DATA VALID
TWLQZ
HIGH Z
EDI8F321024CA
1024Kx32 SRAM Module
4
EDI8F321024CA Rev. 0 7/98 ECO#10589
EDI8F321024CA
1024Kx32 SRAM Module
Write Cycle 2 - E Controlled
TAVAV
A
TAVEL
TELEH
E
TEHAX
TEHDX
TAVEH
TWLEH
W
TDVEH
DATA VALID
D
Q
HIGH Z
5
EDI8F321024CA Rev. 0 7/98 ECO#10589
Ordering Information
Part Number
Speed (ns) Package No.
Part Number
Speed (ns)
Package No.
EDI8F321024CA12MNC
EDI8F321024CA15MNC
EDI8G321024CA12MNC
EDI8G321024CA15MNC
12
15
12
15
176
176
176
176
EDI8F321024CA12MMC
EDI8F321024CA15MMC
EDI8G321024CA12MMC
EDI8G321024CA15MMC
12
15
12
15
356
356
356
356
Note: To order gold SIMM option refer to "EDI8G321024CXXMNC"; to order tin
plated contacts option refer to "EDI8F321024CXXMNC".
Package Descriptions
Package No. 176
72 Lead Angled SIMM
4.255 MAX.
3.984
1.992
.225
MIN.
.680
MAX.
.400
.250
P1
.250 TYP.
.062 R.
.050
TYP.
.125
MIN.
2.045
.062 R.
3.750
.360
MAX.
Package No. 356
72 Pin SIMM
4.255 MAX
3.984
.360
MAX.
.125 DIA (2x)
J4
J2
R.#
.600
MAX.
J1
164
.400
.250
P1
.050 TYP.
2.045
.250
TYP.
1.992
.125
MIN.
3.750
.062 R. (2x)
ElectronicDesigns,Inc.
•OneResearchDrive•Westborough,MA01581USA•508-366-5151• FAX508-836-4850•
http://www.electronic-designs.com
Electronic DesignsInc.reserves the right to change specifications without notice.
CAGE No. 66301
6
EDI8F321024CA Rev. 0 7/98 ECO#10589
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