EDI8L21665V15BC [ETC]
x16 SRAM Module ; X16 SRAM模块\n
| 型号： | EDI8L21665V15BC |
| 厂家： | 
ETC |
| 描述： | x16 SRAM Module
|
| 文件： | 总5页 (文件大小：142K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EDI8L21665V
2x64Kx16 SRAM, DSP Memory Solution
FEATURES
DESCRIPTION
■ Access Times of 10, 12 and 15ns
The EDI8L21665VxxBC is a 3.3V, 2x64Kx16 SRAM constructed
with two 64Kx16 die mounted on a multi-layer laminate substrate.
The device is packaged in a 74 lead, 15mm by 15mm, BGA.
■ DSP Memory Solution
• Texas Instruments TMS320C5x
■ Packaging:
Operating with a 3.3V power supply and with access times as fast
as 10ns, the device allows the user to develop a fast external
memory for Texas Instuments’ TMS320C5x DSP.
• 74 pin BGA, JEDEC MO-151
The device consists of two separate banks of 64Kx16 of memory.
Each bank has a separate Chip Enable pin and higher order
address select pin. Bank ‘A’ is controlled using CE1\ and A15A.
Bank ‘B’ is controlled using CE2\ and A15B. The two banks have
common I/Os (DQ0-15) and control lines (WE\, E\ and G\). E\
connects to the mstrb\ pin of the C54x DSPs and is required for
write and read timing control.
■ 3.3V Operating Supply Voltage
■ Single Write Control and Output Enable Lines
■ One Chip Enable Line per Memory Bank
■ 50% Space Savings vs. Monolithic TSOPs
■ Upgrade Path Available in Same Footprint
■ Multiple VCC and VSS Pins
■ Reduced Inductance and Capacitance
PIN CONFIGURATION
BLOCK DIAGRAM
1
2
3
4
5
6
7
8
9
10
11
A
0
-
14
G
G
A
B
C
D
E
F
G
H
I
Vss Vcc Vcc DQ15 DQ14 Vcc DQ13 DQ11 DQ9 DQ8 NC
Vss Vcc Vcc Vss Vss Vcc DQ12 DQ10 DQ4 Vcc Vcc
A
B
C
D
E
F
G
H
I
U1
W
64K X 16
SSRAM
CE
CE
A
1
A
15
15A
E
Vss Vss
Vss Vss
Vss Vss
A15A CE1
Vcc
Vss Vcc
Vss Vcc
Vss Vcc
DQ3 DQ7
DQ5 DQ0
DQ6 DQ1
DQ2 NC
U2
64K X 16
SSRAM
CE
A
2
CE
A15
15A
E
W
Vss CE2
Vss A14
Vcc
J
Vss A12 Vcc A10
A15B A13 Vcc A11
A8
Vss A6
Vss A7
A4
A2
A0
G
J
K
A9
VSS
A5
A3
A1
K
1
2
3
4
5
6
7
8
9
10
11
1
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
February 1999 Rev. 0
ECO #
EDI8L21665V
PIN DESCRIPTIONS
Pin
Symbol
Type
Description
A0-14
Input
Addresses
A15A
A15B
W
Input
Input
Addresses: A15 on Bank ‘A’ of memory
Addresses: A15 on Bank ‘B’ of memory
Input
Write Enable: This active LOW input allows a full 16-bit WRITE to occur.
Chip Enable: This active LOW input is used to enable the ‘A’ Bank of the device.
Chip Enable: This active LOW input is used to enable the ‘B’ Bank of the device.
Output Enable: This active LOW asynchronous input enables the data output drivers.
Data Inputs/Outputs
CE1
CE2
G
Input
Input
Input
Various
Various
Various
DQ0-15
Vcc
Vss
E
Input/Output
Supply
Ground
Input
Core power supply: +3.3V -5%/+10%
Ground
Enable, This active LOW input controls Write and Read Timing
ABSOLUTE MAXIMUM RATINGS*
RECOMMENDED OPERATING CONDITIONS
Voltage on Vcc Supply Relative to Vss
VIN
-0.5V to 4.6V
-0.5V to Vcc+0.5V
-55°C to +125°C
+125°C
Description
Symbol
VIH
Min
2.2
Max
Vcc+0.5
0.8
Unit
V
Input High Voltage
Input Low Voltage
Supply Voltage
Storage Temperature
Junction Temperature
Power Dissipation
VIL
-0.3
3.0
V
Vcc
3.6
V
3 Watts
Short Circuit Output Current (per I/O)
50 mA
CAPACITANCE
(f = 1MHz, VIN = VCC or VSS)
* Stress greater than those listed under "Absolute Maximum Ratings" may cause perma-
nent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions greater than those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect reliability.
Parameter
Symbol
CA
Max
Unit
Address Lines
Data Lines
8
pF
pF
pF
CD/Q
CC
17
15
Control Lines
DC ELECTRICAL CHARACTERISTICS
(f = 1MHz, VIN = VCC or Vss)
Parameter
Symbol
Conditions
Min
Max
Units
Device Selected; all inputs ≤ VIL or ≥ VIH;
cycle time ≥ tKC MIN;
VCC = MAX; outputs open
-10ns
-12ns
-15ns
380
360
260
mA
Power Supply Current: Operating
ICC1
Device deselected; VCC = MAX;
CMOS Standby
TTL Standby
ISB2
ISB3
all inputs ≤ VSS +0.2 or ≥ VCC -0.2; all inputs static;
CLK frequency = 0
60
mA
mA
Device deselected; all inputs ≤ VIL or ≥ VIH;
all inputs static; VCC = MAX; CLK frequency = 0
120
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage
ILI
0V ≤ VIN ≤ VCC
-5
-5
5
5
µA
µA
V
ILO
Output(s) disabled, 0V ≤ VOUT ≤ VCC
IOH = -4.0mA
VOH
VOL
2.4
IOL = 8.0mA
0.4
V
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
2
EDI8L21665V
AC ELECTRICAL CHARACTERISTICS
Symbol
10ns
12ns
15ns
Read Cycle
Min
Max
Min
Max
Min
Max
Units
Read Cycle Time
tAVAV
tAVQV
tELQV
tAVQX
tELQX
tEHQZ
tGLQV
tGLQX
tGHQZ
10
12
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
10
10
12
12
15
15
Chip Enable Access
Output Hold from Address Change
Chip Enable to Output in Low-Z
Chip Disable to Output in High-Z
Output Enable access time
Output Enable to Output in Low-Z
Output Disable to Output in High-Z
3
3
4
4
4
4
5
5
6
6
7
7
0
0
0
5
6
7
Write Cycle
Write Cycle Time
tAVAV
tELWH
10
8
12
8
15
9
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Enable to End of Write
Address valid to End of Write, with G HIGH
Address Setup Time
tAVGHWH
tAVWL
8
8
9
0
0
0
Address Hold from End of Write
Write Pulse Width
tAVWH
8
8
10
11
9
tWLWH
tWLGHWH
tDVWH
tWHDX
tWHQX
tWLQZ
10
8
10
8
Write Pulse Width, with G HIGH
Data Setup Time
6
6
7
Data Hold Time
0
0
0
Write Disable to Output in Low-Z
Write Enable to Output in High-Z
3
4
5
5
6
7
AC TEST CIRCUIT
AC TEST CONDITIONS
Parameter
I/O
Unit
V
Output
Z0=50Ω
Input Pulse Levels
VSS to 3.0
Input Rise and Fall Times (max)
Input and Output Timing Levels
Output Load
1.5
1.5
ns
V
50Ω
See figure, at left
25V
Vt = 11.
AC Output Load Equivalent
3
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
EDI8L21665V
READ CYCLE TIMING DIAGRAMS
tAVAV
A
E
tAVQV
tAVAV
tEHQZ
tELQV
tELQX
A
ADDRESS 1
ADDRESS 2
G
Q
tAVQV
tAVQX
tGLQV
tGLQX
tGHQZ
Q
DATA 1
DATA 2
READ CYCLE 1 (W HIGH; G, E LOW)
READ CYCLE 2 (W HIGH)
WRITE CYCLE TIMING DIAGRAM
tAVAV
A
tEHAX
tAVEL
tELEH
E
tAVEH
W
tDVEH
tEHDX
D
Q
DATA VALID
HIGH Z
WRITE CYCLE 2, E CONTROLLED
NOTES: All Writes are E controlled when connected to the TMS320C54X. E is connected to MSTRB and W is connected to R/W of the TMS320C54X.
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
4
EDI8L21665V
ORDERING INFORMATION
Industrial Temperature Range (-40°C to +85°C)
Commercial Temperature Range (0°C to +70°C)
Part Number
Speed
(ns)
Package
No.
Part Number
Speed
(ns)
Package
No.
EDI8L21665V10BC
EDI8L21665V12BC
EDI8L21665V15BC
10
12
15
428
428
428
EDI8L21665V15BI
15
428
PACKAGE DESCRIPTION: 74 PIN BGA
PACKAGE NO. 428
THERMAL PACKAGE
PERFORMANCE:
θJA = 28°C/Watt (Natural Connection)
0.591 SQ.
θJB = 4°C/Watt
0.029 MAX
0.125 MAX
ALL DIMENSIONS ARE IN INCHES
5
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
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