EM78P153SPJ_技术文档

EM78P152/3S

8-Bit Microcontroller

with OTP ROM

Product

Specification

DOC. VERSION 1.8

ELAN MICROELECTRONICS CORP.

September 2009

Trademark Acknowledgments:

IBM is a registered trademark and PS/2 is a trademark of IBM.

Windows is a trademark of Microsoft Corporation.

ELAN and ELAN logo

are trademarks of ELAN Microelectronics Corporation.

Printed in Taiwan

The contents of this specification are subject to change without further notice. ELAN Microelectronics assumes no

responsibility concerning the accuracy, adequacy, or completeness of this specification. ELAN Microelectronics

makes no commitment to update, or to keep current the information and material contained in this specification.

Such information and material may change to conform to each confirmed order.

In no event shall ELAN Microelectronics be made responsible for any claims attributed to errors, omissions, or

other inaccuracies in the information or material contained in this specification. ELAN Microelectronics shall not

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or material.

The software (if any) described in this specification is furnished under a license or nondisclosure agreement, and

may be used or copied only in accordance with the terms of such agreement.

ELAN Microelectronics products are not intended for use in life support appliances, devices, or systems. Use of

ELAN Microelectronics product in such applications is not supported and is prohibited.

NO PART OF THIS SPECIFICATION MAY BE REPRODUCED OR TRANSMITTED IN ANY FORM OR BY

ANY MEANS WITHOUT THE EXPRESSED WRITTEN PERMISSION OF ELAN MICROELECTRONICS.

ELAN MICROELECTRONICS CORPORATION

Headquarters:

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USA:

No. 12, Innovation 1st Road

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Elan (HK) Microelectronics

Corporation, Ltd.

Flat A, 19F., World Tech Centre

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Tel: +852 2723-3376

Elan Information

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Elan Microelectronics

Shenzhen, Ltd.

Elan Microelectronics

Shanghai, Ltd.

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Tel: +86 21 5080-3866

Fax: +86 21 5080-4600

elan-sh@elanic.com.cn

Contents

1

2

3

4

General Description ...................................................................................... 1

Features ......................................................................................................... 1

Pin Assignment.............................................................................................. 2

Pin Description .............................................................................................. 3

4.1 EM78P153S ....................................................................................................... 3

4.2 EM78P152S ....................................................................................................... 4

5

Functional Description.................................................................................. 5

5.1 Operational Registers......................................................................................... 5

5.1.1 R0 (Indirect Addressing Register).......................................................................5

5.1.2 R1 (Timer Clock /Counter)..................................................................................5

5.1.3 R2 (Program Counter and Stack) .......................................................................6

5.1.4 R3 (Status Register) ...........................................................................................7

5.1.5 R4 (RAM Select Register) ..................................................................................8

5.1.6 R5 ~ R6 (Port 5 ~ Port 6)....................................................................................8

5.1.7 RF (Interrupt Status Register).............................................................................8

5.1.8 R10 ~ R2F ..........................................................................................................8

5.2 Special Function Registers................................................................................. 9

5.2.1 A (Accumulator) ..................................................................................................9

5.2.2 CONT (Control Register) ....................................................................................9

5.2.3 IOC5 ~ IOC6 (I/O Port Control Register)..........................................................10

5.2.4 IOCB (Pull-down Control Register)...................................................................10

5.2.5 IOCC (Open-drain Control Register) ................................................................10

5.2.6 IOCD (Pull-high Control Register) ....................................................................11

5.2.7 IOCE (WDT Control Register) ..........................................................................11

5.2.8 IOCF (Interrupt Mask Register) ........................................................................12

5.3 TCC/WDT and Prescaler.................................................................................. 12

5.4 I/O Ports ........................................................................................................... 13

5.5 Reset and Wake-up.......................................................................................... 16

5.5.1 Reset ................................................................................................................16

5.5.2 Summary of Registers Initialized Values ..........................................................18

5.5.3 Status of RST, T, and P of the Status Register .................................................20

5.6 Interrupt............................................................................................................ 21

5.7 Oscillator .......................................................................................................... 22

5.7.1 Oscillator Modes...............................................................................................22

5.7.2 Crystal Oscillator/Ceramic Resonators (Crystal)..............................................22

5.7.3 External RC Oscillator Mode ............................................................................24

5.7.4 Internal RC Oscillator Mode .............................................................................25

Product Specification (V1.8) 09.08.2009

• iii

Contents

5.8 Code Option Register....................................................................................... 26

5.8.1 Code Option Register (Word 0)........................................................................26

5.9 Power-on Considerations................................................................................. 28

5.10 Programmable Oscillator Set-up Time ............................................................. 28

5.11 External Power-on Reset Circuits..................................................................... 28

5.12 Residue-Voltage Protection.............................................................................. 29

5.13 Instruction Set .................................................................................................. 30

6

7

Absolute Maximum Ratings........................................................................ 33

Electrical Characteristics............................................................................ 33

7.1 DC Characteristics ........................................................................................... 33

7.2 AC Characteristics............................................................................................ 34

8

Timing Diagrams ......................................................................................... 35

APPENDIX

A

B

C

Package Type............................................................................................... 36

Package Information ................................................................................... 37

Device Characteristics................................................................................ 40

Specification Revision History

Doc. Version

Revision Description

Date

Initial version

1.1

Changed the Initialized Register Values, Internal RC Drift

Rate, DC and AC Electrical Characteristic

1.2

2003/05/02

Changed the Power-on reset contents

1.3

1.4

1.5

1.6

2003/06/25

2003/12/31

2006/01/16

2007/03/30

Added the Device Characteristic at Section 6.3

Added the IRC drift rate in the Features section

Added EM78P152S SSOP 10-pin Package

1. Modified the EM78P152S 10-pin SSOP Package name

2. Added Ceramic Resonators in the Oscillator section

3. Modified the contents of the Program Counter section

1.7

1.8

2009/01/12

2009/09/08

4. Modified the contents of IOCC in the Special Function

Register

1. Modified Section 5.12 Residue-Voltage Protection

iv •

Product Specification (V1.8) 09.08.2009

EM78P152/3S

8-Bit Microcontroller with OTP ROM

1 General Description

The EM78P152/3S are 8-bit microprocessor designed and developed with low-power and

high-speed CMOS technology. The devices have on-chip 1024×13-bit Electrical One Time

Programmable Read Only Memory (OTP-ROM). They provide a protection bit to prevent intrusion

of user’s OTP memory code. Fifteen Code option bits are also available to meet user’s

requirements.

With enhanced OTP-ROM features, the EM78P152/3S provides a convenient way of developing

and verifying user’s programs. Moreover, this OTP devices offer the advantages of easy and

effective program updates, using development and programming tools. You can avail of the ELAN

Writer to easily program your development code.

2 Features

CPU configuration

Peripheral configuration

• 8-bit real time clock/counter (TCC) with

selective signal sources, trigger edges,

and overflow interrupt

• 1K×13 bits on chip ROM

• 32×8 bits on-chip registers (SRAM,

general purpose)

Three available interrupts:

• TCC overflow interrupt

• 5 level stacks for subroutine nesting

• Less than 1.5 mA at 5V/4MHz

• Typically 15 μA, at 3V/32kHz

• Typically 1 μA, during Sleep mode

I/O port configuration

• Input-port status changed interrupt

(wake-up from sleep mode)

• External interrupt

Special features

• 2 bidirectional I/O ports : P5, P6

• 12 I/O pins

• Wake-up port : P6

• 6 Programmable pull-down I/O pins

• 7 programmable pull-high I/O pins

• 7 programmable open-drain I/O pins

• Programmable free running watchdog

timer

• Power saving Sleep mode

• Selectable Oscillation mode

Other features

• Programmable prescaler of oscillator

set-up time

• External interrupt : P60

Operating voltage range:

• One security register to prevent intrusion

of user’s OTP memory code

• One configuration register to match

user’s requirement

• OTP version: 2.3V~5.5V Operating voltage range:

Operating temperature range: 0~70°C

Operating frequency range (base on 2 clocks):

• Crystal mode:

Two clocks per instruction cycle

Package type:

DC~20MHz/2clks @ 5V; DC~100ns inst. cycle @ 5V

DC~8MHz/2clks @ 3V; DC~250ns inst. cycle @ 3V

DC~4MHz/2clks @ 2.3V; DC~500ns inst. cycle @ 2.3V

• ERC mode:

DC~4 MHz/2clks @ 5V; DC~500ns inst. cycle @ 5V

DC~4 MHz/2clks @ 3V; DC~500ns inst. cycle @ 3V

DC~4 MHz/2clks @ 2.3V; DC~500ns inst. cycle @ 2.3V

• IRC mode:

• 14-pin DIP 300mil : EM78P153SP/S/J

• 14-pin SOP 150mil : EM78P153SN/S/J

• 10-pin SSOP 150mil: EM78P152SN/S/J

Note: These are all Green products

which do not contain hazardous

substances.

Oscillation mode : 4MHz, 8MHz, 1MHz, 455kHz

Process deviation : Typ. ± 5.5%, Max ± 6%

Temperature deviation : ±10% (0°C~70°C )

The transient point of system frequency between

HXT and LXT is 400kHz.

Product Specification (V1.8) 09.08.2009

(This specification is subject to change without further notice)

• 1

EM78P152/3S

8-Bit Microcontroller with OTP ROM

3 Pin Assignment

(1) 14-Pin DIP/SOP

(2) 10-Pin SSOP

1

2

3

4

5

6

7

P51

P52

P50

P67

14

13

12

11

10

9

1

10

9

P66

P60//INT

P61

P53

Vss

2

3

4

5

P62/TCC

Vdd

Vss

P67

P66

Vdd

P63//RST

P64/OSCO

P65/OSCI

8

7

6

P65/OSCI

P64/OSCO

P63//RST

P60//INT

P61

8

P62/TCC

Figure 3-2 EM78P152SN/S/J

Figure 3-1 EM78P153SP/N/S/J

2 •

Product Specification (V1.8) 09.08.2009

(This specification is subject to change without further notice)

EM78P152/3S

8-Bit Microcontroller with OTP ROM

4 Pin Description

4.1 EM78P153S

Symbol

Pin No. Type

Function

General purpose input/output pin

Pull-high open-drain

Wake up from sleep mode when the status of the pin

changes.

P66, P67

2, 3

I/O

General purpose input/output pin

External clock signal input

Input pin of XT oscillator

Pull-high open-drain

P65/OSCI

5

I/O

Wake up from sleep mode when the status of the pin

changes.

General purpose input/output pin

External clock signal input

Input pin of XT oscillator

Pull-high open-drain

Wake up from sleep mode when the status of the pin

changes.

P64/OSCO

6

7

I/O

P63 is input pin only

Internal Pull-high is on if defined as /RESET.

If set as /RESET and remains at logic low, the device will be

reset.

P63//RESET

I

Wake-up from sleep mode when pin status changes.

Voltage on /RESET must not exceed Vdd during normal

mode.

General purpose input/output pin

External Timer/Counter input

Pull-high/Pull-down open-drain

Wake up from sleep mode when the status of the pin

changes.

P62/TCC

P61

8

9

I/O

General purpose input/output pin

Pull-high/Pull-down open-drain

Wake up from sleep mode when the status of the pin

changes.

Schmitt Trigger input during programming mode.

General purpose input/output pin

Pull-high/Pull-down open-drain

Wake up from sleep mode when the status of the pin

changes.

Schmitt Trigger input during programming mode.

External interrupt pin triggered by a falling edge.

P60/INT

10

I/O

General purpose input/output pin

Pull-down

1,

13~14

P50, P51~P52

P53

12

4

I/O

–

General purpose input/output pin

Power supply

VDD

VSS

11

–

Ground

Product Specification (V1.8) 09.08.2009

(This specification is subject to change without further notice)

• 3

EM78P152/3S

8-Bit Microcontroller with OTP ROM

4.2 EM78P152S

Symbol

Pin No. Type

Function

General purpose input/output pin

Pull-high open-drain

P66, P67

4, 3

I/O

Wake up from sleep mode when the status of the pin

changes.

General purpose input/output pin

External clock signal input

Input pin of XT oscillator

Pull-high open-drain

P65/OSCI

6

I/O

Wake up from sleep mode when the status of the pin

changes.

General purpose input/output pin

External clock signal input

Input pin of XT oscillator

Pull-high open-drain

P64/OSCO

7

I/O

Wake up from sleep mode when the status of the pin

changes.

P63 is input pin only

Internal Pull-high is on if defined as /RESET.

If set as /RESET and remains at logic low, the device will be

reset.

P63//RESET

8

I

Wake-up from sleep mode when pin status changes

Voltage on /RESET must not exceed Vdd during normal

mode.

General purpose input/output pin

External Timer/Counter input

Pull-high/Pull-down open-drain

P62/TCC

9

I/O

Wake up from sleep mode when the status of the pin

changes.

General purpose input/output pin

Pull-high/Pull-down open-drain

P61

10

Wake up from sleep mode when the status of the pin

changes.

Schmitt Trigger input during programming mode.

General purpose input/output pin

Pull-high/Pull-down open-drain

Wake up from sleep mode when the status of the pin

changes.

P60/INT

1

I/O

Schmitt Trigger input during programming mode.

External interrupt pin triggered by a falling edge.

VDD

VSS

5

2

–

Power supply

Ground

4 •

Product Specification (V1.8) 09.08.2009

(This specification is subject to change without further notice)

EM78P152/3S

8-Bit Microcontroller with OTP ROM

5 Functional Description

OSCO

OSCI

/RESET

TCC

/INT

WDT Timer

Prescaler

Oscillator/Timing

Control

ROM

R2

Stack

ALU

Interrupt

Controller

Instruction

Register

Built-in

OSC

RAM

R4

R3

R1 (TCC)

Instruction

Decoder

ACC

DATA & CONTROL BUS

P60

P61

P62/TCC

IOC6

R6

IOC5

R6

P50

I/O

Port 6

I/O

P63//REST

P64/OSCO

P65/OSCI

P66

P51

P52

P53

Port 5

P67

Figure 5-1 EM78P153S Functional Block Diagram

5.1 Operational Registers

5.1.1 R0 (Indirect Addressing Register)

R0 is not a physically implemented register. It is used as an indirect addressing

pointer. Any instruction using R0 as a pointer actually accesses data pointed by the

RAM Select Register (R4).

5.1.2 R1 (Timer Clock /Counter)

Incremented by an external signal edge, which is defined by TE bit (CONT-4)

through the TCC pin, or by the instruction cycle clock.

Writable and readable as any other registers.

Defined by resetting PAB (CONT-3).

The prescaler is assigned to TCC, if the PAB bit (CONT-3) is reset.

The contents of the prescaler counter will be cleared only when the TCC register is

written with a value.

Product Specification (V1.8) 09.08.2009

(This specification is subject to change without further notice)

• 5

EM78P152/3S

8-Bit Microcontroller with OTP ROM

5.1.3 R2 (Program Counter and Stack)

Depending on the device type, R2 and hardware stack are 10-bit wide. The

structure is depicted in the following figure.

000H

008H

Reset Vector

Interrupt Vector

PC (A9 ~ A0)

On-chip Program

Memory

Stack Level 1

Stack Level 2

Stack Level 3

Stack Level 4

Stack Level 5

3FFH

Figure 5-2 Program Counter Organization

The configuration structure generates 1024×13 bits on-chip OTP ROM addresses

to the relative programming instruction codes. One program page is 1024 words

long.

R2 is set as all "0" when under RESET condition.

"JMP" instruction allows direct loading of the lower 10 program counter bits. Thus,

"JMP" allows PC to go to any location within a page.

"CALL" instruction loads the lower 10 bits of the PC, and then PC+1 are pushed

onto the stack. Thus, the subroutine entry address can be located anywhere

within a page.

"RET" ("RETLk", "RETI") instruction loads the program counter with the contents

of the top-level stack.

"ADD R2, A" allows a relative address to be added to the current PC, and the ninth

and tenth bits of the PC won’t be changed.

"MOV R2, A" allows loading of an address from the "A" register to the lower 8 bits

of the PC, and the ninth and tenth bits (A8 ~ A9) of the PC will remain unchanged.

Any instruction written to R2 (e.g. “ADD R2,A”, "MOV R2, A", "BC R2, 6",⋅⋅⋅⋅⋅) will

cause the ninth bit and the tenth bit (A8 ~ A9) of the PC to be cleared. Hence, the

computed jump is limited to the first 256 locations of a page.

All instructions are single instruction cycle (fclk/2 or fclk/4) except for instructions

that would change the contents of R2. Such instructions will need one more

instruction cycle.

6 •

Product Specification (V1.8) 09.08.2009

(This specification is subject to change without further notice)

EM78P152/3S

8-Bit Microcontroller with OTP ROM

The Data Memory Configuration is as follows:

Address

R PAGE Registers

(IAR)

IOC PAGE Registers

00

01

02

03

04

05

06

07

08

09

0A

0B

0C

0D

0E

0F

R0

R1

R2

R3

R4

R5

R6

Reserve

CONT

Reserve

IOC5

(TCC)

(Control Register)

(PC)

(Status)

(RSR)

(Port 5)

(Port 6)

(I/O Port Control Register)

IOC6

Reserve

IOCB

(Pull-down Register)

IOCC

(Open-drain Control)

IOCD

(Pull-high Control Register)

(WDT Control Register)

(Interrupt Mask Register)

IOCE

RF

(Interrupt Status)

IOCF

10

:

General Registers

2F

Figure 5-3 Data Memory Configuration

5.1.4 R3 (Status Register)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

RST

GP1

GP0

T

P

Z

DC

C

Bit 7 (RST): Bit for reset type

0 : Set to 0 if the device wakes up from other reset type

1 : Set to 1 if the device wakes up from sleep mode on a pin change

Bits 6 ~5 (GP1 ~ GP0): General-purpose read/write bits

Bit 4 (T):

Bit 3 (P):

Bit 2 (Z):

Time-out bit

Set to “1” with the "SLEP" and "WDTC" commands, or during power up;

and reset to “0” by WDT time-out.

Power down bit

Set to “1” during power on or by a "WDTC" command; and reset to “0” by

a "SLEP" command.

Zero flag

Set to "1" if the result of an arithmetic or logic operation is zero.

Bit 1 (DC): Auxiliary carry flag

Bit 0 (C): Carry flag

Product Specification (V1.8) 09.08.2009

(This specification is subject to change without further notice)

• 7

EM78P152/3S

8-Bit Microcontroller with OTP ROM

5.1.5 R4 (RAM Select Register)

Bits 7 ~ 6 are general-purpose read/write bits.

See the Data Memory Configuration in Figure 5-3.

5.1.6 R5 ~ R6 (Port 5 ~ Port 6)

R5 and R6 are I/O registers.

Only the lower 4 bits of R5 are available.

The upper 4 bits of R5 are fixed to 0.

P63 is input only.

5.1.7 RF (Interrupt Status Register)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

-

EXIF

ICIF

TCIF

Note: “ 1 ” means with interrupt request

“ 0 ” means no interrupt occurs

Bits 7 ~ 3: Not used.

Bit 2 (EXIF): External Interrupt Flag. Set by a falling edge on /INT pin, reset by

software.

Bit 1 (ICIF): Port 6 input status changed interrupt flag. Set when Port 6 input changes,

reset by software.

Bit 0 (TCIF): TCC Overflow Interrupt Flag. Set when TCC overflows, reset by

software.

RF can be cleared by instruction but cannot be set.

IOCF is the interrupt mask register.

NOTE

The result of reading RF is the "logic AND" of RF and IOCF.

5.1.8 R10 ~ R2F

These are all 8-bit general-purpose registers.

8 •

Product Specification (V1.8) 09.08.2009

(This specification is subject to change without further notice)

EM78P152/3S

8-Bit Microcontroller with OTP ROM

5.2 Special Function Registers

5.2.1 A (Accumulator)

Internal data transfer operation, or instruction operand holding usually involves the

temporary storage function of the Accumulator, which is not an addressable register.

5.2.2 CONT (Control Register)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

-

/INT

TS

TE

PAB

PSR2

PSR1

PSR0

Bit 7:

Not used

Bit 6 (/INT): Interrupt enable flag

0 : masked by DISI or hardware interrupt

1 : enabled by ENI/RETI instructions

Bit 5 (TS): TCC signal source

0 : internal instruction cycle clock, P62 is a bidirectional I/O pin

1 : transition on TCC pin

Bit 4 (TE): TCC Signal Edge

0 : increment if the transition from low to high takes place on TCC pin

1 : increment if the transition from high to low takes place on TCC pin

Bit 3 (PAB): Prescaler Assigned Bit

0 : TCC

1 : WDT

Bit 2 ~ Bit 0 (PSR2 ~ PSR0) TCC/WDT prescaler bits

PSR2

PSR1

PSR0

TCC Rate

1:2

WDT Rate

1:1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1:4

1:2

1:8

1:4

1:16

1:8

1:32

1:16

1:32

1:64

1:128

1:64

1:128

1:256

The CONT register is both readable and writable.

Product Specification (V1.8) 09.08.2009

(This specification is subject to change without further notice)

• 9

EM78P152/3S

8-Bit Microcontroller with OTP ROM

5.2.3 IOC5 ~ IOC6 (I/O Port Control Register)

0 : defines the relative I/O pin as output

1 : puts the relative I/O pin into high impedance

Only the lower 4 bits of IOC5 are available to be defined.

IOC5 and IOC6 registers are both readable and writable.

5.2.4 IOCB (Pull-down Control Register)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

-

/PD6

/PD5

/PD4

-

/PD2

/PD1

/PD0

Bit 7:

Not used

0 : Enable internal pull-down

1 : Disable internal pull-down

Bit 6 (/PD6): Control bit used to enable pull-down of the P62 pin.

Bit 5 (/PD5): Control bit used to enable pull-down of the P61 pin.

Bit 4 (/PD4): Control bit used to enable pull-down of the P60 pin.

Bit 3:

Not used

Bit 2 (/PD2): Control bit used to enable pull-down of the P52 pin.

Bit 1 (/PD1): Control bit used to enable pull-down of the P51 pin.

Bit 0 (/PD0): Control bit used to enable pull-down of the P50 pin.

The IOCB Register is both readable and writable.

5.2.5 IOCC (Open-drain Control Register)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

OD7

OD6

OD5

OD4

-

OD2

OD1

OD0

Bit 7 (OD7): Control bit used to enable open-drain of the P67 pin.

0 : Disable open-drain output

1 : Enable open-drain output

Bit 6 (OD6): Control bit used to enable open-drain of the P66 pin.

Bit 5 (OD5): Control bit used to enable open-drain of the P65 pin.

Bit 4 (OD4): Control bit used to enable open-drain of the P64 pin.

Bits 3:

Not used

Bit 2 (OD2): Control bit used to enable open-drain of the P62 pin.

Bit 1 (OD1): Control bit used to enable open-drain of the P61 pin.

Bit 0 (OD0): Control bit used to enable open-drain of the P60 pin.

The IOCC Register is both readable and writable.

10 •

Product Specification (V1.8) 09.08.2009

(This specification is subject to change without further notice)

EM78P152/3S

8-Bit Microcontroller with OTP ROM

5.2.6 IOCD (Pull-high Control Register)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

/PH7

/PH6

/PH5

/PH4

-

/PH2

/PH1

/PH0

Bit 7 (/PH7): Control bit is used to enable pull-high of the P67 pin.

0 : Enable internal pull-high

1 : Disable internal pull-high

Bit 6 (/PH6): Control bit used to enable pull-high of the P66 pin.

Bit 5 (/PH5): Control bit used to enable pull-high of the P65 pin.

Bit 4 (/PH4): Control bit used to enable pull-high of the P64 pin.

Bits 3:

Not used

Bit 2 (/PH2): Control bit used to enable pull-high of the P62 pin.

Bit 1 (/PH1): Control bit used to enable pull-high of the P61 pin.

Bit 0 (/PH0): Control bit used to enable pull-high of the P60 pin.

The IOCD Register is both readable and writable.

5.2.7 IOCE (WDT Control Register)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

WDTE

EIS

-

Bit 7 (WDTE): Control bit used to enable the Watchdog timer.

0 : Disable WDT

1 : Enable WDT

Bit 6 (EIS): Control bit is used to define the function of P60 (/INT) pin.

0 : P60, bidirectional I/O pin.

1 : /INT, external interrupt pin. In this case, the I/O control bit of P60

(Bit 0 of IOC6) must be set to "1."

When EIS is "0," the path of /INT is masked. When EIS is "1," the status

of /INT pin can also be read by way of reading Port 6 (R6). See Figure

5-6 under Section 5.4 for reference.

EIS is both readable and writable.

WDTE is both readable and writable.

Not used

Bits 5~ 0:

Product Specification (V1.8) 09.08.2009

(This specification is subject to change without further notice)

• 11

EM78P152/3S

8-Bit Microcontroller with OTP ROM

5.2.8 IOCF (Interrupt Mask Register)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

-

EXIE

ICIE

TCIE

Bits 7~3:

Not used

Individual interrupt is enabled by setting its associated control bit in the

IOCF to "1".

Global interrupt is enabled by the ENI instruction and is disabled by the

DISI instruction. Refer to Figure 9.

Bit 2 (EXIE): EXIF interrupt enable bit

0 : disable EXIF interrupt

1 : enable EXIF interrupt

Bit 1 (ICIE): ICIF interrupt enable bit

0 : disable ICIF interrupt

1 : enable ICIF interrupt

Bit 0 (TCIE): TCIF interrupt enable bit

0 : disable TCIF interrupt

1 : enable TCIF interrupt

The IOCF register is both readable and writable.

5.3 TCC/WDT and Prescaler

There is an 8-bit counter available as prescaler for the TCC or WDT. The prescaler is

available for the TCC only or the WDT only at the same time and the PAB bit of the

CONT register is used to determine the prescaler assignment. The PSR0~PSR2 bits

determine the ratio. The prescaler is cleared each time the instruction is written to TCC

under TCC mode. The WDT and prescaler, when assigned to WDT mode, are cleared

by the “WDTC” or “SLEP” instructions. Figure 5-4 depicts the circuit diagram of

TCC/WDT.

R1 (TCC) is an 8-bit timer/counter. The TCC clock source can be internal or

external clock input (edge selectable from TCC pin). If the TCC signal source is

from an internal clock, TCC will be incremented by 1 at every instruction cycle

(without prescaler). Referring to Figure 5-4, CLK=Fosc/2 or CLK=Fosc/4,

depends on the Code Option bit CLK. CLK=Fosc/2 is used if CLK bit is "0", and

CLK=Fosc/4 is used if CLK bit is "1". If the TCC signal source is from an external

clock input, TCC is incremented by 1 at every falling edge or rising edge of the

TCC pin.

The watchdog timer is a free running on-chip RC oscillator. The WDT will keep

running even when the oscillator driver has been turned off (i.e. in sleep mode).

During normal operation or sleep mode, a WDT time-out (if enabled) will cause the

device to reset. The WDT can be enabled or disabled any time during normal

mode by software programming. Refer to WDTE bit of the IOCE register. Without

prescaler, the WDT time-out period is approximately 18 ms¹(default).

¹Note: Vdd = 5V, set up time period = 16.5ms ± 30%

Vdd = 3V, set up time period = 18ms ± 30%

12 •

Product Specification (V1.8) 09.08.2009

(This specification is subject to change without further notice)

EM78P152/3S

8-Bit Microcontroller with OTP ROM

5.4 I/O Ports

The I/O registers, both Port 5 and Port 6, are bidirectional tri-state I/O ports. Port 6 can

be pulled-high internally by software except P63. In addition, Port 6 can also have

open-drain output by software except P63. Input status changed interrupt (or wake-up)

function is available from Port 6. P50 ~ P52 and P60 ~ P62 pins can be pulled-down by

software. Each I/O pin can be defined as "input" or "output" pin by the I/O control

register (IOC5 ~ IOC6) except P63. The I/O registers and I/O control registers are both

readable and writable. The I/O interface circuits for Port 5 and Port 6 are shown in

Figure 5-5, Figure 5-6 and Figure 5-7 respectively.

Data Bus

CLK (Fosc/2 or Fosc/4)

0

1

M

U

X

M

U

X

TCC

SYNC

2 cycles

TCC (R1)

0

1

TE

TS

PAB

TCC Overflow Interrupt

0

1

M

U

X

8-bit Counter

WDT

PSR0~PSR2

PAB

8-to-1 MUX

PAB

0

1

WDTE

(in IOCE)

MUX

WDT Time Out

Figure 5-4 TCC and WDT Block Diagram

Product Specification (V1.8) 09.08.2009

(This specification is subject to change without further notice)

• 13

EM78P152/3S

8-Bit Microcontroller with OTP ROM

PCRD

P

Q

R

D

PCWR

PDWR

CLK

_

C

Q

L

P

R

IOD

Port

Q

D

CLK

_

Q

C

L

PDRD

0

1

M

U

X

Note: Pull-down is not shown in the figure.

Figure 5-5 I/O Port and I/O Control Register Circuit for Port 5

PC RD

P

Q

_

Q

D

R

PC W R

PD W R

C LK

C

L

IO D

P

Q

_

Q

Port

D

R

C LK

Bit 6 of

IO C E

C

L

0

1

P

M

U

X

D

Q

_

Q

R

C LK

C

L

T10

PD RD

P

R

D

Q

C LK

C

_

Q

L

Note: Pull-high (down) and open-drain are not shown in the figure.

Figure 5-6 I/O Port and I/O Control Register Circuit for P60 (/INT)

14 •

Product Specification (V1.8) 09.08.2009

(This specification is subject to change without further notice)

EM78P152/3S

8-Bit Microcontroller with OTP ROM

P

Q

_

Q

D

CLK

R

PCWR

C

L

IOD

P

R

Q

D

PORT

PDWR

_

Q

CLK

C

L

0

1

M

U

X

TIN

PDRD

P

R

D

Q

CLK

_

Q

C

L

Note: Pull-high (down) and open-drain are not shown in the figure.

Figure 5-7 I/O Port and I/O Control Register Circuit for P61~P67

ICIE

P

Q

D

R

CLK

Interrupt

_

Q

C

L

ICIF

ENI Instruction

P

R

P60

D

Q

P61

P62

P63

P

CLK

Q

D

R

_

Q

C

CLK

L

_

Q

P64

P65

P66

C

L

P67

DISI Instruction

Interrupt

(Wake-up from

SLEEP)

/SLEP

Next Instruction

(Wake-up from

SLEEP)

Figure 5-8 Block Diagram of I/O Port 6 with input change interrupt/wake-up

Product Specification (V1.8) 09.08.2009

(This specification is subject to change without further notice)

• 15

EM78P152/3S

8-Bit Microcontroller with OTP ROM

Table 5-1 Usage of Port 6 Input Change Wake-up/Interrupt Function

Usage of Port 6 Input Status Change Wake-up/Interrupt

(I) Wake-up from Port 6 Input Status Change

(II) Port 6 Input Status Change Interrupt

1. Read I/O Port 6 (MOV R6,R6)

2. Execute “ENI”

(a) Before Sleep

1. Disable WDT

2. Read I/O Port 6 (MOV R6,R6)

3. Execute "ENI" or "DISI"

4. Enable interrupt (Set IOCF.1)

5. Execute "SLEP" instruction

(b) After Wake-up

3. Enable interrupt (Set IOCF.1)

4. IF Port 6 change (interrupt)

→ Interrupt vector (008H)

1. IF "ENI" → Interrupt vector (008H)

2. IF "DISI" → Next instruction

5.5 Reset and Wake-up

5.5.1 Reset

A Reset is initiated by one of the following events:

1) Power-on reset

2) /RESET pin input "low"

3) WDT time-out (if enabled)

The device is kept under reset condition for a period of approximately 18ms²(one

oscillator start-up timer period) after a reset is detected. Once a Reset occurs, the

following functions are performed:

The oscillator is running, or will be started.

The Program Counter (R2) is set to all "0."

All I/O port pins are configured as input mode (high-impedance state)

The Watchdog timer and prescaler are cleared.

When power is switched on, the upper 3 bits of R3 are cleared.

The bits of the CONT register are set to all "1" except for Bit 6 (INT flag).

The bits of the IOCB register are set to all "1."

The IOCC register is cleared.

The bits of the IOCD register are set to all "1."

Bit 7 of the IOCE register is set to "1," and Bits 4 and 6 are cleared.

Bits 0 ~ 2 of RF and Bits 0 ~ 2 of IOCF registers are cleared.

2

Vdd = 5V, set up time period = 16.8ms ± 30%

Vdd = 3V, set up time period = 18ms ± 30%

16 •

Product Specification (V1.8) 09.08.2009

(This specification is subject to change without further notice)

EM78P152/3S

8-Bit Microcontroller with OTP ROM

The Sleep (power down) mode is asserted by executing the “SLEP” instruction. While

entering Sleep mode, WDT (if enabled) is cleared but keeps on running. The controller

can be awakened by:

1) External reset input on /RESET pin

2) WDT time-out (if enabled)

3) Port 6 Input Status changed (if enabled)

The first two cases will cause the EM78P152/3S to reset. The T and P flags of R3 are

used to determine the source of the reset (wake-up). The last case is considered the

continuation of program execution and the global interrupt ("ENI" or "DISI" being

executed) determines whether or not the controller branches to the interrupt vector

following a wake-up. If ENI is executed before SLEP, the instruction will begin to

execute from Address 008H after wake-up. If DISI is executed before SLEP, the

operation will restart from the succeeding instruction right next to SLEP after a

wake-up.

Only one of Cases 2 and 3 can be enabled before going into the Sleep mode. That is,

[a] if Port 6 Input Status Change Interrupt is enabled before SLEP, WDT must be

disabled by software. However, the WDT bit in the option register remains

enabled. Hence, the EM78P152/3S can be awakened only by Case 1 or Case 3.

[b] if WDT is enabled before SLEP, Port 6 Input Status Change Interrupt must be

disabled. Hence, the EM78P152/3S can be awakened only by Case 1 or Case 2.

Refer to Section 5.6, Interrupt for further details.

If Port 6 Input Status Change Interrupt is used to wake-up the EM78P152/3S (Case [a]

above), the following instructions must be executed before SLEP:

MOV A, @xxxx1110b

; Select the WDT prescaler, it must be

; set over 1:1

CONTW

WDTC

; Clear WDT and prescaler

; Disable WDT

MOV A, @0xxxxxxxb

IOW RE

MOV R6, R6

MOV A, @00000x1xb

IOW RF

; Read Port 6

; Enable Port 6 input change interrupt

ENI (or DISI)

SLEP

; Enable (or disable) global interrupt

; Sleep

Product Specification (V1.8) 09.08.2009

(This specification is subject to change without further notice)

• 17

EM78P152/3S

8-Bit Microcontroller with OTP ROM

NOTE

1. After waking up from sleep mode, WDT is automatically enabled. The WDT

enable/disable operation after waking up from sleep mode should be appropriately

defined in the software.

2. To avoid a reset from occurring when the Port 6 Input Status Changed Interrupt

enters into interrupt vector or is used to wake-up the MCU, the WDT prescaler must

be set above the 1:1 ratio.

5.5.2 Summary of Registers Initialized Values

Address

Name

Reset Type

Bit Name

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

C53 C52 C51 C50

×

0

×

0

×

0

×

0

Power-on

1

P

1

P

1

P

1

P

N/A

IOC5

/RESET and WDT

Wake-up from Pin Change

Bit Name

C67 C66 C65 C64 C63 C62 C61 C60

Power-on

1

P

×

1

P

1

P

×

1

P

1

N/A

IOC6

P5

/RESET and WDT

Wake-up from Pin Change

Bit Name

P

×

1

P

×

1

P

P53

1

P52

1

P51

1

P50

1

Power-on

0×05

0×06

N/A

/RESET and WDT

Wake-up from Pin Change

Bit Name

P

P67

1

P

P66

1

P

P65 P64

P63

1

P62

1

P61

1

P60

1

Power-on

1

P

TS

1

P

TE

1

P6

/RESET and WDT

Wake-up from Pin Change

Bit Name

P

×

P

/INT

0

P

PAB PSR2 PSR1 PSR0

Power-on

1

P

-

1

P

-

1

P

-

1

P

-

CONT

R0 (IAR)

R1 (TCC)

R2 (PC)

/RESET and WDT

Wake-up from Pin Change

Bit Name

1

0

1

P

-

0

P

-

P

-

Power-on

U

P

-

U

P

-

U

P

-

U

P

-

U

P

-

U

P

-

U

P

-

U

P

-

0×00

0×01

0×02

/RESET and WDT

Wake-up from Pin Change

Bit Name

Power-on

0

P

-

0

P

-

0

P

-

0

P

-

/RESET and WDT

Wake-up from Pin Change

Bit Name

0

P

-

P

-

P

-

P

-

Power-on

0

N

0

P

0

P

0

P

/RESET and WDT

Wake-up from Pin Change

0

P

18 •

Product Specification (V1.8) 09.08.2009

(This specification is subject to change without further notice)

EM78P152/3S

8-Bit Microcontroller with OTP ROM

Address

Name

Reset Type

Bit Name

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

RST GP1 GP0

T

1

*

P

1

*

Z

U

P

-

DC

U

P

C

U

P

-

Power-on

0

1

0

P

0

P

-

R3 (SR)

0×03

/RESET and WDT

Wake-up from Pin Change

Bit Name

P

*

-

*

-

GP1 GP0

-

Power-on

U

P

×

0

×

1

P

U

P

×

0

U

P

×

0

U

P

×

0

U

P

×

0

x

U

P

U

P

U

P

R4 (RSR)

RF(ISR)

IOCB

0×04

0×0F

0×0B

0×0C

0×0D

0×0E

0×0F

/RESET and WDT

Wake-up from Pin Change

Bit Name

P

EXIF ICIF TCIF

Power-on

0

/RESET and WDT

Wake-up from Pin Change

Bit Name

P

N

P

/PD6 /PD5 /PD4

/PD2 /PD1 /PD0

Power-on

1

P

1

P

×

0

P

×

1

P

×

1

×

1

-

1

/RESET and WDT

Wake-up from Pin Change

Bit Name

P

OD7 OD6 OD5 OD4

OD2 OD1 OD0

Power-on

0

P

0

P

0

IOCC

/RESET and WDT

Wake-up from Pin Change

Bit Name

P

/PH7 /PH6 /PH5 /PH4

/PH2 /PH1 /PH0

Power-on

1

P

1

P

×

1

×

1

-

1

P

×

1

×

1

-

1

P

×

1

P

×

1

P

×

1

IOCD

/RESET and WDT

Wake-up from Pin Change

Bit Name

P

WDTE EIS

Power-on

1

×

1

-

0

P

×

1

-

IOCE

/RESET and WDT

Wake-up from Pin Change

Bit Name

EXIE ICIE TCIE

Power-on

0

P

-

0

P

-

0

P

-

IOCF

/RESET and WDT

Wake-up from Pin Change

Bit Name

Power-on

U

P

U

P

U

P

U

P

U

P

U

P

U

P

U

P

0×10~

0×2F

R10~R2F

/RESET and WDT

Wake-up from Pin Change

Legend: ×: Not used

U: Unknown or don’t care P: Previous value before reset

* Refer to tables provided in the next section (Section 5.5.3).

Product Specification (V1.8) 09.08.2009

(This specification is subject to change without further notice)

• 19

EM78P152/3S

8-Bit Microcontroller with OTP ROM

5.5.3 Status of RST, T, and P of the Status Register

A Reset condition is initiated by the following events

1) A power-on condition

2) A high-low-high pulse on /RESET pin

3) Watchdog timer time-out

The values of T and P listed in the table below are used to check how the processor

wakes up.

Table 5-2 Values of RST, T, and P after a Reset

Reset Type

RST

T

P

1

Power on

0

1

/RESET during Operating mode

/RESET wake-up during Sleep mode

WDT during Operating mode

*P

1

*P

0

*P

0

WDT wake-up during Sleep mode

Wake-up on pin change during Sleep mode

0

1

0

* P: Previous status before reset

The following table shows the events that may affect the status of T and P.

Table 5-3 Status of T and P Being Affected by Events

Event

RST

0

T

P

1

Power on

1

WDTC instruction

WDT time-out

SLEP instruction

*P

0

1

0

1

*P

0

*P

1

Wake-up on pin change during Sleep mode

0

* P: Previous status before reset

VDD

D

CLK

Q

CLK

Oscillator

CLR

Power-on

Reset

Voltage

Detector

WDTE

WDT

Setup Time

RESET

Timeout

/RESET

Figure 5-9 Controller Reset Block Diagram

20 •

Product Specification (V1.8) 09.08.2009

(This specification is subject to change without further notice)

EM78P152/3S

8-Bit Microcontroller with OTP ROM

5.6 Interrupt

The EM78P152/3S has three falling-edge interrupts as listed herewith:

1) TCC overflow interrupt

2) Port 6 Input Status Change Interrupt

3) External interrupt [(P60, /INT) pin]

Before the Port 6 Input Status Changed Interrupt is enabled, reading Port 6 (e.g. "MOV

R6,R6") is necessary. Each pin of Port 6 will have this feature if its status changes.

Any pin configured as output or P60 pin configured as /INT, is excluded from this

function. The Port 6 Input Status Changed Interrupt can wake up the EM78P152/3S

from Sleep mode if Port 6 is enabled prior to going into Sleep mode by executing SLEP

instruction. When the chip wakes-up, the controller will continue to execute the

program in-line if the global interrupt is disabled. If the global interrupt is enabled, it will

branch to the interrupt Vector 008H.

RF is the interrupt status register that records the interrupt requests in the relative

flags/bits. IOCF is an interrupt mask register. The global interrupt is enabled by the

ENI instruction and is disabled by the DISI instruction. When one of the interrupts

(enabled) occurs, the next instruction will be fetched from Address 008H. Once in the

interrupt service routine, the source of an interrupt can be determined by polling the flag

bits in RF. The interrupt flag bit must be cleared by instructions before leaving the

interrupt service routine before interrupts are enabled to avoid recursive interrupts.

The flag (except ICIF bit) in the Interrupt Status Register (RF) is set regardless of the

status of its mask bit or the execution of ENI. Note that the outcome of RF will be the

logic AND of RF and IOCF (refer to Figure 5-10). The RETI instruction ends the

interrupt routine and enables the global interrupt (the execution of ENI).

When an interrupt is generated by the INT instruction (enabled), the next instruction will

be fetched from Address 001H.

VCC

P

IRQ n

IRQ m

D

Q

_

Q

R

/IRQn

CLK

INT

C

RFRD

L

RF

ENI/DISI

P

IO D

Q

_

Q

D

R

CLK

C

L

IO CFW R

IO CF

/RESET

IO CFRD

RFW R

Figure 5-10 Interrupt Input Circuit

Product Specification (V1.8) 09.08.2009

(This specification is subject to change without further notice)

• 21

EM78P152/3S

8-Bit Microcontroller with OTP ROM

5.7 Oscillator

5.7.1 Oscillator Modes

The EM78P152/3S can be operated in four different oscillator modes, such as External

RC oscillator mode (ERC), Internal RC oscillator mode (IRC), High Crystal oscillator

mode (HXT), and Low Crystal oscillator mode (LXT). The desired mode can be

selected by programming OSC1 and OSC2 in the Code Option register. The Table

below describes how these four oscillator modes are defined.

Table 5-4 Oscillator Modes Defined by OSC

Mode

OSC1

OSC2

IRC (Internal RC oscillator mode)

ERC (External RC oscillator mode)

HXT (High Crystal oscillator mode)

LXT(Low Crystal oscillator mode)

1

0

1

0

1

0

Note: The transient point of system frequency between HXT and LXY is 400kHz.

The maximum operational frequency of the crystal/resonator under different VDD is

listed below.

Table 5-5 Summary of Maximum Operating Speeds

Conditions

VDD

Max Freq. (MHz)

2.3

4.0

Two cycles with two clocks

3.0

5.0

8.0

20.0

5.7.2 Crystal Oscillator/Ceramic Resonators (Crystal)

The EM78P152/3S can be driven by an external clock signal through the OSCI pin as

shown in the following figure.

OSCI

Ext. Clock

OSCO

EM78P153S

Figure 5-11 Circuit for External Clock Input

22 •

Product Specification (V1.8) 09.08.2009

(This specification is subject to change without further notice)

EM78P152/3S

8-Bit Microcontroller with OTP ROM

In most applications, pin OSCI and pin OSCO can be connected with a crystal or

ceramic resonator to generate oscillation. Figure 5-12 depicts such circuit. The same

thing applies whether it is in the HXT mode or in the LXT mode.

In Figure 5-12-1, when the connected resonator in OSCI and OSCO is used in

applications, the 1 MΩ R1 needs to be shunt with resonator.

C1

OSCI

EM78P153S

Crystal

OSCO

C2

RS

Figure 5-12 Circuit for Crystal/Resonator

C1

OSCI

Resonator

EM78P153A

OSCO

R1

C2

Figure 5-12-1 Circuit for Crystal/Resonator

The following table provides the recommended values of C1 and C2. Since each

resonator has its own attribute, refer to its specification for appropriate values of C1 and

C2. RS, a serial resistor, may be necessary for AT strip cut crystal or low frequency

mode.

Product Specification (V1.8) 09.08.2009

(This specification is subject to change without further notice)

• 23

EM78P152/3S

8-Bit Microcontroller with OTP ROM

Table 5-6 Capacitor Selection Guide for Crystal Oscillator or Ceramic Resonator

Oscillator Type

Frequency Mode Frequency

C1 (pF)

100~150

20~40

10~30

25

C2 (pF)

100~150

20~40

10~30

15

455kHz

Ceramic Resonators

HXT

LXT

2.0 MHz

4.0 MHz

32.768kHz

100kHz

25

200kHz

25

Crystal Oscillator

455kHz

20~40

15~30

15

20~150

15~30

15

1.0 MHz

2.0 MHz

4.0 MHz

HXT

15

Note: The values of capacitors C1 and C2 are for reference only

5.7.3 External RC Oscillator Mode

For some applications that do not require a very precise timing calculation, the RC

oscillator (Figure 5-13) offers a cost-effective oscillator configuration. Nevertheless, it

should be noted that the frequency of the RC oscillator is influenced by the supply

voltage, the values of the resistor (Rext), the capacitor (Cext), and even by the

operation temperature. Moreover, the frequency also changes slightly from one chip to

another due to manufacturing process variations.

In order to maintain a stable system frequency, the values of the Cext should not be

less than 20pF, and that the value of Rext should not be greater than 1 MΩ. If they

cannot be kept in this range, the frequency can be easily affected by noise, humidity,

and leakage.

The smaller the Rext in the RC oscillator is, the faster its frequency will be. On the

contrary, for very low Rext values, for instance, 1 KΩ, the oscillator becomes unstable

because the NMOS cannot discharge the current of the capacitance correctly.

Based on the above reasons, it must be kept in mind that all of the supply voltage, the

operation temperature, the components of the RC oscillator, the package types, the

way the PCB is layout, will affect the system frequency.

Vcc

Rext

OSCI

Cext

EM78P153S

Figure 5-13 External RC Oscillator Mode Circuit

24 •

Product Specification (V1.8) 09.08.2009

(This specification is subject to change without further notice)

EM78P152/3S

8-Bit Microcontroller with OTP ROM

Table 5-7 RC Oscillator Frequencies

Average Fosc

Cext

Rext

5V, 25°C

3V, 25°C

3.3k

5.1k

10k

3.92 MHz

2.67 MHz

1.4 MHz

150kHz

1.4 MHz

940kHz

476kHz

50kHz

3.65 MHz

2.60 MHz

1.40 MHz

156kHz

1.33 MHz

917kHz

480kHz

52kHz

20pF

100k

3.3k

5.1k

10k

100pF

300pF

100k

3.3k

5.1k

10k

595kHz

400kHz

200kHz

20.9kHz

570kHz

384kHz

203kHz

20kHz

100k

1

Note: : Measured based on DIP packages.

²: The values are for design reference only.

³: The frequency drift is ± 30%.

5.7.4 Internal RC Oscillator Mode

EM78P152/3S offers a versatile internal RC mode with default frequency value of

4MHz. The Internal RC oscillator mode has other frequencies (1MHz, 8MHz, &

455kHz) that can be set by Code Option (Word 1), RCM1, and RCM0. All these four

main frequencies can be calibrated by programming the Option Bits CAL0 ~ CAL2.

The table below describes the EM78P152/3S internal RC drift with variation of voltage,

temperature, and process.

°

Table 5-8 Internal RC Drift Rate (Ta=25 C, VDD=5V±5%, VSS=0V)

Drift Rate

Internal RC

Temperature

(0°C~70°C)

Voltage

(2.3V~5.5V)

Process

Total

8 MHz

4 MHz

1 MHz

455kHz

± 3%

± 5%

± 10%

± 5%

± 18%

± 13%

± 18%

± 10%

Note: These are theoretical values provided for reference only. Actual values may vary

depending on the actual process.

Product Specification (V1.8) 09.08.2009

(This specification is subject to change without further notice)

• 25

EM78P152/3S

8-Bit Microcontroller with OTP ROM

5.8 Code Option Register

The EM78P152/3S has a Code Option word that is not a part of the normal program

memory. The option bits cannot be accessed during normal program execution.

Code Option Register and Customer ID Register Arrangement Distribution:

Word 0

Word 1

Word 2

Bit 12 ~ Bit 0

5.8.1 Code Option Register (Word 0)

Word 0

Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

/RESET /ENWDT CLKS OSC1 OCS0

CS

SUT1 SUT0 TYPE RCOUT C2 C1 C0

Bit 12 (/RESET):

Define Pin 7 as a reset pin

0 : /RESET enable

1 : /RESET disable

Watchdog timer enable bit

0 : Enable

Bit 11 (/ENWTD):

1 : Disable

NOTE

This bit must be enabled and the WDTE register (IOCE reg. Bit 6) must be disabled

when Port 6 pin change wake-up function is used.

Bit 10 (CLKS):

Instruction period option bit.

0 : two oscillator periods

1 : four oscillator periods

Refer to the Instruction Set section.

Bit 9 and Bit 8 (OSC1 and OSC0): Oscillator Modes Selection bits.

Table 5-9 Oscillator Modes defined by OSC1 and OSC0

Mode

OSC1

OSC0

IRC (Internal RC oscillator mode)

ERC (External RC oscillator mode)

HXT (High Crystal oscillator mode)

LXT (Low Crystal oscillator mode)

1

0

1

0

1

0

Note: The transient point of system frequency between HXT and LXY is 400kHz.

26 •

Product Specification (V1.8) 09.08.2009

(This specification is subject to change without further notice)

EM78P152/3S

8-Bit Microcontroller with OTP ROM

Bit 7 (CS):

Code Security Bit

0 : Security On

1 : Security Off

Bit 6 and Bit 5 (SUT1 and SUT0): Set-up Time of device bits.

Table 5-10 Set-up Time of Device Programming

SUT1

SUT0

*Set-up Time

18 ms

1

0

1

0

1

0

4.5 ms

288 ms

72 ms

* Theoretical values, for reference only

Bit 4 (Type): Type selection for EM78P152/3S

Type

Series

0

1

EM78P152/3S

×

Bit 3 (RCOUT): Selection bit of Oscillator output or I/O port

RCOUT

Pin Function

P64

0

1

OSCO

Bits 2~ 0 (C2~C 0): Calibrator of internal RC mode Bit 3

C2, C1, C0 must be set to “1” only.

Code Option Register (Word 1)

Word 1

Bit 1

Bit 0

RCM1

RCM0

Bit 1 and Bit 0 (RCM1, RCM0): RC mode selection bits

RCM 1

RCM 0

*Frequency (MHz)

1

0

1

0

1

0

4

8

1

455kHz

* Theoretical values, for reference only

Customer ID Register (Word 2)

Bit 12~Bit 0

XXXXXXXXXXXXX

Bits 12~ 0: Customer’s ID code

Product Specification (V1.8) 09.08.2009

(This specification is subject to change without further notice)

• 27

EM78P152/3S

8-Bit Microcontroller with OTP ROM

5.9 Power-on Considerations

Any microcontroller is not guaranteed to start to operate properly before the power

supply stabilizes at its steady state. Under customer application, when power is OFF,

Vdd must drop to below 1.8V and remains OFF for 10µs before power can be switched

ON again. This way, the EM78P152/3S will reset and operate normally. The extra

external reset circuit will work well if Vdd can rise at very fast speed (50 ms or less).

However, under most cases where critical applications are involved, extra devices are

required to assist in solving the power-up problems.

5.10 Programmable Oscillator Set-up Time

The Option word contains SUT0 and SUT1 which can be used to define the oscillator

set-up time. Theoretically, the range is from 4.5 ms to 72 ms. For most of crystal or

ceramic resonators, the lower the operation frequency, the longer the Set-up time may

be required. Table 12 describes the values of the Oscillator Set-up Time.

5.11 External Power-on Reset Circuits

The circuitry in the figure

implements an external RC

Vdd

to produce the reset pulse.

R

The pulse width (time

constant) should be kept

long enough for Vdd to

reach minimum operation

voltage. This circuit is

used when the power

supply has a slow rise

time.

/RESET

D

EM78P153S

Rin

C

Figure 5-14 External Power-up Reset Circuit

Since the current leakage from the /RESET pin is ± 5 μA, it is recommended that R

should not be greater than 40K. In this way, the /RESET pin voltage is held below 0.2V.

The diode (D) acts as a short circuit at the moment of power down. The capacitor C will

discharge rapidly and fully. Rin, the current-limited resistor, will prevent high current or

ESD (electrostatic discharge) from flowing to pin /RESET.

28 •

Product Specification (V1.8) 09.08.2009

(This specification is subject to change without further notice)

EM78P152/3S

8-Bit Microcontroller with OTP ROM

5.12 Residue-Voltage Protection

When the battery is replaced, the device power (Vdd) is cut off but residue-voltage

remains. The residue-voltage may trip below the minimum Vdd, but not to zero. This

condition may cause a poor power-on reset. The following figures illustrate two

recommended methods on how to build a residue-voltage protection circuit for the

EM78P152/3S.

Vdd

33K

EM78P153S

/RESET

Q1

10K

100K

1N4684

* Figure 5-15 Residue Voltage Protection Circuit 1

Vdd

R1

EM78P153S

/RESET

Q1

R3

R2

* Figure 5-16 Residue Voltage Protection Circuit 2

Note: * Figure 5-15 and Figure 5-16 should be designed with their /RESET pin voltage larger than VIH(min).

Product Specification (V1.8) 09.08.2009

(This specification is subject to change without further notice)

• 29

EM78P152/3S

8-Bit Microcontroller with OTP ROM

5.13 Instruction Set

Each instruction in the instruction set is a 13-bit word divided into an OP code and one

or more operands. Normally, all instructions are executed within one single instruction

cycle (one instruction consists of two oscillator periods), unless the program counter is

changed by instruction "MOV R2,A", "ADD R2,A", or by instructions of arithmetic or

logic operation on R2 (e.g., "SUB R2,A", "BS(C) R2,6", "CLR R2", ⋅⋅⋅⋅). In this case, the

execution takes two instruction cycles.

If for some reasons, the specification of the instruction cycle is not suitable for certain

applications, try modifying the instruction as follows:

A) Modify one instruction cycle to consist of four oscillator periods.

B) "JMP," "CALL," "RET," "RETL," "RETI," or the conditional skip ("JBS," "JBC," "JZ,"

"JZA," "DJZ,” "DJZA") commands which were tested to be true, are executed within

two instruction cycles. The instructions that are written to the program counter also

take two instruction cycles.

Case (A) is selected by the Code Option bit, called CLK. One instruction cycle consists

of two oscillator clocks if CLK is low; and four oscillator clocks if CLK is high.

Note that once the four oscillator periods within one instruction cycle is selected as in

Case (A), the internal clock source to TCC should be CLK=Fosc/4, instead of Fosc/2.

Moreover, the instruction set has the following features:

1) Every bit of any register can be set, cleared, or tested directly.

2) The I/O register can be regarded as general register. That is, the same instruction

can operate on I/O register.

The following symbols are used in the Instruction Set table:

Convention:

R = Register designator that specifies which one of the registers (including operation and general purpose

registers) is to be utilized by the instruction.

Bits 6 and 7 in R4 determine the selected register bank.

b = Bit field designator that selects the value for the bit located in the register R and which affects the

operation.

k = 8 or 10-bit constant or literal value

Binary Instruction

0 0000 0000 0000

0 0000 0000 0001

0 0000 0000 0010

0 0000 0000 0011

0 0000 0000 0100

Hex

0000

Mnemonic

NOP

Operation

No Operation

Status Affected

None

C

0001

0002

0003

0004

DAA

Decimal Adjust A

A → CONT

CONTW

SLEP

None

T, P

0 → WDT, Stop oscillator

0 → WDT

WDTC

30 •

Product Specification (V1.8) 09.08.2009

(This specification is subject to change without further notice)

EM78P152/3S

8-Bit Microcontroller with OTP ROM

(Continuation)

Binary Instruction

0 0000 0000 rrrr

0 0000 0001 0000

0 0000 0001 0001

0 0000 0001 0010

Hex

000r

Mnemonic

IOW R

ENI

Operation

A → IOCR

Status Affected

None ¹

0010

0011

0012

Enable Interrupt

None

DISI

Disable Interrupt

[Top of Stack] → PC

None

RET

None

[Top of Stack] → PC,

Enable Interrupt

0 0000 0001 0011

0013

RETI

None

0 0000 0001 0100

0 0000 0001 rrrr

0 0000 01rr rrrr

0 0000 1000 0000

0 0000 11rr rrrr

0 0001 00rr rrrr

0 0001 01rr rrrr

0 0001 10rr rrrr

0 0001 11rr rrrr

0 0010 00rr rrrr

0 0010 01rr rrrr

0 0010 10rr rrrr

0 0010 11rr rrrr

0 0011 00rr rrrr

0 0011 01rr rrrr

0 0011 10rr rrrr

0 0011 11rr rrrr

0 0100 00rr rrrr

0 0100 01rr rrrr

0 0100 10rr rrrr

0 0100 11rr rrrr

0 0101 00rr rrrr

0 0101 01rr rrrr

0 0101 10rr rrrr

0 0101 11rr rrrr

0014

001r

00rr

0080

00rr

01rr

02rr

03rr

04rr

05rr

CONTR

IOR R

CONT → A

IOCR → A

A → R

None

None ¹

MOV R,A

CLRA

None

0 → A

Z

CLR R

0 → R

Z

SUB A,R

SUB R,A

DECA R

DEC R

R-A → A

Z, C, DC

R-A → R

Z, C, DC

R-1 → A

Z

R-1 → R

Z

OR A,R

OR R,A

AND A,R

AND R,A

XOR A,R

XOR R,A

ADD A,R

ADD R,A

MOV A,R

MOV R,R

COMA R

COM R

INCA R

INC R

A ∨ R → A

A ∨ R → R

A & R → A

A & R → R

A ⊕ R → A

A ⊕ R → R

A + R → A

A + R → R

R → A

Z

Z, C, DC

Z

R → R

Z

/R → A

/R → R

Z

R+1 → A

R+1 → R

R-1 → A, skip if zero

R-1 → R, skip if zero

Z

DJZA R

None

DJZ R

Note: ¹This instruction is applicable to IOC5~IOC6, IOCB ~ IOCF only.

Product Specification (V1.8) 09.08.2009

(This specification is subject to change without further notice)

• 31

EM78P152/3S

8-Bit Microcontroller with OTP ROM

(Continuation)

Binary Instruction

Hex

06rr

Mnemonic

Operation

R(n) → A(n-1),

R(0) → C, C → A(7)

Status Affected

0 0110 00rr rrrr

0 0110 01rr rrrr

0 0110 10rr rrrr

0 0110 11rr rrrr

0 0111 00rr rrrr

RRCA R

C

R(n) → R(n-1),

R(0) → C, C → R(7)

RRC R

C

R(n) → A(n+1),

R(7) → C, C → A(0)

06rr

07rr

RLCA R

RLC R

R(n) → R(n+1),

R(7) → C, C → R(0)

C

R(0-3) → A(4-7),

R(4-7) → A(0-3)

SWAPA R

None

0 0111 01rr rrrr

0 0111 10rr rrrr

0 0111 11rr rrrr

0 100b bbrr rrrr

0 101b bbrr rrrr

0 110b bbrr rrrr

0 111b bbrr rrrr

07rr

0xxx

SWAP R

JZA R

R(0-3) ↔ R(4-7)

R+1 → A, skip if zero

R+1 → R, skip if zero

0 → R(b)

None

None ²

None ³

None

JZ R

BC R,b

BS R,b

JBC R,b

JBS R,b

1 → R(b)

if R(b)=0, skip

if R(b)=1, skip

PC+1 → [SP],

(Page, k) → PC

1 00kk kkkk kkkk

1kkk

CALL k

None

1 01kk kkkk kkkk

1 1000 kkkk kkkk

1 1001 kkkk kkkk

1 1010 kkkk kkkk

1 1011 kkkk kkkk

1kkk

18kk

19kk

1Akk

1Bkk

JMP k

(Page, k) → PC

k → A

None

MOV A,k

OR A,k

AND A,k

XOR A,k

None

A ∨ k → A

A & k → A

A ⊕ k → A

Z

k → A,

[Top of Stack] → PC

1 1100 kkkk kkkk

1 1101 kkkk kkkk

1 1110 0000 0001

1 1111 kkkk kkkk

1Ckk

1Dkk

1E01

1Fkk

RETL k

SUB A,k

INT

None

Z, C,DC

None

k-A → A

PC+1 → [SP],

001H → PC

ADD A,k

k+A → A

Z, C, DC

Note: ²This instruction is not recommended for RF operation.

³This instruction cannot operate under RF.

32 •

Product Specification (V1.8) 09.08.2009

(This specification is subject to change without further notice)

EM78P152/3S

8-Bit Microcontroller with OTP ROM

6 Absolute Maximum Ratings

EM78P152/3S

Items

Rating

Temperature under bias

Storage temperature

Input voltage

0°C

to

70°C

-65°C

-0.3V

150°C

+6.0V

Output voltage

*

Note: These parameters are theoretical values and have not been tested.

7 Electrical Characteristics

7.1 DC Characteristics

Ta=25°C, VDD=5V±5%, VSS=0V

Symbol

Parameter

Crystal: VDD to 2.3V

Condition

Min. Typ. Max. Unit

Two cycles with two clocks DC

−

4.0

8.0

MHz

FXT

Crystal: VDD to 3V

Crystal: VDD to 5V

20.0 MHz

ERC ERC: VDD to 5V

R: 5KΩ, C: 39 pF

VIN = VDD, VSS

Ports 5, 6

F±30% 1500 F±30% kHz

IIL

Input Leakage Current for input pins

−

2.0

−

±1

−

μA

V

VIH1 Input High Voltage (VDD=5V)

VIL1

Input Low Voltage (VDD=5V)

Input High Threshold Voltage

(VDD=5V)

Ports 5, 6

0.8

V

/RESET, TCC

(Schmitt trigger)

/RESET, TCC

(Schmitt trigger)

OSCI

VIHT1

2.0

−

V

VILT1 Input Low Threshold Voltage (VDD=5V)

−

0.8

VIHX1 Clock Input High Voltage (VDD=5V)

VILX1 Clock Input Low Voltage (VDD=5V)

VIH2 Input High Voltage (VDD=3V)

2.5

−

Vdd+0.3

1.0

V

OSCI

Ports 5, 6

1.5

−

VIL2

Input Low Voltage (VDD=3V)

Input High Threshold Voltage

(VDD=3V)

Ports 5, 6

−

0. 4

/RESET, TCC

(Schmitt trigger)

/RESET, TCC

(Schmitt trigger)

OSCI

VIHT2

1.5

−

V

VILT2 Input Low Threshold Voltage (VDD=3V)

−

0.4

VIHX2 Clock Input High Voltage (VDD=3V)

1.5

−

V

VILX2 Clock Input Low Voltage (VDD=3V)

Output High Voltage (Ports 6)

VOH1 (P60~P63, P66~P67 are Schmitt

trigger)

OSCI

−

0.6

IOH = -12 mA

2.4

−

V

Output Low Voltage (P50~P53,

VOL1

IOL = 12 mA

−

0.4

V

P60~P63 P66~P67 are Schmitt trigger)

VOL2 Output Low Voltage (P64, P65)

IOL = 16.0 mA

Pull-high active,

input pin at VSS

Pull-down active,

input pin at VDD

IPH

IPD

Pull-high current

Pull-down current

–50 –100 –240

20 50 120

μA

Product Specification (V1.8) 09.08.2009

(This specification is subject to change without further notice)

• 33

EM78P152/3S

8-Bit Microcontroller with OTP ROM

Symbol

Parameter

Condition

Min. Typ. Max. Unit

All input and I/O pins at VDD,

Output pin floating,

ISB1 Power down current

ISB2 Power down current

-

1

μA

WDT disabled

All input and I/O pins at VDD,

Output pin floating,

10

WDT enabled

/RESET= 'High', Fosc=32kHz

(Crystal type, CLKS="0"),

Output pin floating,

Operating supply current

ICC1

15

-

15

19

30

35

μA

at two clocks (VDD=3V)

WDT disabled

/RESET= 'High', Fosc=32kHz

(Crystal type, CLKS="0"),

Output pin floating,

Operating supply current

ICC2

at two clocks (VDD=3V)

WDT enabled

/RESET= 'High', Fosc=4 MHz

(Crystal type, CLKS="0"),

Output pin floating

/RESET= 'High', Fosc=10 MHz

(Crystal type, CLKS="0"),

Output pin floating

Operating supply current

ICC3

-

2.0

4.0

mA

at two clocks (VDD=5.0V)

Operating supply current

ICC4

at two clocks (VDD=5.0V)

*

Note: These parameters are theoretical values and have not been tested.

7.2 AC Characteristics

Ta=25°C, VDD=5V ± 5%, VSS=0V

Symbol

Parameter

Conditions

Min.

Typ.

Max.

Unit

Dclk Input CLK duty cycle

-

Crystal type

RC type

-

45

100

500

50

-

55

DC

-

%

ns

Instruction cycle time

(CLKS="0")

Tins

Ttcc TCC input period

-

(Tins+20)/N*

17.6-30%

2000

Ta = 25°C, TXAL,

SUT1, SUT0=1, 1

Tdrh Device reset hold time

17.6 17.6+30% ms

ns

17.6 17.6+30% ms

Trst

/RESET pulse width

-

Ta = 25°C

SUT1, SUT0=1,1

Watchdog timer period

17.6~30%

*Twdt1

Ta = 25°C

Watchdog timer period

4.5+30%

288~30%

72~30%

4.5

288

72

4.5+30%

ms

*Twdt2

*Twdt3

*Twdt4

SUT1, SUT0=1,0

Ta = 25°C

SUT1, SUT0=0,1

Ta = 25°C

SUT1, SUT0=0,0

288+30% ms

72+30%

ms

Tset Input pin setup time

Thold Input pin hold time

Tdelay Output pin delay time

-

0

20

50

-

ns

Cload=20pF

Note: These parameters are theoretical values and have not been tested.

The Watchdog Timer duration is determined by Option Code (Bit 6, Bit 5)

*N = selected prescaler ratio

*Twdt1: The Option word (SUT1, SUT0) is used to define the oscillator set-up time. In Crystal mode the WDT

time-out length is the same as set-up time (18 ms).

*Twdt2: The Option word (SUT1, SUT0) is used to define the oscillator set-up time. In Crystal mode the WDT

time-out length is the same as set-up time (4.5 ms).

*Twdt3: The Option word (SUT1, SUT0) is used to define the oscillator set-up time. In Crystal mode the WDT

time-out length is the same as set-up time (288 ms).

*Twdt4: The Option word (SUT1, SUT0) is used to define the oscillator set-up time. In Crystal mode the WDT

time-out length is the same as set-up time (72 ms).

34 •

Product Specification (V1.8) 09.08.2009

(This specification is subject to change without further notice)

EM78P152/3S

8-Bit Microcontroller with OTP ROM

8 Timing Diagrams

AC Test Input/Output Waveform

2.4

0.4

2.0

0.8

2.0

0.8

TEST POINTS

AC Testing : Input is driven at 2.4V for logic "1",and 0.4V for logic "0".Timing measurements are

made at 2.0V for logic "1",and 0.8V for logic "0".

RESET Timing (CLK="0")

Instruction 1

Executed

NOP

CLK

/RESET

Tdrh

TCC Input Timing (CLKS="0")

Tins

CLK

TCC

Ttcc

Figure 8-1 EM78P152/3S Timing Diagrams

Product Specification (V1.8) 09.08.2009

(This specification is subject to change without further notice)

• 35

EM78P152/3S

8-Bit Microcontroller with OTP ROM

APPENDIX

A Package Type

OTP MCU

EM78P153SP/S/J

EM78P153SN/S/J

EM78P152SN/S/J

Package Type

DIP

Pin Count

Package Size

300 mil

14

10

SOP

150 mil

SSOP

150 mil

These are Green products which do not contain hazardous substances and comply

with the third edition of Sony SS-00259 standard.

Pb content is less than 100ppm and complies with Sony specifications.

Part No.

Electroplate type

Ingredient (%)

EM78P152/3SS/J

Pure Tin

Sn: 100%

°

Melting point ( C)

232 C

Electrical resistivity (μΩ-cm)

Hardness (hv)

11.4

8~10

>50%

Elongation (%)

36 •

Product Specification (V1.8) 09.08.2009

(This specification is subject to change without further notice)

EM78P152/3S

8-Bit Microcontroller with OTP ROM

B Package Information

14-Lead Plastic Dual in line (PDIP) — 300 mil

Figure B-1a EM78P153S 14-Lead PDIP Package Type

Product Specification (V1.8) 09.08.2009

(This specification is subject to change without further notice)

• 37

EM78P152/3S

8-Bit Microcontroller with OTP ROM

14-Lead Plastic Dual in line (SOP) — 150 mil

Figure B-1b EM78P153S 14-Lead SOP Package Type

38 •

Product Specification (V1.8) 09.08.2009

(This specification is subject to change without further notice)

EM78P152/3S

8-Bit Microcontroller with OTP ROM

10-Lead Plastic Shrink Small Outline (SSOP) — 150 mil

Product Specification (V1.8) 09.08.2009

(This specification is subject to change without further notice)

• 39

EM78P152/3S

8-Bit Microcontroller with OTP ROM

C Device Characteristics

The graphs provided in the following pages were derived based on a limited number of

samples and are shown here for reference only. The device characteristics illustrated

herein are not guaranteed for its accuracy. In some graphs, the data maybe out of the

specified warranted operating range.

Vih/Vil (Input pins with Schmitt Inverter)

2

°

Vih max (-40 C to 85 C)

°

Vih typ 25 C

1.5

1

°

Vih min (-40 C to 85 C)

°

Vil max (-40 C to 85 C)

0.5

0

°

Vil typ 25 C

°

Vil min (-40 C to 85 C)

2.5

3

3.5

4

4.5

5

5.5

Vdd (Volt)

Figure C-1 Vih, Vil of P60~P63, P66, P67 vs. VDD

Vth (Input Thershold Voltage) of I/O pins

2.2

2

1.8

1.6

1.4

1.2

1

Max (-40℃ to 85℃)

Typ 25℃

Min(-40℃ to 85℃)

0.8

0.6

0.4

2.5

3

3.5

4

4.5

5

5.5

VDD (Volt)

Figure C-2 Vth (Threshold voltage) of P50~P53, P64~P65 vs. VDD

40 •

Product Specification (V1.8) 09.08.2009

(This specification is subject to change without further notice)

EM78P152/3S

8-Bit Microcontroller with OTP ROM

Voh/Ioh (VDD=5V)

0

-5

-10

-15

-20

-25

Min 70°C

Typ 25°C

Min 0°C

0

1

2

3

4

5

Voh (Volt)

Figure C-3 Port 5 and Port 6 Voh vs. Ioh, VDD=5V

Figure C-4 Port 5 and Port 6 Voh vs. Ioh, VDD=3V

Vol/Iol (VDD=5V)

100

Max 0°C

80

Typ 25°C

Min 70°C

60

40

20

0

1

2

3

4

5

Vol (Volt)

Figure C-5 Port 5, Port 6.0~Port 6.3 and Port 6.6~Port 6.7 Vol vs. Iol, VDD=5V

Product Specification (V1.8) 09.08.2009

(This specification is subject to change without further notice)

• 41

EM78P152/3S

8-Bit Microcontroller with OTP ROM

Vol/Iol (VDD=3V)

40

30

20

10

Max 0°C

Typ 25°C

Min 70°C

0

0.5

1

1.5

2

2.5

3

Vol (Volt)

Figure C-6 Port 5, Port 6.0~Port 6.3 and Port 6.6~Port 6.7 Vol vs. Iol, VDD=3V

Vol/Iol (VDD=5V)

120

Max 0°C

100

Typ 25°C

80

Min 70°C

60

40

20

0

1

2

3

4

5

Vol (Volt)

Figure C-7 Port 6.4 and Port6.5 Vol vs. Iol, VDD=5V

42 •

Product Specification (V1.8) 09.08.2009

(This specification is subject to change without further notice)

EM78P152/3S

8-Bit Microcontroller with OTP ROM

Vol/Iol (VDD=3V)

60

50

40

30

20

10

0

Max 0°C

Typ 25°C

Min 70°C

0

0.5

1

1.5

2

2.5

3

Vol (Volt)

Figure C-8 Port 6.4 and Port 6.5 Vol vs. Iol, VDD=3V

WDT Time-out Period

35

30

Max 70°C

25

Typ 25°C

20

Min 0°C

15

10

2

3

4

5

6

VDD (Volt)

Figure C-9 WDT time-out period vs. VDD, Prescaler set to 1:1

Product Specification (V1.8) 09.08.2009

(This specification is subject to change without further notice)

• 43

EM78P152/3S

8-Bit Microcontroller with OTP ROM

Cext=100pF, Typical RC OSC Frequency

1.4

1.2

1

R = 3.3K

R = 5.1K

0.8

0.6

0.4

0.2

0

R = 10K

R = 100K

2.5

3

3.5

4

4.5

5

5.5

VDD (Volt)

Figure C-10 Typical RC OSC Frequency vs. VDD (Cext=100pF, Temperature at 25°C)

Figure C-11 Typical RC OSC Frequency vs. Temperature (R and C are ideal components)

44 •

Product Specification (V1.8) 09.08.2009

(This specification is subject to change without further notice)

EM78P152/3S

8-Bit Microcontroller with OTP ROM

IRC OSC Frequency (VDD=5V)

9

8

7

6

5

4

3

2

1

0

OSC = 8MHz

OSC = 4MHz

OSC = 1MHz

OSC = 455kHz

0

25

50

70

Temperature (°C)

Figure C-12 Internal RC OSC Frequency vs. Temperature, VDD=5V

IRC OSC Frequency (VDD=3V)

9

8

7

6

5

4

3

2

1

0

OSC = 8MHz

OSC = 4MHz

OSC = 1MHz

OSC = 455kHz

0

25

Temperature (°C)

Figure C-13 Internal RC OSC Frequency vs. Temperature, VDD=3V

50

70

Four conditions exist with the Operating Current ICC1 toICC4. These conditions are as follows:

ICC1: VDD=3V, Fosc=32kHz, 2 clocks, WDT disabled

ICC2: VDD=3V, Fosc=32kHz, 2 clocks, WDT enabled

ICC3: VDD=5V, Fosc=4 MHz, 2 clocks, WDT enabled

ICC4: VDD=5V, Fosc=10 MHz, 2 clocks, WDT enabled

Product Specification (V1.8) 09.08.2009

(This specification is subject to change without further notice)

• 45

EM78P152/3S

8-Bit Microcontroller with OTP ROM

Typical ICC1 and ICC2 vs. Temperature

18

15

12

9

Typ ICC2

Typ ICC1

0

10

20

30

40

50

60

70

Temperature (C)

Figure C-14 Typical Operating Current (ICC1 and ICC2) vs. Temperature

Maximum ICC1 and ICC2 vs. Temperature

24

21

18

15

Max ICC2

Max ICC1

0

10

20

30

40

50

60

70

Temperature (°C)

Figure C-15 Maximum Operating Current (ICC1 and ICC2) vs. Temperature

46 •

Product Specification (V1.8) 09.08.2009

(This specification is subject to change without further notice)

EM78P152/3S

8-Bit Microcontroller with OTP ROM

Typical ICC3 and ICC4 vs. Temperature

4

3.5

3

Typ ICC4

Typ ICC3

2.5

2

1.5

1

0.5

0

10

20

30

40

50

60

70

Temperature (°C)

Figure C-16 Typical operating current (ICC3 and ICC4) vs. Temperature

Maximum ICC3 and ICC4 vs. Temperature

4

3.5

3

Max ICC4

2.5

2

Max ICC3

1.5

1

0

10

20

30

40

50

60

70

Temperature (°C)

Figure C-17 Maximum Operating Current (ICC3 and ICC4) vs. Temperature

The following two conditions exist with the Standby Current ISB1 and ISB2:

ISB1: VDD=5V, WDT disable

ISB2: VDD=5V, WDT enable

Product Specification (V1.8) 09.08.2009

(This specification is subject to change without further notice)

• 47

EM78P152/3S

8-Bit Microcontroller with OTP ROM

Typical ISB1 and ISB2 vs. Temperature

12

9

Typ ISB2

Typ ISB1

6

3

0

10

20

30

40

50

60

70

Temperature (°C)

Figure C-18 Typical Standby Current (ISB1 and ISB2) vs. Temperature

48 •

Product Specification (V1.8) 09.08.2009

(This specification is subject to change without further notice)


型号：	EM78P153SPJ
厂家：	ETC
描述：	8-Bit Microcontroller with OTP ROM OTP只读存储器局域网微控制器
文件：	总52页 (文件大小：661K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

EM78P153SPJ [ETC]

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