EP520 [ETC]

EUREKA TECHNOLOGY; 尤里卡科技


型号：	EP520
厂家：	ETC
描述：	EUREKA TECHNOLOGY 尤里卡科技
文件：	总3页 (文件大小：58K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

EP520 SDRAM Controller

December 5, 2000

Product Specification

AllianceCORE™ Facts

Core Speciﬁcs

Supported Family

Device Tested

Virtex

V50-6

287

Eureka Technology, Inc.

CLB Slices

Clock IOBs¹

4962 El Camino Real, Suite 108

Los Altos, CA 94022 USA

Phone: +1 650-960-3800

IOBs¹

116

Performance (MHz)

Xilinx Tools

Fax:

E-Mail: info@eurekatech.com

URL: www.eurekatech.com

+1 650-960-3805

3.2i

Special Features

Provided with Core

Documentation

None

User guide

EDIF netlist

Top520.ucf

Features

Design File Formats

Constraints File

•

Supports Virtex™, Virtex™-E, and Spartan™-II FPGAs

Supports industry standard SDRAM and PC100

SDRAM DIMM.

Verification

VHDL or Verilog test bench

VHDL, Verilog

None

Instantiation Templates

•

Supports register mode and non-register mode PC100

SDRAM DIMM.

Reference designs &

application notes

•

Programmable memory size and data width.

Supports industrial standard 16Mbit, 64Mbit, 128Mbit

and 256Mbit SDRAMs.

Additional Items

None

Simulation Tool Used

•

Supports burst size of 1 to 8 and full page burst.

Supports zero wait state burst data transfer to maximize

data bandwidth.

Model Technology Modelsim™ 5.4b

Support

Support provided by Eureka Technology

•

Programmable SDRAM access timing parameters.

Automatic refresh generation with programmable

refresh intervals.

Notes:

1. Assuming all core I/Os are routed off-chip

•

Optional Error Correction Code (ECC).

Multiple external SDRAM partitions.

Supports external data buffer between user device and

SDRAM data bus

Applications

•

Networking equipment

Communication equipment

Video systems

Image processing equipment

Medical equipment

Avionics

PC peripherals

December 5, 2000

3-1

EP520 SDRAM Controller

Figure 1: EP520 SDRAM Controller Block Diagram

General Description

Functional Description

The EP520 SDRAM controller interfaces between a pro-

cessor or DMA device with an SDRAM. It performs SDRAM

read and write access based on processor or DMA

requests.

The EP520 core is partitioned into modules as shown in

Figure 1 and described below

State Machine

Based on the request signals ADS_B and CE_B, the state

machine sends control signals to the Counters, Address

Mux, and SDRAM control blocks to access to SDRAM.

READY_B is asserted for each read data that is returned

from the SDRAMs, or for each data that is written to the

SDRAMs. If an access to the Control Registers block is

requested on the CR_ADS_B input, the State Machine

sends appropriate control signals to the Control Registers

block to perform a register write.

SDRAM timing such as row and column latency, precharge

timing, and row access length are automatically handled by

the SDRAM controller. All these timing parameters are set

by the SDRAM controller on system reset and can be pro-

grammed by the user during run time to optimize system

performance.

The EP520 supports all industry standard SDRAM organi-

zations, ranging from 16Mbit to 256Mbit devices, and from

X4 data width to X16 data width. The user can use multiple

SDRAMs to build access word size from16-bit to 64-bit

wide, or use standard SDRAM DIMMs to build the memory

system.The SDRAM size and word size are programmable

by the memory controller.

SDRAM Control

The SDRAM control block generates the CS_B, CAS_B,

RAS_B and WE_B signals and drives the appropriate

address and DQM[7:0] at the proper timing.

Zero wait state data bursting is supported by the SDRAM

controller to maximize data throughput.The back-end inter-

face to user device such as CPU or DMA controller is a

standard microprocessor bus with wait state control. It can

be optimized easily to meet different application require-

ments.

Counters

Under the control of the state machine, the counters keep

track of the burst length and various SDRAM timing param-

eters, such as RAS_B-to-CAS_B delay, active command-

to-precharge time, etc, so that every command is issued at

the correct timing. These timing parameters are program-

mable through the Control Registers.

3-2

December 5, 2000

Eureka Technology, Inc.

Table 1: Core Signal Pinout

Address Mux

The Address Mux takes the input address on ADDR[31:0]

and drives the correct bank address on BA and row or col-

umn address on MADDR.

Signal

Description

Direction

ADDR[31:0]

ADS_B

Input

Address input

Address strobe

Byte enable

Control Registers

BE_B[7:0]

BLAST_B

CE_B

The user can program the SDRAM controller to support dif-

ferent SDRAM sizes, burst lengths, and SDRAM timing

parameters.The registers are accessed through the control

Burst last

Chip enable

CLK

System clock

Control register access

CR_ADR[1:0]

CR_ADS_B

CR_DT[31:0]

CR_RDY_B

CR_WR

OE_B

Core Modiﬁcations

The SDRAM controller is designed in the XCV50PQ240

device. Cores for other packages can also be supported.

Eureka Technology will contract to modify the core to your

speciﬁcations.

Output Control register ready

Input Register write

Output Output enable

Output Out of range

Output Ready

OFR_B

Pinout

READY_B

RESET_B

T_R_B

The pinout of the EP520 core has not been ﬁxed to speciﬁc

FPGA I/O, thereby allowing ﬂexibility with a user’s applica-

tion. Signal names are shown in Figure 1 and described in

Table 2.

Input

Output Transmit/Receive

Input Write enable

System reset

BA[1:0]

Output Bank address

Output Column address select

Output Chip select

CAS_B

Veriﬁcation Methods

CS_B[3:0]

DQM[7:0]

MADDR[12:0]

RAS_B

Functional simulation has been done using Model Technol-

ogy ModelsimTM 5.4b. Static timing analysis has been

done for all paths using the timing analyzer in Xilinx Foun-

dation Series 2.1i.Recommended Design Experience

Output Data mask

Output Memory address

Output Row address select

Output Register mode select

Output Write enable

REGE

The user must be familiar with HDL design methodology as

well as instantiation of Xilinx netlists in a hierarchical design

environment.

WE_B

Related Information

Recommended Design

Experience

Users should have a basic knowledge about SDRAM and

decide the target device.

Xilinx Programmable Logic

For information on Xilinx programmable logic or develop-

ment system software, contact your local Xilinx sales ofﬁce,

or:

Xilinx, Inc.

2100 Logic Drive

San Jose, CA 95124

Phone: +1 408-559-7778

Ordering Information

If you have inquiries or want to license our core, please

contact Eureka Technology directly. Eureka Technology

retains the right to make changes to these speciﬁcations at

any time without notice.

Fax:

URL:

+1 408-559-7114

www.xilinx.com

Phone : (650)960 3800

Email : info@eurekatech.com

For general Xilinx literature, contact:

Phone: 408-231-3386 (inside the USA)

408-879-5017 (outside the USA)

Email:

literature@xilinx.com

December 5, 2000

3-3

EP520 [ETC]

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