EPC2105ENG [ETC]
TRANS GAN 2N-CH 80V BUMPED DIE;型号: | EPC2105ENG |
厂家: | ETC |
描述: | TRANS GAN 2N-CH 80V BUMPED DIE |
文件: | 总9页 (文件大小:2210K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
eGaN® FET DATASHEET
EPC2105
EPC2105 – Enhancement-Mode GaN Power
Transistor Half-Bridge
VDS , 80 V
EFFICIENT POWER CONVERSION
RDS(on) , 14.5 mΩ (Q1), 3.6 mΩ (Q2)
ID , 10 A (Q1), 40 A (Q2)
HAL
Gallium Nitride’s exceptionally high electron mobility and low temperature coefficient allows very
low RDS(on), while its lateral device structure and majority carrier diode provide exceptionally low QG
and zero QRR. The end result is a device that can handle tasks where very high switching frequency,
and low on-time are beneficial as well as those where on-state losses dominate.
Maximum Ratings
DEVICE
PARAMETER
VALUE
UNIT
EPC2105 eGaN® ICs are supplied only in
passivated die form with solder bumps
Die Size: 6.05 mm x 2.3 mm
Drain-to-Source Voltage (Continuous)
Drain-to-Source Voltage (up to 10,000 5 ms pulses at 150°C)
Continuous (TA = 25°C, RθJA = 45°C/W)
Pulsed (25°C, TPULSE = 300 µs)
80
VDS
V
96
10
ID
A
V
Applications
70
Q1
Gate-to-Source Voltage
6
• High Frequency DC-DC
VGS
TJ
Gate-to-Source Voltage
-4
Benefits
Operating Temperature
–40 to 150
°C
V
TSTG Storage Temperature
–40 to 150
• High Frequency Operation
Drain-to-Source Voltage (Continuous)
VDS
80
• Ultra High Efficiency
Drain-to-Source Voltage (up to 10,000 5 ms pulses at 150°C)
96
Continuous (TA = 25°C, RθJA = 11°C/W)
40
• High Density Footprint
ID
A
Pulsed (25°C, TPULSE = 300 µs)
300
6
Q2
Gate-to-Source Voltage
VGS
V
Gate-to-Source Voltage
-4
TJ
Operating Temperature
–40 to 150
–40 to 150
°C
TSTG Storage Temperature
Thermal Characteristics
PARAMETER
TYP
0.4
2.5
42
UNIT
RθJC
RθJB
RθJA
Thermal Resistance, Junction-to-Case
Thermal Resistance, Junction-to-Board
Thermal Resistance, Junction-to-Ambient (Note 1)
Q1
°C/W
Note 1: RθJA is determined with the device mounted on one square inch of copper pad, single layer 2 oz copper on FR4 board.
See https://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf for details
EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2020 |
|
1
eGaN® FET DATASHEET
EPC2105
Static Characteristics (TJ = 25°C unless otherwise stated)
DEVICE
BVDSS
IDSS
PARAMETER
TEST CONDITIONS
VGS = 0 V, ID = 0.3 mA
VDS = 64 V, VGS = 0 V
VGS = 5 V
MIN
TYP
MAX
UNIT
V
Drain-to-Source Voltage
80
Drain-Source Leakage
0.003
0.005
0.003
1.3
0.2
2.5
mA
mA
mA
V
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Gate Threshold Voltage
IGSS
Q1
V
GS = -4 V
0.2
VGS(TH)
RDS(on)
VSD
VDS = VGS, ID = 2.5 mA
VGS = 5 V, ID = 20 A
IS = 0.5 A, VGS = 0 V
VGS = 0 V, ID = 0.75 mA
VDS = 64 V, VGS = 0 V
VGS = 5 V
0.8
80
2.5
Drain-Source On Resistance
Source-Drain Forward Voltage
Drain-to-Source Voltage
10
14.5
mΩ
V
1.7
BVDSS
IDSS
V
Drain-Source Leakage
0.01
0.02
0.01
1.3
0.55
9
mA
mA
mA
V
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Gate Threshold Voltage
IGSS
Q2
V
GS = -4 V
0.55
2.5
3.6
VGS(TH)
RDS(on)
VSD
VDS = VGS, ID = 10 mA
VGS = 5 V, ID = 20 A
IS = 0.5 A, VGS = 0 V
0.8
Drain-Source On Resistance
Source-Drain Forward Voltage
2.4
mΩ
V
1.5
Dynamic Characteristics (TJ = 25°C unless otherwise stated)
DEVICE
PARAMETER
TEST CONDITIONS
MIN TYP
300
3
MAX
UNIT
CISS
Input Capacitance
360
CRSS
Reverse Transfer Capacitance
Output Capacitance
VDS = 40 V, VGS = 0 V
COSS
COSS(ER)
COSS(TR)
QG
170
215
269
2.7
255
3.5
pF
Effective Output Capacitance, Energy Related (Note 2)
Effective Output Capacitance, Time Related (Note 3)
Total Gate Charge
VDS = 0 to 40 V, VGS = 0 V
Q1
VDS = 40 V, VGS = 5 V, ID = 20 A
VDS = 40 V, ID = 20 A
QGS
Gate-to-Source Charge
0.9
QGD
Gate-to-Drain Charge
0.5
nC
pF
nC
QG(TH)
QOSS
QRR
Gate Charge at Threshold
0.6
Output Charge
VDS = 40 V, VGS = 0 V
11
17
Source-Drain Recovery Charge
Input Capacitance
0
CISS
1170
12
1410
1170
CRSS
Reverse Transfer Capacitance
Output Capacitance
VDS = 40 V, VGS = 0 V
COSS
COSS(ER)
COSS(TR)
QG
780
1000
1270
11
Effective Output Capacitance, Energy Related (Note 2)
Effective Output Capacitance, Time Related (Note 3)
Total Gate Charge
VDS = 0 to 40 V, VGS = 0 V
Q2
VDS = 40 V, VGS = 5 V, ID = 20 A
15
77
QGS
Gate-to-Source Charge
3
QGD
Gate-to-Drain Charge
VDS = 40 V, ID = 20 A
VDS = 40 V, VGS = 0 V
2.1
QG(TH)
QOSS
QRR
Gate Charge at Threshold
2
Output Charge
51
Source-Drain Recovery Charge
0
Note 2: COSS(ER) is a fixed capacitance that gives the same stored energy as COSS while VDS is rising from 0 to 50% BVDSS
Note 3: COSS(TR) is a fixed capacitance that gives the same charging time as COSS while VDS is rising from 0 to 50% BVDSS
.
.
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| 2
eGaN® FET DATASHEET
EPC2105
Fꢃꢏꢆꢂe ꢐa ꢈꢑꢐꢉꢒ Tꢓꢔꢃꢍaꢎ ꢕꢆꢇꢔꢆꢇ ꢅꢖaꢂaꢍꢇeꢂꢃꢗꢇꢃꢍꢗ aꢇ ꢘꢙꢚꢅ
Fꢃꢏꢆꢂe ꢐꢑ ꢈꢒꢓꢉꢔ Tꢕꢖꢃꢍaꢎ ꢗꢆꢇꢖꢆꢇ ꢅꢘaꢂaꢍꢇeꢂꢃꢙꢇꢃꢍꢙ aꢇ ꢓꢚꢛꢅ
ꢀ00
200
100
0
ꢀ0
ꢁ0
20
0
ꢄ
ꢄ
ꢄ
ꢄ
ꢇ 5 ꢄ
ꢇ ꢁ ꢄ
ꢇ ꢃ ꢄ
ꢇ 2 ꢄ
ꢅꢆ
ꢅꢆ
ꢅꢆ
ꢅꢆ
ꢂ
ꢂ
ꢂ
ꢂ
ꢅ 5 ꢂ
ꢅ ꢆ ꢂ
ꢅ ꢀ ꢂ
ꢅ 2 ꢂ
ꢃꢄ
ꢃꢄ
ꢃꢄ
ꢃꢄ
0
0ꢂ5
1ꢂ0
1ꢂ5
2ꢂ0
2ꢂ5
ꢃꢂ0
0
0ꢁ5
1ꢁ0
1ꢁ5
2ꢁ0
2ꢁ5
ꢀꢁ0
ꢊDS ꢁ DꢂaꢃꢄꢋꢇꢌꢋSꢌꢆꢂꢍe ꢊꢌꢎꢇaꢏe ꢈꢊꢉ
ꢊDS ꢁ DꢂaꢃꢄꢋꢇꢌꢋSꢌꢆꢂꢍe ꢊꢌꢎꢇaꢏe ꢈꢊꢉ
Fꢃꢏꢆꢂe ꢐa ꢈꢑꢒꢉꢓ Tꢂaꢄꢔꢕeꢂ ꢅꢖaꢂaꢍꢇeꢂꢃꢔꢇꢃꢍꢔ
Fꢃꢏꢆꢂe ꢐꢑ ꢈꢒꢐꢉꢓ Tꢂaꢄꢔꢕeꢂ ꢅꢖaꢂaꢍꢇeꢂꢃꢔꢇꢃꢍꢔ
300
200
100
0
60
40
20
0
25˚C
125˚C
25˚C
125˚C
VDS = 3 V
VDS = 3 V
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
ꢊGS ꢁ GaꢇeꢋꢇꢌꢋSꢌꢆꢂꢍe ꢊꢌꢎꢇaꢏe ꢈꢊꢉ
ꢊGS ꢁ GaꢇeꢋꢇꢌꢋSꢌꢆꢂꢍe ꢊꢌꢎꢇaꢏe ꢈꢊꢉ
Fꢇꢐꢊꢆe ꢑa ꢁꢒꢓꢄꢔ ꢀDSꢁꢂꢃꢄ ꢕꢌꢖ ꢎGS ꢗꢂꢆ ꢎaꢆꢇꢂꢊꢌ Dꢆaꢇꢃ ꢘꢊꢆꢆeꢃꢉꢌ
Fꢇꢐꢊꢆe ꢑꢒ ꢁꢓꢔꢄꢕ ꢀDSꢁꢂꢃꢄ ꢖꢌꢗ ꢎGS ꢘꢂꢆ ꢎaꢆꢇꢂꢊꢌ Dꢆaꢇꢃ ꢙꢊꢆꢆeꢃꢉꢌ
ꢂ0
ꢀ0
20
10
0
ꢇ
ꢈ
ꢂ
2
0
ꢃꢄ ꢅ 10 ꢆ
ꢃꢄ ꢅ 20 ꢆ
ꢃꢄ ꢅ ꢀ0 ꢆ
ꢃꢄ ꢅ ꢂ0 ꢆ
ꢃꢄ ꢅ 10 ꢆ
ꢃꢄ ꢅ 20 ꢆ
ꢃꢄ ꢅ ꢀ0 ꢆ
ꢃꢄ ꢅ ꢂ0 ꢆ
2ꢁ5
ꢀꢁ0
ꢀꢁ5
ꢂꢁ0
ꢂꢁ5
5ꢁ0
2ꢁ0
2ꢁ5
ꢀꢁ0
ꢀꢁ5
ꢂꢁ0
ꢂꢁ5
5ꢁ0
ꢎGS ꢅ GaꢉeꢈꢉꢂꢈSꢂꢊꢆꢋe ꢎꢂꢏꢉaꢐe ꢁꢎꢄ
ꢎGS ꢅ GaꢉeꢈꢉꢂꢈSꢂꢊꢆꢋe ꢎꢂꢏꢉaꢐe ꢁꢎꢄ
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| 3
eGaN® FET DATASHEET
EPC2105
Fꢀꢁꢂꢃe ꢄa ꢅꢆꢇꢈꢉ ꢊDSꢅꢋꢌꢈ ꢍꢎꢏ ꢐGS ꢑꢋꢃ ꢐaꢃꢀꢋꢂꢎ Teꢒꢓeꢃaꢔꢂꢃeꢎ
Fꢀꢁꢂꢃe ꢄꢅ ꢆꢇꢈꢉꢊ ꢋDSꢆꢌꢍꢉ ꢎꢏꢐ ꢑGS ꢒꢌꢃ ꢑaꢃꢀꢌꢂꢏ Teꢓꢔeꢃaꢕꢂꢃeꢏ
40
30
20
10
0
8
6
4
2
0
25˚C
125˚C
25˚C
125˚C
ID = 20 A
ID = 20 A
2.5
3.0
3.5
4.0
4.5
5.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
ꢐGS ꢕ GaꢔeꢖꢔꢋꢖSꢋꢂꢃꢗe ꢐꢋꢘꢔaꢁe ꢅꢐꢈ
ꢑGS ꢖ GaꢕeꢗꢕꢌꢗSꢌꢂꢃꢘe ꢑꢌꢙꢕaꢁe ꢆꢑꢉ
Fꢃꢈꢉꢊe ꢋa ꢆꢌꢍꢇꢎ ꢀaꢁaꢂꢃꢄaꢅꢂe ꢆꢏꢃꢅeaꢊ Sꢂaꢐeꢇ
Fꢃꢈꢉꢊe ꢋꢌ ꢆꢍꢎꢇꢏ ꢀaꢁaꢂꢃꢄaꢅꢂe ꢆꢐꢑꢈ Sꢂaꢒeꢇ
500
ꢀ00
ꢋ00
200
100
0
1000
100
10
Cꢃꢄꢄ ꢅ Cꢆꢇ ꢈ Cꢄꢇ
Cꢉꢄꢄ ꢅ Cꢆꢇ ꢈ Cꢆꢄ
Cꢊꢄꢄ ꢅ Cꢆꢇ
Cꢃꢄꢄ ꢅ Cꢆꢇ ꢈ Cꢄꢇ
Cꢉꢄꢄ ꢅ Cꢆꢇ ꢈ Cꢆꢄ
Cꢊꢄꢄ ꢅ Cꢆꢇ
1
0
20
ꢀ0
ꢁ0
ꢂ0
0
20
ꢀ0
ꢂ0
ꢁ0
ꢑDS ꢒ DꢊaꢃꢅꢓꢄꢔꢓSꢔꢉꢊꢂe ꢑꢔꢐꢄaꢈe ꢆꢑꢇ
ꢓDS ꢔ DꢊaꢃꢅꢕꢄꢑꢕSꢑꢉꢊꢂe ꢓꢑꢒꢄaꢈe ꢆꢓꢇ
Fꢃꢈꢉꢊe ꢋꢂ ꢆꢌꢍꢇꢎ ꢀaꢁaꢂꢃꢄaꢅꢂe ꢆꢏꢃꢅeaꢊ Sꢂaꢐeꢇ
Fꢃꢈꢉꢊe ꢋꢌ ꢆꢍꢎꢇꢏ ꢀaꢁaꢂꢃꢄaꢅꢂe ꢆꢐꢑꢈ Sꢂaꢒeꢇ
2500
2000
1500
1000
500
1000
100
10
Cꢀꢁꢁ ꢂ Cꢃꢄ ꢅ Cꢁꢄ
Cꢆꢁꢁ ꢂ Cꢃꢄ ꢅ Cꢃꢁ
Cꢇꢁꢁ ꢂ Cꢃꢄ
Cꢀꢁꢁ ꢂ Cꢃꢄ ꢅ Cꢁꢄ
Cꢆꢁꢁ ꢂ Cꢃꢄ ꢅ Cꢃꢁ
Cꢇꢁꢁ ꢂ Cꢃꢄ
0
1
0
20
ꢈ0
ꢊ0
ꢉ0
0
20
ꢈ0
ꢊ0
ꢉ0
ꢑDS ꢒ DꢊaꢃꢅꢓꢄꢔꢓSꢔꢉꢊꢂe ꢑꢔꢐꢄaꢈe ꢆꢑꢇ
ꢓDS ꢔ DꢊaꢃꢅꢕꢄꢑꢕSꢑꢉꢊꢂe ꢓꢑꢒꢄaꢈe ꢆꢓꢇ
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4
eGaN® FET DATASHEET
EPC2105
Figure 6b (Q2): Output Charge and COSS Stored Energy
Figure 6a (Q1): Output Charge and COSS Stored Energy
ꢃꢄ0
0ꢀꢁ
0ꢀꢂ
0ꢀꢃ
0ꢀ2
0ꢀ0
20
15
10
5
100
ꢀ0
ꢁ0
ꢂ0
20
0
2ꢄꢂ
1ꢄꢀ
1ꢄꢂ
0ꢄꢁ
0ꢄ0
0
0
20
ꢃ0
ꢂ0
ꢁ0
0
20
ꢂ0
ꢁ0
ꢀ0
VDS – Drain-to-Source Voltage (V)
VDS – Drain-to-Source Voltage (V)
Fꢀꢁꢂꢃe ꢄa ꢅꢆꢇꢈꢉ Gaꢊe ꢋꢌaꢃꢁe
Fꢀꢁꢂꢃe ꢄꢅ ꢆꢇꢈꢉꢊ Gaꢋe ꢌꢍaꢃꢁe
5
5
ꢇ
ꢆ
2
1
0
ꢂꢃ ꢄ 20 ꢅ
ꢀꢁ ꢂ 20 ꢃ
ꢄꢁꢅ ꢂ ꢆ0 ꢄ
ꢈ
ꢁ
2
1
0
ꢆꢃꢇ ꢄ ꢈ0 ꢆ
0
0ꢀ5
1ꢀ0
1ꢀ5
2ꢀ0
2ꢀ5
ꢁꢀ0
0
2
ꢇ
ꢈ
ꢉ
10
12
ꢆG ꢎ Gaꢊe ꢋꢌaꢃꢁe ꢅꢓꢋꢈ
ꢇG ꢏ Gaꢋe ꢌꢍaꢃꢁe ꢆꢔꢌꢉ
Fꢈꢏꢃꢄe ꢐa ꢋꢑꢒꢌꢓ ꢔeꢕeꢄꢖe DꢄaꢈꢉꢆSꢂꢃꢄꢅe ꢊꢗaꢄaꢅꢇeꢄꢈꢖꢇꢈꢅꢖ
Fꢈꢏꢃꢄe ꢐꢑ ꢋꢒꢓꢌꢔ ꢕeꢖeꢄꢗe DꢄaꢈꢉꢆSꢂꢃꢄꢅe ꢊꢘaꢄaꢅꢇeꢄꢈꢗꢇꢈꢅꢗ
300
200
100
0
60
40
20
0
25˚C
125˚C
25˚C
125˚C
VGS = 0V
VGS = 0V
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
ꢍSD ꢁ SꢂꢃꢄꢅeꢆꢇꢂꢆDꢄaꢈꢉ ꢍꢂꢎꢇaꢏe ꢋꢍꢌ
ꢍSD ꢁ SꢂꢃꢄꢅeꢆꢇꢂꢆDꢄaꢈꢉ ꢍꢂꢎꢇaꢏe ꢋꢍꢌ
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| 5
eGaN® FET DATASHEET
EPC2105
Fꢀꢁꢂꢃe ꢄa ꢅꢆꢇꢈꢉ
Nꢊꢃꢋaꢌꢀꢍeꢎ ꢏꢐꢑSꢒaꢒe ꢓeꢔꢀꢔꢒaꢐꢕe ꢖꢔꢗ Teꢋꢘeꢃaꢒꢂꢃe
Fꢀꢁꢂꢃe ꢄꢅ ꢆꢇꢈꢉꢊ
Nꢋꢃꢌaꢍꢀꢎeꢏ ꢐꢑꢒSꢓaꢓe ꢔeꢕꢀꢕꢓaꢑꢖe ꢗꢕꢘ Teꢌꢙeꢃaꢓꢂꢃe
2ꢇ0
1ꢇꢈ
1ꢇꢉ
1ꢇꢊ
1ꢇ2
1ꢇ0
0ꢇꢈ
2ꢇ0
1ꢇꢈ
1ꢇꢉ
1ꢇꢊ
1ꢇ2
1ꢇ0
0ꢇꢈ
ꢀꢁ ꢂ 20 ꢃ
ꢄꢅꢆ ꢂ 5 ꢄ
ꢀꢁ ꢂ 20 ꢃ
ꢄꢅꢆ ꢂ 5 ꢄ
0
25
50
ꢋ5
100
125
150
0
25
50
ꢋ5
100
125
150
Tꢙ ꢚ ꢙꢂꢐꢕꢒꢀꢊꢐ Teꢋꢘeꢃaꢒꢂꢃe ꢅꢛꢜꢈ
Tꢚ ꢛ ꢚꢂꢑꢖꢓꢀꢋꢑ Teꢌꢙeꢃaꢓꢂꢃe ꢆꢜꢝꢉ
Fꢀꢁꢂꢃe ꢄꢅa ꢆꢇꢄꢈꢉ
Nꢊꢃꢋaꢌꢀꢍeꢎ Tꢏꢃeꢐꢏꢊꢌꢎ ꢑꢊꢌꢒaꢁe ꢓꢐꢔ Teꢋꢕeꢃaꢒꢂꢃe
Fꢀꢁꢂꢃe ꢄꢅꢆ ꢇꢈꢉꢊꢋ
Nꢌꢃꢍaꢎꢀꢏeꢐ Tꢑꢃeꢒꢑꢌꢎꢐ ꢓꢌꢎꢔaꢁe ꢕꢒꢖ Teꢍꢗeꢃaꢔꢂꢃe
1ꢀꢁ
1ꢀꢂ
1ꢀ2
1ꢀ1
1ꢀ0
0ꢀꢃ
0ꢀꢄ
0ꢀꢅ
0ꢀꢆ
1ꢀꢁ
1ꢀꢂ
1ꢀ2
1ꢀ1
1ꢀ0
0ꢀꢃ
0ꢀꢄ
0ꢀꢅ
0ꢀꢆ
ꢇꢈ ꢉ 2ꢀ5 ꢊꢋ
ꢇꢈ ꢉ 10 ꢊꢋ
0
25
50
ꢅ5
100
125
150
0
25
50
ꢅ5
100
125
150
Tꢖ ꢗ ꢖꢂꢘꢙꢒꢀꢊꢘ Teꢋꢕeꢃaꢒꢂꢃe ꢆꢚꢛꢈ
Tꢘ ꢙ ꢘꢂꢚꢛꢔꢀꢌꢚ Teꢍꢗeꢃaꢔꢂꢃe ꢇꢜꢝꢊ
Fꢃꢏꢆꢂe ꢝꢝa ꢈꢞꢝꢉꢟ Saꢠe ꢡꢢeꢂaꢇꢃꢄꢏ Aꢂea
Fꢃꢏꢆꢂe ꢝꢝꢞ ꢈꢟꢘꢉꢠ Saꢡe ꢢꢣeꢂaꢇꢃꢄꢏ Aꢂea
1000
100
10
1000
100
10
ꢁꢂꢃꢂꢄꢅꢆ ꢇꢈ ꢉꢊꢋꢌꢍꢎꢏ
ꢌꢆꢊꢆꢈꢄꢇ ꢍꢎ ꢏꢐꢑꢒꢓꢔꢕ
Pꢑꢒꢐꢅ ꢓꢂꢆꢄꢔ
Pꢁꢂꢃꢄ ꢅꢆꢇꢈꢉ
1 ꢃꢐ
1 ꢊꢃ
250 ꢋꢃ
100 ꢋꢃ
1
1
250 ꢕꢐ
100 ꢕꢐ
0ꢀ1
0ꢀ1
0ꢀ1
0ꢀ1
1
10
100
1
10
100
ꢊDS ꢁ DꢂaꢃꢄꢋSꢌꢆꢂꢍe ꢊꢌꢎꢇaꢏe ꢈꢊꢉ
Tꢐ ꢑ ꢒaꢓ ꢔaꢇeꢕꢖ Tꢅ ꢑ ꢗꢘꢙꢚꢅꢖ Sꢃꢄꢏꢎe ꢛꢆꢎꢜe
ꢊDS ꢁ DꢂaꢃꢄꢋSꢌꢆꢂꢍe ꢊꢌꢎꢇaꢏe ꢈꢊꢉ
Tꢐ ꢑ ꢒaꢓ ꢔaꢇeꢕꢖ Tꢅ ꢑ ꢗꢘꢙꢚꢅꢖ Sꢃꢄꢏꢎe ꢛꢆꢎꢜe
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| 6
eGaN® FET DATASHEET
EPC2105
Figure 12a
Transient Thermal
Response Curves
(Q1 & Q2) Junction-to-Board
1
0ꢃ1
Duty Cycle:
0.5
0.2
0.1
0.05
PDM
0.02
t1
0ꢃ01
0ꢃ001
t2
0.01
Notes:
Duty Factor: D = t1/t2
Peak TJ = PDM x ZθJB x RθJB + TB
Single Pulse
10ꢀ5
10ꢀꢁ
10ꢀꢂ
10ꢀ2
10ꢀ1
1
101
tp, Rectangular Pulse Duration, seconds
(Q1 & Q2) Junction-to-Case
Figure 12b
1
0ꢄ1
Transient Thermal
Response Curves
Duty Cycle:
0.5
0.2
0.1
0.05
PDM
0.02
0.01
t1
0ꢄ01
Notes:
Duty Factor: D = t1/t2
Peak TJ = PDM x ZθJC x RθJC + TC
Single Pulse
10ꢀ5
0ꢄ001
10ꢀꢁ
10ꢀꢂ
10ꢀꢃ
10ꢀ2
10ꢀ1
1
tp, Rectangular Pulse Duration, seconds
Figure 13
Typical Application Circuit
ꢇꢈꢁ
ꢉ
eGaNIC
Gaꢀe ꢁꢂꢃꢄeꢂꢅ
ꢆꢇꢈꢀꢂꢇꢉꢉeꢂ
ꢇꢈꢁ
ꢊ
ꢇꢔ
ꢓ1
ꢀꢃꢄꢅ 1
ꢇꢋꢌꢍ
ꢉ
ꢕꢋ
ꢇꢑ
ꢀꢆ1
ꢇꢑꢒ
ꢇCC
ꢎꢋ
ꢆꢎꢏꢃꢐ
ꢓ2
ꢀꢃꢄꢅ 2
ꢀꢁꢂ
Pꢀꢁꢂ
ꢊ
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| 7
eGaN® FET DATASHEET
EPC2105
TAꢀE AND ꢁEEꢂ ꢃꢄNFꢅGꢆꢁATꢅꢄN
ꢀ ꢁꢁ ꢂꢃꢄꢅꢆꢇ 12 ꢁꢁ ꢈꢃꢉꢊ ꢄꢋꢂꢊ ꢌꢍ ꢎꢏ ꢐꢊꢊꢑ
e
ꢛꢌꢋꢉꢊꢉ ꢜꢋꢂꢊ ꢝꢊꢊꢉ ꢒꢃꢐꢊꢅꢄꢃꢌꢍ
ꢉ
ꢇ
ꢈ
ꢓꢋꢄꢊ ꢔꢌꢑꢉꢊꢐ ꢕꢖꢁꢂ
ꢃꢔ ꢖꢍꢉꢊꢐ ꢄꢆꢃꢔ
ꢅꢌꢐꢍꢊꢐ
ꢎꢏ ꢃꢍꢅꢆ ꢐꢊꢊꢑ
ꢒꢃꢊ
ꢌꢐꢃꢊꢍꢄꢋꢄꢃꢌꢍ
ꢉꢌꢄ
Z Z Z Z
a ꢌ ꢋ
Y
Y Y Y
2 1 0 5
ꢒꢃꢊ ꢃꢔ ꢂꢑꢋꢅꢊꢉ ꢃꢍꢄꢌ ꢂꢌꢅꢗꢊꢄ
ꢔꢌꢑꢉꢊꢐ ꢕꢖꢁꢂ ꢔꢃꢉꢊ ꢉꢌꢈꢍ
ꢘꢙꢋꢅꢊ ꢔꢃꢉꢊ ꢉꢌꢈꢍꢚ
ꢊ
DIM
Dimension (mm)
EPC2105 (Note 1) Target MIN MAX
12.00 11.90 12.30
a
1.75
5.50
4.00
8.00
2.00
1.50
1.50
1.65 1.85
5.45 5.55
3.90 4.10
7.90 8.10
1.95 2.05
1.50 1.60
1.50 1.75
b
c (Note 2)
d
e
f (Note 2)
g
h
Note 1: MSL 1 (moisture sensitivity level 1) classified according to IPC/
JEDEC industry standard.
Note 2: Pocket position is relative to the sprocket hole measured as
true position of the pocket, not the pocket hole.
DIE MARKINGS
2105
YYYY
ZZZZ
Laser Markings
Part
Number
Part #
Marking Line 1
Lot_Date Code
Marking Line 2
Lot_Date Code
Marking Line 3
ꢀꢁꢂ ꢃꢄꢁꢂꢅꢆꢇꢆꢁꢃꢅ ꢈꢃꢆ
EPC2105
2105
YYYY
ZZZZ
ꢉꢇꢆꢂ ꢊꢋꢌꢍꢎ ꢇꢄꢂ ꢇꢏꢃꢅꢐ ꢆꢑꢁꢎ ꢂꢈꢐꢂ ꢃꢒ ꢆꢑꢂ ꢈꢁꢂ
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| 8
eGaN® FET DATASHEET
EPC2105
DIE OUTLINE
DIM
A
B
c
d
MIN
6020
2270
400
450
210
Nominal
6050
2300
400
450
225
MAX
6080
2330
400
450
240
Solder Bump View
A
40
39
38
37
36
5
4
3
2
1
10
9
15
14
13
12
11
20
19
18
17
16
25
24
23
22
21
30
29
28
27
26
35
34
33
32
31
45
44
43
42
41
50
49
48
47
55
54
53
52
51
60
59
58
57
56
65
64
63
62
61
70
69
68
67
66
75
74
73
72
71
e
f
187
208
240
8
Pad 2 is Gate1 (high side); Pad 4 is Gate2 (low side);
Pad 3 is HS Gate Return;
7
6
46
f
Pads 5, 12, 13, 14, 15, 22, 23, 24, 25, 32, 33, 34, 35,
42, 43, 44, 45, 52, 53, 54, 55, 62, 63, 64, 65, 72, 73,
74, 75 are Ground;
e
c
Pads 1, 11, 21, 31, 41, 51, 61, 71 are VIN ;
Pads 6, 7, 8, 9, 10, 16, 17, 18, 19, 20, 26, 27, 28, 29,
30, 36, 37, 38, 39, 40, 46, 47, 48, 49, 50, 56, 57, 58,
59, 60, 66, 67, 68, 69, 70 are Switch Node
Side View
Seating plane
RECOMMENDED LAND PATTERN
(measurements in µm)
6050
The land pattern is solder mask defined.
Suggest SMD Pads at 200 +20/ꢀ10 µm.
190 µm minimum.
1
2
3
4
5
6
7
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
8
9
10
400
RECOMMENDED STENCIL DRAWING
(measurements in µm)
6050
Recommended stencil should be 4 mil (100 µm)
thick, must be laser cut, openings per drawing.
Intended for use with SAC305 Type 4 solder,
reference 88.5% metals content.
225
Additional assembly resources available at:
https://epc-co.com/epc/DesignSupport/
AssemblyBasics.aspx
400
Efficient Power Conversion Corporation (EPC) reserves the right to make changes without further notice to any products herein to
improve reliability, function or design. EPC does not assume any liability arising out of the application or use of any product or circuit
described herein; neither does it convey any license under its patent rights, nor the rights of others.
Information subject to
change without notice.
eGaN® is a registered trademark of Efficient Power Conversion Corporation.
EPC Patent Listing: epc-co.com/epc/AboutEPC/Patents.aspx
Revised June, 2020
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