ES4118 [ETC]
Super VCD Processor Product Brief; 超级VCD处理器产品简介
| 型号： | ES4118 |
| 厂家： | 
ETC |
| 描述： | Super VCD Processor Product Brief |
| 文件： | 总4页 (文件大小：68K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Swan ES4118
Super VCD Processor
Product Brief
DESCRIPTION
FEATURES
The Swan ES4118 processor is a single-chip solution for Super
Video Compact Disk (SVCD) players that integrates MPEG
audio and video decoding, as well as system control software.
The fully programmable The ES4118 offers the best feature set
compared to existing SVCD chips and includes a glueless
interface to various peripheral components. The ES4118 is the
most cost-effective solution in its class, with levels of integration
and quality that establish new benchmarks.
• Single-chip SVCD decoder in a 208-pin plastic quad flat
package (PQFP)
• Supports MPEG-1 system and MPEG-2 program streams
• Programmable multimedia processor architecture
• Compatible with Audio CD, Video CD 1.1, 2.0, Interactive VCD
3.0, and Super Video CD
Video
The ES4118 processor is capable of decoding MPEG-2 audio
simultaneously with MPEG-1 or MPEG-2 video. For embedded
applications, the RISC processor core of the ES4118 can be
used in place of a microcontroller to provide a rich set of system
control features. On-chip, multitap filters provide arbitrary scaling
with state-of-the-art SmartScale™ technology that is useful for
video standards conversion. SmartStream™ provides video
error concealment and video postprocessing, ensuring the
highest playability and video quality.
• Trick modes, including Slow, Fast Forward, Fast Reverse, Step,
and Goto
• 4-bit onscreen display (OSD) with 4-bit blending
• 8-bit YUV output
Audio
• Karaoke function
• Supports 256/384iframe sync audio system clock
• Bidirectional I2S audio interface
The ES4118 connects directly with both 8- and 16-bit ROM and
with either 16-bit SDRAM ICs or with EDO DRAM ICs. An 8-bit
YUV video interface supports many TV encoders. General-
purpose auxiliary pins are provided to control various peripheral
devices. A standard I2S interface supports popular audio DACs
and ADCs. Figure 1 shows a block diagram of a typical
standalone system, using the ES4118 with the glueless SDRAM
interface.
Smart Technology
• SmartScale™ for NTSC to PAL conversion and vice versa
• SmartStream™ for video error concealment
Peripheral
• Independent audio bit clock for transmit and receive port
• Direct servo/loader interface
• Supports up to 4 MB of SDRAM and/or 4 MB of EDO DRAM
• Eight general-purpose auxiliary ports
• Single 27-MHz clock input
The SVCD data system stream from a CD disc is passed to the
ES4118 through the I2S interface. The ES4118 parses the system
layer and demultiplexes the audio and video streams. Audio is
decoded and passed through the I2S audio serial bus to an
external audio DAC and then to the speakers. Video is decoded
and output as YUV pixels to an NTSC or PAL video encoder.
Onchip system control and housekeeping functions (keypad and
remote control) are also provided.
• Power management
BLOCK DIAGRAM
Video
NTSC/PAL
Encoder
TV
EPROM
Audio
MIC
Audio
Codec
Swan™
ES4118
CD loader
Speakers
Remote Control/
Keypad
Panel
Interface
2 MB
SDRAM
Figure 1 Typical ES4118 System Block Diagram
ESS Technology, Inc.
SAM0422-052901
1
ES4118 PRODUCT BRIEF
ES4118 PINOUT
Figure 2 shows the ES4118 device pinout.
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
VCC
NC
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
VCC
VSS
VPP
DSCK
DQM
AUX0
AUX1
AUX2
VSS
VCC
AUX3
AUX4
AUX5
AUX6
AUX7
LOE#
VSS
DCS0#
VCC
VSS
DCS1#
DB15
DB14
DB13
DB12
VCC
VSS
DB11
DB10
DB9
VCC
LCS0#
LCS1#
LCS2#
LCS3#
VSS
DB8
DB7
DB6
VSS
LD0
VCC
LD1
DB5
LD2
DB4
LD3
Swan ES4118F
DB3
LD4
DB2
VCC
VSS
DB1
DB0
208-Pin PQFP Package
LD5
VSS
LD6
VCC
LD7
DRAS2#
DRAS1#
DRAS0#
DWE#
DOE#/DSCK_EN
DCAS#
VCC
LD8
LD9
LD10
LD11
VSS
VCC
LD12
LD13
LD14
LD15
LWRLL#
LWRHL#
VSS
VSS
DMA11
DMA10
DMA9
DMA8
DMA7
DMA6
VSS
VCC
NC
VCC
NC
DMA5
DMA4
DMA3
DMA2
DMA1
DMA0
LA0
LA1
LA2
LA3
54
53
VSS
Figure 2 ES4118 Device Pinout
2
SAM0422-052901
ESS Technology, Inc.
ES4118 PRODUCT BRIEF
ES4118 PIN DESCRIPTION
Table 1 lists the ES4118 pin descriptions.
Table 1 ES4118 Pin Descriptions List
Name
Number
I/O
Definition
1, 9, 18, 27, 35, 44,
51, 59, 68, 75, 83, 92,
99, 104, 111, 121, 130,
139, 148, 157, 164,
172, 183, 193, 201
I
VCC
3.3V power supply.
7:2, 16:10, 23:19,
207:204
O
I
LA[21:0]
VSS
Device address output.
8, 17, 26, 34, 43, 52,
60, 67, 76, 84, 91, 98,
103, 112, 120, 129,
138, 147, 156, 163,
171, 177, 184, 192,
200, 208
Ground.
RESET#
TDMDX
24
25
I
O
I
Reset input, active low.
TDM transmit data.
ROM Select.
RSEL
0
1
Selection
16-bit ROM
8-bit ROM.
RSEL
TDMDR
TDMCLK
TDMFS
TDMTSC#
TWS
28
29
30
31
32
33
I
I
TDM receive data.
TDM clock input.
TDM frame sync.
I
O
O
O
I
TDM output enable.
Audio transmit frame sync.
Audio transmit serial data port.
Select PLL0:
TSD
SEL_PLL2 SEL_PLL1 SEL_PLL0 Notes
0
0
1
1
0
1
0
1
2.5 x DCLK
SEL_PLL0
3 x DCLK
3.5 x DCLK
4 x DCLK.
SEL_PLL2
NC
36
I
Select PLL2. (Refer to the definitions table in pin number 33.)
No connect.
37, 38, 41, 42,
142:146, 149:155,
158, 202, 203
MCLK
39
I/O
I/O
I
Audio master clock for audio DAC.
Audio transmit bit clock.
Audio receive serial data.
Audio receive frame sync.
Audio receive bit clock.
Analog PLL capacitor.
Crystal input.
TBCK
40
RSD
45
RWS
46
I
RBCK
47
I
APLLCAP
XIN
48
I
49
I
XOUT
50
53:58, 61:66
69
O
O
O
O
O
O
O
I/O
O
O
O
Crystal output.
DMA[11:0]
DCAS#
DOE#
DRAM address bus.
DRAM column address strobe.
DRAM output enable.
DRAM clock enable
70
DSCK_EN
DWE#
71
74:72
DRAM write enable.
DRAS[2:0]#
DB[15:0]
DCS[1:0]#
DQM
DRAM row address strobe.
DRAM data bus.
77:82, 85:90, 93:96
97, 100
SDRAM chip select [1:0], active low.
Data input/output mask.
Clock to SDRAM.
101
DSCK
102
3
SAM0422-052901
ESS Technology, Inc.
ES4118 PRODUCT BRIEF
Table 1 ES4118 Pin Descriptions List (Continued)
Name
Number
I/O
I
Definition
DCLK
105
Clock input (bypass/test mode).
8-bit YUV output.
YUV[7:0]
PCLK2XSCN
PCLKQSCN
VSYNC#
HSYNC#
106:110, 113:115
O
116
117
118
119
I/O
I/O
I/O
I/O
I/O
27 MHz doubled pixel clock.
13.5 MHz pixel clock.
Vertical sync.
Horizontal sync.
122:128, 131:137,
140:141
HD[15:0]
Host data bus.
VPP
159
160:162, 165:169
170
I
5V power supply.
Auxiliary ports.
AUX[7:0]
LOE#
I/O
O
Device output enable.
Chip select [3:0].
LCS[3:0]#
173:176
O
178:182, 185:191,
194:197
I/O
LD[15:0]
Device data bus.
LWRLL#
LWRHL#
198
199
O
O
Device write enable.
Device write enable.
ORDERING INFORMATION
Part Number
Description
Super VCD Processor
Package
ES4118F
208-pin PQFP
No part of this publication may be reproduced, stored in a
ESS Technology, Inc. assumes no responsibility for any
retrieval system, transmitted, or translated in any form or errors contained herein.
by any means, electronic, mechanical, manual, optical, or
(P) U.S. Patent 4,214,125 and others, other patents
pending.
VideoDrive® is a registered trademark of ESS Technology,
Inc.
otherwise, without the prior written permission of ESS
Technology, Inc.
ESS Technology, Inc. makes no representations or
warranties regarding the content of this document.
All other trademarks are owned by their respective
holders and are used for identification purposes only.
All specifications are subject to change without prior
notice.
4
© 2001 ESS Technology, Inc. All rights reserved.
SAM0422-052901
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