ESC1621 [ETC]

RAM Mapping 32 X 4 LCD Controller for I/O uC; 内存映射32× 4 LCD控制器的I / O的uC


型号：	ESC1621
厂家：	ETC
描述：	RAM Mapping 32 X 4 LCD Controller for I/O uC 内存映射32× 4 LCD控制器的I / O的uC 控制器 CD
文件：	总7页 (文件大小：60K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

RAM Mapping 32 X 4 LCD Controller for I/O uC

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General Descriptions

The ESC1621 is a 128-pattern (32x4), memory mapping, and multi-function LCD driver. The

S/W configuration feature of the ESC1621 makes it suitable for multiple LCD applications includ-

ing LCD modules and display subsystems. Only three or four lines are required for the interface

between the host controller and the ESC1621. The ESC1621 contains a power down command to

reduce power consumption.

Features

• Operating voltage: 2.4V~5.2V.

• Built-in 256kHz RC oscillator.

• External 32.768kHz crystal or 256kHz frequency source input.

• Selection of 1/2 or 1/3 bias, and selection of 1/2 or 1/3 or 1/4 duty LCD applications.

• Internal time base frequency sources.

• Two selectable buzzer frequencies (2kHz/4kHz).

• Built-in time base generator and WDT.

• Time base or WDT overflow output.

• Power down command reduces power Consumption.

• 8 kinds of time base/WDT clock sources.

• 32x4 LCD driver.

• Built-in 32x4 bit display RAM.

• 3-wire serial interface.

• Internal LCD driving frequency source.

• Software configuration feature.

• Data mode and command mode instructions.

• R/W address auto increment.

• Three data accessing modes.

• VLCD pin for adjusting LCD operating voltage.

Last update: 2004-03-05 12:03

p. 1

ESC1621

Block Diagram

Watchdog Timer

Time Base Generator

Tone

Generator

IRQ

VDD

GND

VLCD

COM0

COM3

SEG0

LCD Driver

Bias Circuit

Control

Logic

DATA

SEG31

Timing

Generator

OSCI

OSCO

Display Memory

Note: CS: Chip selection

BZ, BZ: Tone outputs

WR, RD, DATA: Serial interface

IRQ: Time base or WDT overflow output

COM0~COM3, SEG0~SEG31: LCD outputs

Last update: 2004-03-05 12:13

p. 2

ESC1621

Pin Assignment

ESC1621D-28SKDIP

ESC1621B-48SSOP

Last update: 2004-03-05 12:13

p. 3

ESC1621

Pad Description

Pad No.

Pad Name

I/O

Function

Chip selection input with pull-high resistor

When the CS is logic high, the data and command read from or written

to the ESC1621 are disabled. The serial interface circuit is also reset. But

if CS is at logic low level and is input to the CS pad, the data and com-

mand transmission between the host controller and the ESC1621 are all

enabled.

READ clock input with pull-high resistor

Data in the RAM of the ESC1621 are clocked out on the falling edge of

the RD signal. The clocked out data will appear on the DATA line. The

host controller can use the next rising edge to latch the clocked out data.

WRITE clock input with pull-high resistor

Data on the DATA line are latched into the ESC1621 on the rising edge

of the WR signal.

DATA

GND

I/O Serialdata input/output with pull-high resistor

—

Negative power supply, ground

OSCO

The OSCI and OSCO pads are connected to a 32.768kHz crystal in order

to generate a system clock. If the system clock comes from an external

clock source, the external clock source should be connected to the OSCI

pad. But if and on-chip RC oscillator is selected instead, the OSCI and

OSCO pads can be left open.

OSCI

VLCD

VDD

LCD power input

—

Positive power supply

IRQ

Time base or WDT overflow flag, NMOS open drain output

2kHz or 4kHz tone frequency output pair

LCD common outputs

11,12

13~16

48~17

BZ, BZ

COM0~COM3

SEG0~SEG31

LCD segment outputs

Absolute Maximum Ratings

Supply Voltage…………...…..… -0.3V ~ 5.5V

Input Voltage……… V_SS- 0.3V ~ V_DD+ 0.3V

Storage Temperature……………-50^°C ~ 125^°C

Operating Temperature………….. -25^°C ~ 75^°C

Note: These are stress ratings only. Stresses exceeding the range specified under “Absolute Maxi-

mum Ratings” may cause substantial damage to the device. Functional operation of this de-

vice at other conditions beyond those listed in the specification is not implied and prolonged

exposure to extreme conditions may affect device reliability.

Last update: 2004-03-05 12:13

p. 4

ESC1621

D.C. Characteristics

Test Conditions

Conditions

Symbol

Parameter

Min.

Typ.

Max.

Unit

V_DD

I_DD1

Operating Voltage

Operating Current

—

2.4

—

220

450

5.2

300

600

120

240

200

400

µA

3V No load/LCD ON

On-chip RC oscillator

—

3V No load/LCD ON

—

I_DD2

I_DD3

I_STB

Operating Current

Standby Current

Crystal oscillator

—

180

150

300

0.1

0.3

—

3V No load/LCD ON

—

External clock source

—

3V No load

—

Power down mode

—

0.6

1.0

3.0

5.0

—

Input Low Voltage

Input High Voltage

DATA, WR, CS, RD

—

2.4

4.0

0.5

1.3

-0.4

-0.9

—

DATA, WR, CS, RD

—

3V V_OL=0.3V

5V V_OL=0.5V

3V V_OH=2.7V

5V V_OH=4.5 V

3V V_OL=0.3V

5V V_OL=0.5V

3V V_OH=2.7V

5V V_OH=4.5 V

3V V_OL=0.3V

5V V_OL=0.5V

3V V_OH=2.7V

5V V_OH=4.5 V

1.2

2.6

-0.8

-1.8

150

250

-120

-200

120

200

-70

-100

µA

I_OL1

I_OH1

I_OL2

I_OH2

I_OL3

I_OH3

R_PH

DATA, BZ, BZ, IRQ

DATA, BZ, BZ

—

LCD Common Sink Current

150

-80

-120

—

LCD Common Source Cur-

rent

—

LCD Segment Sink Current

120

-40

-70

—

LCD Segment Source Cur-

rent

—

150

100

Pull-high Resistor

DATA, WR, CS, RD

Last update: 2004-03-05 12:13

p. 5

ESC1621

A.C. Characteristics

Test Conditions

Conditions

Sym.

Parameter

Min.

Typ.

Max.

Unit

V_DD

—

256

—

kHz

f_SYS1System Clock

f_SYS2System Clock

f_SYS3System Clock

On-chip RC oscillator

Crystal oscillator

32.768

256

—

External clock source

256

—

On-chip RC oscillator

Crystal oscillator

F_SYS1/1024

F_SYS2/128

F_SYS3/1024

n/f_LCD

—

f_LCDLCD Clock

—

External clock source

n: Number of COM

—

t_COMLCD Common Period

—

150

300

kHz

f_CLK1Serial Data Clock (WR Pin)

Duty cycle 50%

f_CLK2Serial Data Clock (RD Pin)

f_TONETone Frequency

150

—

On-chip RC oscillator

2.0 or 4.0

250

Serial Interface Reset Pulse Width

t_CS

—

µs

(Figure 3)

Write mode

Read mode

Write mode

Read mode

3.34

6.67

1.67

3.34

—

WR, RD Input Pulse Width

t_CLK

(Figure 1)

Rise/Fall Time Serial Data Clock

t_r,t_f

t_su

t_h

—

120

100

—

Width

(Figure 1)

Setup Time for DATA to WR, RD

Clock Width

(Figure 2)

Hold Time for DATA to WR, RD

Clock Width

(Figure 2)

Setup Time for CS to WR, RD

Clock Width

t_su1

(Figure 3)

Hold Time for CS to WR, RD

Clock Width

t_h1

(Figure 3)

Last update: 2004-03-05 12:13

p. 6

ESC1621

Application Circuits

Host controller with a ESC1621 display system

VDD

VLCD

DATA

ESC1621

µC

Piezo

IRQ

OSCI

Clock Out

OSCO COM0~COM3

SEG0~SEG31

External Clock

1/2 or 1/3 Bias; 1/2, 1/3 or 1/4 Duty

On-chip OSC

LCD PANEL

Crystal

32768Hz

Note: The connection of IRQ and RD pin can be selected depending on the requirement of the µC.

The voltage applied to V_LCDpin must be lower than V_DD.

Adjust VR to fit LCD display, at V_DD=5V, V_LCD=4V, VR=15kO+20%

Adjust R (external pull-high resistance) to fit user’s time base clock.

Last update: 2004-03-05 12:13

p. 7

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