ESDALC6V1W [ETC]
QUAD TRANSIL ARRAY FOR ESD PROTECTION ; QUAD TRANSIL阵列，用于ESD保护\n
| 型号： | ESDALC6V1W |
| 厂家： | 
ETC |
| 描述： | QUAD TRANSIL ARRAY FOR ESD PROTECTION
|
| 文件： | 总9页 (文件大小：147K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
ESDALC6V1W5
QUAD TRANSIL™ ARRAY
FOR ESD PROTECTION
Application Specific Discretes
A.S.D.
MAIN APPLICATIONS
Where transient overvoltage protection in ESD
sensitive equipment is required, such as :
■
■
■
■
■
Computers
Printers
Communication systems and cellular phones
Video equipment
Set top boxes
FEATURES
SOT323-5L
■
■
■
■
■
4 unidirectional TRANSIL™ functions.
ESD Protection: IEC61000-4-2 level 4
Breakdown voltage VBR = 6.1V min
Low leakage current < 1µA @ 3 Volts
Low capacitance device
FUNCTIONAL DIAGRAM
DESCRIPTION
The ESDALC6V1W5 is a 4-bit wide monolithic
suppressor which is designed to protect component
connected to data and transmission lines against
ESD.
I/01
GND
I/02
I/04
I/03
It clamps the voltage just above the logic level
supply for positive transients, and to a diode drop
below ground for negative transients.
BENEFITS
■
■
■
■
High ESD protection level : up to 25 kV.
Capacitance: 12pF @ 0V Typ.
High integration.
Suitable for high density boards.
COMPLIES WITH THE FOLLOWING STANDARDS :
■
IEC61000-4-2 level 4: 15 kV (air discharge)
8 kV (contact discharge)
■
MIL STD 883C-Method 3015-6 : class 3.
(human body model) 25kV (HBM)
June 2002 - Ed: 4A
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ESDALC6V1W5
ABSOLUTE MAXIMUM RATINGS (Tamb = 25°C)
Symbol
Parameter
Test conditions
Value
Unit
VPP
ESD discharge - MIL STD 883E - Method 3015-7
IEC61000-4-2 air discharge
± 25
± 15
± 8
kV
IEC61000-4-2 contact discharge
PPP
Tj
Peak pulse power (8/20 µs)
Junction temperature
25
W
°C
°C
°C
150
Tstg
Top
Storage temperature range
Operating temperature range
- 55 to + 150
- 40 to + 150
ELECTRICAL CHARACTERISTICS (Tamb = 25°C)
Symbol
VRM
VBR
VCL
IRM
Parameter
Stand-off voltage
I
Breakdown voltage
Clamping voltage
Leakage current
VCL VBR VRM
V
IRM
IR
IPP
Peak pulse current
Capacitance per line
Dynamic resistance
C
Rd
slope : 1 / Rd
IPP
Types
VBR
@
IR
IRM
@
VRM
Rd
αT
C
C
min.
max.
max.
typ.
note 1
mΩ
max.
note 2
10-4/°C
6
typ.
max.
3V bias 3V bias
V
V
mA
1
µA
V
3
pF
pF
6.1
7.2
1
1100
7.5
9.5
ESDALC6V1W5
Note 1 : Square pulse Ipp = 15A, tp=2.5µs.
Note 2 : ∆ V
= αT* (Tamb -25°C) * V
(25°C)
BR
BR
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ESDALC6V1W5
Fig. 1: Relative variation of peak pulse power
versus initial junction temperature.
Fig. 2: Peak pulse power versus exponential pulse
duration.
Ppp[Tj initial] / Ppp [Tj initial = 25°C]
1.1
Ppp(W)
100
Tj initial = 25°C
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
tp(µs)
Tj(°C)
0.0
10
0
25
50
75
100
125
150
175
1
10
100
Fig. 3: Junction capacitance versus reverse voltage
applied (typical values).
Fig. 4: Clamping voltage versus peak pulse cur-
rent (maximum values, rectangular waveform).
Ipp(A)
100.0
C(pF)
14
F=1MHz
Vosc=30mVRMS
Tj=25°C
12
10
8
10.0
1.0
6
4
2
tp=2.5µs
Tj initial =25°C
Vcl(V)
VR(V)
0.1
0
0
10
20
30
40
50
60
0
1
2
3
4
5
Fig. 5: Relative variation of leakage current versus
junction temperature (typical values).
Fig. 6: Application example
IR [Tj] / IR [Tj=25°C]
100
I/02
I/01
IC
to be
I/04
protected
I/03
10
Tj(°C)
75
1
25
50
100
125
3/9
ESDALC6V1W5
TECHNICAL INFORMATION
1. ESD protection by ESDALC6V1W5
With the focus of lowering the operation levels, the problem of malfunction caused by the environment is
critical. Electrostatic discharge (ESD) is a major cause of failure in electronic systems.
As a transient voltage suppressor, ESDALC6V1W5 is an ideal choice for ESD protection by suppressing
ESD events. It is capable of clamping the incoming transient to a low enough level such that any damage is
prevented on the device protected by ESDALC6V1W5.
ESDALC6V1W5 serves as a parallel protection elements, connected between the signal line and ground.
As the transient rises above the operating voltage of the device, the ESDALC6V1W5 becomes a low
impedance path diverting the transient current to ground.
The clamping voltage is given by the following formula:
VCL = VBR + Rd.IPP
As shown in figure A1, the ESD strikes are clamped by the transient voltage suppressor.
Fig. A1: ESD clamping behavior
RG
I
PP
Rd
RL OAD
V
G
V(i/o)
V
BR
Device
to be
ESD surge
ESDALC6V1W5
protected
To have a good approximation of the remaining voltages at both Vi/o side, we provide the typical dynamical
resistance value Rd. By taking into account the following hypothesis:
Rg > Rd and Rload > Rd
we have:
Vg
V i / o = V + Rd ×
( )
BR
Rg
The results of the calculation done Vg = 8kV, Rg = 330Ω (IEC61000-4-2 standard), VBR = 6.1V (min) and
Rd = 1.1Ω (typ.) give:
V i / o = 32,8Volts
( )
This confirms the very low remaining voltage across the device to be protected. It is also important to note
that in this approximation the parasitic inductance effect was not taken into account. This could be a few
tenths of volts during a few ns at the Vi/o side.
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ESDALC6V1W5
Fig. A2: ESD test board
Fig. A3: ESD test configuration
TEST BOARD
I/O1, I/O2, I/O3 or I/O4
(i/o)
± 8kV
ESD Contact
discharge
V(i/o)
B2
The measurements done here after show very clearly (Fig. A4) the high efficiency of the ESD protection:
the clamping voltage V(i/o) becomes very close to +VBR (positive way, Fig. A4a) and -VBR (negative way,
Fig. A4b).
Fig. A4: Remaining voltage during ESD surge
V(i/o)
V(i/o)
a: Response in the positive way
b: Response in the negative way
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ESDALC6V1W5
CROSSTALK BEHAVIOR
Fig. A5: Crosstalk phenomenon
RG1
Line 1
Line 2
VG1
RL1
α1VG1 + β12VG2
RG2
VG2
RL2
α2VG2 + β21VG1
DRIVERS
RECEIVERS
The crosstalk phenomena are due to the coupling between 2 lines. Coupling factors ( β12 or β21 ) increase
when the gap across lines decreases, particularly in silicon dice. In the example above, the expected
signal on load RL2 is α2VG2, in fact the real voltage at this point has got an extra value β21VG2. This part of
the VG1 signal represents the effect of the crosstalk phenomenon of the line 1 on the line 2. This
phenomenon has to be taken into account when the drivers impose fast digital data or high frequency
analog signals. The perturbed line will be more affected if it works with low voltage signal or high load
impedance (few kΩ)
Fig. A6: Analog crosstalk measurements
TESTBOARD
I/O4
To Port1
To Port2
I/O1
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ESDALC6V1W5
Fig. A7: Typical analog crosstalk measurements.
ESDALC6V1W5 : typical analog crosstalk response
0.00
dB
-10.00
-20.00
-30.00
-40.00
-50.00
-60.00
-70.00
-80.00
-90.00
-100.0
1.0M
3.0M
10.0M
30.0M
100.0M 300.0M
f/Hz
1.0G
3.0G
Figure A6 gives the measurement circuit for the analog crosstalk application. In figure A7, the curve shows
the effect of the line I/O1 on the line I/O4. In usual frequency range of analog signals (up to 100MHz) the
effect on disturbed line is less than -60dB.
Fig. A8: Digital crosstalk measurements configu-
ration.
Fig. A9: Digital crosstalk results.
I/O1
unloaded
rise time: t10-90% = 3ns
VG1
V
G1
0 - 3kV
pulse generator
GND
F= 5MHz
tR = 3ns
β21VG1
β21VG1
crosstalk
unloaded
I/O4
Figure A8 shows the measurement circuit used to quantify the crosstalk effect in a classical digital
application.
Figure A9 shows that in such a condition, the impact on the disturbed line is less than 50 mV peak to peak.
No data disturbance was noted on the concerned line. The measurements performed with falling edges
give an impact within the same range.
7/9
ESDALC6V1W5
Fig. A10: Aplac model
Lbond
D6V1
Lbond
D6V1
Cz 9.2pF
Rs 100m
I/O1
I/O4
Lbond 1.2nH
Lhole 380pH
Caphole 0.2pF
Rhole 450m
caphole
Model D6V1
BV = 7
IBV = 1m
CJO = Cz
M = 0.3333
RS = 1
Rhole Lhole
Lbond
D6V1
D6V1
Lbond
VJ = 0.6
TT = 100n
I/O2
I/O3
ORDER CODE
ESDA LC 6V1 W5
PACKAGE: SOT323-5L
ESD ARRAY
LOW CAPACITANCE
VBR min
Ordering type
Marking
Package
Weight
Base qty
Delivery mode
ESDALC6V1W5
C61
SOT323-5L
5.4 mg.
3000
Tape & reel
8/9
ESDALC6V1W5
PACKAGE MECHANICAL DATA
SOT323-5L
DIMENSIONS
Millimeters Inches
Min. Max. Min.
0.8 1.1
REF.
A
A2
Max.
0.043
0.004
0.039
0.012
0.007
0.086
0.053
A1
A
A1
A2
b
0.031
0
0
0.1
1
0.8
0.031
0.006
0.004
0.071
0.045
D
e
e
0.15
0.1
0.3
0.18
2.2
1.35
c
D
1.8
H
E
E
1.15
e
0.65 Typ.
0.026 Typ.
H
1.8
0.1
2.4
0.4
0.071
0.004
0.094
0.016
Q1
c
Q1
b
FOOT PRINT (in millimeters)
0.3mm
Mechanical specifications
Lead plating Tin-lead
1mm
Lead plating thickness 5µm min.
25 µm max.
Lead material
Sn / Pb
(70% to 90% Sn)
2.9mm
Lead coplanarity
Body material
Epoxy meets
10µm max.
1mm
Molded epoxy
UL94,V0
0.35mm
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of
use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by
implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to
change without notice. This publication supersedes and replaces all information previously supplied.
STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written ap-
proval of STMicroelectronics.
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